Subversion Repositories pci

-cdslib ../bin/cds.lib
-hdlvar ../bin/hdl.var
-logfile ../log/ncvlog.log
-update
-messages
-INCDIR ../../../bench/verilog
-INCDIR ../../../rtl/verilog
-DEFINE REGRESSION
-DEFINE REGR_FIFO_SMALL_GENERIC
-DEFINE GUEST                       
-DEFINE WB_DECODE_FAST              
-DEFINE PCI_DECODE_MAX              
-DEFINE WB_DECODE_MED               
-DEFINE PCI66                       
-DEFINE WB_CLK66                    
-DEFINE ACTIVE_HIGH_OE              
-DEFINE WB_CNF_BASE_ZERO            
-DEFINE NO_CNF_IMAGE                
-DEFINE PCI_CLOCK_FOLLOWS_WB_CLOCK=2
../../../rtl/verilog/pci_parity_check.v
../../../rtl/verilog/pci_target_unit.v
../../../rtl/verilog/pci_wb_addr_mux.v
../../../rtl/verilog/pci_cbe_en_crit.v
../../../rtl/verilog/pci_pcir_fifo_control.v
../../../rtl/verilog/pci_out_reg.v
../../../rtl/verilog/pci_pci_tpram.v
../../../rtl/verilog/pci_wb_master.v
../../../rtl/verilog/pci_conf_cyc_addr_dec.v
../../../rtl/verilog/pci_frame_crit.v
../../../rtl/verilog/pci_target32_clk_en.v
../../../rtl/verilog/pci_pciw_fifo_control.v
../../../rtl/verilog/pci_wb_slave.v
../../../rtl/verilog/pci_conf_space.v
../../../rtl/verilog/pci_frame_en_crit.v
../../../rtl/verilog/pci_par_crit.v
../../../rtl/verilog/pci_pciw_pcir_fifos.v
../../../rtl/verilog/pci_wb_slave_unit.v
../../../rtl/verilog/pci_frame_load_crit.v
../../../rtl/verilog/pci_bridge32.v
../../../rtl/verilog/pci_target32_devs_crit.v
../../../rtl/verilog/pci_perr_crit.v
../../../rtl/verilog/pci_wbr_fifo_control.v
../../../rtl/verilog/pci_cur_out_reg.v
../../../rtl/verilog/pci_pci_decoder.v
../../../rtl/verilog/pci_target32_interface.v
../../../rtl/verilog/pci_perr_en_crit.v
../../../rtl/verilog/pci_wbw_fifo_control.v
../../../rtl/verilog/pci_wb_decoder.v
../../../rtl/verilog/pci_in_reg.v
../../../rtl/verilog/pci_serr_crit.v
../../../rtl/verilog/pci_wbw_wbr_fifos.v
../../../rtl/verilog/pci_delayed_sync.v
../../../rtl/verilog/pci_irdy_out_crit.v
../../../rtl/verilog/pci_io_mux.v
../../../rtl/verilog/pci_io_mux_ad_en_crit.v
../../../rtl/verilog/pci_io_mux_ad_load_crit.v
../../../rtl/verilog/pci_target32_sm.v
../../../rtl/verilog/pci_serr_en_crit.v
../../../rtl/verilog/pci_delayed_write_reg.v
../../../rtl/verilog/pci_mas_ad_en_crit.v
../../../rtl/verilog/pci_mas_ad_load_crit.v
../../../rtl/verilog/pci_master32_sm.v
../../../rtl/verilog/pci_target32_stop_crit.v
../../../rtl/verilog/pci_synchronizer_flop.v
../../../rtl/verilog/pci_async_reset_flop.v
../../../rtl/verilog/pci_mas_ch_state_crit.v
../../../rtl/verilog/pci_master32_sm_if.v
../../../rtl/verilog/pci_target32_trdy_crit.v
../../../rtl/verilog/top.v
../../../rtl/verilog/pci_rst_int.v
../../../rtl/verilog/pci_sync_module.v
../../../rtl/verilog/pci_wb_tpram.v
../../../rtl/verilog/pci_wbs_wbb3_2_wbb2.v
../../../bench/verilog/wb_master32.v
../../../bench/verilog/wb_master_behavioral.v
../../../bench/verilog/system.v
../../../bench/verilog/pci_blue_arbiter.v
../../../bench/verilog/pci_bus_monitor.v
../../../bench/verilog/pci_behaviorial_device.v
../../../bench/verilog/pci_behaviorial_master.v
../../../bench/verilog/pci_behaviorial_target.v
../../../bench/verilog/wb_slave_behavioral.v
../../../bench/verilog/wb_bus_mon.v
../../../bench/verilog/pci_unsupported_commands_master.v
../../../bench/verilog/pci_behavioral_pci2pci_bridge.v