Subversion Repositories pci

ncsim: v03.30.(p001): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc.
ncsim: v03.30.(p001): Started on Jul 08, 2001 at 11:29:06
ncsim
    -f ./ncsim.args
        -cdslib ../bin/cds.lib
        -hdlvar ../bin/hdl.var
        -logfile ../log/ncsim.log
        -messages
        -input ../bin/ncsim_waves.rc
        worklib.bridge32:fun

Loading snapshot worklib.bridge32:fun .................... Done
ncsim> source /usr/cad/ncsim/tools/inca/files/ncsimrc
ncsim> set dump_level all
all
ncsim> 
ncsim> database -open waves -shm -into ../out/waves.shm
Created SHM database waves
ncsim> probe -create -database waves SYSTEM -shm -all -depth $dump_level 
Created probe 1
ncsim> 
ncsim> run
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at             69795000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at             70785000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at             92895000
 test target 1 - Starting Config Write, at             93735000
 test target 1 - Starting Config Write, at             94575000
 test target 2 - Starting Config Write, at             95415000
 test target 2 - Starting Config Write, at             96255000
 test target 2 - Starting Config Write, at             97095000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at             98685000
 test target 1 - Starting Memory Read, at             98985000
 test target 1 - Starting Memory Write, at             99585000
 test target 1 - Starting Memory Read, at             99885000
 test target 1 - Starting Memory Write, at            100695000
 test target 1 - Starting Memory Read, at            102015000
 test target 1 - Starting Memory Read, at            102675000
 test target 1 - Starting Memory Read, at            103365000
 test target 1 - Starting Memory Read, at            104025000
 test target 1 - Starting Memory Read, at            104835000
 test target 1 - Starting Memory Read, at            106005000
 test target 1 - Starting Memory Read, at            106755000
 test target 1 - Starting Memory Read, at            108015000
 test target 1 - Starting Memory Read, at            108735000
 test target 1 - Starting Memory Read, at            111645000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at            116955000
 test target 1 - Starting Memory Read, at            117255000
 test target 1 - Starting Memory Write, at            117855000
 test target 1 - Starting Memory Read, at            118155000
 test target 1 - Starting Memory Write, at            118995000
 test target 1 - Starting Memory Read, at            120315000
 test target 1 - Starting Memory Read, at            120975000
 test target 1 - Starting Memory Read, at            121665000
 test target 1 - Starting Memory Read, at            122325000
 test target 1 - Starting Memory Read, at            123135000
 test target 1 - Starting Memory Read, at            124305000
 test target 1 - Starting Memory Read, at            125055000
 test target 1 - Starting Memory Read, at            126315000
 test target 1 - Starting Memory Read, at            127035000
 test target 1 - Starting Memory Read, at            129945000
 test target 1 - Starting Memory Write, at            135255000
 test target 1 - Starting Memory Read, at            135555000
 test target 1 - Starting Memory Write, at            136155000
 test target 1 - Starting Memory Read, at            136455000
 test target 1 - Starting Memory Write, at            137295000
 test target 1 - Starting Memory Read, at            138615000
 test target 1 - Starting Memory Read, at            139275000
 test target 1 - Starting Memory Read, at            139965000
 test target 1 - Starting Memory Read, at            140625000
 test target 1 - Starting Memory Read, at            141435000
 test target 1 - Starting Memory Read, at            142605000
 test target 1 - Starting Memory Read, at            143355000
 test target 1 - Starting Memory Read, at            144615000
 test target 1 - Starting Memory Read, at            145335000
 test target 1 - Starting Memory Read, at            148245000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at            157275000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at            162465000
 test target 1 - Starting Memory Write, at            163275000
 test target 1 - Starting Memory Read, at            163875000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at            165165000
 test target 1 - Starting Config Write, at            166875000
 test target 1 - Starting Memory Read, at            167595000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at            168765000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at            170655000
 test target 1 - Starting Memory Write, at            171705000
 test target 1 - Starting Memory Write, at            172035000
 test target 1 - Starting Memory Read, at            172335000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at            174255000
 test target 1 - Starting Memory Write, at            176715000
 test target 1 - Starting Memory Write, at            177195000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at            180615000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at            182235000
 test target 1 - Starting Memory Read, at            183495000
 test target 1 - Starting Memory Read, at            184665000
 test target 1 - Starting Memory Read, at            186255000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at            191175000
 test target 2 - Starting Config Write, at            192015000
 test target 1 - Starting Memory Write, at            192705000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at            192915000
 test target 1 - Starting Memory Write, at            193755000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at            193965000
 test target 1 - Starting Memory Write, at            194805000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at            196035000
 test target 1 - Starting Memory Read, at            197895000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at            198105000
 test target 1 - Starting Memory Read, at            199815000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at            201225000
 test master 2 - Starting Memory Write, at            201225000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at            201285000
*** monitor - CBE Bus Changed when TRDY Desserted, at            202035000
*** monitor - CBE Bus Changed when TRDY Desserted, at            202065000
*** monitor - CBE Bus Changed when TRDY Desserted, at            202365000
*** monitor - CBE Bus Changed when TRDY Desserted, at            202395000
*** monitor - CBE Bus Changed when TRDY Desserted, at            203145000
*** monitor - CBE Bus Changed when TRDY Desserted, at            203175000
 test target 1 - Starting Memory Write, at            204705000
 test master 2 - Starting Memory Write, at            204705000
*** monitor - CBE Bus Changed when TRDY Desserted, at            206205000
*** monitor - CBE Bus Changed when TRDY Desserted, at            206235000
*** monitor - CBE Bus Changed when TRDY Desserted, at            207645000
*** monitor - CBE Bus Changed when TRDY Desserted, at            207675000
*** monitor - CBE Bus Changed when TRDY Desserted, at            209085000
*** monitor - CBE Bus Changed when TRDY Desserted, at            209115000
 test target 1 - Starting Memory Write, at            210825000
 test master 2 - Starting Memory Write, at            210825000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at            210885000
*** monitor - CBE Bus Changed when TRDY Desserted, at            212295000
*** monitor - CBE Bus Changed when TRDY Desserted, at            212325000
*** monitor - CBE Bus Changed when TRDY Desserted, at            212625000
*** monitor - CBE Bus Changed when TRDY Desserted, at            212655000
*** monitor - CBE Bus Changed when TRDY Desserted, at            213405000
*** monitor - CBE Bus Changed when TRDY Desserted, at            213435000
 test target 1 - Starting Memory Write, at            214485000
 test master 2 - Starting Memory Write, at            214485000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at            216855000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at            218265000
 test master 1 - Starting Memory Read, at            218685000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at            218895000
 test target 1 - Starting Config Write, at            220905000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at            222795000
 test target 1 - Starting Memory Write, at            223035000
 test target 1 - Starting Memory Write, at            223275000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at            223755000
 test target 1 - Starting Memory Write, at            224025000
 test target 1 - Starting Memory Write, at            224295000
 test target 1 - Starting Memory Write, at            224775000
 test target 1 - Starting Memory Write, at            225165000
 test target 1 - Starting Memory Write, at            225645000
 test target 1 - Starting Memory Write, at            226335000
 test target 1 - Starting Memory Write, at            226605000
 test target 1 - Starting Memory Write, at            227295000
 test target 1 - Starting Memory Write, at            227715000
 test target 1 - Starting Memory Write, at            228255000
 test target 1 - Starting Memory Write, at            231435000
 test target 1 - Starting Memory Write, at            231705000
 test target 1 - Starting Memory Write, at            231975000
 test target 1 - Starting Memory Write, at            232395000
 test target 1 - Starting Memory Write, at            232815000
 test target 1 - Starting Memory Read, at            241665000
 test target 1 - Starting Memory Read, at            242925000
 test target 1 - Starting Memory Read, at            244125000
 test target 1 - Starting Memory Read, at            245325000
 test target 1 - Starting Memory Read, at            246525000
 test target 1 - Starting Memory Read, at            247725000
 test target 1 - Starting Memory Read, at            248925000
 test target 1 - Starting Memory Read, at            250125000
 test target 1 - Starting Memory Read, at            251325000
 test target 1 - Starting Memory Read, at            252525000
 test target 1 - Starting Memory Read, at            253725000
 test target 1 - Starting Memory Read, at            254925000
 test target 1 - Starting Memory Read, at            256125000
 test target 1 - Starting Memory Read, at            257325000
 test target 1 - Starting Memory Read, at            258525000
 test target 1 - Starting Memory Read, at            259725000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at            260865000
 test target 1 - Starting Memory Read, at            261105000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at            262335000
 test target 1 - Starting Memory Read, at            264885000
 test target 1 - Starting Memory Read, at            265545000
 test target 1 - Starting Memory Read, at            266265000
 test target 1 - Starting Memory Read, at            267075000
 test target 1 - Starting Memory Read, at            267855000
 test target 1 - Starting Memory Read, at            269115000
 test target 1 - Starting Memory Read, at            270375000
 test target 1 - Starting Memory Read, at            271095000
 test target 1 - Starting Memory Read, at            274425000
 test target 1 - Starting Memory Read, at            277515000
 test target 1 - Starting Memory Read, at            278295000
 test target 1 - Starting Memory Read, at            279075000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at            280095000
 test master 1 - Starting Memory Write, at            280455000
 test target 1 - Starting Memory Write, at            280455000
 test target 1 - Starting Memory Write, at            280695000
 test target 1 - Starting Memory Read, at            281445000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at            284445000
 test master 1 - Starting Memory Write, at            284805000
 test target 1 - Starting Memory Write, at            284805000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at            289185000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at            290295000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at            312525000
 test target 1 - Starting Config Write, at            313365000
 test target 1 - Starting Config Write, at            314205000
 test target 2 - Starting Config Write, at            315045000
 test target 2 - Starting Config Write, at            315885000
 test target 2 - Starting Config Write, at            316725000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at            318315000
 test target 1 - Starting Memory Read, at            318645000
 test target 1 - Starting Memory Write, at            319335000
 test target 1 - Starting Memory Read, at            319665000
 test target 1 - Starting Memory Write, at            320535000
 test target 1 - Starting Memory Read, at            321915000
 test target 1 - Starting Memory Read, at            322545000
 test target 1 - Starting Memory Read, at            323235000
 test target 1 - Starting Memory Read, at            323925000
 test target 1 - Starting Memory Read, at            324735000
 test target 1 - Starting Memory Read, at            325995000
 test target 1 - Starting Memory Read, at            326835000
 test target 1 - Starting Memory Read, at            328095000
 test target 1 - Starting Memory Read, at            328935000
 test target 1 - Starting Memory Read, at            331845000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at            337125000
 test target 1 - Starting Memory Read, at            337455000
 test target 1 - Starting Memory Write, at            338115000
 test target 1 - Starting Memory Read, at            338445000
 test target 1 - Starting Memory Write, at            339345000
 test target 1 - Starting Memory Read, at            340695000
 test target 1 - Starting Memory Read, at            341355000
 test target 1 - Starting Memory Read, at            342045000
 test target 1 - Starting Memory Read, at            342705000
 test target 1 - Starting Memory Read, at            343515000
 test target 1 - Starting Memory Read, at            344805000
 test target 1 - Starting Memory Read, at            345615000
 test target 1 - Starting Memory Read, at            346905000
 test target 1 - Starting Memory Read, at            347715000
 test target 1 - Starting Memory Read, at            350625000
 test target 1 - Starting Memory Write, at            355935000
 test target 1 - Starting Memory Read, at            356265000
 test target 1 - Starting Memory Write, at            356955000
 test target 1 - Starting Memory Read, at            357285000
 test target 1 - Starting Memory Write, at            358155000
 test target 1 - Starting Memory Read, at            359535000
 test target 1 - Starting Memory Read, at            360165000
 test target 1 - Starting Memory Read, at            360855000
 test target 1 - Starting Memory Read, at            361545000
 test target 1 - Starting Memory Read, at            362355000
 test target 1 - Starting Memory Read, at            363615000
 test target 1 - Starting Memory Read, at            364455000
 test target 1 - Starting Memory Read, at            365715000
 test target 1 - Starting Memory Read, at            366555000
 test target 1 - Starting Memory Read, at            369465000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at            378465000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at            383685000
 test target 1 - Starting Memory Write, at            384495000
 test target 1 - Starting Memory Read, at            385125000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at            386505000
 test target 1 - Starting Config Write, at            388215000
 test target 1 - Starting Memory Read, at            388935000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at            390195000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at            392085000
 test target 1 - Starting Memory Write, at            393135000
 test target 1 - Starting Memory Write, at            393495000
 test target 1 - Starting Memory Read, at            393825000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at            395715000
 test target 1 - Starting Memory Write, at            398205000
 test target 1 - Starting Memory Write, at            398715000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at            402195000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at            403815000
 test target 1 - Starting Memory Read, at            405075000
 test target 1 - Starting Memory Read, at            406365000
 test target 1 - Starting Memory Read, at            408015000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at            413025000
 test target 2 - Starting Config Write, at            413865000
 test target 1 - Starting Memory Write, at            414555000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at            414795000
 test target 1 - Starting Memory Write, at            415635000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at            415875000
 test target 1 - Starting Memory Write, at            416715000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at            417975000
 test target 1 - Starting Memory Read, at            419835000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at            420075000
 test target 1 - Starting Memory Read, at            421755000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at            423165000
 test master 2 - Starting Memory Write, at            423165000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at            423225000
*** monitor - CBE Bus Changed when TRDY Desserted, at            424005000
*** monitor - CBE Bus Changed when TRDY Desserted, at            424035000
*** monitor - CBE Bus Changed when TRDY Desserted, at            424335000
*** monitor - CBE Bus Changed when TRDY Desserted, at            424365000
*** monitor - CBE Bus Changed when TRDY Desserted, at            425115000
*** monitor - CBE Bus Changed when TRDY Desserted, at            425145000
 test target 1 - Starting Memory Write, at            426675000
 test master 2 - Starting Memory Write, at            426675000
*** monitor - CBE Bus Changed when TRDY Desserted, at            428205000
*** monitor - CBE Bus Changed when TRDY Desserted, at            428235000
*** monitor - CBE Bus Changed when TRDY Desserted, at            429645000
*** monitor - CBE Bus Changed when TRDY Desserted, at            429675000
*** monitor - CBE Bus Changed when TRDY Desserted, at            431085000
*** monitor - CBE Bus Changed when TRDY Desserted, at            431115000
 test target 1 - Starting Memory Write, at            432825000
 test master 2 - Starting Memory Write, at            432825000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at            432885000
*** monitor - CBE Bus Changed when TRDY Desserted, at            434325000
*** monitor - CBE Bus Changed when TRDY Desserted, at            434355000
*** monitor - CBE Bus Changed when TRDY Desserted, at            434655000
*** monitor - CBE Bus Changed when TRDY Desserted, at            434685000
*** monitor - CBE Bus Changed when TRDY Desserted, at            435435000
*** monitor - CBE Bus Changed when TRDY Desserted, at            435465000
 test target 1 - Starting Memory Write, at            436515000
 test master 2 - Starting Memory Write, at            436515000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at            438915000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at            440325000
 test master 1 - Starting Memory Read, at            440745000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at            440955000
 test target 1 - Starting Config Write, at            442965000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at            444855000
 test target 1 - Starting Memory Write, at            445125000
 test target 1 - Starting Memory Write, at            445395000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at            445905000
 test target 1 - Starting Memory Write, at            446205000
 test target 1 - Starting Memory Write, at            446505000
 test target 1 - Starting Memory Write, at            447015000
 test target 1 - Starting Memory Write, at            447435000
 test target 1 - Starting Memory Write, at            447945000
 test target 1 - Starting Memory Write, at            448635000
 test target 1 - Starting Memory Write, at            448935000
 test target 1 - Starting Memory Write, at            449655000
 test target 1 - Starting Memory Write, at            450105000
 test target 1 - Starting Memory Write, at            450675000
 test target 1 - Starting Memory Write, at            453885000
 test target 1 - Starting Memory Write, at            454185000
 test target 1 - Starting Memory Write, at            454485000
 test target 1 - Starting Memory Write, at            454935000
 test target 1 - Starting Memory Write, at            455385000
 test target 1 - Starting Memory Read, at            464265000
 test target 1 - Starting Memory Read, at            465555000
 test target 1 - Starting Memory Read, at            466755000
 test target 1 - Starting Memory Read, at            467955000
 test target 1 - Starting Memory Read, at            469155000
 test target 1 - Starting Memory Read, at            470355000
 test target 1 - Starting Memory Read, at            471555000
 test target 1 - Starting Memory Read, at            472755000
 test target 1 - Starting Memory Read, at            473955000
 test target 1 - Starting Memory Read, at            475155000
 test target 1 - Starting Memory Read, at            476355000
 test target 1 - Starting Memory Read, at            477555000
 test target 1 - Starting Memory Read, at            478755000
 test target 1 - Starting Memory Read, at            479955000
 test target 1 - Starting Memory Read, at            481155000
 test target 1 - Starting Memory Read, at            482355000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at            483525000
 test target 1 - Starting Memory Read, at            483795000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at            485055000
 test target 1 - Starting Memory Read, at            487635000
 test target 1 - Starting Memory Read, at            488265000
 test target 1 - Starting Memory Read, at            489015000
 test target 1 - Starting Memory Read, at            489915000
 test target 1 - Starting Memory Read, at            490785000
 test target 1 - Starting Memory Read, at            492015000
 test target 1 - Starting Memory Read, at            493305000
 test target 1 - Starting Memory Read, at            494115000
 test target 1 - Starting Memory Read, at            497445000
 test target 1 - Starting Memory Read, at            500535000
 test target 1 - Starting Memory Read, at            501315000
 test target 1 - Starting Memory Read, at            502095000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at            503115000
 test master 1 - Starting Memory Write, at            503505000
 test target 1 - Starting Memory Write, at            503505000
 test target 1 - Starting Memory Write, at            503775000
 test target 1 - Starting Memory Read, at            504555000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at            507585000
 test master 1 - Starting Memory Write, at            507975000
 test target 1 - Starting Memory Write, at            507975000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at            512445000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at            513555000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at            535785000
 test target 1 - Starting Config Write, at            536625000
 test target 1 - Starting Config Write, at            537465000
 test target 2 - Starting Config Write, at            538305000
 test target 2 - Starting Config Write, at            539145000
 test target 2 - Starting Config Write, at            539985000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at            541575000
 test target 1 - Starting Memory Read, at            541935000
 test target 1 - Starting Memory Write, at            542595000
 test target 1 - Starting Memory Read, at            542955000
 test target 1 - Starting Memory Write, at            543795000
 test target 1 - Starting Memory Read, at            545175000
 test target 1 - Starting Memory Read, at            545835000
 test target 1 - Starting Memory Read, at            546525000
 test target 1 - Starting Memory Read, at            547185000
 test target 1 - Starting Memory Read, at            547995000
 test target 1 - Starting Memory Read, at            549285000
 test target 1 - Starting Memory Read, at            550095000
 test target 1 - Starting Memory Read, at            551385000
 test target 1 - Starting Memory Read, at            552195000
 test target 1 - Starting Memory Read, at            555105000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at            560415000
 test target 1 - Starting Memory Read, at            560775000
 test target 1 - Starting Memory Write, at            561435000
 test target 1 - Starting Memory Read, at            561795000
 test target 1 - Starting Memory Write, at            562635000
 test target 1 - Starting Memory Read, at            564015000
 test target 1 - Starting Memory Read, at            564675000
 test target 1 - Starting Memory Read, at            565365000
 test target 1 - Starting Memory Read, at            566025000
 test target 1 - Starting Memory Read, at            566835000
 test target 1 - Starting Memory Read, at            568125000
 test target 1 - Starting Memory Read, at            568935000
 test target 1 - Starting Memory Read, at            570225000
 test target 1 - Starting Memory Read, at            571035000
 test target 1 - Starting Memory Read, at            573945000
 test target 1 - Starting Memory Write, at            579255000
 test target 1 - Starting Memory Read, at            579615000
 test target 1 - Starting Memory Write, at            580275000
 test target 1 - Starting Memory Read, at            580635000
 test target 1 - Starting Memory Write, at            581475000
 test target 1 - Starting Memory Read, at            582855000
 test target 1 - Starting Memory Read, at            583515000
 test target 1 - Starting Memory Read, at            584205000
 test target 1 - Starting Memory Read, at            584865000
 test target 1 - Starting Memory Read, at            585675000
 test target 1 - Starting Memory Read, at            586965000
 test target 1 - Starting Memory Read, at            587775000
 test target 1 - Starting Memory Read, at            589065000
 test target 1 - Starting Memory Read, at            589875000
 test target 1 - Starting Memory Read, at            592785000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at            601815000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at            607005000
 test target 1 - Starting Memory Write, at            607815000
 test target 1 - Starting Memory Read, at            608475000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at            609825000
 test target 1 - Starting Config Write, at            611535000
 test target 1 - Starting Memory Read, at            612255000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at            613515000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at            615405000
 test target 1 - Starting Memory Write, at            616455000
 test target 1 - Starting Memory Write, at            616845000
 test target 1 - Starting Memory Read, at            617205000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at            619095000
 test target 1 - Starting Memory Write, at            621615000
 test target 1 - Starting Memory Write, at            622155000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at            625635000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at            627375000
 test target 1 - Starting Memory Read, at            628635000
 test target 1 - Starting Memory Read, at            629925000
 test target 1 - Starting Memory Read, at            631575000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at            636585000
 test target 2 - Starting Config Write, at            637425000
 test target 1 - Starting Memory Write, at            638115000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at            638385000
 test target 1 - Starting Memory Write, at            639225000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at            639495000
 test target 1 - Starting Memory Write, at            640335000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at            641595000
 test target 1 - Starting Memory Read, at            643515000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at            643785000
 test target 1 - Starting Memory Read, at            645495000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at            646935000
 test master 2 - Starting Memory Write, at            646935000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at            646995000
*** monitor - CBE Bus Changed when TRDY Desserted, at            647805000
*** monitor - CBE Bus Changed when TRDY Desserted, at            647835000
*** monitor - CBE Bus Changed when TRDY Desserted, at            648135000
*** monitor - CBE Bus Changed when TRDY Desserted, at            648165000
*** monitor - CBE Bus Changed when TRDY Desserted, at            648915000
*** monitor - CBE Bus Changed when TRDY Desserted, at            648945000
 test target 1 - Starting Memory Write, at            650475000
 test master 2 - Starting Memory Write, at            650475000
*** monitor - CBE Bus Changed when TRDY Desserted, at            652035000
*** monitor - CBE Bus Changed when TRDY Desserted, at            652065000
*** monitor - CBE Bus Changed when TRDY Desserted, at            653475000
*** monitor - CBE Bus Changed when TRDY Desserted, at            653505000
*** monitor - CBE Bus Changed when TRDY Desserted, at            654915000
*** monitor - CBE Bus Changed when TRDY Desserted, at            654945000
 test target 1 - Starting Memory Write, at            656655000
 test master 2 - Starting Memory Write, at            656655000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at            656715000
*** monitor - CBE Bus Changed when TRDY Desserted, at            658185000
*** monitor - CBE Bus Changed when TRDY Desserted, at            658215000
*** monitor - CBE Bus Changed when TRDY Desserted, at            658515000
*** monitor - CBE Bus Changed when TRDY Desserted, at            658545000
*** monitor - CBE Bus Changed when TRDY Desserted, at            659295000
*** monitor - CBE Bus Changed when TRDY Desserted, at            659325000
 test target 1 - Starting Memory Write, at            660375000
 test master 2 - Starting Memory Write, at            660375000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at            662805000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at            664215000
 test master 1 - Starting Memory Read, at            664605000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at            664815000
 test target 1 - Starting Config Write, at            666825000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at            668835000
 test target 1 - Starting Memory Write, at            669135000
 test target 1 - Starting Memory Write, at            669435000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at            669975000
 test target 1 - Starting Memory Write, at            670305000
 test target 1 - Starting Memory Write, at            670635000
 test target 1 - Starting Memory Write, at            671175000
 test target 1 - Starting Memory Write, at            671625000
 test target 1 - Starting Memory Write, at            672165000
 test target 1 - Starting Memory Write, at            672915000
 test target 1 - Starting Memory Write, at            673245000
 test target 1 - Starting Memory Write, at            673995000
 test target 1 - Starting Memory Write, at            674475000
 test target 1 - Starting Memory Write, at            675075000
 test target 1 - Starting Memory Write, at            678315000
 test target 1 - Starting Memory Write, at            678645000
 test target 1 - Starting Memory Write, at            678975000
 test target 1 - Starting Memory Write, at            679455000
 test target 1 - Starting Memory Write, at            679935000
 test target 1 - Starting Memory Read, at            688845000
 test target 1 - Starting Memory Read, at            690105000
 test target 1 - Starting Memory Read, at            691395000
 test target 1 - Starting Memory Read, at            692685000
 test target 1 - Starting Memory Read, at            694005000
 test target 1 - Starting Memory Read, at            695295000
 test target 1 - Starting Memory Read, at            696585000
 test target 1 - Starting Memory Read, at            697905000
 test target 1 - Starting Memory Read, at            699195000
 test target 1 - Starting Memory Read, at            700485000
 test target 1 - Starting Memory Read, at            701805000
 test target 1 - Starting Memory Read, at            703095000
 test target 1 - Starting Memory Read, at            704385000
 test target 1 - Starting Memory Read, at            705705000
 test target 1 - Starting Memory Read, at            706995000
 test target 1 - Starting Memory Read, at            708285000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at            709545000
 test target 1 - Starting Memory Read, at            709845000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at            711105000
 test target 1 - Starting Memory Read, at            713715000
 test target 1 - Starting Memory Read, at            714405000
 test target 1 - Starting Memory Read, at            715155000
 test target 1 - Starting Memory Read, at            716055000
 test target 1 - Starting Memory Read, at            716925000
 test target 1 - Starting Memory Read, at            718275000
 test target 1 - Starting Memory Read, at            719565000
 test target 1 - Starting Memory Read, at            720375000
 test target 1 - Starting Memory Read, at            723705000
 test target 1 - Starting Memory Read, at            726795000
 test target 1 - Starting Memory Read, at            727635000
 test target 1 - Starting Memory Read, at            728415000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at            729435000
 test master 1 - Starting Memory Write, at            729855000
 test target 1 - Starting Memory Write, at            729855000
 test target 1 - Starting Memory Write, at            730155000
 test target 1 - Starting Memory Read, at            730965000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at            734025000
 test master 1 - Starting Memory Write, at            734445000
 test target 1 - Starting Memory Write, at            734445000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at            738885000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at            739995000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at            762225000
 test target 1 - Starting Config Write, at            763065000
 test target 1 - Starting Config Write, at            763905000
 test target 2 - Starting Config Write, at            764745000
 test target 2 - Starting Config Write, at            765585000
 test target 2 - Starting Config Write, at            766425000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at            768015000
 test target 1 - Starting Memory Read, at            768405000
 test target 1 - Starting Memory Write, at            769125000
 test target 1 - Starting Memory Read, at            769515000
 test target 1 - Starting Memory Write, at            770445000
 test target 1 - Starting Memory Read, at            771855000
 test target 1 - Starting Memory Read, at            772605000
 test target 1 - Starting Memory Read, at            773295000
 test target 1 - Starting Memory Read, at            774075000
 test target 1 - Starting Memory Read, at            774975000
 test target 1 - Starting Memory Read, at            776265000
 test target 1 - Starting Memory Read, at            777075000
 test target 1 - Starting Memory Read, at            778365000
 test target 1 - Starting Memory Read, at            779175000
 test target 1 - Starting Memory Read, at            782205000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at            787605000
 test target 1 - Starting Memory Read, at            787995000
 test target 1 - Starting Memory Write, at            788715000
 test target 1 - Starting Memory Read, at            789105000
 test target 1 - Starting Memory Write, at            790035000
 test target 1 - Starting Memory Read, at            791475000
 test target 1 - Starting Memory Read, at            792225000
 test target 1 - Starting Memory Read, at            793005000
 test target 1 - Starting Memory Read, at            793785000
 test target 1 - Starting Memory Read, at            794655000
 test target 1 - Starting Memory Read, at            795945000
 test target 1 - Starting Memory Read, at            796755000
 test target 1 - Starting Memory Read, at            798045000
 test target 1 - Starting Memory Read, at            798855000
 test target 1 - Starting Memory Read, at            801885000
 test target 1 - Starting Memory Write, at            807285000
 test target 1 - Starting Memory Read, at            807675000
 test target 1 - Starting Memory Write, at            808395000
 test target 1 - Starting Memory Read, at            808785000
 test target 1 - Starting Memory Write, at            809715000
 test target 1 - Starting Memory Read, at            811155000
 test target 1 - Starting Memory Read, at            811905000
 test target 1 - Starting Memory Read, at            812685000
 test target 1 - Starting Memory Read, at            813465000
 test target 1 - Starting Memory Read, at            814335000
 test target 1 - Starting Memory Read, at            815625000
 test target 1 - Starting Memory Read, at            816435000
 test target 1 - Starting Memory Read, at            817725000
 test target 1 - Starting Memory Read, at            818535000
 test target 1 - Starting Memory Read, at            821565000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at            830685000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at            835905000
 test target 1 - Starting Memory Write, at            836715000
 test target 1 - Starting Memory Read, at            837405000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at            838815000
 test target 1 - Starting Config Write, at            840525000
 test target 1 - Starting Memory Read, at            841245000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at            842535000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at            844425000
 test target 1 - Starting Memory Write, at            845475000
 test target 1 - Starting Memory Write, at            845895000
 test target 1 - Starting Memory Read, at            846285000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at            848235000
 test target 1 - Starting Memory Write, at            850785000
 test target 1 - Starting Memory Write, at            851355000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at            854895000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at            856635000
 test target 1 - Starting Memory Read, at            857895000
 test target 1 - Starting Memory Read, at            859185000
 test target 1 - Starting Memory Read, at            860835000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at            865845000
 test target 2 - Starting Config Write, at            866685000
 test target 1 - Starting Memory Write, at            867375000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at            867675000
 test target 1 - Starting Memory Write, at            868515000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at            868815000
 test target 1 - Starting Memory Write, at            869655000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at            870975000
 test target 1 - Starting Memory Read, at            872955000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at            873255000
 test target 1 - Starting Memory Read, at            874935000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at            876465000
 test master 2 - Starting Memory Write, at            876465000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at            876525000
*** monitor - CBE Bus Changed when TRDY Desserted, at            877365000
*** monitor - CBE Bus Changed when TRDY Desserted, at            877395000
*** monitor - CBE Bus Changed when TRDY Desserted, at            877695000
*** monitor - CBE Bus Changed when TRDY Desserted, at            877725000
*** monitor - CBE Bus Changed when TRDY Desserted, at            878475000
*** monitor - CBE Bus Changed when TRDY Desserted, at            878505000
 test target 1 - Starting Memory Write, at            880035000
 test master 2 - Starting Memory Write, at            880035000
*** monitor - CBE Bus Changed when TRDY Desserted, at            881625000
*** monitor - CBE Bus Changed when TRDY Desserted, at            881655000
*** monitor - CBE Bus Changed when TRDY Desserted, at            883065000
*** monitor - CBE Bus Changed when TRDY Desserted, at            883095000
*** monitor - CBE Bus Changed when TRDY Desserted, at            884505000
*** monitor - CBE Bus Changed when TRDY Desserted, at            884535000
 test target 1 - Starting Memory Write, at            886245000
 test master 2 - Starting Memory Write, at            886245000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at            886305000
*** monitor - CBE Bus Changed when TRDY Desserted, at            887805000
*** monitor - CBE Bus Changed when TRDY Desserted, at            887835000
*** monitor - CBE Bus Changed when TRDY Desserted, at            888135000
*** monitor - CBE Bus Changed when TRDY Desserted, at            888165000
*** monitor - CBE Bus Changed when TRDY Desserted, at            888915000
*** monitor - CBE Bus Changed when TRDY Desserted, at            888945000
 test target 1 - Starting Memory Write, at            889995000
 test master 2 - Starting Memory Write, at            889995000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at            892455000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at            893865000
 test master 1 - Starting Memory Read, at            894285000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at            894495000
 test target 1 - Starting Config Write, at            896505000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at            898515000
 test target 1 - Starting Memory Write, at            898845000
 test target 1 - Starting Memory Write, at            899175000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at            899745000
 test target 1 - Starting Memory Write, at            900105000
 test target 1 - Starting Memory Write, at            900465000
 test target 1 - Starting Memory Write, at            901035000
 test target 1 - Starting Memory Write, at            901515000
 test target 1 - Starting Memory Write, at            902085000
 test target 1 - Starting Memory Write, at            902835000
 test target 1 - Starting Memory Write, at            903195000
 test target 1 - Starting Memory Write, at            903975000
 test target 1 - Starting Memory Write, at            904485000
 test target 1 - Starting Memory Write, at            905115000
 test target 1 - Starting Memory Write, at            908385000
 test target 1 - Starting Memory Write, at            908745000
 test target 1 - Starting Memory Write, at            909105000
 test target 1 - Starting Memory Write, at            909615000
 test target 1 - Starting Memory Write, at            910125000
 test target 1 - Starting Memory Read, at            919065000
 test target 1 - Starting Memory Read, at            920355000
 test target 1 - Starting Memory Read, at            921645000
 test target 1 - Starting Memory Read, at            922965000
 test target 1 - Starting Memory Read, at            924255000
 test target 1 - Starting Memory Read, at            925545000
 test target 1 - Starting Memory Read, at            926865000
 test target 1 - Starting Memory Read, at            928155000
 test target 1 - Starting Memory Read, at            929445000
 test target 1 - Starting Memory Read, at            930765000
 test target 1 - Starting Memory Read, at            932055000
 test target 1 - Starting Memory Read, at            933345000
 test target 1 - Starting Memory Read, at            934665000
 test target 1 - Starting Memory Read, at            935955000
 test target 1 - Starting Memory Read, at            937245000
 test target 1 - Starting Memory Read, at            938565000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at            939825000
 test target 1 - Starting Memory Read, at            940155000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at            941475000
 test target 1 - Starting Memory Read, at            944115000
 test target 1 - Starting Memory Read, at            944865000
 test target 1 - Starting Memory Read, at            945615000
 test target 1 - Starting Memory Read, at            946515000
 test target 1 - Starting Memory Read, at            947385000
 test target 1 - Starting Memory Read, at            948735000
 test target 1 - Starting Memory Read, at            950025000
 test target 1 - Starting Memory Read, at            950835000
 test target 1 - Starting Memory Read, at            954255000
 test target 1 - Starting Memory Read, at            957435000
 test target 1 - Starting Memory Read, at            958335000
 test target 1 - Starting Memory Read, at            959175000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at            960315000
 test master 1 - Starting Memory Write, at            960765000
 test target 1 - Starting Memory Write, at            960765000
 test target 1 - Starting Memory Write, at            961095000
 test target 1 - Starting Memory Read, at            961935000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at            965055000
 test master 1 - Starting Memory Write, at            965505000
 test target 1 - Starting Memory Write, at            965505000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at            969795000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at            970095000
 test master 2 - Starting Memory Read, at            970335000
 test master 2 - Starting Memory Read, at            970575000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at            972105000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at            972555000
 test master 2 - Starting Memory Read, at            972795000
 test master 2 - Starting Memory Read, at            973035000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at            974265000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at            974895000
 test master 2 - Starting Memory Read Line Multiple, at            975135000
 test master 2 - Starting Memory Read Line Multiple, at            975405000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at            977385000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at            988035000
 test master 2 - Starting Memory Read Line Multiple, at            988275000
 test master 2 - Starting Memory Read Line Multiple, at            988545000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at            989685000
 test master 2 - Starting Memory Read Line Multiple, at            989925000
 test master 2 - Starting Memory Read Line Multiple, at            990225000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at            991365000
 test master 2 - Starting Memory Read Line Multiple, at            991605000
 test master 2 - Starting Memory Read Line Multiple, at            991905000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at            993045000
 test master 2 - Starting Memory Read Line Multiple, at            993285000
 test master 2 - Starting Memory Read Line Multiple, at            993585000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at            994725000
 test master 2 - Starting Memory Read Line Multiple, at            994965000
 test master 2 - Starting Memory Read Line Multiple, at            995265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at            996405000
 test master 2 - Starting Memory Read Line Multiple, at            996645000
 test master 2 - Starting Memory Read Line Multiple, at            996945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at            998085000
 test master 2 - Starting Memory Read Line Multiple, at            998325000
 test master 2 - Starting Memory Read Line Multiple, at            998625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at            999765000
 test master 2 - Starting Memory Read Line Multiple, at           1000005000
 test master 2 - Starting Memory Read Line Multiple, at           1000305000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           1001445000
 test master 2 - Starting Memory Read Line, at           1001685000
 test master 2 - Starting Memory Read Line, at           1001925000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           1002615000
 test master 2 - Starting Memory Read Line, at           1002855000
 test master 2 - Starting Memory Read Line, at           1003095000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1004145000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1005435000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1007835000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1009455000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           1013715000
 test master 2 - Starting Memory Write, at           1014015000
 test master 2 - Starting Memory Write, at           1014315000
 test master 2 - Starting Memory Write, at           1014615000
 test master 2 - Starting Memory Write, at           1014915000
 test master 1 - Starting Memory Read, at           1015335000
 test master 1 - Starting Memory Read, at           1015695000
 test master 1 - Starting Memory Read, at           1016235000
 test master 1 - Starting Memory Read, at           1016595000
 test master 1 - Starting Memory Read, at           1017135000
 test master 1 - Starting Memory Read, at           1017495000
 test master 2 - Starting Memory Write, at           1018635000
 test master 2 - Starting Memory Write, at           1018935000
 test master 2 - Starting Memory Write, at           1019235000
 test master 2 - Starting Memory Write, at           1019535000
 test master 2 - Starting Memory Write, at           1019835000
 test master 1 - Starting Memory Read, at           1020255000
 test master 1 - Starting Memory Read, at           1020615000
 test master 1 - Starting Memory Read, at           1021155000
 test master 1 - Starting Memory Read, at           1021515000
 test master 1 - Starting Memory Read, at           1022055000
 test master 1 - Starting Memory Read, at           1022415000
 test master 2 - Starting Memory Write, at           1023915000
 test master 2 - Starting Memory Write, at           1024905000
 test master 2 - Starting Memory Write, at           1025925000
 test master 2 - Starting Memory Write, at           1026945000
 test master 2 - Starting Memory Write, at           1028805000
 test master 2 - Starting Memory Write, at           1029825000
 test master 2 - Starting Memory Write, at           1030845000
 test master 2 - Starting Memory Write, at           1031865000
 test master 2 - Starting Memory Write, at           1033725000
 test master 2 - Starting Memory Write, at           1035495000
 test master 2 - Starting Memory Write, at           1037235000
 test master 2 - Starting Memory Write, at           1038975000
 test master 2 - Starting Memory Write, at           1041555000
 test master 2 - Starting Memory Write, at           1043475000
 test master 2 - Starting Memory Write, at           1045395000
 test master 2 - Starting Memory Write, at           1047315000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           1051365000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1051395000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1053045000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           1053345000
 test master 2 - Starting Memory Read, at           1053585000
 test master 2 - Starting Memory Read, at           1053825000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1055355000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           1055835000
 test master 2 - Starting Memory Read, at           1056075000
 test master 2 - Starting Memory Read, at           1056315000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1057545000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1058175000
 test master 2 - Starting Memory Read Line Multiple, at           1058415000
 test master 2 - Starting Memory Read Line Multiple, at           1058685000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1060665000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1071315000
 test master 2 - Starting Memory Read Line Multiple, at           1071555000
 test master 2 - Starting Memory Read Line Multiple, at           1071825000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1072965000
 test master 2 - Starting Memory Read Line Multiple, at           1073205000
 test master 2 - Starting Memory Read Line Multiple, at           1073505000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1074645000
 test master 2 - Starting Memory Read Line Multiple, at           1074885000
 test master 2 - Starting Memory Read Line Multiple, at           1075185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1076325000
 test master 2 - Starting Memory Read Line Multiple, at           1076565000
 test master 2 - Starting Memory Read Line Multiple, at           1076865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1078005000
 test master 2 - Starting Memory Read Line Multiple, at           1078245000
 test master 2 - Starting Memory Read Line Multiple, at           1078545000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1079685000
 test master 2 - Starting Memory Read Line Multiple, at           1079925000
 test master 2 - Starting Memory Read Line Multiple, at           1080225000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1081365000
 test master 2 - Starting Memory Read Line Multiple, at           1081605000
 test master 2 - Starting Memory Read Line Multiple, at           1081905000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1083045000
 test master 2 - Starting Memory Read Line Multiple, at           1083285000
 test master 2 - Starting Memory Read Line Multiple, at           1083585000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           1084725000
 test master 2 - Starting Memory Read Line, at           1084965000
 test master 2 - Starting Memory Read Line, at           1085205000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           1085895000
 test master 2 - Starting Memory Read Line, at           1086135000
 test master 2 - Starting Memory Read Line, at           1086375000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1087425000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1088715000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1091115000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1092735000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           1096995000
 test master 2 - Starting Memory Write, at           1097295000
 test master 2 - Starting Memory Write, at           1097595000
 test master 2 - Starting Memory Write, at           1097895000
 test master 2 - Starting Memory Write, at           1098195000
 test master 1 - Starting Memory Read, at           1098615000
 test master 1 - Starting Memory Read, at           1098975000
 test master 1 - Starting Memory Read, at           1099515000
 test master 1 - Starting Memory Read, at           1099875000
 test master 1 - Starting Memory Read, at           1100415000
 test master 1 - Starting Memory Read, at           1100775000
 test master 2 - Starting Memory Write, at           1101915000
 test master 2 - Starting Memory Write, at           1102215000
 test master 2 - Starting Memory Write, at           1102515000
 test master 2 - Starting Memory Write, at           1102815000
 test master 2 - Starting Memory Write, at           1103115000
 test master 1 - Starting Memory Read, at           1103535000
 test master 1 - Starting Memory Read, at           1103895000
 test master 1 - Starting Memory Read, at           1104435000
 test master 1 - Starting Memory Read, at           1104795000
 test master 1 - Starting Memory Read, at           1105335000
 test master 1 - Starting Memory Read, at           1105695000
 test master 2 - Starting Memory Write, at           1107195000
 test master 2 - Starting Memory Write, at           1108185000
 test master 2 - Starting Memory Write, at           1109205000
 test master 2 - Starting Memory Write, at           1110225000
 test master 2 - Starting Memory Write, at           1112085000
 test master 2 - Starting Memory Write, at           1113105000
 test master 2 - Starting Memory Write, at           1114125000
 test master 2 - Starting Memory Write, at           1115145000
 test master 2 - Starting Memory Write, at           1117005000
 test master 2 - Starting Memory Write, at           1118775000
 test master 2 - Starting Memory Write, at           1120515000
 test master 2 - Starting Memory Write, at           1122255000
 test master 2 - Starting Memory Write, at           1124835000
 test master 2 - Starting Memory Write, at           1126755000
 test master 2 - Starting Memory Write, at           1128675000
 test master 2 - Starting Memory Write, at           1130595000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           1134645000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1134675000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1136325000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           1136625000
 test master 2 - Starting Memory Read, at           1136865000
 test master 2 - Starting Memory Read, at           1137105000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1138635000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           1139115000
 test master 2 - Starting Memory Read, at           1139355000
 test master 2 - Starting Memory Read, at           1139595000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1140825000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1141455000
 test master 2 - Starting Memory Read Line Multiple, at           1141695000
 test master 2 - Starting Memory Read Line Multiple, at           1141965000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1143945000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1154595000
 test master 2 - Starting Memory Read Line Multiple, at           1154835000
 test master 2 - Starting Memory Read Line Multiple, at           1155105000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1156245000
 test master 2 - Starting Memory Read Line Multiple, at           1156485000
 test master 2 - Starting Memory Read Line Multiple, at           1156785000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1157925000
 test master 2 - Starting Memory Read Line Multiple, at           1158165000
 test master 2 - Starting Memory Read Line Multiple, at           1158465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1159605000
 test master 2 - Starting Memory Read Line Multiple, at           1159845000
 test master 2 - Starting Memory Read Line Multiple, at           1160145000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1161285000
 test master 2 - Starting Memory Read Line Multiple, at           1161525000
 test master 2 - Starting Memory Read Line Multiple, at           1161825000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1162965000
 test master 2 - Starting Memory Read Line Multiple, at           1163205000
 test master 2 - Starting Memory Read Line Multiple, at           1163505000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1164645000
 test master 2 - Starting Memory Read Line Multiple, at           1164885000
 test master 2 - Starting Memory Read Line Multiple, at           1165185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1166325000
 test master 2 - Starting Memory Read Line Multiple, at           1166565000
 test master 2 - Starting Memory Read Line Multiple, at           1166865000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           1168005000
 test master 2 - Starting Memory Read Line, at           1168245000
 test master 2 - Starting Memory Read Line, at           1168485000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           1169175000
 test master 2 - Starting Memory Read Line, at           1169415000
 test master 2 - Starting Memory Read Line, at           1169655000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1170705000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1171995000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1174395000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1176015000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           1180275000
 test master 2 - Starting Memory Write, at           1180575000
 test master 2 - Starting Memory Write, at           1180875000
 test master 2 - Starting Memory Write, at           1181175000
 test master 2 - Starting Memory Write, at           1181475000
 test master 1 - Starting Memory Read, at           1181895000
 test master 1 - Starting Memory Read, at           1182255000
 test master 1 - Starting Memory Read, at           1182795000
 test master 1 - Starting Memory Read, at           1183155000
 test master 1 - Starting Memory Read, at           1183695000
 test master 1 - Starting Memory Read, at           1184055000
 test master 2 - Starting Memory Write, at           1185195000
 test master 2 - Starting Memory Write, at           1185495000
 test master 2 - Starting Memory Write, at           1185795000
 test master 2 - Starting Memory Write, at           1186095000
 test master 2 - Starting Memory Write, at           1186395000
 test master 1 - Starting Memory Read, at           1186815000
 test master 1 - Starting Memory Read, at           1187175000
 test master 1 - Starting Memory Read, at           1187715000
 test master 1 - Starting Memory Read, at           1188075000
 test master 1 - Starting Memory Read, at           1188615000
 test master 1 - Starting Memory Read, at           1188975000
 test master 2 - Starting Memory Write, at           1190475000
 test master 2 - Starting Memory Write, at           1191465000
 test master 2 - Starting Memory Write, at           1192485000
 test master 2 - Starting Memory Write, at           1193505000
 test master 2 - Starting Memory Write, at           1195365000
 test master 2 - Starting Memory Write, at           1196385000
 test master 2 - Starting Memory Write, at           1197405000
 test master 2 - Starting Memory Write, at           1198425000
 test master 2 - Starting Memory Write, at           1200285000
 test master 2 - Starting Memory Write, at           1202055000
 test master 2 - Starting Memory Write, at           1203795000
 test master 2 - Starting Memory Write, at           1205535000
 test master 2 - Starting Memory Write, at           1208115000
 test master 2 - Starting Memory Write, at           1210035000
 test master 2 - Starting Memory Write, at           1211955000
 test master 2 - Starting Memory Write, at           1213875000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           1217925000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1217955000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1219605000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           1219905000
 test master 2 - Starting Memory Read, at           1220145000
 test master 2 - Starting Memory Read, at           1220385000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1221915000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           1222395000
 test master 2 - Starting Memory Read, at           1222635000
 test master 2 - Starting Memory Read, at           1222875000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1224105000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1224735000
 test master 2 - Starting Memory Read Line Multiple, at           1224975000
 test master 2 - Starting Memory Read Line Multiple, at           1225245000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1227225000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1237875000
 test master 2 - Starting Memory Read Line Multiple, at           1238115000
 test master 2 - Starting Memory Read Line Multiple, at           1238385000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1239525000
 test master 2 - Starting Memory Read Line Multiple, at           1239765000
 test master 2 - Starting Memory Read Line Multiple, at           1240065000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1241205000
 test master 2 - Starting Memory Read Line Multiple, at           1241445000
 test master 2 - Starting Memory Read Line Multiple, at           1241745000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1242885000
 test master 2 - Starting Memory Read Line Multiple, at           1243125000
 test master 2 - Starting Memory Read Line Multiple, at           1243425000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1244565000
 test master 2 - Starting Memory Read Line Multiple, at           1244805000
 test master 2 - Starting Memory Read Line Multiple, at           1245105000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1246245000
 test master 2 - Starting Memory Read Line Multiple, at           1246485000
 test master 2 - Starting Memory Read Line Multiple, at           1246785000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1247925000
 test master 2 - Starting Memory Read Line Multiple, at           1248165000
 test master 2 - Starting Memory Read Line Multiple, at           1248465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           1249605000
 test master 2 - Starting Memory Read Line Multiple, at           1249845000
 test master 2 - Starting Memory Read Line Multiple, at           1250145000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           1251285000
 test master 2 - Starting Memory Read Line, at           1251525000
 test master 2 - Starting Memory Read Line, at           1251765000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           1252455000
 test master 2 - Starting Memory Read Line, at           1252695000
 test master 2 - Starting Memory Read Line, at           1252935000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1253985000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1255275000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1257675000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           1259295000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           1263555000
 test master 2 - Starting Memory Write, at           1263855000
 test master 2 - Starting Memory Write, at           1264155000
 test master 2 - Starting Memory Write, at           1264455000
 test master 2 - Starting Memory Write, at           1264755000
 test master 1 - Starting Memory Read, at           1265175000
 test master 1 - Starting Memory Read, at           1265535000
 test master 1 - Starting Memory Read, at           1266075000
 test master 1 - Starting Memory Read, at           1266435000
 test master 1 - Starting Memory Read, at           1266975000
 test master 1 - Starting Memory Read, at           1267335000
 test master 2 - Starting Memory Write, at           1268475000
 test master 2 - Starting Memory Write, at           1268775000
 test master 2 - Starting Memory Write, at           1269075000
 test master 2 - Starting Memory Write, at           1269375000
 test master 2 - Starting Memory Write, at           1269675000
 test master 1 - Starting Memory Read, at           1270095000
 test master 1 - Starting Memory Read, at           1270455000
 test master 1 - Starting Memory Read, at           1270995000
 test master 1 - Starting Memory Read, at           1271355000
 test master 1 - Starting Memory Read, at           1271895000
 test master 1 - Starting Memory Read, at           1272255000
 test master 2 - Starting Memory Write, at           1273755000
 test master 2 - Starting Memory Write, at           1274745000
 test master 2 - Starting Memory Write, at           1275765000
 test master 2 - Starting Memory Write, at           1276785000
 test master 2 - Starting Memory Write, at           1278645000
 test master 2 - Starting Memory Write, at           1279665000
 test master 2 - Starting Memory Write, at           1280685000
 test master 2 - Starting Memory Write, at           1281705000
 test master 2 - Starting Memory Write, at           1283565000
 test master 2 - Starting Memory Write, at           1285335000
 test master 2 - Starting Memory Write, at           1287075000
 test master 2 - Starting Memory Write, at           1288815000
 test master 2 - Starting Memory Write, at           1291395000
 test master 2 - Starting Memory Write, at           1293315000
 test master 2 - Starting Memory Write, at           1295235000
 test master 2 - Starting Memory Write, at           1297155000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           1301205000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1301235000
 test master 1 - Starting Memory Read, at           1302885000
 test master 1 - Starting Memory Read, at           1303275000
 test master 1 - Starting Memory Read, at           1304325000
 test master 1 - Starting Memory Read, at           1304715000
 test master 1 - Starting Memory Read Line, at           1305765000
 test master 1 - Starting Memory Read Line, at           1306155000
 test master 1 - Starting Memory Read Line, at           1307205000
 test master 1 - Starting Memory Read Line, at           1307625000
 test master 1 - Starting Memory Read Line, at           1308765000
 test master 1 - Starting Memory Read Line, at           1309215000
 test master 1 - Starting Memory Read Line, at           1310625000
 test master 1 - Starting Memory Read Line, at           1311075000
 test master 1 - Starting Memory Read Line Multiple, at           1312485000
 test master 1 - Starting Memory Read Line Multiple, at           1312995000
 test master 1 - Starting Memory Read Line Multiple, at           1314885000
 test master 1 - Starting Memory Read Line Multiple, at           1315395000
 test master 1 - Starting Memory Read Line, at           1317285000
 test master 1 - Starting Memory Read Line, at           1317735000
 test master 1 - Starting Memory Read, at           1319835000
 test master 1 - Starting Memory Read, at           1320225000
 test target 1 - Starting Config Write, at           1322775000
 test master 1 - Starting Memory Write, at           1323405000
 test master 1 - Starting Memory Write, at           1332735000
 test master 1 - Starting Memory Write, at           1334055000
 test master 1 - Starting Memory Write, at           1342785000
 test master 1 - Starting Memory Write, at           1344135000
 test master 1 - Starting Memory Read Line, at           1353465000
 test master 1 - Starting Memory Write, at           1354965000
 test master 1 - Starting Memory Read Line, at           1364295000
 test target 1 - Starting Config Write, at           1367115000
 test master 1 - Starting Memory Write, at           1367745000
 test master 1 - Starting Memory Write, at           1367925000
 test master 1 - Starting Memory Write, at           1368225000
 test master 1 - Starting Memory Read, at           1368405000
 test master 1 - Starting Memory Write, at           1368795000
 test master 1 - Starting Memory Read, at           1368975000
 test master 1 - Starting Memory Write, at           1370265000
 test master 1 - Starting Memory Write, at           1380915000
 test master 2 - Starting Memory Read Line, at           1391715000
 test master 2 - Starting Memory Read Line, at           1392135000
 test master 2 - Starting Memory Read Line, at           1392855000
 test master 2 - Starting Memory Read Line, at           1393275000
 test master 1 - Starting Memory Write, at           1394085000
 test master 1 - Starting Memory Write, at           1394475000
 test master 1 - Starting Memory Write, at           1394895000
 test master 2 - Starting Memory Read Line, at           1395435000
 test master 2 - Starting Memory Read Line, at           1395825000
 test master 2 - Starting Memory Read Line, at           1396215000
 test master 2 - Starting Memory Read Line, at           1396605000
 test master 2 - Starting Memory Read Line Multiple, at           1397025000
 test master 2 - Starting Memory Read Line Multiple, at           1397415000
 test master 1 - Starting Memory Write, at           1399035000
 test master 1 - Starting Memory Write, at           1399425000
 test master 2 - Starting Memory Read, at           1399965000
 test master 2 - Starting Memory Read, at           1400355000
 test master 2 - Starting Memory Read, at           1400745000
 test master 2 - Starting Memory Read, at           1401135000
 test master 1 - Starting Memory Write, at           1402575000
 test master 1 - Starting Memory Read, at           1402785000
 test master 1 - Starting Memory Write, at           1402995000
 test master 1 - Starting Memory Read, at           1403205000
 test master 1 - Starting Memory Write, at           1403415000
 test master 1 - Starting Memory Read, at           1403625000
 test master 1 - Starting Memory Read, at           1403835000
 test master 1 - Starting Memory Write, at           1404045000
 test master 1 - Starting Memory Write, at           1404255000
 test master 1 - Starting Memory Read, at           1404465000
 test master 1 - Starting Memory Write, at           1404675000
 test master 1 - Starting Memory Write, at           1404885000
 test master 1 - Starting Memory Write, at           1405095000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at           1408515000
 test target 1 - Starting Memory Write, at           1408845000
 test master 1 - Starting Memory Write, at           1409145000
 test target 1 - Starting Memory Write, at           1409385000
 test target 1 - Starting Memory Write, at           1409715000
 test target 1 - Starting Memory Write, at           1410045000
 test master 1 - Starting Memory Write, at           1410465000
 test target 1 - Starting Memory Write, at           1411035000
 test target 1 - Starting Memory Write, at           1411695000
 test target 1 - Starting Memory Write, at           1412055000
 test master 1 - Starting Memory Write, at           1412385000
 test target 1 - Starting Memory Write, at           1412925000
 test target 1 - Starting Memory Write, at           1413285000
 test target 1 - Starting Memory Write, at           1413645000
 test master 1 - Starting Memory Write, at           1414365000
 test target 1 - Starting Memory Write, at           1415385000
 test target 1 - Starting Memory Write, at           1416435000
 test target 1 - Starting Memory Write, at           1416765000
 test master 1 - Starting Memory Read, at           1417065000
 test target 1 - Starting Memory Write, at           1417305000
 test master 1 - Starting Memory Read, at           1417605000
 test target 1 - Starting Memory Write, at           1417845000
 test master 1 - Starting Memory Read, at           1418145000
 test target 1 - Starting Memory Write, at           1418385000
 test master 1 - Starting Memory Read, at           1418685000
 test target 1 - Starting Memory Write, at           1418925000
 test master 1 - Starting Memory Read, at           1419225000
 test target 1 - Starting Memory Write, at           1419465000
 test master 1 - Starting Memory Write, at           1419765000
 test target 1 - Starting Memory Write, at           1420005000
 test target 1 - Starting Memory Write, at           1420335000
 test target 1 - Starting Memory Write, at           1420665000
 test target 1 - Starting Memory Read, at           1421055000
 test master 1 - Starting Memory Write, at           1421475000
 test master 1 - Starting Memory Read, at           1421775000
 test target 1 - Starting Memory Write, at           1422345000
 test master 1 - Starting Memory Write, at           1422855000
 test target 1 - Starting Memory Read, at           1423365000
 test target 1 - Starting Memory Write, at           1424295000
 test master 1 - Starting Memory Read, at           1424715000
 test master 1 - Starting Memory Write, at           1425105000
 test master 1 - Starting Memory Write, at           1425525000
 test master 1 - Starting Memory Read, at           1425825000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           1428045000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           1429065000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           1451775000
 test target 1 - Starting Config Write, at           1452615000
 test target 1 - Starting Config Write, at           1453455000
 test target 2 - Starting Config Write, at           1454295000
 test target 2 - Starting Config Write, at           1455135000
 test target 2 - Starting Config Write, at           1455975000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           1457565000
 test target 1 - Starting Memory Read, at           1457865000
 test target 1 - Starting Memory Write, at           1458525000
 test target 1 - Starting Memory Read, at           1458825000
 test target 1 - Starting Memory Write, at           1459815000
 test target 1 - Starting Memory Read, at           1461015000
 test target 1 - Starting Memory Read, at           1461645000
 test target 1 - Starting Memory Read, at           1462365000
 test target 1 - Starting Memory Read, at           1463055000
 test target 1 - Starting Memory Read, at           1463895000
 test target 1 - Starting Memory Read, at           1465065000
 test target 1 - Starting Memory Read, at           1465935000
 test target 1 - Starting Memory Read, at           1467105000
 test target 1 - Starting Memory Read, at           1467975000
 test target 1 - Starting Memory Read, at           1470525000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           1475925000
 test target 1 - Starting Memory Read, at           1476225000
 test target 1 - Starting Memory Write, at           1476885000
 test target 1 - Starting Memory Read, at           1477185000
 test target 1 - Starting Memory Write, at           1478175000
 test target 1 - Starting Memory Read, at           1479375000
 test target 1 - Starting Memory Read, at           1480005000
 test target 1 - Starting Memory Read, at           1480725000
 test target 1 - Starting Memory Read, at           1481415000
 test target 1 - Starting Memory Read, at           1482255000
 test target 1 - Starting Memory Read, at           1483425000
 test target 1 - Starting Memory Read, at           1484295000
 test target 1 - Starting Memory Read, at           1485465000
 test target 1 - Starting Memory Read, at           1486335000
 test target 1 - Starting Memory Read, at           1488885000
 test target 1 - Starting Memory Write, at           1494285000
 test target 1 - Starting Memory Read, at           1494585000
 test target 1 - Starting Memory Write, at           1495245000
 test target 1 - Starting Memory Read, at           1495545000
 test target 1 - Starting Memory Write, at           1496535000
 test target 1 - Starting Memory Read, at           1497735000
 test target 1 - Starting Memory Read, at           1498365000
 test target 1 - Starting Memory Read, at           1499085000
 test target 1 - Starting Memory Read, at           1499775000
 test target 1 - Starting Memory Read, at           1500615000
 test target 1 - Starting Memory Read, at           1501785000
 test target 1 - Starting Memory Read, at           1502655000
 test target 1 - Starting Memory Read, at           1503825000
 test target 1 - Starting Memory Read, at           1504695000
 test target 1 - Starting Memory Read, at           1507245000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           1516785000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           1522275000
 test target 1 - Starting Memory Write, at           1523085000
 test target 1 - Starting Memory Read, at           1523625000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           1524885000
 test target 1 - Starting Config Write, at           1526625000
 test target 1 - Starting Memory Read, at           1527285000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           1528545000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           1530435000
 test target 1 - Starting Memory Write, at           1531485000
 test target 1 - Starting Memory Write, at           1531815000
 test target 1 - Starting Memory Read, at           1532115000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           1534215000
 test target 1 - Starting Memory Write, at           1536855000
 test target 1 - Starting Memory Write, at           1537305000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           1540845000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           1542555000
 test target 1 - Starting Memory Read, at           1543815000
 test target 1 - Starting Memory Read, at           1544955000
 test target 1 - Starting Memory Read, at           1546575000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           1551705000
 test target 2 - Starting Config Write, at           1552545000
 test target 1 - Starting Memory Write, at           1553205000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           1553415000
 test target 1 - Starting Memory Write, at           1554285000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           1554495000
 test target 1 - Starting Memory Write, at           1555365000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           1556595000
 test target 1 - Starting Memory Read, at           1558575000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           1558785000
 test target 1 - Starting Memory Read, at           1560495000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           1561995000
 test master 2 - Starting Memory Write, at           1561995000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           1562055000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1562835000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1562865000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1563165000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1563195000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1563975000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1564005000
 test target 1 - Starting Memory Write, at           1565595000
 test master 2 - Starting Memory Write, at           1565595000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1567155000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1567185000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1568655000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1568685000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1570155000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1570185000
 test target 1 - Starting Memory Write, at           1571955000
 test master 2 - Starting Memory Write, at           1571955000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           1572015000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1573485000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1573515000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1573815000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1573845000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1574625000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1574655000
 test target 1 - Starting Memory Write, at           1575735000
 test master 2 - Starting Memory Write, at           1575735000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           1578195000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           1579665000
 test master 1 - Starting Memory Read, at           1580145000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           1580355000
 test target 1 - Starting Config Write, at           1582485000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           1584525000
 test target 1 - Starting Memory Write, at           1584765000
 test target 1 - Starting Memory Write, at           1585005000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           1585515000
 test target 1 - Starting Memory Write, at           1585785000
 test target 1 - Starting Memory Write, at           1586055000
 test target 1 - Starting Memory Write, at           1586565000
 test target 1 - Starting Memory Write, at           1586925000
 test target 1 - Starting Memory Write, at           1587435000
 test target 1 - Starting Memory Write, at           1588125000
 test target 1 - Starting Memory Write, at           1588395000
 test target 1 - Starting Memory Write, at           1589085000
 test target 1 - Starting Memory Write, at           1589475000
 test target 1 - Starting Memory Write, at           1590045000
 test target 1 - Starting Memory Write, at           1594395000
 test target 1 - Starting Memory Write, at           1594665000
 test target 1 - Starting Memory Write, at           1594935000
 test target 1 - Starting Memory Write, at           1595325000
 test target 1 - Starting Memory Write, at           1595715000
 test target 1 - Starting Memory Read, at           1602855000
 test target 1 - Starting Memory Read, at           1604085000
 test target 1 - Starting Memory Read, at           1605315000
 test target 1 - Starting Memory Read, at           1606545000
 test target 1 - Starting Memory Read, at           1607805000
 test target 1 - Starting Memory Read, at           1609035000
 test target 1 - Starting Memory Read, at           1610265000
 test target 1 - Starting Memory Read, at           1611525000
 test target 1 - Starting Memory Read, at           1612755000
 test target 1 - Starting Memory Read, at           1613985000
 test target 1 - Starting Memory Read, at           1615245000
 test target 1 - Starting Memory Read, at           1616475000
 test target 1 - Starting Memory Read, at           1617705000
 test target 1 - Starting Memory Read, at           1618965000
 test target 1 - Starting Memory Read, at           1620195000
 test target 1 - Starting Memory Read, at           1621425000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           1622595000
 test target 1 - Starting Memory Read, at           1622835000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           1624395000
 test target 1 - Starting Memory Read, at           1626495000
 test target 1 - Starting Memory Read, at           1627125000
 test target 1 - Starting Memory Read, at           1627815000
 test target 1 - Starting Memory Read, at           1628625000
 test target 1 - Starting Memory Read, at           1629405000
 test target 1 - Starting Memory Read, at           1630695000
 test target 1 - Starting Memory Read, at           1631865000
 test target 1 - Starting Memory Read, at           1632735000
 test target 1 - Starting Memory Read, at           1635915000
 test target 1 - Starting Memory Read, at           1638615000
 test target 1 - Starting Memory Read, at           1639395000
 test target 1 - Starting Memory Read, at           1640175000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           1641315000
 test master 1 - Starting Memory Write, at           1641645000
 test target 1 - Starting Memory Write, at           1641645000
 test target 1 - Starting Memory Write, at           1641885000
 test target 1 - Starting Memory Read, at           1642545000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           1645215000
 test master 1 - Starting Memory Write, at           1645545000
 test target 1 - Starting Memory Write, at           1645545000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           1650105000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           1651245000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           1674075000
 test target 1 - Starting Config Write, at           1674915000
 test target 1 - Starting Config Write, at           1675755000
 test target 2 - Starting Config Write, at           1676595000
 test target 2 - Starting Config Write, at           1677435000
 test target 2 - Starting Config Write, at           1678275000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           1679865000
 test target 1 - Starting Memory Read, at           1680195000
 test target 1 - Starting Memory Write, at           1680825000
 test target 1 - Starting Memory Read, at           1681155000
 test target 1 - Starting Memory Write, at           1682115000
 test target 1 - Starting Memory Read, at           1683315000
 test target 1 - Starting Memory Read, at           1683945000
 test target 1 - Starting Memory Read, at           1684665000
 test target 1 - Starting Memory Read, at           1685355000
 test target 1 - Starting Memory Read, at           1686195000
 test target 1 - Starting Memory Read, at           1687365000
 test target 1 - Starting Memory Read, at           1688235000
 test target 1 - Starting Memory Read, at           1689405000
 test target 1 - Starting Memory Read, at           1690275000
 test target 1 - Starting Memory Read, at           1692825000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           1698225000
 test target 1 - Starting Memory Read, at           1698555000
 test target 1 - Starting Memory Write, at           1699185000
 test target 1 - Starting Memory Read, at           1699515000
 test target 1 - Starting Memory Write, at           1700475000
 test target 1 - Starting Memory Read, at           1701675000
 test target 1 - Starting Memory Read, at           1702305000
 test target 1 - Starting Memory Read, at           1703025000
 test target 1 - Starting Memory Read, at           1703715000
 test target 1 - Starting Memory Read, at           1704555000
 test target 1 - Starting Memory Read, at           1705725000
 test target 1 - Starting Memory Read, at           1706595000
 test target 1 - Starting Memory Read, at           1707765000
 test target 1 - Starting Memory Read, at           1708635000
 test target 1 - Starting Memory Read, at           1711185000
 test target 1 - Starting Memory Write, at           1716585000
 test target 1 - Starting Memory Read, at           1716915000
 test target 1 - Starting Memory Write, at           1717545000
 test target 1 - Starting Memory Read, at           1717875000
 test target 1 - Starting Memory Write, at           1718835000
 test target 1 - Starting Memory Read, at           1720035000
 test target 1 - Starting Memory Read, at           1720665000
 test target 1 - Starting Memory Read, at           1721385000
 test target 1 - Starting Memory Read, at           1722075000
 test target 1 - Starting Memory Read, at           1722915000
 test target 1 - Starting Memory Read, at           1724085000
 test target 1 - Starting Memory Read, at           1724955000
 test target 1 - Starting Memory Read, at           1726125000
 test target 1 - Starting Memory Read, at           1726995000
 test target 1 - Starting Memory Read, at           1729545000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           1739085000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           1744575000
 test target 1 - Starting Memory Write, at           1745385000
 test target 1 - Starting Memory Read, at           1745955000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           1747305000
 test target 1 - Starting Config Write, at           1749045000
 test target 1 - Starting Memory Read, at           1749705000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           1751085000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           1752975000
 test target 1 - Starting Memory Write, at           1754025000
 test target 1 - Starting Memory Write, at           1754385000
 test target 1 - Starting Memory Read, at           1754715000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           1756875000
 test target 1 - Starting Memory Write, at           1759515000
 test target 1 - Starting Memory Write, at           1759995000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           1763565000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           1765275000
 test target 1 - Starting Memory Read, at           1766535000
 test target 1 - Starting Memory Read, at           1767795000
 test target 1 - Starting Memory Read, at           1769415000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           1774545000
 test target 2 - Starting Config Write, at           1775385000
 test target 1 - Starting Memory Write, at           1776045000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           1776285000
 test target 1 - Starting Memory Write, at           1777155000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           1777395000
 test target 1 - Starting Memory Write, at           1778265000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           1779555000
 test target 1 - Starting Memory Read, at           1781535000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           1781775000
 test target 1 - Starting Memory Read, at           1783575000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           1785075000
 test master 2 - Starting Memory Write, at           1785075000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           1785135000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1785945000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1785975000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1786275000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1786305000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1787085000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1787115000
 test target 1 - Starting Memory Write, at           1788705000
 test master 2 - Starting Memory Write, at           1788705000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1790295000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1790325000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1791795000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1791825000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1793295000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1793325000
 test target 1 - Starting Memory Write, at           1795095000
 test master 2 - Starting Memory Write, at           1795095000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           1795155000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1796655000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1796685000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1796985000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1797015000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1797795000
*** monitor - CBE Bus Changed when TRDY Desserted, at           1797825000
 test target 1 - Starting Memory Write, at           1798905000
 test master 2 - Starting Memory Write, at           1798905000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           1801395000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           1802865000
 test master 1 - Starting Memory Read, at           1803345000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           1803555000
 test target 1 - Starting Config Write, at           1805685000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           1807725000
 test target 1 - Starting Memory Write, at           1807995000
 test target 1 - Starting Memory Write, at           1808265000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           1808805000
 test target 1 - Starting Memory Write, at           1809105000
 test target 1 - Starting Memory Write, at           1809405000
 test target 1 - Starting Memory Write, at           1809945000
 test target 1 - Starting Memory Write, at           1810335000
 test target 1 - Starting Memory Write, at           1810875000
 test target 1 - Starting Memory Write, at           1811595000
 test target 1 - Starting Memory Write, at           1811895000
 test target 1 - Starting Memory Write, at           1812615000
 test target 1 - Starting Memory Write, at           1813035000
 test target 1 - Starting Memory Write, at           1813635000
 test target 1 - Starting Memory Write, at           1818015000
 test target 1 - Starting Memory Write, at           1818315000
 test target 1 - Starting Memory Write, at           1818615000
 test target 1 - Starting Memory Write, at           1819035000
 test target 1 - Starting Memory Write, at           1819455000
 test target 1 - Starting Memory Read, at           1826625000
 test target 1 - Starting Memory Read, at           1827825000
 test target 1 - Starting Memory Read, at           1829055000
 test target 1 - Starting Memory Read, at           1830285000
 test target 1 - Starting Memory Read, at           1831545000
 test target 1 - Starting Memory Read, at           1832775000
 test target 1 - Starting Memory Read, at           1834005000
 test target 1 - Starting Memory Read, at           1835265000
 test target 1 - Starting Memory Read, at           1836495000
 test target 1 - Starting Memory Read, at           1837725000
 test target 1 - Starting Memory Read, at           1838985000
 test target 1 - Starting Memory Read, at           1840215000
 test target 1 - Starting Memory Read, at           1841445000
 test target 1 - Starting Memory Read, at           1842705000
 test target 1 - Starting Memory Read, at           1843935000
 test target 1 - Starting Memory Read, at           1845165000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           1846335000
 test target 1 - Starting Memory Read, at           1846605000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           1848135000
 test target 1 - Starting Memory Read, at           1850265000
 test target 1 - Starting Memory Read, at           1850985000
 test target 1 - Starting Memory Read, at           1851675000
 test target 1 - Starting Memory Read, at           1852485000
 test target 1 - Starting Memory Read, at           1853265000
 test target 1 - Starting Memory Read, at           1854555000
 test target 1 - Starting Memory Read, at           1855845000
 test target 1 - Starting Memory Read, at           1856715000
 test target 1 - Starting Memory Read, at           1859895000
 test target 1 - Starting Memory Read, at           1862595000
 test target 1 - Starting Memory Read, at           1863375000
 test target 1 - Starting Memory Read, at           1864155000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           1865295000
 test master 1 - Starting Memory Write, at           1865655000
 test target 1 - Starting Memory Write, at           1865655000
 test target 1 - Starting Memory Write, at           1865925000
 test target 1 - Starting Memory Read, at           1866615000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           1869345000
 test master 1 - Starting Memory Write, at           1869705000
 test target 1 - Starting Memory Write, at           1869705000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           1874265000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           1875405000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           1898235000
 test target 1 - Starting Config Write, at           1899075000
 test target 1 - Starting Config Write, at           1899915000
 test target 2 - Starting Config Write, at           1900755000
 test target 2 - Starting Config Write, at           1901595000
 test target 2 - Starting Config Write, at           1902435000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           1904025000
 test target 1 - Starting Memory Read, at           1904385000
 test target 1 - Starting Memory Write, at           1905105000
 test target 1 - Starting Memory Read, at           1905465000
 test target 1 - Starting Memory Write, at           1906515000
 test target 1 - Starting Memory Read, at           1907775000
 test target 1 - Starting Memory Read, at           1908525000
 test target 1 - Starting Memory Read, at           1909245000
 test target 1 - Starting Memory Read, at           1909935000
 test target 1 - Starting Memory Read, at           1910775000
 test target 1 - Starting Memory Read, at           1912065000
 test target 1 - Starting Memory Read, at           1912935000
 test target 1 - Starting Memory Read, at           1914225000
 test target 1 - Starting Memory Read, at           1915095000
 test target 1 - Starting Memory Read, at           1917765000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           1923285000
 test target 1 - Starting Memory Read, at           1923645000
 test target 1 - Starting Memory Write, at           1924365000
 test target 1 - Starting Memory Read, at           1924725000
 test target 1 - Starting Memory Write, at           1925775000
 test target 1 - Starting Memory Read, at           1927035000
 test target 1 - Starting Memory Read, at           1927785000
 test target 1 - Starting Memory Read, at           1928505000
 test target 1 - Starting Memory Read, at           1929195000
 test target 1 - Starting Memory Read, at           1930035000
 test target 1 - Starting Memory Read, at           1931325000
 test target 1 - Starting Memory Read, at           1932195000
 test target 1 - Starting Memory Read, at           1933485000
 test target 1 - Starting Memory Read, at           1934355000
 test target 1 - Starting Memory Read, at           1937025000
 test target 1 - Starting Memory Write, at           1942545000
 test target 1 - Starting Memory Read, at           1942905000
 test target 1 - Starting Memory Write, at           1943625000
 test target 1 - Starting Memory Read, at           1943985000
 test target 1 - Starting Memory Write, at           1945035000
 test target 1 - Starting Memory Read, at           1946295000
 test target 1 - Starting Memory Read, at           1947045000
 test target 1 - Starting Memory Read, at           1947765000
 test target 1 - Starting Memory Read, at           1948455000
 test target 1 - Starting Memory Read, at           1949295000
 test target 1 - Starting Memory Read, at           1950585000
 test target 1 - Starting Memory Read, at           1951455000
 test target 1 - Starting Memory Read, at           1952745000
 test target 1 - Starting Memory Read, at           1953615000
 test target 1 - Starting Memory Read, at           1956285000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           1965945000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           1971615000
 test target 1 - Starting Memory Write, at           1972425000
 test target 1 - Starting Memory Read, at           1973025000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           1974345000
 test target 1 - Starting Config Write, at           1976205000
 test target 1 - Starting Memory Read, at           1976895000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           1978275000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           1980195000
 test target 1 - Starting Memory Write, at           1981245000
 test target 1 - Starting Memory Write, at           1981635000
 test target 1 - Starting Memory Read, at           1981995000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           1984095000
 test target 1 - Starting Memory Write, at           1986795000
 test target 1 - Starting Memory Write, at           1987305000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           1990905000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           1992735000
 test target 1 - Starting Memory Read, at           1994115000
 test target 1 - Starting Memory Read, at           1995375000
 test target 1 - Starting Memory Read, at           1996995000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           2002245000
 test target 2 - Starting Config Write, at           2003205000
 test target 1 - Starting Memory Write, at           2003895000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           2004165000
 test target 1 - Starting Memory Write, at           2005035000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           2005305000
 test target 1 - Starting Memory Write, at           2006175000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           2007495000
 test target 1 - Starting Memory Read, at           2009595000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           2009865000
 test target 1 - Starting Memory Read, at           2011635000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           2013255000
 test master 2 - Starting Memory Write, at           2013255000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           2013315000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2014155000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2014185000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2014485000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2014515000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2015295000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2015325000
 test target 1 - Starting Memory Write, at           2016915000
 test master 2 - Starting Memory Write, at           2016915000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2018535000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2018565000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2020035000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2020065000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2021535000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2021565000
 test target 1 - Starting Memory Write, at           2023335000
 test master 2 - Starting Memory Write, at           2023335000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           2023395000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2024925000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2024955000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2025255000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2025285000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2026065000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2026095000
 test target 1 - Starting Memory Write, at           2027175000
 test master 2 - Starting Memory Write, at           2027175000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           2029695000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           2031165000
 test master 1 - Starting Memory Read, at           2031645000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           2031855000
 test target 1 - Starting Config Write, at           2033985000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           2036025000
 test target 1 - Starting Memory Write, at           2036325000
 test target 1 - Starting Memory Write, at           2036625000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           2037195000
 test target 1 - Starting Memory Write, at           2037525000
 test target 1 - Starting Memory Write, at           2037855000
 test target 1 - Starting Memory Write, at           2038425000
 test target 1 - Starting Memory Write, at           2038845000
 test target 1 - Starting Memory Write, at           2039415000
 test target 1 - Starting Memory Write, at           2040165000
 test target 1 - Starting Memory Write, at           2040495000
 test target 1 - Starting Memory Write, at           2041245000
 test target 1 - Starting Memory Write, at           2041695000
 test target 1 - Starting Memory Write, at           2042325000
 test target 1 - Starting Memory Write, at           2046735000
 test target 1 - Starting Memory Write, at           2047065000
 test target 1 - Starting Memory Write, at           2047395000
 test target 1 - Starting Memory Write, at           2047845000
 test target 1 - Starting Memory Write, at           2048295000
 test target 1 - Starting Memory Read, at           2055495000
 test target 1 - Starting Memory Read, at           2056785000
 test target 1 - Starting Memory Read, at           2058015000
 test target 1 - Starting Memory Read, at           2059245000
 test target 1 - Starting Memory Read, at           2060505000
 test target 1 - Starting Memory Read, at           2061735000
 test target 1 - Starting Memory Read, at           2062965000
 test target 1 - Starting Memory Read, at           2064225000
 test target 1 - Starting Memory Read, at           2065455000
 test target 1 - Starting Memory Read, at           2066685000
 test target 1 - Starting Memory Read, at           2067945000
 test target 1 - Starting Memory Read, at           2069175000
 test target 1 - Starting Memory Read, at           2070405000
 test target 1 - Starting Memory Read, at           2071665000
 test target 1 - Starting Memory Read, at           2072895000
 test target 1 - Starting Memory Read, at           2074125000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           2075295000
 test target 1 - Starting Memory Read, at           2075595000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           2077215000
 test target 1 - Starting Memory Read, at           2079375000
 test target 1 - Starting Memory Read, at           2080065000
 test target 1 - Starting Memory Read, at           2080845000
 test target 1 - Starting Memory Read, at           2081775000
 test target 1 - Starting Memory Read, at           2082675000
 test target 1 - Starting Memory Read, at           2083935000
 test target 1 - Starting Memory Read, at           2085225000
 test target 1 - Starting Memory Read, at           2086095000
 test target 1 - Starting Memory Read, at           2089305000
 test target 1 - Starting Memory Read, at           2091975000
 test target 1 - Starting Memory Read, at           2092875000
 test target 1 - Starting Memory Read, at           2093775000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           2095035000
 test master 1 - Starting Memory Write, at           2095425000
 test target 1 - Starting Memory Write, at           2095425000
 test target 1 - Starting Memory Write, at           2095725000
 test target 1 - Starting Memory Read, at           2096445000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           2099235000
 test master 1 - Starting Memory Write, at           2099625000
 test target 1 - Starting Memory Write, at           2099625000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           2104125000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           2105265000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           2128095000
 test target 1 - Starting Config Write, at           2129085000
 test target 1 - Starting Config Write, at           2130045000
 test target 2 - Starting Config Write, at           2131035000
 test target 2 - Starting Config Write, at           2132025000
 test target 2 - Starting Config Write, at           2132985000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           2134725000
 test target 1 - Starting Memory Read, at           2135115000
 test target 1 - Starting Memory Write, at           2135805000
 test target 1 - Starting Memory Read, at           2136195000
 test target 1 - Starting Memory Write, at           2137215000
 test target 1 - Starting Memory Read, at           2138475000
 test target 1 - Starting Memory Read, at           2139225000
 test target 1 - Starting Memory Read, at           2139945000
 test target 1 - Starting Memory Read, at           2140635000
 test target 1 - Starting Memory Read, at           2141475000
 test target 1 - Starting Memory Read, at           2142765000
 test target 1 - Starting Memory Read, at           2143635000
 test target 1 - Starting Memory Read, at           2144925000
 test target 1 - Starting Memory Read, at           2145795000
 test target 1 - Starting Memory Read, at           2148465000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           2153985000
 test target 1 - Starting Memory Read, at           2154375000
 test target 1 - Starting Memory Write, at           2155065000
 test target 1 - Starting Memory Read, at           2155455000
 test target 1 - Starting Memory Write, at           2156475000
 test target 1 - Starting Memory Read, at           2157735000
 test target 1 - Starting Memory Read, at           2158485000
 test target 1 - Starting Memory Read, at           2159205000
 test target 1 - Starting Memory Read, at           2159895000
 test target 1 - Starting Memory Read, at           2160735000
 test target 1 - Starting Memory Read, at           2162025000
 test target 1 - Starting Memory Read, at           2162895000
 test target 1 - Starting Memory Read, at           2164185000
 test target 1 - Starting Memory Read, at           2165055000
 test target 1 - Starting Memory Read, at           2167725000
 test target 1 - Starting Memory Write, at           2173245000
 test target 1 - Starting Memory Read, at           2173635000
 test target 1 - Starting Memory Write, at           2174325000
 test target 1 - Starting Memory Read, at           2174715000
 test target 1 - Starting Memory Write, at           2175735000
 test target 1 - Starting Memory Read, at           2176995000
 test target 1 - Starting Memory Read, at           2177745000
 test target 1 - Starting Memory Read, at           2178465000
 test target 1 - Starting Memory Read, at           2179155000
 test target 1 - Starting Memory Read, at           2179995000
 test target 1 - Starting Memory Read, at           2181285000
 test target 1 - Starting Memory Read, at           2182155000
 test target 1 - Starting Memory Read, at           2183445000
 test target 1 - Starting Memory Read, at           2184315000
 test target 1 - Starting Memory Read, at           2186985000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           2196645000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           2202315000
 test target 1 - Starting Memory Write, at           2203275000
 test target 1 - Starting Memory Read, at           2203905000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           2205285000
 test target 1 - Starting Config Write, at           2207145000
 test target 1 - Starting Memory Read, at           2207985000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           2209335000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           2211375000
 test target 1 - Starting Memory Write, at           2212545000
 test target 1 - Starting Memory Write, at           2212965000
 test target 1 - Starting Memory Read, at           2213355000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           2215515000
 test target 1 - Starting Memory Write, at           2218215000
 test target 1 - Starting Memory Write, at           2218755000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           2222385000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           2224215000
 test target 1 - Starting Memory Read, at           2225595000
 test target 1 - Starting Memory Read, at           2226855000
 test target 1 - Starting Memory Read, at           2228595000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           2233845000
 test target 2 - Starting Config Write, at           2234805000
 test target 1 - Starting Memory Write, at           2235615000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           2235915000
 test target 1 - Starting Memory Write, at           2236785000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           2237085000
 test target 1 - Starting Memory Write, at           2237955000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           2239275000
 test target 1 - Starting Memory Read, at           2241375000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           2241675000
 test target 1 - Starting Memory Read, at           2243415000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           2245035000
 test master 2 - Starting Memory Write, at           2245035000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           2245095000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2245965000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2245995000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2246295000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2246325000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2247105000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2247135000
 test target 1 - Starting Memory Write, at           2248725000
 test master 2 - Starting Memory Write, at           2248725000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2250375000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2250405000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2251875000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2251905000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2253375000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2253405000
 test target 1 - Starting Memory Write, at           2255175000
 test master 2 - Starting Memory Write, at           2255175000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           2255235000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2256795000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2256825000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2257125000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2257155000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2257935000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2257965000
 test target 1 - Starting Memory Write, at           2259045000
 test master 2 - Starting Memory Write, at           2259045000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           2261595000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           2263065000
 test master 1 - Starting Memory Read, at           2263545000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           2263755000
 test target 1 - Starting Config Write, at           2265885000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           2267925000
 test target 1 - Starting Memory Write, at           2268255000
 test target 1 - Starting Memory Write, at           2268585000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           2269185000
 test target 1 - Starting Memory Write, at           2269545000
 test target 1 - Starting Memory Write, at           2269905000
 test target 1 - Starting Memory Write, at           2270505000
 test target 1 - Starting Memory Write, at           2270955000
 test target 1 - Starting Memory Write, at           2271555000
 test target 1 - Starting Memory Write, at           2272335000
 test target 1 - Starting Memory Write, at           2272695000
 test target 1 - Starting Memory Write, at           2273475000
 test target 1 - Starting Memory Write, at           2273955000
 test target 1 - Starting Memory Write, at           2274615000
 test target 1 - Starting Memory Write, at           2279055000
 test target 1 - Starting Memory Write, at           2279415000
 test target 1 - Starting Memory Write, at           2279775000
 test target 1 - Starting Memory Write, at           2280255000
 test target 1 - Starting Memory Write, at           2280735000
 test target 1 - Starting Memory Read, at           2287965000
 test target 1 - Starting Memory Read, at           2289225000
 test target 1 - Starting Memory Read, at           2290455000
 test target 1 - Starting Memory Read, at           2291685000
 test target 1 - Starting Memory Read, at           2292945000
 test target 1 - Starting Memory Read, at           2294175000
 test target 1 - Starting Memory Read, at           2295405000
 test target 1 - Starting Memory Read, at           2296665000
 test target 1 - Starting Memory Read, at           2297895000
 test target 1 - Starting Memory Read, at           2299125000
 test target 1 - Starting Memory Read, at           2300385000
 test target 1 - Starting Memory Read, at           2301615000
 test target 1 - Starting Memory Read, at           2302845000
 test target 1 - Starting Memory Read, at           2304105000
 test target 1 - Starting Memory Read, at           2305335000
 test target 1 - Starting Memory Read, at           2306565000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           2307735000
 test target 1 - Starting Memory Read, at           2308065000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           2309655000
 test target 1 - Starting Memory Read, at           2311845000
 test target 1 - Starting Memory Read, at           2312625000
 test target 1 - Starting Memory Read, at           2313405000
 test target 1 - Starting Memory Read, at           2314335000
 test target 1 - Starting Memory Read, at           2315235000
 test target 1 - Starting Memory Read, at           2316495000
 test target 1 - Starting Memory Read, at           2317785000
 test target 1 - Starting Memory Read, at           2318655000
 test target 1 - Starting Memory Read, at           2321955000
 test target 1 - Starting Memory Read, at           2324775000
 test target 1 - Starting Memory Read, at           2325675000
 test target 1 - Starting Memory Read, at           2326575000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           2327835000
 test master 1 - Starting Memory Write, at           2328255000
 test target 1 - Starting Memory Write, at           2328255000
 test target 1 - Starting Memory Write, at           2328585000
 test target 1 - Starting Memory Read, at           2329335000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           2332065000
 test master 1 - Starting Memory Write, at           2332485000
 test target 1 - Starting Memory Write, at           2332485000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2337015000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           2337375000
 test master 2 - Starting Memory Read, at           2337615000
 test master 2 - Starting Memory Read, at           2337855000
 test master 2 - Starting Memory Read, at           2338095000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2339595000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           2340135000
 test master 2 - Starting Memory Read, at           2340375000
 test master 2 - Starting Memory Read, at           2340825000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2342055000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2342805000
 test master 2 - Starting Memory Read Line Multiple, at           2343045000
 test master 2 - Starting Memory Read Line Multiple, at           2343285000
 test master 2 - Starting Memory Read Line Multiple, at           2343525000
 test master 2 - Starting Memory Read Line Multiple, at           2343765000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2345595000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2358135000
 test master 2 - Starting Memory Read Line Multiple, at           2358375000
 test master 2 - Starting Memory Read Line Multiple, at           2358615000
 test master 2 - Starting Memory Read Line Multiple, at           2358855000
 test master 2 - Starting Memory Read Line Multiple, at           2359095000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2360055000
 test master 2 - Starting Memory Read Line Multiple, at           2360295000
 test master 2 - Starting Memory Read Line Multiple, at           2360535000
 test master 2 - Starting Memory Read Line Multiple, at           2360775000
 test master 2 - Starting Memory Read Line Multiple, at           2361015000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2361975000
 test master 2 - Starting Memory Read Line Multiple, at           2362215000
 test master 2 - Starting Memory Read Line Multiple, at           2362455000
 test master 2 - Starting Memory Read Line Multiple, at           2362695000
 test master 2 - Starting Memory Read Line Multiple, at           2362935000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2363895000
 test master 2 - Starting Memory Read Line Multiple, at           2364135000
 test master 2 - Starting Memory Read Line Multiple, at           2364375000
 test master 2 - Starting Memory Read Line Multiple, at           2364615000
 test master 2 - Starting Memory Read Line Multiple, at           2364855000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2365815000
 test master 2 - Starting Memory Read Line Multiple, at           2366055000
 test master 2 - Starting Memory Read Line Multiple, at           2366295000
 test master 2 - Starting Memory Read Line Multiple, at           2366535000
 test master 2 - Starting Memory Read Line Multiple, at           2366775000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2367735000
 test master 2 - Starting Memory Read Line Multiple, at           2367975000
 test master 2 - Starting Memory Read Line Multiple, at           2368215000
 test master 2 - Starting Memory Read Line Multiple, at           2368455000
 test master 2 - Starting Memory Read Line Multiple, at           2368695000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2369655000
 test master 2 - Starting Memory Read Line Multiple, at           2369895000
 test master 2 - Starting Memory Read Line Multiple, at           2370135000
 test master 2 - Starting Memory Read Line Multiple, at           2370375000
 test master 2 - Starting Memory Read Line Multiple, at           2370615000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2371575000
 test master 2 - Starting Memory Read Line Multiple, at           2371815000
 test master 2 - Starting Memory Read Line Multiple, at           2372055000
 test master 2 - Starting Memory Read Line Multiple, at           2372295000
 test master 2 - Starting Memory Read Line Multiple, at           2372535000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           2373495000
 test master 2 - Starting Memory Read Line, at           2373735000
 test master 2 - Starting Memory Read Line, at           2373975000
 test master 2 - Starting Memory Read Line, at           2374215000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           2374815000
 test master 2 - Starting Memory Read Line, at           2375055000
 test master 2 - Starting Memory Read Line, at           2375505000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2376555000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2377995000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2380575000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2382375000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           2387025000
 test master 2 - Starting Memory Write, at           2387385000
 test master 2 - Starting Memory Write, at           2387745000
 test master 2 - Starting Memory Write, at           2388105000
 test master 2 - Starting Memory Write, at           2388465000
 test master 1 - Starting Memory Read, at           2388945000
 test master 1 - Starting Memory Read, at           2389365000
 test master 1 - Starting Memory Read, at           2389905000
 test master 1 - Starting Memory Read, at           2390325000
 test master 1 - Starting Memory Read, at           2390865000
 test master 1 - Starting Memory Read, at           2391285000
 test master 2 - Starting Memory Write, at           2392455000
 test master 2 - Starting Memory Write, at           2392815000
 test master 2 - Starting Memory Write, at           2393175000
 test master 2 - Starting Memory Write, at           2393535000
 test master 2 - Starting Memory Write, at           2393895000
 test master 1 - Starting Memory Read, at           2394375000
 test master 1 - Starting Memory Read, at           2394795000
 test master 1 - Starting Memory Read, at           2395335000
 test master 1 - Starting Memory Read, at           2395755000
 test master 1 - Starting Memory Read, at           2396295000
 test master 1 - Starting Memory Read, at           2396715000
 test master 2 - Starting Memory Write, at           2398275000
 test master 2 - Starting Memory Write, at           2399355000
 test master 2 - Starting Memory Write, at           2400435000
 test master 2 - Starting Memory Write, at           2401515000
 test master 2 - Starting Memory Write, at           2403495000
 test master 2 - Starting Memory Write, at           2404575000
 test master 2 - Starting Memory Write, at           2405655000
 test master 2 - Starting Memory Write, at           2406735000
 test master 2 - Starting Memory Write, at           2408715000
 test master 2 - Starting Memory Write, at           2410635000
 test master 2 - Starting Memory Write, at           2412555000
 test master 2 - Starting Memory Write, at           2414475000
 test master 2 - Starting Memory Write, at           2417295000
 test master 2 - Starting Memory Write, at           2419395000
 test master 2 - Starting Memory Write, at           2421495000
 test master 2 - Starting Memory Write, at           2423595000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           2427825000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2427855000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2429535000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           2429895000
 test master 2 - Starting Memory Read, at           2430135000
 test master 2 - Starting Memory Read, at           2430375000
 test master 2 - Starting Memory Read, at           2430615000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2432115000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           2432655000
 test master 2 - Starting Memory Read, at           2432895000
 test master 2 - Starting Memory Read, at           2433345000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2434575000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2435325000
 test master 2 - Starting Memory Read Line Multiple, at           2435565000
 test master 2 - Starting Memory Read Line Multiple, at           2435805000
 test master 2 - Starting Memory Read Line Multiple, at           2436045000
 test master 2 - Starting Memory Read Line Multiple, at           2436285000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2438115000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2450655000
 test master 2 - Starting Memory Read Line Multiple, at           2450895000
 test master 2 - Starting Memory Read Line Multiple, at           2451135000
 test master 2 - Starting Memory Read Line Multiple, at           2451375000
 test master 2 - Starting Memory Read Line Multiple, at           2451615000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2452575000
 test master 2 - Starting Memory Read Line Multiple, at           2452815000
 test master 2 - Starting Memory Read Line Multiple, at           2453055000
 test master 2 - Starting Memory Read Line Multiple, at           2453295000
 test master 2 - Starting Memory Read Line Multiple, at           2453535000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2454495000
 test master 2 - Starting Memory Read Line Multiple, at           2454735000
 test master 2 - Starting Memory Read Line Multiple, at           2454975000
 test master 2 - Starting Memory Read Line Multiple, at           2455215000
 test master 2 - Starting Memory Read Line Multiple, at           2455455000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2456415000
 test master 2 - Starting Memory Read Line Multiple, at           2456655000
 test master 2 - Starting Memory Read Line Multiple, at           2456895000
 test master 2 - Starting Memory Read Line Multiple, at           2457135000
 test master 2 - Starting Memory Read Line Multiple, at           2457375000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2458335000
 test master 2 - Starting Memory Read Line Multiple, at           2458575000
 test master 2 - Starting Memory Read Line Multiple, at           2458815000
 test master 2 - Starting Memory Read Line Multiple, at           2459055000
 test master 2 - Starting Memory Read Line Multiple, at           2459295000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2460255000
 test master 2 - Starting Memory Read Line Multiple, at           2460495000
 test master 2 - Starting Memory Read Line Multiple, at           2460735000
 test master 2 - Starting Memory Read Line Multiple, at           2460975000
 test master 2 - Starting Memory Read Line Multiple, at           2461215000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2462175000
 test master 2 - Starting Memory Read Line Multiple, at           2462415000
 test master 2 - Starting Memory Read Line Multiple, at           2462655000
 test master 2 - Starting Memory Read Line Multiple, at           2462895000
 test master 2 - Starting Memory Read Line Multiple, at           2463135000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2464095000
 test master 2 - Starting Memory Read Line Multiple, at           2464335000
 test master 2 - Starting Memory Read Line Multiple, at           2464575000
 test master 2 - Starting Memory Read Line Multiple, at           2464815000
 test master 2 - Starting Memory Read Line Multiple, at           2465055000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           2466015000
 test master 2 - Starting Memory Read Line, at           2466255000
 test master 2 - Starting Memory Read Line, at           2466495000
 test master 2 - Starting Memory Read Line, at           2466735000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           2467335000
 test master 2 - Starting Memory Read Line, at           2467575000
 test master 2 - Starting Memory Read Line, at           2468025000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2469075000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2470515000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2473095000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2474895000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           2479545000
 test master 2 - Starting Memory Write, at           2479905000
 test master 2 - Starting Memory Write, at           2480265000
 test master 2 - Starting Memory Write, at           2480625000
 test master 2 - Starting Memory Write, at           2480985000
 test master 1 - Starting Memory Read, at           2481465000
 test master 1 - Starting Memory Read, at           2481885000
 test master 1 - Starting Memory Read, at           2482425000
 test master 1 - Starting Memory Read, at           2482845000
 test master 1 - Starting Memory Read, at           2483385000
 test master 1 - Starting Memory Read, at           2483805000
 test master 2 - Starting Memory Write, at           2484975000
 test master 2 - Starting Memory Write, at           2485335000
 test master 2 - Starting Memory Write, at           2485695000
 test master 2 - Starting Memory Write, at           2486055000
 test master 2 - Starting Memory Write, at           2486415000
 test master 1 - Starting Memory Read, at           2486895000
 test master 1 - Starting Memory Read, at           2487315000
 test master 1 - Starting Memory Read, at           2487855000
 test master 1 - Starting Memory Read, at           2488275000
 test master 1 - Starting Memory Read, at           2488815000
 test master 1 - Starting Memory Read, at           2489235000
 test master 2 - Starting Memory Write, at           2490795000
 test master 2 - Starting Memory Write, at           2491875000
 test master 2 - Starting Memory Write, at           2492955000
 test master 2 - Starting Memory Write, at           2494035000
 test master 2 - Starting Memory Write, at           2496015000
 test master 2 - Starting Memory Write, at           2497095000
 test master 2 - Starting Memory Write, at           2498175000
 test master 2 - Starting Memory Write, at           2499255000
 test master 2 - Starting Memory Write, at           2501235000
 test master 2 - Starting Memory Write, at           2503155000
 test master 2 - Starting Memory Write, at           2505075000
 test master 2 - Starting Memory Write, at           2506995000
 test master 2 - Starting Memory Write, at           2509815000
 test master 2 - Starting Memory Write, at           2511915000
 test master 2 - Starting Memory Write, at           2514015000
 test master 2 - Starting Memory Write, at           2516115000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           2520345000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2520375000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2522055000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           2522415000
 test master 2 - Starting Memory Read, at           2522655000
 test master 2 - Starting Memory Read, at           2522895000
 test master 2 - Starting Memory Read, at           2523135000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2524635000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           2525175000
 test master 2 - Starting Memory Read, at           2525415000
 test master 2 - Starting Memory Read, at           2525865000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2527095000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2527845000
 test master 2 - Starting Memory Read Line Multiple, at           2528085000
 test master 2 - Starting Memory Read Line Multiple, at           2528325000
 test master 2 - Starting Memory Read Line Multiple, at           2528565000
 test master 2 - Starting Memory Read Line Multiple, at           2528805000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2530635000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2543175000
 test master 2 - Starting Memory Read Line Multiple, at           2543415000
 test master 2 - Starting Memory Read Line Multiple, at           2543655000
 test master 2 - Starting Memory Read Line Multiple, at           2543895000
 test master 2 - Starting Memory Read Line Multiple, at           2544135000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2545095000
 test master 2 - Starting Memory Read Line Multiple, at           2545335000
 test master 2 - Starting Memory Read Line Multiple, at           2545575000
 test master 2 - Starting Memory Read Line Multiple, at           2545815000
 test master 2 - Starting Memory Read Line Multiple, at           2546055000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2547015000
 test master 2 - Starting Memory Read Line Multiple, at           2547255000
 test master 2 - Starting Memory Read Line Multiple, at           2547495000
 test master 2 - Starting Memory Read Line Multiple, at           2547735000
 test master 2 - Starting Memory Read Line Multiple, at           2547975000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2548935000
 test master 2 - Starting Memory Read Line Multiple, at           2549175000
 test master 2 - Starting Memory Read Line Multiple, at           2549415000
 test master 2 - Starting Memory Read Line Multiple, at           2549655000
 test master 2 - Starting Memory Read Line Multiple, at           2549895000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2550855000
 test master 2 - Starting Memory Read Line Multiple, at           2551095000
 test master 2 - Starting Memory Read Line Multiple, at           2551335000
 test master 2 - Starting Memory Read Line Multiple, at           2551575000
 test master 2 - Starting Memory Read Line Multiple, at           2551815000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2552775000
 test master 2 - Starting Memory Read Line Multiple, at           2553015000
 test master 2 - Starting Memory Read Line Multiple, at           2553255000
 test master 2 - Starting Memory Read Line Multiple, at           2553495000
 test master 2 - Starting Memory Read Line Multiple, at           2553735000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2554695000
 test master 2 - Starting Memory Read Line Multiple, at           2554935000
 test master 2 - Starting Memory Read Line Multiple, at           2555175000
 test master 2 - Starting Memory Read Line Multiple, at           2555415000
 test master 2 - Starting Memory Read Line Multiple, at           2555655000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2556615000
 test master 2 - Starting Memory Read Line Multiple, at           2556855000
 test master 2 - Starting Memory Read Line Multiple, at           2557095000
 test master 2 - Starting Memory Read Line Multiple, at           2557335000
 test master 2 - Starting Memory Read Line Multiple, at           2557575000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           2558535000
 test master 2 - Starting Memory Read Line, at           2558775000
 test master 2 - Starting Memory Read Line, at           2559015000
 test master 2 - Starting Memory Read Line, at           2559255000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           2559855000
 test master 2 - Starting Memory Read Line, at           2560095000
 test master 2 - Starting Memory Read Line, at           2560545000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2561595000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2563035000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2565615000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2567415000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           2572065000
 test master 2 - Starting Memory Write, at           2572425000
 test master 2 - Starting Memory Write, at           2572785000
 test master 2 - Starting Memory Write, at           2573145000
 test master 2 - Starting Memory Write, at           2573505000
 test master 1 - Starting Memory Read, at           2573985000
 test master 1 - Starting Memory Read, at           2574405000
 test master 1 - Starting Memory Read, at           2574945000
 test master 1 - Starting Memory Read, at           2575365000
 test master 1 - Starting Memory Read, at           2575905000
 test master 1 - Starting Memory Read, at           2576325000
 test master 2 - Starting Memory Write, at           2577495000
 test master 2 - Starting Memory Write, at           2577855000
 test master 2 - Starting Memory Write, at           2578215000
 test master 2 - Starting Memory Write, at           2578575000
 test master 2 - Starting Memory Write, at           2578935000
 test master 1 - Starting Memory Read, at           2579415000
 test master 1 - Starting Memory Read, at           2579835000
 test master 1 - Starting Memory Read, at           2580375000
 test master 1 - Starting Memory Read, at           2580795000
 test master 1 - Starting Memory Read, at           2581335000
 test master 1 - Starting Memory Read, at           2581755000
 test master 2 - Starting Memory Write, at           2583315000
 test master 2 - Starting Memory Write, at           2584395000
 test master 2 - Starting Memory Write, at           2585475000
 test master 2 - Starting Memory Write, at           2586555000
 test master 2 - Starting Memory Write, at           2588535000
 test master 2 - Starting Memory Write, at           2589615000
 test master 2 - Starting Memory Write, at           2590695000
 test master 2 - Starting Memory Write, at           2591775000
 test master 2 - Starting Memory Write, at           2593755000
 test master 2 - Starting Memory Write, at           2595675000
 test master 2 - Starting Memory Write, at           2597595000
 test master 2 - Starting Memory Write, at           2599515000
 test master 2 - Starting Memory Write, at           2602335000
 test master 2 - Starting Memory Write, at           2604435000
 test master 2 - Starting Memory Write, at           2606535000
 test master 2 - Starting Memory Write, at           2608635000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           2612865000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2612895000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2614575000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           2614935000
 test master 2 - Starting Memory Read, at           2615175000
 test master 2 - Starting Memory Read, at           2615415000
 test master 2 - Starting Memory Read, at           2615655000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2617155000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           2617695000
 test master 2 - Starting Memory Read, at           2617935000
 test master 2 - Starting Memory Read, at           2618385000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2619615000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2620365000
 test master 2 - Starting Memory Read Line Multiple, at           2620605000
 test master 2 - Starting Memory Read Line Multiple, at           2620845000
 test master 2 - Starting Memory Read Line Multiple, at           2621085000
 test master 2 - Starting Memory Read Line Multiple, at           2621325000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2623155000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2635695000
 test master 2 - Starting Memory Read Line Multiple, at           2635935000
 test master 2 - Starting Memory Read Line Multiple, at           2636175000
 test master 2 - Starting Memory Read Line Multiple, at           2636415000
 test master 2 - Starting Memory Read Line Multiple, at           2636655000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2637615000
 test master 2 - Starting Memory Read Line Multiple, at           2637855000
 test master 2 - Starting Memory Read Line Multiple, at           2638095000
 test master 2 - Starting Memory Read Line Multiple, at           2638335000
 test master 2 - Starting Memory Read Line Multiple, at           2638575000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2639535000
 test master 2 - Starting Memory Read Line Multiple, at           2639775000
 test master 2 - Starting Memory Read Line Multiple, at           2640015000
 test master 2 - Starting Memory Read Line Multiple, at           2640255000
 test master 2 - Starting Memory Read Line Multiple, at           2640495000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2641455000
 test master 2 - Starting Memory Read Line Multiple, at           2641695000
 test master 2 - Starting Memory Read Line Multiple, at           2641935000
 test master 2 - Starting Memory Read Line Multiple, at           2642175000
 test master 2 - Starting Memory Read Line Multiple, at           2642415000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2643375000
 test master 2 - Starting Memory Read Line Multiple, at           2643615000
 test master 2 - Starting Memory Read Line Multiple, at           2643855000
 test master 2 - Starting Memory Read Line Multiple, at           2644095000
 test master 2 - Starting Memory Read Line Multiple, at           2644335000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2645295000
 test master 2 - Starting Memory Read Line Multiple, at           2645535000
 test master 2 - Starting Memory Read Line Multiple, at           2645775000
 test master 2 - Starting Memory Read Line Multiple, at           2646015000
 test master 2 - Starting Memory Read Line Multiple, at           2646255000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2647215000
 test master 2 - Starting Memory Read Line Multiple, at           2647455000
 test master 2 - Starting Memory Read Line Multiple, at           2647695000
 test master 2 - Starting Memory Read Line Multiple, at           2647935000
 test master 2 - Starting Memory Read Line Multiple, at           2648175000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           2649135000
 test master 2 - Starting Memory Read Line Multiple, at           2649375000
 test master 2 - Starting Memory Read Line Multiple, at           2649615000
 test master 2 - Starting Memory Read Line Multiple, at           2649855000
 test master 2 - Starting Memory Read Line Multiple, at           2650095000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           2651055000
 test master 2 - Starting Memory Read Line, at           2651295000
 test master 2 - Starting Memory Read Line, at           2651535000
 test master 2 - Starting Memory Read Line, at           2651775000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           2652375000
 test master 2 - Starting Memory Read Line, at           2652615000
 test master 2 - Starting Memory Read Line, at           2653065000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2654115000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2655555000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2658135000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           2659935000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           2664585000
 test master 2 - Starting Memory Write, at           2664945000
 test master 2 - Starting Memory Write, at           2665305000
 test master 2 - Starting Memory Write, at           2665665000
 test master 2 - Starting Memory Write, at           2666025000
 test master 1 - Starting Memory Read, at           2666505000
 test master 1 - Starting Memory Read, at           2666925000
 test master 1 - Starting Memory Read, at           2667465000
 test master 1 - Starting Memory Read, at           2667885000
 test master 1 - Starting Memory Read, at           2668425000
 test master 1 - Starting Memory Read, at           2668845000
 test master 2 - Starting Memory Write, at           2670015000
 test master 2 - Starting Memory Write, at           2670375000
 test master 2 - Starting Memory Write, at           2670735000
 test master 2 - Starting Memory Write, at           2671095000
 test master 2 - Starting Memory Write, at           2671455000
 test master 1 - Starting Memory Read, at           2671935000
 test master 1 - Starting Memory Read, at           2672355000
 test master 1 - Starting Memory Read, at           2672895000
 test master 1 - Starting Memory Read, at           2673315000
 test master 1 - Starting Memory Read, at           2673855000
 test master 1 - Starting Memory Read, at           2674275000
 test master 2 - Starting Memory Write, at           2675835000
 test master 2 - Starting Memory Write, at           2676915000
 test master 2 - Starting Memory Write, at           2677995000
 test master 2 - Starting Memory Write, at           2679075000
 test master 2 - Starting Memory Write, at           2681055000
 test master 2 - Starting Memory Write, at           2682135000
 test master 2 - Starting Memory Write, at           2683215000
 test master 2 - Starting Memory Write, at           2684295000
 test master 2 - Starting Memory Write, at           2686275000
 test master 2 - Starting Memory Write, at           2688195000
 test master 2 - Starting Memory Write, at           2690115000
 test master 2 - Starting Memory Write, at           2692035000
 test master 2 - Starting Memory Write, at           2694855000
 test master 2 - Starting Memory Write, at           2696955000
 test master 2 - Starting Memory Write, at           2699055000
 test master 2 - Starting Memory Write, at           2701155000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           2705385000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2705415000
 test master 1 - Starting Memory Read, at           2707095000
 test master 1 - Starting Memory Read, at           2707545000
 test master 1 - Starting Memory Read, at           2708625000
 test master 1 - Starting Memory Read, at           2709075000
 test master 1 - Starting Memory Read Line, at           2710185000
 test master 1 - Starting Memory Read Line, at           2710635000
 test master 1 - Starting Memory Read Line, at           2711745000
 test master 1 - Starting Memory Read Line, at           2712285000
 test master 1 - Starting Memory Read Line, at           2713485000
 test master 1 - Starting Memory Read Line, at           2714175000
 test master 1 - Starting Memory Read Line, at           2715585000
 test master 1 - Starting Memory Read Line, at           2716275000
 test master 1 - Starting Memory Read Line Multiple, at           2717685000
 test master 1 - Starting Memory Read Line Multiple, at           2718615000
 test master 1 - Starting Memory Read Line Multiple, at           2720385000
 test master 1 - Starting Memory Read Line Multiple, at           2721315000
 test master 1 - Starting Memory Read Line, at           2723085000
 test master 1 - Starting Memory Read Line, at           2723775000
 test master 1 - Starting Memory Read, at           2725875000
 test master 1 - Starting Memory Read, at           2726325000
 test target 1 - Starting Config Write, at           2728965000
 test master 1 - Starting Memory Write, at           2729595000
 test master 1 - Starting Memory Write, at           2737095000
 test master 1 - Starting Memory Write, at           2742135000
 test master 1 - Starting Memory Write, at           2749155000
 test master 1 - Starting Memory Write, at           2754075000
 test master 1 - Starting Memory Read Line, at           2761575000
 test master 1 - Starting Memory Write, at           2767035000
 test master 1 - Starting Memory Read Line, at           2774535000
 test target 1 - Starting Config Write, at           2781165000
 test master 1 - Starting Memory Write, at           2781795000
 test master 1 - Starting Memory Write, at           2781975000
 test master 1 - Starting Memory Write, at           2782335000
 test master 1 - Starting Memory Read, at           2782515000
 test master 1 - Starting Memory Write, at           2782965000
 test master 1 - Starting Memory Read, at           2783145000
 test master 1 - Starting Memory Write, at           2784435000
 test master 1 - Starting Memory Write, at           2796975000
 test master 2 - Starting Memory Read Line, at           2809635000
 test master 2 - Starting Memory Read Line, at           2810295000
 test master 2 - Starting Memory Read Line, at           2810925000
 test master 2 - Starting Memory Read Line, at           2811585000
 test master 1 - Starting Memory Write, at           2812305000
 test master 1 - Starting Memory Write, at           2812665000
 test master 1 - Starting Memory Write, at           2813055000
 test master 2 - Starting Memory Read Line, at           2813565000
 test master 2 - Starting Memory Read Line, at           2814015000
 test master 2 - Starting Memory Read Line, at           2814375000
 test master 2 - Starting Memory Read Line, at           2814825000
 test master 2 - Starting Memory Read Line Multiple, at           2815215000
 test master 2 - Starting Memory Read Line Multiple, at           2815665000
 test master 1 - Starting Memory Write, at           2817255000
 test master 1 - Starting Memory Write, at           2817615000
 test master 2 - Starting Memory Read, at           2818125000
 test master 2 - Starting Memory Read, at           2818575000
 test master 2 - Starting Memory Read, at           2818935000
 test master 2 - Starting Memory Read, at           2819385000
 test master 1 - Starting Memory Write, at           2820795000
 test master 1 - Starting Memory Read, at           2821005000
 test master 1 - Starting Memory Write, at           2821215000
 test master 1 - Starting Memory Read, at           2821425000
 test master 1 - Starting Memory Write, at           2821635000
 test master 1 - Starting Memory Read, at           2821845000
 test master 1 - Starting Memory Read, at           2822055000
 test master 1 - Starting Memory Write, at           2822265000
 test master 1 - Starting Memory Write, at           2822475000
 test master 1 - Starting Memory Read, at           2822685000
 test master 1 - Starting Memory Write, at           2822895000
 test master 1 - Starting Memory Write, at           2823105000
 test master 1 - Starting Memory Write, at           2823315000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at           2826825000
 test target 1 - Starting Memory Write, at           2827155000
 test master 1 - Starting Memory Write, at           2827455000
 test target 1 - Starting Memory Write, at           2827695000
 test target 1 - Starting Memory Write, at           2828025000
 test target 1 - Starting Memory Write, at           2828355000
 test master 1 - Starting Memory Write, at           2828775000
 test target 1 - Starting Memory Write, at           2829405000
 test target 1 - Starting Memory Write, at           2830155000
 test target 1 - Starting Memory Write, at           2830515000
 test master 1 - Starting Memory Write, at           2830845000
 test target 1 - Starting Memory Write, at           2831325000
 test target 1 - Starting Memory Write, at           2831685000
 test target 1 - Starting Memory Write, at           2832045000
 test master 1 - Starting Memory Write, at           2832705000
 test target 1 - Starting Memory Write, at           2833725000
 test target 1 - Starting Memory Write, at           2834895000
 test target 1 - Starting Memory Write, at           2835225000
 test master 1 - Starting Memory Read, at           2835525000
 test target 1 - Starting Memory Write, at           2835765000
 test master 1 - Starting Memory Read, at           2836065000
 test target 1 - Starting Memory Write, at           2836305000
 test master 1 - Starting Memory Read, at           2836605000
 test target 1 - Starting Memory Write, at           2836845000
 test master 1 - Starting Memory Read, at           2837145000
 test target 1 - Starting Memory Write, at           2837385000
 test master 1 - Starting Memory Read, at           2837685000
 test target 1 - Starting Memory Write, at           2837925000
 test master 1 - Starting Memory Write, at           2838225000
 test target 1 - Starting Memory Write, at           2838465000
 test target 1 - Starting Memory Write, at           2838795000
 test target 1 - Starting Memory Write, at           2839125000
 test target 1 - Starting Memory Read, at           2839515000
 test master 1 - Starting Memory Write, at           2839935000
 test master 1 - Starting Memory Read, at           2840235000
 test target 1 - Starting Memory Write, at           2840805000
 test master 1 - Starting Memory Write, at           2841315000
 test target 1 - Starting Memory Read, at           2841825000
 test target 1 - Starting Memory Write, at           2842755000
 test master 1 - Starting Memory Read, at           2843175000
 test master 1 - Starting Memory Write, at           2843625000
 test master 1 - Starting Memory Write, at           2844045000
 test master 1 - Starting Memory Read, at           2844405000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           2846745000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           2847795000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           2871585000
 test target 1 - Starting Config Write, at           2872545000
 test target 1 - Starting Config Write, at           2873505000
 test target 2 - Starting Config Write, at           2874465000
 test target 2 - Starting Config Write, at           2875425000
 test target 2 - Starting Config Write, at           2876385000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           2878185000
 test target 1 - Starting Memory Read, at           2878485000
 test target 1 - Starting Memory Write, at           2879175000
 test target 1 - Starting Memory Read, at           2879475000
 test target 1 - Starting Memory Write, at           2880555000
 test target 1 - Starting Memory Read, at           2881635000
 test target 1 - Starting Memory Read, at           2882325000
 test target 1 - Starting Memory Read, at           2883015000
 test target 1 - Starting Memory Read, at           2883705000
 test target 1 - Starting Memory Read, at           2884515000
 test target 1 - Starting Memory Read, at           2885745000
 test target 1 - Starting Memory Read, at           2886615000
 test target 1 - Starting Memory Read, at           2887845000
 test target 1 - Starting Memory Read, at           2888715000
 test target 1 - Starting Memory Read, at           2890965000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           2896785000
 test target 1 - Starting Memory Read, at           2897085000
 test target 1 - Starting Memory Write, at           2897775000
 test target 1 - Starting Memory Read, at           2898075000
 test target 1 - Starting Memory Write, at           2899155000
 test target 1 - Starting Memory Read, at           2900235000
 test target 1 - Starting Memory Read, at           2900925000
 test target 1 - Starting Memory Read, at           2901615000
 test target 1 - Starting Memory Read, at           2902305000
 test target 1 - Starting Memory Read, at           2903115000
 test target 1 - Starting Memory Read, at           2904345000
 test target 1 - Starting Memory Read, at           2905215000
 test target 1 - Starting Memory Read, at           2906445000
 test target 1 - Starting Memory Read, at           2907315000
 test target 1 - Starting Memory Read, at           2909565000
 test target 1 - Starting Memory Write, at           2915385000
 test target 1 - Starting Memory Read, at           2915685000
 test target 1 - Starting Memory Write, at           2916375000
 test target 1 - Starting Memory Read, at           2916675000
 test target 1 - Starting Memory Write, at           2917755000
 test target 1 - Starting Memory Read, at           2918835000
 test target 1 - Starting Memory Read, at           2919525000
 test target 1 - Starting Memory Read, at           2920215000
 test target 1 - Starting Memory Read, at           2920905000
 test target 1 - Starting Memory Read, at           2921715000
 test target 1 - Starting Memory Read, at           2922945000
 test target 1 - Starting Memory Read, at           2923815000
 test target 1 - Starting Memory Read, at           2925045000
 test target 1 - Starting Memory Read, at           2925915000
 test target 1 - Starting Memory Read, at           2928165000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           2938605000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           2944485000
 test target 1 - Starting Memory Write, at           2945445000
 test target 1 - Starting Memory Read, at           2945925000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           2947245000
 test target 1 - Starting Config Write, at           2949225000
 test target 1 - Starting Memory Read, at           2949975000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           2951385000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           2953545000
 test target 1 - Starting Memory Write, at           2954745000
 test target 1 - Starting Memory Write, at           2955075000
 test target 1 - Starting Memory Read, at           2955375000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           2957595000
 test target 1 - Starting Memory Write, at           2960355000
 test target 1 - Starting Memory Write, at           2960775000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           2964435000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           2966295000
 test target 1 - Starting Memory Read, at           2967555000
 test target 1 - Starting Memory Read, at           2968755000
 test target 1 - Starting Memory Read, at           2970375000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           2975865000
 test target 2 - Starting Config Write, at           2976825000
 test target 1 - Starting Memory Write, at           2977605000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           2977815000
 test target 1 - Starting Memory Write, at           2978745000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           2978955000
 test target 1 - Starting Memory Write, at           2979885000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           2981235000
 test target 1 - Starting Memory Read, at           2983335000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           2983545000
 test target 1 - Starting Memory Read, at           2985495000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           2987145000
 test master 2 - Starting Memory Write, at           2987145000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           2987205000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2988015000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2988045000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2988345000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2988375000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2989215000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2989245000
 test target 1 - Starting Memory Write, at           2990895000
 test master 2 - Starting Memory Write, at           2990895000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2992515000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2992545000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2994075000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2994105000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2995635000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2995665000
 test target 1 - Starting Memory Write, at           2997525000
 test master 2 - Starting Memory Write, at           2997525000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           2997585000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2999115000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2999145000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2999445000
*** monitor - CBE Bus Changed when TRDY Desserted, at           2999475000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3000315000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3000345000
 test target 1 - Starting Memory Write, at           3001455000
 test master 2 - Starting Memory Write, at           3001455000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           3004125000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           3005655000
 test master 1 - Starting Memory Read, at           3006045000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           3006255000
 test target 1 - Starting Config Write, at           3008505000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           3010695000
 test target 1 - Starting Memory Write, at           3010935000
 test target 1 - Starting Memory Write, at           3011175000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           3011715000
 test target 1 - Starting Memory Write, at           3011985000
 test target 1 - Starting Memory Write, at           3012255000
 test target 1 - Starting Memory Write, at           3012795000
 test target 1 - Starting Memory Write, at           3013125000
 test target 1 - Starting Memory Write, at           3013635000
 test target 1 - Starting Memory Write, at           3014325000
 test target 1 - Starting Memory Write, at           3014595000
 test target 1 - Starting Memory Write, at           3015285000
 test target 1 - Starting Memory Write, at           3015645000
 test target 1 - Starting Memory Write, at           3016245000
 test target 1 - Starting Memory Write, at           3021795000
 test target 1 - Starting Memory Write, at           3022065000
 test target 1 - Starting Memory Write, at           3022335000
 test target 1 - Starting Memory Write, at           3022695000
 test target 1 - Starting Memory Write, at           3023055000
 test target 1 - Starting Memory Read, at           3028485000
 test target 1 - Starting Memory Read, at           3029685000
 test target 1 - Starting Memory Read, at           3030885000
 test target 1 - Starting Memory Read, at           3032085000
 test target 1 - Starting Memory Read, at           3033285000
 test target 1 - Starting Memory Read, at           3034485000
 test target 1 - Starting Memory Read, at           3035685000
 test target 1 - Starting Memory Read, at           3036885000
 test target 1 - Starting Memory Read, at           3038085000
 test target 1 - Starting Memory Read, at           3039285000
 test target 1 - Starting Memory Read, at           3040485000
 test target 1 - Starting Memory Read, at           3041685000
 test target 1 - Starting Memory Read, at           3042885000
 test target 1 - Starting Memory Read, at           3044085000
 test target 1 - Starting Memory Read, at           3045285000
 test target 1 - Starting Memory Read, at           3046485000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           3047565000
 test target 1 - Starting Memory Read, at           3047805000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           3049695000
 test target 1 - Starting Memory Read, at           3051345000
 test target 1 - Starting Memory Read, at           3052005000
 test target 1 - Starting Memory Read, at           3052725000
 test target 1 - Starting Memory Read, at           3053565000
 test target 1 - Starting Memory Read, at           3054315000
 test target 1 - Starting Memory Read, at           3055515000
 test target 1 - Starting Memory Read, at           3056745000
 test target 1 - Starting Memory Read, at           3057615000
 test target 1 - Starting Memory Read, at           3060585000
 test target 1 - Starting Memory Read, at           3062895000
 test target 1 - Starting Memory Read, at           3063735000
 test target 1 - Starting Memory Read, at           3064635000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           3065925000
 test master 1 - Starting Memory Write, at           3066225000
 test target 1 - Starting Memory Write, at           3066225000
 test target 1 - Starting Memory Write, at           3066465000
 test target 1 - Starting Memory Read, at           3067035000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           3069405000
 test master 1 - Starting Memory Write, at           3069705000
 test target 1 - Starting Memory Write, at           3069705000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           3074445000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           3075615000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           3099525000
 test target 1 - Starting Config Write, at           3100485000
 test target 1 - Starting Config Write, at           3101445000
 test target 2 - Starting Config Write, at           3102405000
 test target 2 - Starting Config Write, at           3103365000
 test target 2 - Starting Config Write, at           3104325000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           3106125000
 test target 1 - Starting Memory Read, at           3106455000
 test target 1 - Starting Memory Write, at           3107115000
 test target 1 - Starting Memory Read, at           3107445000
 test target 1 - Starting Memory Write, at           3108495000
 test target 1 - Starting Memory Read, at           3109575000
 test target 1 - Starting Memory Read, at           3110295000
 test target 1 - Starting Memory Read, at           3110985000
 test target 1 - Starting Memory Read, at           3111645000
 test target 1 - Starting Memory Read, at           3112515000
 test target 1 - Starting Memory Read, at           3113745000
 test target 1 - Starting Memory Read, at           3114615000
 test target 1 - Starting Memory Read, at           3115845000
 test target 1 - Starting Memory Read, at           3116715000
 test target 1 - Starting Memory Read, at           3118965000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           3124905000
 test target 1 - Starting Memory Read, at           3125235000
 test target 1 - Starting Memory Write, at           3125895000
 test target 1 - Starting Memory Read, at           3126225000
 test target 1 - Starting Memory Write, at           3127275000
 test target 1 - Starting Memory Read, at           3128355000
 test target 1 - Starting Memory Read, at           3129075000
 test target 1 - Starting Memory Read, at           3129765000
 test target 1 - Starting Memory Read, at           3130425000
 test target 1 - Starting Memory Read, at           3131295000
 test target 1 - Starting Memory Read, at           3132525000
 test target 1 - Starting Memory Read, at           3133395000
 test target 1 - Starting Memory Read, at           3134625000
 test target 1 - Starting Memory Read, at           3135495000
 test target 1 - Starting Memory Read, at           3137745000
 test target 1 - Starting Memory Write, at           3143685000
 test target 1 - Starting Memory Read, at           3144015000
 test target 1 - Starting Memory Write, at           3144675000
 test target 1 - Starting Memory Read, at           3145005000
 test target 1 - Starting Memory Write, at           3146055000
 test target 1 - Starting Memory Read, at           3147135000
 test target 1 - Starting Memory Read, at           3147855000
 test target 1 - Starting Memory Read, at           3148545000
 test target 1 - Starting Memory Read, at           3149205000
 test target 1 - Starting Memory Read, at           3150075000
 test target 1 - Starting Memory Read, at           3151305000
 test target 1 - Starting Memory Read, at           3152175000
 test target 1 - Starting Memory Read, at           3153405000
 test target 1 - Starting Memory Read, at           3154275000
 test target 1 - Starting Memory Read, at           3156525000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           3167085000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           3172965000
 test target 1 - Starting Memory Write, at           3173925000
 test target 1 - Starting Memory Read, at           3174435000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           3175725000
 test target 1 - Starting Config Write, at           3177705000
 test target 1 - Starting Memory Read, at           3178455000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           3179865000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           3182025000
 test target 1 - Starting Memory Write, at           3183225000
 test target 1 - Starting Memory Write, at           3183585000
 test target 1 - Starting Memory Read, at           3183915000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           3186075000
 test target 1 - Starting Memory Write, at           3188895000
 test target 1 - Starting Memory Write, at           3189345000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           3193035000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           3194895000
 test target 1 - Starting Memory Read, at           3196275000
 test target 1 - Starting Memory Read, at           3197475000
 test target 1 - Starting Memory Read, at           3199095000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           3204585000
 test target 2 - Starting Config Write, at           3205545000
 test target 1 - Starting Memory Write, at           3206325000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           3206565000
 test target 1 - Starting Memory Write, at           3207465000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           3207705000
 test target 1 - Starting Memory Write, at           3208605000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           3209955000
 test target 1 - Starting Memory Read, at           3212055000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           3212295000
 test target 1 - Starting Memory Read, at           3214215000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           3215865000
 test master 2 - Starting Memory Write, at           3215865000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           3215925000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3216795000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3216825000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3217125000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3217155000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3217995000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3218025000
 test target 1 - Starting Memory Write, at           3219675000
 test master 2 - Starting Memory Write, at           3219675000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3221355000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3221385000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3222915000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3222945000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3224475000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3224505000
 test target 1 - Starting Memory Write, at           3226365000
 test master 2 - Starting Memory Write, at           3226365000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           3226425000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3228015000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3228045000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3228345000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3228375000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3229215000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3229245000
 test target 1 - Starting Memory Write, at           3230355000
 test master 2 - Starting Memory Write, at           3230355000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           3233025000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           3234555000
 test master 1 - Starting Memory Read, at           3234945000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           3235155000
 test target 1 - Starting Config Write, at           3237405000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           3239595000
 test target 1 - Starting Memory Write, at           3239865000
 test target 1 - Starting Memory Write, at           3240135000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           3240675000
 test target 1 - Starting Memory Write, at           3240975000
 test target 1 - Starting Memory Write, at           3241275000
 test target 1 - Starting Memory Write, at           3241815000
 test target 1 - Starting Memory Write, at           3242175000
 test target 1 - Starting Memory Write, at           3242715000
 test target 1 - Starting Memory Write, at           3243435000
 test target 1 - Starting Memory Write, at           3243735000
 test target 1 - Starting Memory Write, at           3244455000
 test target 1 - Starting Memory Write, at           3244845000
 test target 1 - Starting Memory Write, at           3245475000
 test target 1 - Starting Memory Write, at           3251055000
 test target 1 - Starting Memory Write, at           3251355000
 test target 1 - Starting Memory Write, at           3251655000
 test target 1 - Starting Memory Write, at           3252045000
 test target 1 - Starting Memory Write, at           3252435000
 test target 1 - Starting Memory Read, at           3257895000
 test target 1 - Starting Memory Read, at           3259095000
 test target 1 - Starting Memory Read, at           3260295000
 test target 1 - Starting Memory Read, at           3261495000
 test target 1 - Starting Memory Read, at           3262695000
 test target 1 - Starting Memory Read, at           3263895000
 test target 1 - Starting Memory Read, at           3265095000
 test target 1 - Starting Memory Read, at           3266295000
 test target 1 - Starting Memory Read, at           3267495000
 test target 1 - Starting Memory Read, at           3268695000
 test target 1 - Starting Memory Read, at           3269895000
 test target 1 - Starting Memory Read, at           3271095000
 test target 1 - Starting Memory Read, at           3272295000
 test target 1 - Starting Memory Read, at           3273495000
 test target 1 - Starting Memory Read, at           3274695000
 test target 1 - Starting Memory Read, at           3275895000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           3276975000
 test target 1 - Starting Memory Read, at           3277245000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           3279105000
 test target 1 - Starting Memory Read, at           3280785000
 test target 1 - Starting Memory Read, at           3281415000
 test target 1 - Starting Memory Read, at           3282135000
 test target 1 - Starting Memory Read, at           3282975000
 test target 1 - Starting Memory Read, at           3283725000
 test target 1 - Starting Memory Read, at           3284895000
 test target 1 - Starting Memory Read, at           3286125000
 test target 1 - Starting Memory Read, at           3286995000
 test target 1 - Starting Memory Read, at           3290085000
 test target 1 - Starting Memory Read, at           3292335000
 test target 1 - Starting Memory Read, at           3293235000
 test target 1 - Starting Memory Read, at           3294075000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           3295395000
 test master 1 - Starting Memory Write, at           3295725000
 test target 1 - Starting Memory Write, at           3295725000
 test target 1 - Starting Memory Write, at           3295995000
 test target 1 - Starting Memory Read, at           3296595000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           3299025000
 test master 1 - Starting Memory Write, at           3299355000
 test target 1 - Starting Memory Write, at           3299355000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           3304065000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           3305235000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           3329145000
 test target 1 - Starting Config Write, at           3330105000
 test target 1 - Starting Config Write, at           3331065000
 test target 2 - Starting Config Write, at           3332025000
 test target 2 - Starting Config Write, at           3332985000
 test target 2 - Starting Config Write, at           3333945000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           3335745000
 test target 1 - Starting Memory Read, at           3336105000
 test target 1 - Starting Memory Write, at           3336855000
 test target 1 - Starting Memory Read, at           3337215000
 test target 1 - Starting Memory Write, at           3338415000
 test target 1 - Starting Memory Read, at           3339555000
 test target 1 - Starting Memory Read, at           3340245000
 test target 1 - Starting Memory Read, at           3340935000
 test target 1 - Starting Memory Read, at           3341625000
 test target 1 - Starting Memory Read, at           3342435000
 test target 1 - Starting Memory Read, at           3343665000
 test target 1 - Starting Memory Read, at           3344535000
 test target 1 - Starting Memory Read, at           3345765000
 test target 1 - Starting Memory Read, at           3346635000
 test target 1 - Starting Memory Read, at           3348885000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           3354705000
 test target 1 - Starting Memory Read, at           3355065000
 test target 1 - Starting Memory Write, at           3355815000
 test target 1 - Starting Memory Read, at           3356175000
 test target 1 - Starting Memory Write, at           3357375000
 test target 1 - Starting Memory Read, at           3358515000
 test target 1 - Starting Memory Read, at           3359205000
 test target 1 - Starting Memory Read, at           3359895000
 test target 1 - Starting Memory Read, at           3360585000
 test target 1 - Starting Memory Read, at           3361395000
 test target 1 - Starting Memory Read, at           3362625000
 test target 1 - Starting Memory Read, at           3363495000
 test target 1 - Starting Memory Read, at           3364725000
 test target 1 - Starting Memory Read, at           3365595000
 test target 1 - Starting Memory Read, at           3367845000
 test target 1 - Starting Memory Write, at           3373665000
 test target 1 - Starting Memory Read, at           3374025000
 test target 1 - Starting Memory Write, at           3374775000
 test target 1 - Starting Memory Read, at           3375135000
 test target 1 - Starting Memory Write, at           3376335000
 test target 1 - Starting Memory Read, at           3377475000
 test target 1 - Starting Memory Read, at           3378165000
 test target 1 - Starting Memory Read, at           3378855000
 test target 1 - Starting Memory Read, at           3379545000
 test target 1 - Starting Memory Read, at           3380355000
 test target 1 - Starting Memory Read, at           3381585000
 test target 1 - Starting Memory Read, at           3382455000
 test target 1 - Starting Memory Read, at           3383685000
 test target 1 - Starting Memory Read, at           3384555000
 test target 1 - Starting Memory Read, at           3386805000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           3397245000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           3403125000
 test target 1 - Starting Memory Write, at           3404085000
 test target 1 - Starting Memory Read, at           3404625000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           3405885000
 test target 1 - Starting Config Write, at           3407865000
 test target 1 - Starting Memory Read, at           3408615000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           3410025000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           3412185000
 test target 1 - Starting Memory Write, at           3413385000
 test target 1 - Starting Memory Write, at           3413775000
 test target 1 - Starting Memory Read, at           3414135000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           3416355000
 test target 1 - Starting Memory Write, at           3419175000
 test target 1 - Starting Memory Write, at           3419655000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           3423375000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           3425235000
 test target 1 - Starting Memory Read, at           3426615000
 test target 1 - Starting Memory Read, at           3427815000
 test target 1 - Starting Memory Read, at           3429555000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           3435045000
 test target 2 - Starting Config Write, at           3436005000
 test target 1 - Starting Memory Write, at           3436785000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           3437055000
 test target 1 - Starting Memory Write, at           3437985000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           3438255000
 test target 1 - Starting Memory Write, at           3439185000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           3440595000
 test target 1 - Starting Memory Read, at           3442695000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           3442965000
 test target 1 - Starting Memory Read, at           3444855000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           3446505000
 test master 2 - Starting Memory Write, at           3446505000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           3446565000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3447435000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3447465000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3447765000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3447795000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3448635000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3448665000
 test target 1 - Starting Memory Write, at           3450315000
 test master 2 - Starting Memory Write, at           3450315000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3451995000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3452025000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3453555000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3453585000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3455115000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3455145000
 test target 1 - Starting Memory Write, at           3457005000
 test master 2 - Starting Memory Write, at           3457005000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           3457065000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3458655000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3458685000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3458985000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3459015000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3459855000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3459885000
 test target 1 - Starting Memory Write, at           3460995000
 test master 2 - Starting Memory Write, at           3460995000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           3463725000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           3465255000
 test master 1 - Starting Memory Read, at           3465645000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           3465855000
 test target 1 - Starting Config Write, at           3468105000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           3470295000
 test target 1 - Starting Memory Write, at           3470595000
 test target 1 - Starting Memory Write, at           3470895000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           3471495000
 test target 1 - Starting Memory Write, at           3471825000
 test target 1 - Starting Memory Write, at           3472155000
 test target 1 - Starting Memory Write, at           3472755000
 test target 1 - Starting Memory Write, at           3473145000
 test target 1 - Starting Memory Write, at           3473715000
 test target 1 - Starting Memory Write, at           3474465000
 test target 1 - Starting Memory Write, at           3474795000
 test target 1 - Starting Memory Write, at           3475545000
 test target 1 - Starting Memory Write, at           3475965000
 test target 1 - Starting Memory Write, at           3476625000
 test target 1 - Starting Memory Write, at           3482235000
 test target 1 - Starting Memory Write, at           3482565000
 test target 1 - Starting Memory Write, at           3482895000
 test target 1 - Starting Memory Write, at           3483315000
 test target 1 - Starting Memory Write, at           3483735000
 test target 1 - Starting Memory Read, at           3489225000
 test target 1 - Starting Memory Read, at           3490425000
 test target 1 - Starting Memory Read, at           3491625000
 test target 1 - Starting Memory Read, at           3492825000
 test target 1 - Starting Memory Read, at           3494025000
 test target 1 - Starting Memory Read, at           3495225000
 test target 1 - Starting Memory Read, at           3496425000
 test target 1 - Starting Memory Read, at           3497625000
 test target 1 - Starting Memory Read, at           3498825000
 test target 1 - Starting Memory Read, at           3500025000
 test target 1 - Starting Memory Read, at           3501225000
 test target 1 - Starting Memory Read, at           3502425000
 test target 1 - Starting Memory Read, at           3503625000
 test target 1 - Starting Memory Read, at           3504825000
 test target 1 - Starting Memory Read, at           3506025000
 test target 1 - Starting Memory Read, at           3507225000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           3508305000
 test target 1 - Starting Memory Read, at           3508605000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           3510555000
 test target 1 - Starting Memory Read, at           3512265000
 test target 1 - Starting Memory Read, at           3513015000
 test target 1 - Starting Memory Read, at           3513825000
 test target 1 - Starting Memory Read, at           3514665000
 test target 1 - Starting Memory Read, at           3515565000
 test target 1 - Starting Memory Read, at           3516735000
 test target 1 - Starting Memory Read, at           3517965000
 test target 1 - Starting Memory Read, at           3518835000
 test target 1 - Starting Memory Read, at           3521925000
 test target 1 - Starting Memory Read, at           3524355000
 test target 1 - Starting Memory Read, at           3525195000
 test target 1 - Starting Memory Read, at           3526095000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           3527385000
 test master 1 - Starting Memory Write, at           3527745000
 test target 1 - Starting Memory Write, at           3527745000
 test target 1 - Starting Memory Write, at           3528045000
 test target 1 - Starting Memory Read, at           3528675000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           3531045000
 test master 1 - Starting Memory Write, at           3531405000
 test target 1 - Starting Memory Write, at           3531405000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           3536085000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           3537255000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           3561165000
 test target 1 - Starting Config Write, at           3562125000
 test target 1 - Starting Config Write, at           3563085000
 test target 2 - Starting Config Write, at           3564045000
 test target 2 - Starting Config Write, at           3565005000
 test target 2 - Starting Config Write, at           3565965000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           3567765000
 test target 1 - Starting Memory Read, at           3568155000
 test target 1 - Starting Memory Write, at           3568875000
 test target 1 - Starting Memory Read, at           3569265000
 test target 1 - Starting Memory Write, at           3570435000
 test target 1 - Starting Memory Read, at           3571575000
 test target 1 - Starting Memory Read, at           3572295000
 test target 1 - Starting Memory Read, at           3573105000
 test target 1 - Starting Memory Read, at           3573795000
 test target 1 - Starting Memory Read, at           3574755000
 test target 1 - Starting Memory Read, at           3575985000
 test target 1 - Starting Memory Read, at           3576975000
 test target 1 - Starting Memory Read, at           3578205000
 test target 1 - Starting Memory Read, at           3579195000
 test target 1 - Starting Memory Read, at           3581445000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           3587265000
 test target 1 - Starting Memory Read, at           3587655000
 test target 1 - Starting Memory Write, at           3588375000
 test target 1 - Starting Memory Read, at           3588765000
 test target 1 - Starting Memory Write, at           3589935000
 test target 1 - Starting Memory Read, at           3591075000
 test target 1 - Starting Memory Read, at           3591795000
 test target 1 - Starting Memory Read, at           3592605000
 test target 1 - Starting Memory Read, at           3593295000
 test target 1 - Starting Memory Read, at           3594255000
 test target 1 - Starting Memory Read, at           3595485000
 test target 1 - Starting Memory Read, at           3596475000
 test target 1 - Starting Memory Read, at           3597705000
 test target 1 - Starting Memory Read, at           3598695000
 test target 1 - Starting Memory Read, at           3600945000
 test target 1 - Starting Memory Write, at           3606765000
 test target 1 - Starting Memory Read, at           3607155000
 test target 1 - Starting Memory Write, at           3607875000
 test target 1 - Starting Memory Read, at           3608265000
 test target 1 - Starting Memory Write, at           3609435000
 test target 1 - Starting Memory Read, at           3610575000
 test target 1 - Starting Memory Read, at           3611295000
 test target 1 - Starting Memory Read, at           3612105000
 test target 1 - Starting Memory Read, at           3612795000
 test target 1 - Starting Memory Read, at           3613755000
 test target 1 - Starting Memory Read, at           3614985000
 test target 1 - Starting Memory Read, at           3615975000
 test target 1 - Starting Memory Read, at           3617205000
 test target 1 - Starting Memory Read, at           3618195000
 test target 1 - Starting Memory Read, at           3620445000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           3630885000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           3636765000
 test target 1 - Starting Memory Write, at           3637725000
 test target 1 - Starting Memory Read, at           3638295000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           3639645000
 test target 1 - Starting Config Write, at           3641625000
 test target 1 - Starting Memory Read, at           3642375000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           3643785000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           3645945000
 test target 1 - Starting Memory Write, at           3647145000
 test target 1 - Starting Memory Write, at           3647565000
 test target 1 - Starting Memory Read, at           3647955000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           3650295000
 test target 1 - Starting Memory Write, at           3653175000
 test target 1 - Starting Memory Write, at           3653685000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           3657435000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           3659295000
 test target 1 - Starting Memory Read, at           3660675000
 test target 1 - Starting Memory Read, at           3661875000
 test target 1 - Starting Memory Read, at           3663615000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           3669105000
 test target 2 - Starting Config Write, at           3670065000
 test target 1 - Starting Memory Write, at           3670845000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           3671145000
 test target 1 - Starting Memory Write, at           3672045000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           3672345000
 test target 1 - Starting Memory Write, at           3673245000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           3674655000
 test target 1 - Starting Memory Read, at           3676755000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           3677055000
 test target 1 - Starting Memory Read, at           3678915000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           3680565000
 test master 2 - Starting Memory Write, at           3680565000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           3680625000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3681555000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3681585000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3681885000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3681915000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3682755000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3682785000
 test target 1 - Starting Memory Write, at           3684435000
 test master 2 - Starting Memory Write, at           3684435000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3686175000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3686205000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3687735000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3687765000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3689295000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3689325000
 test target 1 - Starting Memory Write, at           3691185000
 test master 2 - Starting Memory Write, at           3691185000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           3691245000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3692895000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3692925000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3693225000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3693255000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3694095000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3694125000
 test target 1 - Starting Memory Write, at           3695235000
 test master 2 - Starting Memory Write, at           3695235000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           3697965000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           3699495000
 test master 1 - Starting Memory Read, at           3699885000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           3700095000
 test target 1 - Starting Config Write, at           3702345000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           3704535000
 test target 1 - Starting Memory Write, at           3704865000
 test target 1 - Starting Memory Write, at           3705195000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           3705795000
 test target 1 - Starting Memory Write, at           3706155000
 test target 1 - Starting Memory Write, at           3706515000
 test target 1 - Starting Memory Write, at           3707115000
 test target 1 - Starting Memory Write, at           3707535000
 test target 1 - Starting Memory Write, at           3708135000
 test target 1 - Starting Memory Write, at           3708915000
 test target 1 - Starting Memory Write, at           3709275000
 test target 1 - Starting Memory Write, at           3710055000
 test target 1 - Starting Memory Write, at           3710505000
 test target 1 - Starting Memory Write, at           3711195000
 test target 1 - Starting Memory Write, at           3716835000
 test target 1 - Starting Memory Write, at           3717195000
 test target 1 - Starting Memory Write, at           3717555000
 test target 1 - Starting Memory Write, at           3718005000
 test target 1 - Starting Memory Write, at           3718455000
 test target 1 - Starting Memory Read, at           3723975000
 test target 1 - Starting Memory Read, at           3725295000
 test target 1 - Starting Memory Read, at           3726495000
 test target 1 - Starting Memory Read, at           3727695000
 test target 1 - Starting Memory Read, at           3728895000
 test target 1 - Starting Memory Read, at           3730095000
 test target 1 - Starting Memory Read, at           3731295000
 test target 1 - Starting Memory Read, at           3732495000
 test target 1 - Starting Memory Read, at           3733695000
 test target 1 - Starting Memory Read, at           3734895000
 test target 1 - Starting Memory Read, at           3736095000
 test target 1 - Starting Memory Read, at           3737295000
 test target 1 - Starting Memory Read, at           3738495000
 test target 1 - Starting Memory Read, at           3739695000
 test target 1 - Starting Memory Read, at           3740895000
 test target 1 - Starting Memory Read, at           3742095000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           3743175000
 test target 1 - Starting Memory Read, at           3743505000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           3745455000
 test target 1 - Starting Memory Read, at           3747195000
 test target 1 - Starting Memory Read, at           3747885000
 test target 1 - Starting Memory Read, at           3748725000
 test target 1 - Starting Memory Read, at           3749655000
 test target 1 - Starting Memory Read, at           3750525000
 test target 1 - Starting Memory Read, at           3751755000
 test target 1 - Starting Memory Read, at           3752985000
 test target 1 - Starting Memory Read, at           3753975000
 test target 1 - Starting Memory Read, at           3757065000
 test target 1 - Starting Memory Read, at           3759495000
 test target 1 - Starting Memory Read, at           3760335000
 test target 1 - Starting Memory Read, at           3761235000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           3762525000
 test master 1 - Starting Memory Write, at           3762915000
 test target 1 - Starting Memory Write, at           3762915000
 test target 1 - Starting Memory Write, at           3763245000
 test target 1 - Starting Memory Read, at           3763905000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           3766365000
 test master 1 - Starting Memory Write, at           3766755000
 test target 1 - Starting Memory Write, at           3766755000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3771615000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           3771915000
 test master 2 - Starting Memory Read, at           3772155000
 test master 2 - Starting Memory Read, at           3772395000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3773895000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           3774315000
 test master 2 - Starting Memory Read, at           3774555000
 test master 2 - Starting Memory Read, at           3774795000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3776115000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3776625000
 test master 2 - Starting Memory Read Line Multiple, at           3776865000
 test master 2 - Starting Memory Read Line Multiple, at           3777135000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3778875000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3785895000
 test master 2 - Starting Memory Read Line Multiple, at           3786135000
 test master 2 - Starting Memory Read Line Multiple, at           3786405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3787185000
 test master 2 - Starting Memory Read Line Multiple, at           3787425000
 test master 2 - Starting Memory Read Line Multiple, at           3787725000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3788505000
 test master 2 - Starting Memory Read Line Multiple, at           3788745000
 test master 2 - Starting Memory Read Line Multiple, at           3789045000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3789825000
 test master 2 - Starting Memory Read Line Multiple, at           3790065000
 test master 2 - Starting Memory Read Line Multiple, at           3790365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3791145000
 test master 2 - Starting Memory Read Line Multiple, at           3791385000
 test master 2 - Starting Memory Read Line Multiple, at           3791685000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3792465000
 test master 2 - Starting Memory Read Line Multiple, at           3792705000
 test master 2 - Starting Memory Read Line Multiple, at           3793005000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3793785000
 test master 2 - Starting Memory Read Line Multiple, at           3794025000
 test master 2 - Starting Memory Read Line Multiple, at           3794325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3795105000
 test master 2 - Starting Memory Read Line Multiple, at           3795345000
 test master 2 - Starting Memory Read Line Multiple, at           3795645000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           3796425000
 test master 2 - Starting Memory Read Line, at           3796665000
 test master 2 - Starting Memory Read Line, at           3796905000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           3797415000
 test master 2 - Starting Memory Read Line, at           3797655000
 test master 2 - Starting Memory Read Line, at           3797895000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3799005000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3800445000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3803025000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3804645000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           3808875000
 test master 2 - Starting Memory Write, at           3809175000
 test master 2 - Starting Memory Write, at           3809475000
 test master 2 - Starting Memory Write, at           3809775000
 test master 2 - Starting Memory Write, at           3810075000
 test master 1 - Starting Memory Read, at           3810495000
 test master 1 - Starting Memory Read, at           3810855000
 test master 1 - Starting Memory Read, at           3811395000
 test master 1 - Starting Memory Read, at           3811755000
 test master 1 - Starting Memory Read, at           3812295000
 test master 1 - Starting Memory Read, at           3812655000
 test master 2 - Starting Memory Write, at           3813855000
 test master 2 - Starting Memory Write, at           3814155000
 test master 2 - Starting Memory Write, at           3814455000
 test master 2 - Starting Memory Write, at           3814755000
 test master 2 - Starting Memory Write, at           3815055000
 test master 1 - Starting Memory Read, at           3815475000
 test master 1 - Starting Memory Read, at           3815835000
 test master 1 - Starting Memory Read, at           3816375000
 test master 1 - Starting Memory Read, at           3816735000
 test master 1 - Starting Memory Read, at           3817275000
 test master 1 - Starting Memory Read, at           3817635000
 test master 2 - Starting Memory Write, at           3819255000
 test master 2 - Starting Memory Write, at           3820305000
 test master 2 - Starting Memory Write, at           3821385000
 test master 2 - Starting Memory Write, at           3822465000
 test master 2 - Starting Memory Write, at           3824535000
 test master 2 - Starting Memory Write, at           3825585000
 test master 2 - Starting Memory Write, at           3826665000
 test master 2 - Starting Memory Write, at           3827745000
 test master 2 - Starting Memory Write, at           3829815000
 test master 2 - Starting Memory Write, at           3831705000
 test master 2 - Starting Memory Write, at           3833625000
 test master 2 - Starting Memory Write, at           3835545000
 test master 2 - Starting Memory Write, at           3838455000
 test master 2 - Starting Memory Write, at           3840555000
 test master 2 - Starting Memory Write, at           3842655000
 test master 2 - Starting Memory Write, at           3844755000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           3848985000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3849015000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3850875000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           3851175000
 test master 2 - Starting Memory Read, at           3851415000
 test master 2 - Starting Memory Read, at           3851655000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3853155000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           3853575000
 test master 2 - Starting Memory Read, at           3853815000
 test master 2 - Starting Memory Read, at           3854055000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3855375000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3855885000
 test master 2 - Starting Memory Read Line Multiple, at           3856125000
 test master 2 - Starting Memory Read Line Multiple, at           3856395000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3858135000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3865155000
 test master 2 - Starting Memory Read Line Multiple, at           3865395000
 test master 2 - Starting Memory Read Line Multiple, at           3865665000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3866445000
 test master 2 - Starting Memory Read Line Multiple, at           3866685000
 test master 2 - Starting Memory Read Line Multiple, at           3866985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3867765000
 test master 2 - Starting Memory Read Line Multiple, at           3868005000
 test master 2 - Starting Memory Read Line Multiple, at           3868305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3869085000
 test master 2 - Starting Memory Read Line Multiple, at           3869325000
 test master 2 - Starting Memory Read Line Multiple, at           3869625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3870405000
 test master 2 - Starting Memory Read Line Multiple, at           3870645000
 test master 2 - Starting Memory Read Line Multiple, at           3870945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3871725000
 test master 2 - Starting Memory Read Line Multiple, at           3871965000
 test master 2 - Starting Memory Read Line Multiple, at           3872265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3873045000
 test master 2 - Starting Memory Read Line Multiple, at           3873285000
 test master 2 - Starting Memory Read Line Multiple, at           3873585000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3874365000
 test master 2 - Starting Memory Read Line Multiple, at           3874605000
 test master 2 - Starting Memory Read Line Multiple, at           3874905000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           3875685000
 test master 2 - Starting Memory Read Line, at           3875925000
 test master 2 - Starting Memory Read Line, at           3876165000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           3876675000
 test master 2 - Starting Memory Read Line, at           3876915000
 test master 2 - Starting Memory Read Line, at           3877155000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3878265000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3879705000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3882285000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3883905000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           3888135000
 test master 2 - Starting Memory Write, at           3888435000
 test master 2 - Starting Memory Write, at           3888735000
 test master 2 - Starting Memory Write, at           3889035000
 test master 2 - Starting Memory Write, at           3889335000
 test master 1 - Starting Memory Read, at           3889755000
 test master 1 - Starting Memory Read, at           3890115000
 test master 1 - Starting Memory Read, at           3890655000
 test master 1 - Starting Memory Read, at           3891015000
 test master 1 - Starting Memory Read, at           3891555000
 test master 1 - Starting Memory Read, at           3891915000
 test master 2 - Starting Memory Write, at           3893115000
 test master 2 - Starting Memory Write, at           3893415000
 test master 2 - Starting Memory Write, at           3893715000
 test master 2 - Starting Memory Write, at           3894015000
 test master 2 - Starting Memory Write, at           3894315000
 test master 1 - Starting Memory Read, at           3894735000
 test master 1 - Starting Memory Read, at           3895095000
 test master 1 - Starting Memory Read, at           3895635000
 test master 1 - Starting Memory Read, at           3895995000
 test master 1 - Starting Memory Read, at           3896535000
 test master 1 - Starting Memory Read, at           3896895000
 test master 2 - Starting Memory Write, at           3898515000
 test master 2 - Starting Memory Write, at           3899565000
 test master 2 - Starting Memory Write, at           3900645000
 test master 2 - Starting Memory Write, at           3901725000
 test master 2 - Starting Memory Write, at           3903795000
 test master 2 - Starting Memory Write, at           3904845000
 test master 2 - Starting Memory Write, at           3905925000
 test master 2 - Starting Memory Write, at           3907005000
 test master 2 - Starting Memory Write, at           3909075000
 test master 2 - Starting Memory Write, at           3910965000
 test master 2 - Starting Memory Write, at           3912885000
 test master 2 - Starting Memory Write, at           3914805000
 test master 2 - Starting Memory Write, at           3917715000
 test master 2 - Starting Memory Write, at           3919815000
 test master 2 - Starting Memory Write, at           3921915000
 test master 2 - Starting Memory Write, at           3924015000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           3928245000
*** monitor - CBE Bus Changed when TRDY Desserted, at           3928275000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3930135000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           3930435000
 test master 2 - Starting Memory Read, at           3930675000
 test master 2 - Starting Memory Read, at           3930915000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3932415000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           3932835000
 test master 2 - Starting Memory Read, at           3933075000
 test master 2 - Starting Memory Read, at           3933315000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3934635000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3935145000
 test master 2 - Starting Memory Read Line Multiple, at           3935385000
 test master 2 - Starting Memory Read Line Multiple, at           3935655000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3937395000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3944415000
 test master 2 - Starting Memory Read Line Multiple, at           3944655000
 test master 2 - Starting Memory Read Line Multiple, at           3944925000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3945705000
 test master 2 - Starting Memory Read Line Multiple, at           3945945000
 test master 2 - Starting Memory Read Line Multiple, at           3946245000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3947025000
 test master 2 - Starting Memory Read Line Multiple, at           3947265000
 test master 2 - Starting Memory Read Line Multiple, at           3947565000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3948345000
 test master 2 - Starting Memory Read Line Multiple, at           3948585000
 test master 2 - Starting Memory Read Line Multiple, at           3948885000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3949665000
 test master 2 - Starting Memory Read Line Multiple, at           3949905000
 test master 2 - Starting Memory Read Line Multiple, at           3950205000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3950985000
 test master 2 - Starting Memory Read Line Multiple, at           3951225000
 test master 2 - Starting Memory Read Line Multiple, at           3951525000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3952305000
 test master 2 - Starting Memory Read Line Multiple, at           3952545000
 test master 2 - Starting Memory Read Line Multiple, at           3952845000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           3953625000
 test master 2 - Starting Memory Read Line Multiple, at           3953865000
 test master 2 - Starting Memory Read Line Multiple, at           3954165000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           3954945000
 test master 2 - Starting Memory Read Line, at           3955185000
 test master 2 - Starting Memory Read Line, at           3955425000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           3955935000
 test master 2 - Starting Memory Read Line, at           3956175000
 test master 2 - Starting Memory Read Line, at           3956415000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3957525000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3958965000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3961545000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           3963165000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           3967395000
 test master 2 - Starting Memory Write, at           3967695000
 test master 2 - Starting Memory Write, at           3967995000
 test master 2 - Starting Memory Write, at           3968295000
 test master 2 - Starting Memory Write, at           3968595000
 test master 1 - Starting Memory Read, at           3969015000
 test master 1 - Starting Memory Read, at           3969375000
 test master 1 - Starting Memory Read, at           3969915000
 test master 1 - Starting Memory Read, at           3970275000
 test master 1 - Starting Memory Read, at           3970815000
 test master 1 - Starting Memory Read, at           3971175000
 test master 2 - Starting Memory Write, at           3972375000
 test master 2 - Starting Memory Write, at           3972675000
 test master 2 - Starting Memory Write, at           3972975000
 test master 2 - Starting Memory Write, at           3973275000
 test master 2 - Starting Memory Write, at           3973575000
 test master 1 - Starting Memory Read, at           3973995000
 test master 1 - Starting Memory Read, at           3974355000
 test master 1 - Starting Memory Read, at           3974895000
 test master 1 - Starting Memory Read, at           3975255000
 test master 1 - Starting Memory Read, at           3975795000
 test master 1 - Starting Memory Read, at           3976155000
 test master 2 - Starting Memory Write, at           3977775000
 test master 2 - Starting Memory Write, at           3978825000
 test master 2 - Starting Memory Write, at           3979905000
 test master 2 - Starting Memory Write, at           3980985000
 test master 2 - Starting Memory Write, at           3983055000
 test master 2 - Starting Memory Write, at           3984105000
 test master 2 - Starting Memory Write, at           3985185000
 test master 2 - Starting Memory Write, at           3986265000
 test master 2 - Starting Memory Write, at           3988335000
 test master 2 - Starting Memory Write, at           3990225000
 test master 2 - Starting Memory Write, at           3992145000
 test master 2 - Starting Memory Write, at           3994065000
 test master 2 - Starting Memory Write, at           3996975000
 test master 2 - Starting Memory Write, at           3999075000
 test master 2 - Starting Memory Write, at           4001175000
 test master 2 - Starting Memory Write, at           4003275000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           4007505000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4007535000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           4009395000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           4009695000
 test master 2 - Starting Memory Read, at           4009935000
 test master 2 - Starting Memory Read, at           4010175000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           4011675000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           4012095000
 test master 2 - Starting Memory Read, at           4012335000
 test master 2 - Starting Memory Read, at           4012575000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           4013895000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           4014405000
 test master 2 - Starting Memory Read Line Multiple, at           4014645000
 test master 2 - Starting Memory Read Line Multiple, at           4014915000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           4016655000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           4023675000
 test master 2 - Starting Memory Read Line Multiple, at           4023915000
 test master 2 - Starting Memory Read Line Multiple, at           4024185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           4024965000
 test master 2 - Starting Memory Read Line Multiple, at           4025205000
 test master 2 - Starting Memory Read Line Multiple, at           4025505000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           4026285000
 test master 2 - Starting Memory Read Line Multiple, at           4026525000
 test master 2 - Starting Memory Read Line Multiple, at           4026825000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           4027605000
 test master 2 - Starting Memory Read Line Multiple, at           4027845000
 test master 2 - Starting Memory Read Line Multiple, at           4028145000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           4028925000
 test master 2 - Starting Memory Read Line Multiple, at           4029165000
 test master 2 - Starting Memory Read Line Multiple, at           4029465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           4030245000
 test master 2 - Starting Memory Read Line Multiple, at           4030485000
 test master 2 - Starting Memory Read Line Multiple, at           4030785000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           4031565000
 test master 2 - Starting Memory Read Line Multiple, at           4031805000
 test master 2 - Starting Memory Read Line Multiple, at           4032105000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           4032885000
 test master 2 - Starting Memory Read Line Multiple, at           4033125000
 test master 2 - Starting Memory Read Line Multiple, at           4033425000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           4034205000
 test master 2 - Starting Memory Read Line, at           4034445000
 test master 2 - Starting Memory Read Line, at           4034685000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           4035195000
 test master 2 - Starting Memory Read Line, at           4035435000
 test master 2 - Starting Memory Read Line, at           4035675000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           4036785000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           4038225000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           4040805000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           4042425000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           4046655000
 test master 2 - Starting Memory Write, at           4046955000
 test master 2 - Starting Memory Write, at           4047255000
 test master 2 - Starting Memory Write, at           4047555000
 test master 2 - Starting Memory Write, at           4047855000
 test master 1 - Starting Memory Read, at           4048275000
 test master 1 - Starting Memory Read, at           4048635000
 test master 1 - Starting Memory Read, at           4049175000
 test master 1 - Starting Memory Read, at           4049535000
 test master 1 - Starting Memory Read, at           4050075000
 test master 1 - Starting Memory Read, at           4050435000
 test master 2 - Starting Memory Write, at           4051635000
 test master 2 - Starting Memory Write, at           4051935000
 test master 2 - Starting Memory Write, at           4052235000
 test master 2 - Starting Memory Write, at           4052535000
 test master 2 - Starting Memory Write, at           4052835000
 test master 1 - Starting Memory Read, at           4053255000
 test master 1 - Starting Memory Read, at           4053615000
 test master 1 - Starting Memory Read, at           4054155000
 test master 1 - Starting Memory Read, at           4054515000
 test master 1 - Starting Memory Read, at           4055055000
 test master 1 - Starting Memory Read, at           4055415000
 test master 2 - Starting Memory Write, at           4057035000
 test master 2 - Starting Memory Write, at           4058085000
 test master 2 - Starting Memory Write, at           4059165000
 test master 2 - Starting Memory Write, at           4060245000
 test master 2 - Starting Memory Write, at           4062315000
 test master 2 - Starting Memory Write, at           4063365000
 test master 2 - Starting Memory Write, at           4064445000
 test master 2 - Starting Memory Write, at           4065525000
 test master 2 - Starting Memory Write, at           4067595000
 test master 2 - Starting Memory Write, at           4069485000
 test master 2 - Starting Memory Write, at           4071405000
 test master 2 - Starting Memory Write, at           4073325000
 test master 2 - Starting Memory Write, at           4076235000
 test master 2 - Starting Memory Write, at           4078335000
 test master 2 - Starting Memory Write, at           4080435000
 test master 2 - Starting Memory Write, at           4082535000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           4086765000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4086795000
 test master 1 - Starting Memory Read, at           4088655000
 test master 1 - Starting Memory Read, at           4089045000
 test master 1 - Starting Memory Read, at           4090155000
 test master 1 - Starting Memory Read, at           4090545000
 test master 1 - Starting Memory Read Line, at           4091655000
 test master 1 - Starting Memory Read Line, at           4092045000
 test master 1 - Starting Memory Read Line, at           4093155000
 test master 1 - Starting Memory Read Line, at           4093545000
 test master 1 - Starting Memory Read Line, at           4094775000
 test master 1 - Starting Memory Read Line, at           4095225000
 test master 1 - Starting Memory Read Line, at           4096635000
 test master 1 - Starting Memory Read Line, at           4097085000
 test master 1 - Starting Memory Read Line Multiple, at           4098495000
 test master 1 - Starting Memory Read Line Multiple, at           4099005000
 test master 1 - Starting Memory Read Line Multiple, at           4100655000
 test master 1 - Starting Memory Read Line Multiple, at           4101165000
 test master 1 - Starting Memory Read Line, at           4102815000
 test master 1 - Starting Memory Read Line, at           4103265000
 test master 1 - Starting Memory Read, at           4105515000
 test master 1 - Starting Memory Read, at           4105905000
 test target 1 - Starting Config Write, at           4108785000
 test master 1 - Starting Memory Write, at           4109535000
 test master 1 - Starting Memory Write, at           4115205000
 test master 1 - Starting Memory Write, at           4116555000
 test master 1 - Starting Memory Write, at           4121865000
 test master 1 - Starting Memory Write, at           4123215000
 test master 1 - Starting Memory Read Line, at           4128885000
 test master 1 - Starting Memory Write, at           4130385000
 test master 1 - Starting Memory Read Line, at           4136055000
 test target 1 - Starting Config Write, at           4139145000
 test master 1 - Starting Memory Write, at           4139895000
 test master 1 - Starting Memory Write, at           4140075000
 test master 1 - Starting Memory Write, at           4140375000
 test master 1 - Starting Memory Read, at           4140555000
 test master 1 - Starting Memory Write, at           4140945000
 test master 1 - Starting Memory Read, at           4141125000
 test master 1 - Starting Memory Write, at           4142595000
 test master 1 - Starting Memory Write, at           4149615000
 test master 2 - Starting Memory Read Line, at           4156755000
 test master 2 - Starting Memory Read Line, at           4157175000
 test master 2 - Starting Memory Read Line, at           4157715000
 test master 2 - Starting Memory Read Line, at           4158135000
 test master 1 - Starting Memory Write, at           4158765000
 test master 1 - Starting Memory Write, at           4159095000
 test master 1 - Starting Memory Write, at           4159455000
 test master 2 - Starting Memory Read Line, at           4159935000
 test master 2 - Starting Memory Read Line, at           4160325000
 test master 2 - Starting Memory Read Line, at           4160655000
 test master 2 - Starting Memory Read Line, at           4161045000
 test master 2 - Starting Memory Read Line Multiple, at           4161405000
 test master 2 - Starting Memory Read Line Multiple, at           4161795000
 test master 1 - Starting Memory Write, at           4163535000
 test master 1 - Starting Memory Write, at           4163865000
 test master 2 - Starting Memory Read, at           4164345000
 test master 2 - Starting Memory Read, at           4164735000
 test master 2 - Starting Memory Read, at           4165065000
 test master 2 - Starting Memory Read, at           4165455000
 test master 1 - Starting Memory Write, at           4166985000
 test master 1 - Starting Memory Read, at           4167195000
 test master 1 - Starting Memory Write, at           4167405000
 test master 1 - Starting Memory Read, at           4167615000
 test master 1 - Starting Memory Write, at           4167825000
 test master 1 - Starting Memory Read, at           4168035000
 test master 1 - Starting Memory Read, at           4168245000
 test master 1 - Starting Memory Write, at           4168455000
 test master 1 - Starting Memory Write, at           4168665000
 test master 1 - Starting Memory Read, at           4168875000
 test master 1 - Starting Memory Write, at           4169085000
 test master 1 - Starting Memory Write, at           4169295000
 test master 1 - Starting Memory Write, at           4169505000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at           4173375000
 test target 1 - Starting Memory Write, at           4173705000
 test master 1 - Starting Memory Write, at           4174005000
 test target 1 - Starting Memory Write, at           4174245000
 test target 1 - Starting Memory Write, at           4174575000
 test target 1 - Starting Memory Write, at           4174905000
 test master 1 - Starting Memory Write, at           4175325000
 test target 1 - Starting Memory Write, at           4175895000
 test target 1 - Starting Memory Write, at           4176555000
 test target 1 - Starting Memory Write, at           4176915000
 test master 1 - Starting Memory Write, at           4177245000
 test target 1 - Starting Memory Write, at           4177665000
 test target 1 - Starting Memory Write, at           4178025000
 test target 1 - Starting Memory Write, at           4178385000
 test master 1 - Starting Memory Write, at           4178985000
 test target 1 - Starting Memory Write, at           4179885000
 test target 1 - Starting Memory Write, at           4180755000
 test target 1 - Starting Memory Write, at           4181085000
 test master 1 - Starting Memory Read, at           4181385000
 test target 1 - Starting Memory Write, at           4181625000
 test master 1 - Starting Memory Read, at           4181925000
 test target 1 - Starting Memory Write, at           4182165000
 test master 1 - Starting Memory Read, at           4182465000
 test target 1 - Starting Memory Write, at           4182705000
 test master 1 - Starting Memory Read, at           4183005000
 test target 1 - Starting Memory Write, at           4183245000
 test master 1 - Starting Memory Read, at           4183545000
 test target 1 - Starting Memory Write, at           4183785000
 test master 1 - Starting Memory Write, at           4184085000
 test target 1 - Starting Memory Write, at           4184325000
 test target 1 - Starting Memory Write, at           4184655000
 test target 1 - Starting Memory Write, at           4184985000
 test target 1 - Starting Memory Read, at           4185375000
 test master 1 - Starting Memory Write, at           4185795000
 test master 1 - Starting Memory Read, at           4186095000
 test target 1 - Starting Memory Write, at           4186665000
 test master 1 - Starting Memory Write, at           4187175000
 test target 1 - Starting Memory Read, at           4187685000
 test target 1 - Starting Memory Write, at           4188615000
 test master 1 - Starting Memory Read, at           4189035000
 test master 1 - Starting Memory Write, at           4189425000
 test master 1 - Starting Memory Write, at           4189845000
 test master 1 - Starting Memory Read, at           4190145000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           4192575000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           4193625000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           4218015000
 test target 1 - Starting Config Write, at           4218915000
 test target 1 - Starting Config Write, at           4219815000
 test target 2 - Starting Config Write, at           4220715000
 test target 2 - Starting Config Write, at           4221615000
 test target 2 - Starting Config Write, at           4222515000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           4224405000
 test target 1 - Starting Memory Read, at           4224705000
 test target 1 - Starting Memory Write, at           4225365000
 test target 1 - Starting Memory Read, at           4225665000
 test target 1 - Starting Memory Write, at           4226835000
 test target 1 - Starting Memory Read, at           4227795000
 test target 1 - Starting Memory Read, at           4228425000
 test target 1 - Starting Memory Read, at           4229025000
 test target 1 - Starting Memory Read, at           4229655000
 test target 1 - Starting Memory Read, at           4230435000
 test target 1 - Starting Memory Read, at           4231545000
 test target 1 - Starting Memory Read, at           4232535000
 test target 1 - Starting Memory Read, at           4233615000
 test target 1 - Starting Memory Read, at           4234575000
 test target 1 - Starting Memory Read, at           4236345000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           4242525000
 test target 1 - Starting Memory Read, at           4242825000
 test target 1 - Starting Memory Write, at           4243485000
 test target 1 - Starting Memory Read, at           4243785000
 test target 1 - Starting Memory Write, at           4244955000
 test target 1 - Starting Memory Read, at           4245915000
 test target 1 - Starting Memory Read, at           4246545000
 test target 1 - Starting Memory Read, at           4247145000
 test target 1 - Starting Memory Read, at           4247775000
 test target 1 - Starting Memory Read, at           4248555000
 test target 1 - Starting Memory Read, at           4249665000
 test target 1 - Starting Memory Read, at           4250655000
 test target 1 - Starting Memory Read, at           4251735000
 test target 1 - Starting Memory Read, at           4252695000
 test target 1 - Starting Memory Read, at           4254465000
 test target 1 - Starting Memory Write, at           4260645000
 test target 1 - Starting Memory Read, at           4260945000
 test target 1 - Starting Memory Write, at           4261605000
 test target 1 - Starting Memory Read, at           4261905000
 test target 1 - Starting Memory Write, at           4263075000
 test target 1 - Starting Memory Read, at           4264035000
 test target 1 - Starting Memory Read, at           4264665000
 test target 1 - Starting Memory Read, at           4265265000
 test target 1 - Starting Memory Read, at           4265895000
 test target 1 - Starting Memory Read, at           4266675000
 test target 1 - Starting Memory Read, at           4267785000
 test target 1 - Starting Memory Read, at           4268775000
 test target 1 - Starting Memory Read, at           4269855000
 test target 1 - Starting Memory Read, at           4270815000
 test target 1 - Starting Memory Read, at           4272585000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           4283925000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           4290105000
 test target 1 - Starting Memory Write, at           4291035000
 test target 1 - Starting Memory Read, at           4291455000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           4292745000
 test target 1 - Starting Config Write, at           4294605000
 test target 1 - Starting Memory Read, at           4295295000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           4296735000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           4298775000
 test target 1 - Starting Memory Write, at           4299945000
 test target 1 - Starting Memory Write, at           4300275000
 test target 1 - Starting Memory Read, at           4300575000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           4302975000
 test target 1 - Starting Memory Write, at           4305975000
 test target 1 - Starting Memory Write, at           4306365000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           4310235000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           4312155000
 test target 1 - Starting Memory Read, at           4313535000
 test target 1 - Starting Memory Read, at           4314585000
 test target 1 - Starting Memory Read, at           4316235000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           4321965000
 test target 2 - Starting Config Write, at           4322865000
 test target 1 - Starting Memory Write, at           4323555000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           4323765000
 test target 1 - Starting Memory Write, at           4324725000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           4324935000
 test target 1 - Starting Memory Write, at           4325895000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           4327275000
 test target 1 - Starting Memory Read, at           4329435000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           4329645000
 test target 1 - Starting Memory Read, at           4331655000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           4333365000
 test master 2 - Starting Memory Write, at           4333365000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           4333425000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4334295000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4334325000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4334625000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4334655000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4335525000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4335555000
 test target 1 - Starting Memory Write, at           4337325000
 test master 2 - Starting Memory Write, at           4337325000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4339065000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4339095000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4340745000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4340775000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4342425000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4342455000
 test target 1 - Starting Memory Write, at           4344465000
 test master 2 - Starting Memory Write, at           4344465000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           4344525000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4346175000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4346205000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4346505000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4346535000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4347405000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4347435000
 test target 1 - Starting Memory Write, at           4348605000
 test master 2 - Starting Memory Write, at           4348605000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           4351515000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           4353165000
 test master 1 - Starting Memory Read, at           4353645000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           4353855000
 test target 1 - Starting Config Write, at           4356285000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           4358775000
 test target 1 - Starting Memory Write, at           4359015000
 test target 1 - Starting Memory Write, at           4359255000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           4359795000
 test target 1 - Starting Memory Write, at           4360065000
 test target 1 - Starting Memory Write, at           4360335000
 test target 1 - Starting Memory Write, at           4360875000
 test target 1 - Starting Memory Write, at           4361175000
 test target 1 - Starting Memory Write, at           4361715000
 test target 1 - Starting Memory Write, at           4362435000
 test target 1 - Starting Memory Write, at           4362705000
 test target 1 - Starting Memory Write, at           4363395000
 test target 1 - Starting Memory Write, at           4363725000
 test target 1 - Starting Memory Write, at           4364355000
 test target 1 - Starting Memory Write, at           4371075000
 test target 1 - Starting Memory Write, at           4371345000
 test target 1 - Starting Memory Write, at           4371615000
 test target 1 - Starting Memory Write, at           4371945000
 test target 1 - Starting Memory Write, at           4372275000
 test target 1 - Starting Memory Read, at           4375995000
 test target 1 - Starting Memory Read, at           4377075000
 test target 1 - Starting Memory Read, at           4378155000
 test target 1 - Starting Memory Read, at           4379235000
 test target 1 - Starting Memory Read, at           4380315000
 test target 1 - Starting Memory Read, at           4381395000
 test target 1 - Starting Memory Read, at           4382475000
 test target 1 - Starting Memory Read, at           4383555000
 test target 1 - Starting Memory Read, at           4384635000
 test target 1 - Starting Memory Read, at           4385715000
 test target 1 - Starting Memory Read, at           4386795000
 test target 1 - Starting Memory Read, at           4387875000
 test target 1 - Starting Memory Read, at           4388955000
 test target 1 - Starting Memory Read, at           4390035000
 test target 1 - Starting Memory Read, at           4391115000
 test target 1 - Starting Memory Read, at           4392195000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           4393125000
 test target 1 - Starting Memory Read, at           4393365000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           4395525000
 test target 1 - Starting Memory Read, at           4396725000
 test target 1 - Starting Memory Read, at           4397355000
 test target 1 - Starting Memory Read, at           4398105000
 test target 1 - Starting Memory Read, at           4398945000
 test target 1 - Starting Memory Read, at           4399785000
 test target 1 - Starting Memory Read, at           4401015000
 test target 1 - Starting Memory Read, at           4402095000
 test target 1 - Starting Memory Read, at           4403055000
 test target 1 - Starting Memory Read, at           4405905000
 test target 1 - Starting Memory Read, at           4407855000
 test target 1 - Starting Memory Read, at           4408695000
 test target 1 - Starting Memory Read, at           4409475000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           4410855000
 test master 1 - Starting Memory Write, at           4411125000
 test target 1 - Starting Memory Write, at           4411125000
 test target 1 - Starting Memory Write, at           4411365000
 test target 1 - Starting Memory Read, at           4411845000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           4413945000
 test master 1 - Starting Memory Write, at           4414215000
 test target 1 - Starting Memory Write, at           4414215000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           4419105000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           4420275000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           4444785000
 test target 1 - Starting Config Write, at           4445685000
 test target 1 - Starting Config Write, at           4446585000
 test target 2 - Starting Config Write, at           4447485000
 test target 2 - Starting Config Write, at           4448385000
 test target 2 - Starting Config Write, at           4449285000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           4451175000
 test target 1 - Starting Memory Read, at           4451505000
 test target 1 - Starting Memory Write, at           4452315000
 test target 1 - Starting Memory Read, at           4452645000
 test target 1 - Starting Memory Write, at           4453935000
 test target 1 - Starting Memory Read, at           4454895000
 test target 1 - Starting Memory Read, at           4455525000
 test target 1 - Starting Memory Read, at           4456155000
 test target 1 - Starting Memory Read, at           4456935000
 test target 1 - Starting Memory Read, at           4457895000
 test target 1 - Starting Memory Read, at           4459155000
 test target 1 - Starting Memory Read, at           4460115000
 test target 1 - Starting Memory Read, at           4461375000
 test target 1 - Starting Memory Read, at           4462335000
 test target 1 - Starting Memory Read, at           4464285000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           4470465000
 test target 1 - Starting Memory Read, at           4470795000
 test target 1 - Starting Memory Write, at           4471575000
 test target 1 - Starting Memory Read, at           4471905000
 test target 1 - Starting Memory Write, at           4473225000
 test target 1 - Starting Memory Read, at           4474215000
 test target 1 - Starting Memory Read, at           4474995000
 test target 1 - Starting Memory Read, at           4475775000
 test target 1 - Starting Memory Read, at           4476555000
 test target 1 - Starting Memory Read, at           4477515000
 test target 1 - Starting Memory Read, at           4478775000
 test target 1 - Starting Memory Read, at           4479735000
 test target 1 - Starting Memory Read, at           4480995000
 test target 1 - Starting Memory Read, at           4481955000
 test target 1 - Starting Memory Read, at           4483905000
 test target 1 - Starting Memory Write, at           4490085000
 test target 1 - Starting Memory Read, at           4490415000
 test target 1 - Starting Memory Write, at           4491195000
 test target 1 - Starting Memory Read, at           4491525000
 test target 1 - Starting Memory Write, at           4492845000
 test target 1 - Starting Memory Read, at           4493835000
 test target 1 - Starting Memory Read, at           4494615000
 test target 1 - Starting Memory Read, at           4495395000
 test target 1 - Starting Memory Read, at           4496175000
 test target 1 - Starting Memory Read, at           4497135000
 test target 1 - Starting Memory Read, at           4498395000
 test target 1 - Starting Memory Read, at           4499355000
 test target 1 - Starting Memory Read, at           4500615000
 test target 1 - Starting Memory Read, at           4501575000
 test target 1 - Starting Memory Read, at           4503525000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           4514865000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           4521045000
 test target 1 - Starting Memory Write, at           4521975000
 test target 1 - Starting Memory Read, at           4522425000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           4523685000
 test target 1 - Starting Config Write, at           4525545000
 test target 1 - Starting Memory Read, at           4526235000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           4527825000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           4529895000
 test target 1 - Starting Memory Write, at           4531065000
 test target 1 - Starting Memory Write, at           4531425000
 test target 1 - Starting Memory Read, at           4531755000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           4534095000
 test target 1 - Starting Memory Write, at           4537125000
 test target 1 - Starting Memory Write, at           4537545000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           4541415000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           4543455000
 test target 1 - Starting Memory Read, at           4544895000
 test target 1 - Starting Memory Read, at           4546065000
 test target 1 - Starting Memory Read, at           4547775000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           4553655000
 test target 2 - Starting Config Write, at           4554555000
 test target 1 - Starting Memory Write, at           4555245000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           4555485000
 test target 1 - Starting Memory Write, at           4556445000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           4556685000
 test target 1 - Starting Memory Write, at           4557645000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           4559055000
 test target 1 - Starting Memory Read, at           4561215000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           4561455000
 test target 1 - Starting Memory Read, at           4563435000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           4565145000
 test master 2 - Starting Memory Write, at           4565145000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           4565205000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4566105000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4566135000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4566435000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4566465000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4567335000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4567365000
 test target 1 - Starting Memory Write, at           4569135000
 test master 2 - Starting Memory Write, at           4569135000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4570905000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4570935000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4572585000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4572615000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4574265000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4574295000
 test target 1 - Starting Memory Write, at           4576305000
 test master 2 - Starting Memory Write, at           4576305000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           4576365000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4578045000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4578075000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4578375000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4578405000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4579275000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4579305000
 test target 1 - Starting Memory Write, at           4580475000
 test master 2 - Starting Memory Write, at           4580475000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           4583415000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           4585065000
 test master 1 - Starting Memory Read, at           4585545000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           4585755000
 test target 1 - Starting Config Write, at           4588185000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           4590675000
 test target 1 - Starting Memory Write, at           4590945000
 test target 1 - Starting Memory Write, at           4591215000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           4591785000
 test target 1 - Starting Memory Write, at           4592085000
 test target 1 - Starting Memory Write, at           4592385000
 test target 1 - Starting Memory Write, at           4592955000
 test target 1 - Starting Memory Write, at           4593285000
 test target 1 - Starting Memory Write, at           4593855000
 test target 1 - Starting Memory Write, at           4594575000
 test target 1 - Starting Memory Write, at           4594875000
 test target 1 - Starting Memory Write, at           4595595000
 test target 1 - Starting Memory Write, at           4595955000
 test target 1 - Starting Memory Write, at           4596615000
 test target 1 - Starting Memory Write, at           4603365000
 test target 1 - Starting Memory Write, at           4603665000
 test target 1 - Starting Memory Write, at           4603965000
 test target 1 - Starting Memory Write, at           4604325000
 test target 1 - Starting Memory Write, at           4604685000
 test target 1 - Starting Memory Read, at           4608435000
 test target 1 - Starting Memory Read, at           4609665000
 test target 1 - Starting Memory Read, at           4610925000
 test target 1 - Starting Memory Read, at           4612155000
 test target 1 - Starting Memory Read, at           4613385000
 test target 1 - Starting Memory Read, at           4614645000
 test target 1 - Starting Memory Read, at           4615875000
 test target 1 - Starting Memory Read, at           4617105000
 test target 1 - Starting Memory Read, at           4618365000
 test target 1 - Starting Memory Read, at           4619595000
 test target 1 - Starting Memory Read, at           4620825000
 test target 1 - Starting Memory Read, at           4622085000
 test target 1 - Starting Memory Read, at           4623315000
 test target 1 - Starting Memory Read, at           4624545000
 test target 1 - Starting Memory Read, at           4625805000
 test target 1 - Starting Memory Read, at           4627035000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           4628115000
 test target 1 - Starting Memory Read, at           4628385000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           4630695000
 test target 1 - Starting Memory Read, at           4631925000
 test target 1 - Starting Memory Read, at           4632675000
 test target 1 - Starting Memory Read, at           4633425000
 test target 1 - Starting Memory Read, at           4634265000
 test target 1 - Starting Memory Read, at           4635105000
 test target 1 - Starting Memory Read, at           4636335000
 test target 1 - Starting Memory Read, at           4637565000
 test target 1 - Starting Memory Read, at           4638555000
 test target 1 - Starting Memory Read, at           4641525000
 test target 1 - Starting Memory Read, at           4643475000
 test target 1 - Starting Memory Read, at           4644435000
 test target 1 - Starting Memory Read, at           4645275000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           4646775000
 test master 1 - Starting Memory Write, at           4647075000
 test target 1 - Starting Memory Write, at           4647075000
 test target 1 - Starting Memory Write, at           4647345000
 test target 1 - Starting Memory Read, at           4647855000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           4649865000
 test master 1 - Starting Memory Write, at           4650165000
 test target 1 - Starting Memory Write, at           4650165000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           4655055000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           4656225000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           4680735000
 test target 1 - Starting Config Write, at           4681815000
 test target 1 - Starting Config Write, at           4682895000
 test target 2 - Starting Config Write, at           4683975000
 test target 2 - Starting Config Write, at           4685055000
 test target 2 - Starting Config Write, at           4686135000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           4688205000
 test target 1 - Starting Memory Read, at           4688565000
 test target 1 - Starting Memory Write, at           4689315000
 test target 1 - Starting Memory Read, at           4689675000
 test target 1 - Starting Memory Write, at           4690965000
 test target 1 - Starting Memory Read, at           4691955000
 test target 1 - Starting Memory Read, at           4692765000
 test target 1 - Starting Memory Read, at           4693545000
 test target 1 - Starting Memory Read, at           4694325000
 test target 1 - Starting Memory Read, at           4695255000
 test target 1 - Starting Memory Read, at           4696515000
 test target 1 - Starting Memory Read, at           4697475000
 test target 1 - Starting Memory Read, at           4698735000
 test target 1 - Starting Memory Read, at           4699695000
 test target 1 - Starting Memory Read, at           4701645000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           4707825000
 test target 1 - Starting Memory Read, at           4708185000
 test target 1 - Starting Memory Write, at           4708935000
 test target 1 - Starting Memory Read, at           4709295000
 test target 1 - Starting Memory Write, at           4710585000
 test target 1 - Starting Memory Read, at           4711575000
 test target 1 - Starting Memory Read, at           4712385000
 test target 1 - Starting Memory Read, at           4713165000
 test target 1 - Starting Memory Read, at           4713945000
 test target 1 - Starting Memory Read, at           4714875000
 test target 1 - Starting Memory Read, at           4716135000
 test target 1 - Starting Memory Read, at           4717095000
 test target 1 - Starting Memory Read, at           4718355000
 test target 1 - Starting Memory Read, at           4719315000
 test target 1 - Starting Memory Read, at           4721265000
 test target 1 - Starting Memory Write, at           4727445000
 test target 1 - Starting Memory Read, at           4727805000
 test target 1 - Starting Memory Write, at           4728555000
 test target 1 - Starting Memory Read, at           4728915000
 test target 1 - Starting Memory Write, at           4730205000
 test target 1 - Starting Memory Read, at           4731195000
 test target 1 - Starting Memory Read, at           4732005000
 test target 1 - Starting Memory Read, at           4732785000
 test target 1 - Starting Memory Read, at           4733565000
 test target 1 - Starting Memory Read, at           4734495000
 test target 1 - Starting Memory Read, at           4735755000
 test target 1 - Starting Memory Read, at           4736715000
 test target 1 - Starting Memory Read, at           4737975000
 test target 1 - Starting Memory Read, at           4738935000
 test target 1 - Starting Memory Read, at           4740885000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           4752225000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           4758585000
 test target 1 - Starting Memory Write, at           4759695000
 test target 1 - Starting Memory Read, at           4760175000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           4761405000
 test target 1 - Starting Config Write, at           4763445000
 test target 1 - Starting Memory Read, at           4764315000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           4765905000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           4768155000
 test target 1 - Starting Memory Write, at           4769505000
 test target 1 - Starting Memory Write, at           4769895000
 test target 1 - Starting Memory Read, at           4770255000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           4772715000
 test target 1 - Starting Memory Write, at           4775775000
 test target 1 - Starting Memory Write, at           4776225000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           4780155000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           4782195000
 test target 1 - Starting Memory Read, at           4783635000
 test target 1 - Starting Memory Read, at           4784805000
 test target 1 - Starting Memory Read, at           4786515000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           4792395000
 test target 2 - Starting Config Write, at           4793475000
 test target 1 - Starting Memory Write, at           4794345000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           4794615000
 test target 1 - Starting Memory Write, at           4795575000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           4795845000
 test target 1 - Starting Memory Write, at           4796805000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           4798275000
 test target 1 - Starting Memory Read, at           4800615000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           4800885000
 test target 1 - Starting Memory Read, at           4803015000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           4804875000
 test master 2 - Starting Memory Write, at           4804875000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           4804935000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4805865000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4805895000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4806195000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4806225000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4807095000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4807125000
 test target 1 - Starting Memory Write, at           4808895000
 test master 2 - Starting Memory Write, at           4808895000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4810695000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4810725000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4812375000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4812405000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4814055000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4814085000
 test target 1 - Starting Memory Write, at           4816095000
 test master 2 - Starting Memory Write, at           4816095000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           4816155000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4817865000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4817895000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4818195000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4818225000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4819095000
*** monitor - CBE Bus Changed when TRDY Desserted, at           4819125000
 test target 1 - Starting Memory Write, at           4820295000
 test master 2 - Starting Memory Write, at           4820295000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           4823265000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           4824915000
 test master 1 - Starting Memory Read, at           4825365000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           4825575000
 test target 1 - Starting Config Write, at           4828005000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           4830495000
 test target 1 - Starting Memory Write, at           4830795000
 test target 1 - Starting Memory Write, at           4831095000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           4831695000
 test target 1 - Starting Memory Write, at           4832025000
 test target 1 - Starting Memory Write, at           4832355000
 test target 1 - Starting Memory Write, at           4832955000
 test target 1 - Starting Memory Write, at           4833315000
 test target 1 - Starting Memory Write, at           4833915000
 test target 1 - Starting Memory Write, at           4834695000
 test target 1 - Starting Memory Write, at           4835025000
 test target 1 - Starting Memory Write, at           4835775000
 test target 1 - Starting Memory Write, at           4836165000
 test target 1 - Starting Memory Write, at           4836855000
 test target 1 - Starting Memory Write, at           4843635000
 test target 1 - Starting Memory Write, at           4843965000
 test target 1 - Starting Memory Write, at           4844295000
 test target 1 - Starting Memory Write, at           4844685000
 test target 1 - Starting Memory Write, at           4845075000
 test target 1 - Starting Memory Read, at           4848855000
 test target 1 - Starting Memory Read, at           4850115000
 test target 1 - Starting Memory Read, at           4851345000
 test target 1 - Starting Memory Read, at           4852605000
 test target 1 - Starting Memory Read, at           4853835000
 test target 1 - Starting Memory Read, at           4855065000
 test target 1 - Starting Memory Read, at           4856325000
 test target 1 - Starting Memory Read, at           4857555000
 test target 1 - Starting Memory Read, at           4858785000
 test target 1 - Starting Memory Read, at           4860045000
 test target 1 - Starting Memory Read, at           4861275000
 test target 1 - Starting Memory Read, at           4862505000
 test target 1 - Starting Memory Read, at           4863765000
 test target 1 - Starting Memory Read, at           4864995000
 test target 1 - Starting Memory Read, at           4866225000
 test target 1 - Starting Memory Read, at           4867485000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           4868565000
 test target 1 - Starting Memory Read, at           4868865000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           4871115000
 test target 1 - Starting Memory Read, at           4872375000
 test target 1 - Starting Memory Read, at           4873095000
 test target 1 - Starting Memory Read, at           4873845000
 test target 1 - Starting Memory Read, at           4874715000
 test target 1 - Starting Memory Read, at           4875525000
 test target 1 - Starting Memory Read, at           4876755000
 test target 1 - Starting Memory Read, at           4878015000
 test target 1 - Starting Memory Read, at           4878975000
 test target 1 - Starting Memory Read, at           4881945000
 test target 1 - Starting Memory Read, at           4883895000
 test target 1 - Starting Memory Read, at           4884855000
 test target 1 - Starting Memory Read, at           4885815000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           4887315000
 test master 1 - Starting Memory Write, at           4887645000
 test target 1 - Starting Memory Write, at           4887645000
 test target 1 - Starting Memory Write, at           4887945000
 test target 1 - Starting Memory Read, at           4888485000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           4890615000
 test master 1 - Starting Memory Write, at           4890945000
 test target 1 - Starting Memory Write, at           4890945000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           4895955000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           4897125000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           4921635000
 test target 1 - Starting Config Write, at           4922715000
 test target 1 - Starting Config Write, at           4923795000
 test target 2 - Starting Config Write, at           4924875000
 test target 2 - Starting Config Write, at           4925955000
 test target 2 - Starting Config Write, at           4927035000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           4929105000
 test target 1 - Starting Memory Read, at           4929495000
 test target 1 - Starting Memory Write, at           4930215000
 test target 1 - Starting Memory Read, at           4930605000
 test target 1 - Starting Memory Write, at           4931865000
 test target 1 - Starting Memory Read, at           4932915000
 test target 1 - Starting Memory Read, at           4933695000
 test target 1 - Starting Memory Read, at           4934475000
 test target 1 - Starting Memory Read, at           4935255000
 test target 1 - Starting Memory Read, at           4936215000
 test target 1 - Starting Memory Read, at           4937475000
 test target 1 - Starting Memory Read, at           4938435000
 test target 1 - Starting Memory Read, at           4939695000
 test target 1 - Starting Memory Read, at           4940655000
 test target 1 - Starting Memory Read, at           4942605000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           4948785000
 test target 1 - Starting Memory Read, at           4949175000
 test target 1 - Starting Memory Write, at           4949895000
 test target 1 - Starting Memory Read, at           4950285000
 test target 1 - Starting Memory Write, at           4951545000
 test target 1 - Starting Memory Read, at           4952595000
 test target 1 - Starting Memory Read, at           4953375000
 test target 1 - Starting Memory Read, at           4954155000
 test target 1 - Starting Memory Read, at           4954935000
 test target 1 - Starting Memory Read, at           4955895000
 test target 1 - Starting Memory Read, at           4957155000
 test target 1 - Starting Memory Read, at           4958115000
 test target 1 - Starting Memory Read, at           4959375000
 test target 1 - Starting Memory Read, at           4960335000
 test target 1 - Starting Memory Read, at           4962285000
 test target 1 - Starting Memory Write, at           4968465000
 test target 1 - Starting Memory Read, at           4968855000
 test target 1 - Starting Memory Write, at           4969575000
 test target 1 - Starting Memory Read, at           4969965000
 test target 1 - Starting Memory Write, at           4971225000
 test target 1 - Starting Memory Read, at           4972275000
 test target 1 - Starting Memory Read, at           4973055000
 test target 1 - Starting Memory Read, at           4973835000
 test target 1 - Starting Memory Read, at           4974615000
 test target 1 - Starting Memory Read, at           4975575000
 test target 1 - Starting Memory Read, at           4976835000
 test target 1 - Starting Memory Read, at           4977795000
 test target 1 - Starting Memory Read, at           4979055000
 test target 1 - Starting Memory Read, at           4980015000
 test target 1 - Starting Memory Read, at           4981965000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           4993305000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           4999665000
 test target 1 - Starting Memory Write, at           5000775000
 test target 1 - Starting Memory Read, at           5001285000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           5002635000
 test target 1 - Starting Config Write, at           5004675000
 test target 1 - Starting Memory Read, at           5005515000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           5007135000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           5009355000
 test target 1 - Starting Memory Write, at           5010705000
 test target 1 - Starting Memory Write, at           5011125000
 test target 1 - Starting Memory Read, at           5011515000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           5014095000
 test target 1 - Starting Memory Write, at           5017185000
 test target 1 - Starting Memory Write, at           5017665000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           5021595000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           5023635000
 test target 1 - Starting Memory Read, at           5025075000
 test target 1 - Starting Memory Read, at           5026245000
 test target 1 - Starting Memory Read, at           5027955000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           5033835000
 test target 2 - Starting Config Write, at           5034915000
 test target 1 - Starting Memory Write, at           5035785000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           5036085000
 test target 1 - Starting Memory Write, at           5037045000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           5037345000
 test target 1 - Starting Memory Write, at           5038305000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           5039775000
 test target 1 - Starting Memory Read, at           5042115000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           5042415000
 test target 1 - Starting Memory Read, at           5044515000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           5046405000
 test master 2 - Starting Memory Write, at           5046405000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           5046465000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5047425000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5047455000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5047755000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5047785000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5048655000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5048685000
 test target 1 - Starting Memory Write, at           5050455000
 test master 2 - Starting Memory Write, at           5050455000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5052285000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5052315000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5053965000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5053995000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5055645000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5055675000
 test target 1 - Starting Memory Write, at           5057685000
 test master 2 - Starting Memory Write, at           5057685000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           5057745000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5059485000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5059515000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5059815000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5059845000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5060715000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5060745000
 test target 1 - Starting Memory Write, at           5061915000
 test master 2 - Starting Memory Write, at           5061915000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           5064915000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           5066565000
 test master 1 - Starting Memory Read, at           5067045000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           5067255000
 test target 1 - Starting Config Write, at           5069685000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           5072175000
 test target 1 - Starting Memory Write, at           5072505000
 test target 1 - Starting Memory Write, at           5072835000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           5073465000
 test target 1 - Starting Memory Write, at           5073825000
 test target 1 - Starting Memory Write, at           5074185000
 test target 1 - Starting Memory Write, at           5074815000
 test target 1 - Starting Memory Write, at           5075205000
 test target 1 - Starting Memory Write, at           5075835000
 test target 1 - Starting Memory Write, at           5076615000
 test target 1 - Starting Memory Write, at           5076975000
 test target 1 - Starting Memory Write, at           5077755000
 test target 1 - Starting Memory Write, at           5078175000
 test target 1 - Starting Memory Write, at           5078895000
 test target 1 - Starting Memory Write, at           5085705000
 test target 1 - Starting Memory Write, at           5086065000
 test target 1 - Starting Memory Write, at           5086425000
 test target 1 - Starting Memory Write, at           5086845000
 test target 1 - Starting Memory Write, at           5087265000
 test target 1 - Starting Memory Read, at           5091075000
 test target 1 - Starting Memory Read, at           5092335000
 test target 1 - Starting Memory Read, at           5093565000
 test target 1 - Starting Memory Read, at           5094825000
 test target 1 - Starting Memory Read, at           5096055000
 test target 1 - Starting Memory Read, at           5097285000
 test target 1 - Starting Memory Read, at           5098545000
 test target 1 - Starting Memory Read, at           5099775000
 test target 1 - Starting Memory Read, at           5101005000
 test target 1 - Starting Memory Read, at           5102265000
 test target 1 - Starting Memory Read, at           5103495000
 test target 1 - Starting Memory Read, at           5104725000
 test target 1 - Starting Memory Read, at           5105985000
 test target 1 - Starting Memory Read, at           5107215000
 test target 1 - Starting Memory Read, at           5108445000
 test target 1 - Starting Memory Read, at           5109705000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           5110785000
 test target 1 - Starting Memory Read, at           5111115000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           5113515000
 test target 1 - Starting Memory Read, at           5114805000
 test target 1 - Starting Memory Read, at           5115645000
 test target 1 - Starting Memory Read, at           5116485000
 test target 1 - Starting Memory Read, at           5117355000
 test target 1 - Starting Memory Read, at           5118165000
 test target 1 - Starting Memory Read, at           5119395000
 test target 1 - Starting Memory Read, at           5120655000
 test target 1 - Starting Memory Read, at           5121615000
 test target 1 - Starting Memory Read, at           5124585000
 test target 1 - Starting Memory Read, at           5126655000
 test target 1 - Starting Memory Read, at           5127615000
 test target 1 - Starting Memory Read, at           5128575000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           5130075000
 test master 1 - Starting Memory Write, at           5130435000
 test target 1 - Starting Memory Write, at           5130435000
 test target 1 - Starting Memory Write, at           5130765000
 test target 1 - Starting Memory Read, at           5131335000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           5133555000
 test master 1 - Starting Memory Write, at           5133915000
 test target 1 - Starting Memory Write, at           5133915000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5139135000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           5139495000
 test master 2 - Starting Memory Read, at           5139735000
 test master 2 - Starting Memory Read, at           5139975000
 test master 2 - Starting Memory Read, at           5140215000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5141715000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           5142195000
 test master 2 - Starting Memory Read, at           5142435000
 test master 2 - Starting Memory Read, at           5142885000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5144265000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5144895000
 test master 2 - Starting Memory Read Line Multiple, at           5145135000
 test master 2 - Starting Memory Read Line Multiple, at           5145375000
 test master 2 - Starting Memory Read Line Multiple, at           5145615000
 test master 2 - Starting Memory Read Line Multiple, at           5145855000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5147535000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5156415000
 test master 2 - Starting Memory Read Line Multiple, at           5156655000
 test master 2 - Starting Memory Read Line Multiple, at           5156895000
 test master 2 - Starting Memory Read Line Multiple, at           5157135000
 test master 2 - Starting Memory Read Line Multiple, at           5157375000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5157975000
 test master 2 - Starting Memory Read Line Multiple, at           5158215000
 test master 2 - Starting Memory Read Line Multiple, at           5158455000
 test master 2 - Starting Memory Read Line Multiple, at           5158695000
 test master 2 - Starting Memory Read Line Multiple, at           5158935000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5159535000
 test master 2 - Starting Memory Read Line Multiple, at           5159775000
 test master 2 - Starting Memory Read Line Multiple, at           5160015000
 test master 2 - Starting Memory Read Line Multiple, at           5160255000
 test master 2 - Starting Memory Read Line Multiple, at           5160495000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5161095000
 test master 2 - Starting Memory Read Line Multiple, at           5161335000
 test master 2 - Starting Memory Read Line Multiple, at           5161575000
 test master 2 - Starting Memory Read Line Multiple, at           5161815000
 test master 2 - Starting Memory Read Line Multiple, at           5162055000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5162655000
 test master 2 - Starting Memory Read Line Multiple, at           5162895000
 test master 2 - Starting Memory Read Line Multiple, at           5163135000
 test master 2 - Starting Memory Read Line Multiple, at           5163375000
 test master 2 - Starting Memory Read Line Multiple, at           5163615000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5164215000
 test master 2 - Starting Memory Read Line Multiple, at           5164455000
 test master 2 - Starting Memory Read Line Multiple, at           5164695000
 test master 2 - Starting Memory Read Line Multiple, at           5164935000
 test master 2 - Starting Memory Read Line Multiple, at           5165175000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5165775000
 test master 2 - Starting Memory Read Line Multiple, at           5166015000
 test master 2 - Starting Memory Read Line Multiple, at           5166255000
 test master 2 - Starting Memory Read Line Multiple, at           5166495000
 test master 2 - Starting Memory Read Line Multiple, at           5166735000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5167335000
 test master 2 - Starting Memory Read Line Multiple, at           5167575000
 test master 2 - Starting Memory Read Line Multiple, at           5167815000
 test master 2 - Starting Memory Read Line Multiple, at           5168055000
 test master 2 - Starting Memory Read Line Multiple, at           5168295000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           5168895000
 test master 2 - Starting Memory Read Line, at           5169135000
 test master 2 - Starting Memory Read Line, at           5169375000
 test master 2 - Starting Memory Read Line, at           5169615000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           5170035000
 test master 2 - Starting Memory Read Line, at           5170275000
 test master 2 - Starting Memory Read Line, at           5170725000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5171865000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5173455000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5176305000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5178165000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           5182935000
 test master 2 - Starting Memory Write, at           5183295000
 test master 2 - Starting Memory Write, at           5183655000
 test master 2 - Starting Memory Write, at           5184015000
 test master 2 - Starting Memory Write, at           5184375000
 test master 1 - Starting Memory Read, at           5184855000
 test master 1 - Starting Memory Read, at           5185275000
 test master 1 - Starting Memory Read, at           5185815000
 test master 1 - Starting Memory Read, at           5186235000
 test master 1 - Starting Memory Read, at           5186775000
 test master 1 - Starting Memory Read, at           5187195000
 test master 2 - Starting Memory Write, at           5188455000
 test master 2 - Starting Memory Write, at           5188815000
 test master 2 - Starting Memory Write, at           5189175000
 test master 2 - Starting Memory Write, at           5189535000
 test master 2 - Starting Memory Write, at           5189895000
 test master 1 - Starting Memory Read, at           5190375000
 test master 1 - Starting Memory Read, at           5190795000
 test master 1 - Starting Memory Read, at           5191335000
 test master 1 - Starting Memory Read, at           5191755000
 test master 1 - Starting Memory Read, at           5192295000
 test master 1 - Starting Memory Read, at           5192715000
 test master 2 - Starting Memory Write, at           5194455000
 test master 2 - Starting Memory Write, at           5195625000
 test master 2 - Starting Memory Write, at           5196825000
 test master 2 - Starting Memory Write, at           5198025000
 test master 2 - Starting Memory Write, at           5200305000
 test master 2 - Starting Memory Write, at           5201505000
 test master 2 - Starting Memory Write, at           5202705000
 test master 2 - Starting Memory Write, at           5203905000
 test master 2 - Starting Memory Write, at           5206185000
 test master 2 - Starting Memory Write, at           5208315000
 test master 2 - Starting Memory Write, at           5210415000
 test master 2 - Starting Memory Write, at           5212515000
 test master 2 - Starting Memory Write, at           5215695000
 test master 2 - Starting Memory Write, at           5218035000
 test master 2 - Starting Memory Write, at           5220375000
 test master 2 - Starting Memory Write, at           5222715000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           5227185000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5227215000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5229285000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           5229645000
 test master 2 - Starting Memory Read, at           5229885000
 test master 2 - Starting Memory Read, at           5230125000
 test master 2 - Starting Memory Read, at           5230365000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5231865000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           5232375000
 test master 2 - Starting Memory Read, at           5232615000
 test master 2 - Starting Memory Read, at           5233065000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5234445000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5235075000
 test master 2 - Starting Memory Read Line Multiple, at           5235315000
 test master 2 - Starting Memory Read Line Multiple, at           5235555000
 test master 2 - Starting Memory Read Line Multiple, at           5235795000
 test master 2 - Starting Memory Read Line Multiple, at           5236035000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5237715000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5246595000
 test master 2 - Starting Memory Read Line Multiple, at           5246835000
 test master 2 - Starting Memory Read Line Multiple, at           5247075000
 test master 2 - Starting Memory Read Line Multiple, at           5247315000
 test master 2 - Starting Memory Read Line Multiple, at           5247555000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5248155000
 test master 2 - Starting Memory Read Line Multiple, at           5248395000
 test master 2 - Starting Memory Read Line Multiple, at           5248635000
 test master 2 - Starting Memory Read Line Multiple, at           5248875000
 test master 2 - Starting Memory Read Line Multiple, at           5249115000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5249715000
 test master 2 - Starting Memory Read Line Multiple, at           5249955000
 test master 2 - Starting Memory Read Line Multiple, at           5250195000
 test master 2 - Starting Memory Read Line Multiple, at           5250435000
 test master 2 - Starting Memory Read Line Multiple, at           5250675000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5251275000
 test master 2 - Starting Memory Read Line Multiple, at           5251515000
 test master 2 - Starting Memory Read Line Multiple, at           5251755000
 test master 2 - Starting Memory Read Line Multiple, at           5251995000
 test master 2 - Starting Memory Read Line Multiple, at           5252235000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5252835000
 test master 2 - Starting Memory Read Line Multiple, at           5253075000
 test master 2 - Starting Memory Read Line Multiple, at           5253315000
 test master 2 - Starting Memory Read Line Multiple, at           5253555000
 test master 2 - Starting Memory Read Line Multiple, at           5253795000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5254395000
 test master 2 - Starting Memory Read Line Multiple, at           5254635000
 test master 2 - Starting Memory Read Line Multiple, at           5254875000
 test master 2 - Starting Memory Read Line Multiple, at           5255115000
 test master 2 - Starting Memory Read Line Multiple, at           5255355000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5255955000
 test master 2 - Starting Memory Read Line Multiple, at           5256195000
 test master 2 - Starting Memory Read Line Multiple, at           5256435000
 test master 2 - Starting Memory Read Line Multiple, at           5256675000
 test master 2 - Starting Memory Read Line Multiple, at           5256915000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5257515000
 test master 2 - Starting Memory Read Line Multiple, at           5257755000
 test master 2 - Starting Memory Read Line Multiple, at           5257995000
 test master 2 - Starting Memory Read Line Multiple, at           5258235000
 test master 2 - Starting Memory Read Line Multiple, at           5258475000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           5259075000
 test master 2 - Starting Memory Read Line, at           5259315000
 test master 2 - Starting Memory Read Line, at           5259555000
 test master 2 - Starting Memory Read Line, at           5259795000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           5260215000
 test master 2 - Starting Memory Read Line, at           5260455000
 test master 2 - Starting Memory Read Line, at           5260905000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5262045000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5263635000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5266485000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5268345000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           5273115000
 test master 2 - Starting Memory Write, at           5273475000
 test master 2 - Starting Memory Write, at           5273835000
 test master 2 - Starting Memory Write, at           5274195000
 test master 2 - Starting Memory Write, at           5274555000
 test master 1 - Starting Memory Read, at           5275035000
 test master 1 - Starting Memory Read, at           5275455000
 test master 1 - Starting Memory Read, at           5275995000
 test master 1 - Starting Memory Read, at           5276415000
 test master 1 - Starting Memory Read, at           5276955000
 test master 1 - Starting Memory Read, at           5277375000
 test master 2 - Starting Memory Write, at           5278635000
 test master 2 - Starting Memory Write, at           5278995000
 test master 2 - Starting Memory Write, at           5279355000
 test master 2 - Starting Memory Write, at           5279715000
 test master 2 - Starting Memory Write, at           5280075000
 test master 1 - Starting Memory Read, at           5280555000
 test master 1 - Starting Memory Read, at           5280975000
 test master 1 - Starting Memory Read, at           5281515000
 test master 1 - Starting Memory Read, at           5281935000
 test master 1 - Starting Memory Read, at           5282475000
 test master 1 - Starting Memory Read, at           5282895000
 test master 2 - Starting Memory Write, at           5284635000
 test master 2 - Starting Memory Write, at           5285805000
 test master 2 - Starting Memory Write, at           5287005000
 test master 2 - Starting Memory Write, at           5288205000
 test master 2 - Starting Memory Write, at           5290485000
 test master 2 - Starting Memory Write, at           5291685000
 test master 2 - Starting Memory Write, at           5292885000
 test master 2 - Starting Memory Write, at           5294085000
 test master 2 - Starting Memory Write, at           5296365000
 test master 2 - Starting Memory Write, at           5298495000
 test master 2 - Starting Memory Write, at           5300595000
 test master 2 - Starting Memory Write, at           5302695000
 test master 2 - Starting Memory Write, at           5305875000
 test master 2 - Starting Memory Write, at           5308215000
 test master 2 - Starting Memory Write, at           5310555000
 test master 2 - Starting Memory Write, at           5312895000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           5317365000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5317395000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5319465000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           5319825000
 test master 2 - Starting Memory Read, at           5320065000
 test master 2 - Starting Memory Read, at           5320305000
 test master 2 - Starting Memory Read, at           5320545000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5322045000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           5322555000
 test master 2 - Starting Memory Read, at           5322795000
 test master 2 - Starting Memory Read, at           5323245000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5324625000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5325255000
 test master 2 - Starting Memory Read Line Multiple, at           5325495000
 test master 2 - Starting Memory Read Line Multiple, at           5325735000
 test master 2 - Starting Memory Read Line Multiple, at           5325975000
 test master 2 - Starting Memory Read Line Multiple, at           5326215000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5327895000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5336775000
 test master 2 - Starting Memory Read Line Multiple, at           5337015000
 test master 2 - Starting Memory Read Line Multiple, at           5337255000
 test master 2 - Starting Memory Read Line Multiple, at           5337495000
 test master 2 - Starting Memory Read Line Multiple, at           5337735000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5338335000
 test master 2 - Starting Memory Read Line Multiple, at           5338575000
 test master 2 - Starting Memory Read Line Multiple, at           5338815000
 test master 2 - Starting Memory Read Line Multiple, at           5339055000
 test master 2 - Starting Memory Read Line Multiple, at           5339295000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5339895000
 test master 2 - Starting Memory Read Line Multiple, at           5340135000
 test master 2 - Starting Memory Read Line Multiple, at           5340375000
 test master 2 - Starting Memory Read Line Multiple, at           5340615000
 test master 2 - Starting Memory Read Line Multiple, at           5340855000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5341455000
 test master 2 - Starting Memory Read Line Multiple, at           5341695000
 test master 2 - Starting Memory Read Line Multiple, at           5341935000
 test master 2 - Starting Memory Read Line Multiple, at           5342175000
 test master 2 - Starting Memory Read Line Multiple, at           5342415000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5343015000
 test master 2 - Starting Memory Read Line Multiple, at           5343255000
 test master 2 - Starting Memory Read Line Multiple, at           5343495000
 test master 2 - Starting Memory Read Line Multiple, at           5343735000
 test master 2 - Starting Memory Read Line Multiple, at           5343975000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5344575000
 test master 2 - Starting Memory Read Line Multiple, at           5344815000
 test master 2 - Starting Memory Read Line Multiple, at           5345055000
 test master 2 - Starting Memory Read Line Multiple, at           5345295000
 test master 2 - Starting Memory Read Line Multiple, at           5345535000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5346135000
 test master 2 - Starting Memory Read Line Multiple, at           5346375000
 test master 2 - Starting Memory Read Line Multiple, at           5346615000
 test master 2 - Starting Memory Read Line Multiple, at           5346855000
 test master 2 - Starting Memory Read Line Multiple, at           5347095000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5347695000
 test master 2 - Starting Memory Read Line Multiple, at           5347935000
 test master 2 - Starting Memory Read Line Multiple, at           5348175000
 test master 2 - Starting Memory Read Line Multiple, at           5348415000
 test master 2 - Starting Memory Read Line Multiple, at           5348655000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           5349255000
 test master 2 - Starting Memory Read Line, at           5349495000
 test master 2 - Starting Memory Read Line, at           5349735000
 test master 2 - Starting Memory Read Line, at           5349975000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           5350395000
 test master 2 - Starting Memory Read Line, at           5350635000
 test master 2 - Starting Memory Read Line, at           5351085000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5352225000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5353815000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5356665000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5358525000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           5363295000
 test master 2 - Starting Memory Write, at           5363655000
 test master 2 - Starting Memory Write, at           5364015000
 test master 2 - Starting Memory Write, at           5364375000
 test master 2 - Starting Memory Write, at           5364735000
 test master 1 - Starting Memory Read, at           5365215000
 test master 1 - Starting Memory Read, at           5365635000
 test master 1 - Starting Memory Read, at           5366175000
 test master 1 - Starting Memory Read, at           5366595000
 test master 1 - Starting Memory Read, at           5367135000
 test master 1 - Starting Memory Read, at           5367555000
 test master 2 - Starting Memory Write, at           5368815000
 test master 2 - Starting Memory Write, at           5369175000
 test master 2 - Starting Memory Write, at           5369535000
 test master 2 - Starting Memory Write, at           5369895000
 test master 2 - Starting Memory Write, at           5370255000
 test master 1 - Starting Memory Read, at           5370735000
 test master 1 - Starting Memory Read, at           5371155000
 test master 1 - Starting Memory Read, at           5371695000
 test master 1 - Starting Memory Read, at           5372115000
 test master 1 - Starting Memory Read, at           5372655000
 test master 1 - Starting Memory Read, at           5373075000
 test master 2 - Starting Memory Write, at           5374815000
 test master 2 - Starting Memory Write, at           5375985000
 test master 2 - Starting Memory Write, at           5377185000
 test master 2 - Starting Memory Write, at           5378385000
 test master 2 - Starting Memory Write, at           5380665000
 test master 2 - Starting Memory Write, at           5381865000
 test master 2 - Starting Memory Write, at           5383065000
 test master 2 - Starting Memory Write, at           5384265000
 test master 2 - Starting Memory Write, at           5386545000
 test master 2 - Starting Memory Write, at           5388675000
 test master 2 - Starting Memory Write, at           5390775000
 test master 2 - Starting Memory Write, at           5392875000
 test master 2 - Starting Memory Write, at           5396055000
 test master 2 - Starting Memory Write, at           5398395000
 test master 2 - Starting Memory Write, at           5400735000
 test master 2 - Starting Memory Write, at           5403075000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           5407545000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5407575000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5409645000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           5410005000
 test master 2 - Starting Memory Read, at           5410245000
 test master 2 - Starting Memory Read, at           5410485000
 test master 2 - Starting Memory Read, at           5410725000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5412225000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           5412735000
 test master 2 - Starting Memory Read, at           5412975000
 test master 2 - Starting Memory Read, at           5413425000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5414805000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5415435000
 test master 2 - Starting Memory Read Line Multiple, at           5415675000
 test master 2 - Starting Memory Read Line Multiple, at           5415915000
 test master 2 - Starting Memory Read Line Multiple, at           5416155000
 test master 2 - Starting Memory Read Line Multiple, at           5416395000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5418075000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5426955000
 test master 2 - Starting Memory Read Line Multiple, at           5427195000
 test master 2 - Starting Memory Read Line Multiple, at           5427435000
 test master 2 - Starting Memory Read Line Multiple, at           5427675000
 test master 2 - Starting Memory Read Line Multiple, at           5427915000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5428515000
 test master 2 - Starting Memory Read Line Multiple, at           5428755000
 test master 2 - Starting Memory Read Line Multiple, at           5428995000
 test master 2 - Starting Memory Read Line Multiple, at           5429235000
 test master 2 - Starting Memory Read Line Multiple, at           5429475000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5430075000
 test master 2 - Starting Memory Read Line Multiple, at           5430315000
 test master 2 - Starting Memory Read Line Multiple, at           5430555000
 test master 2 - Starting Memory Read Line Multiple, at           5430795000
 test master 2 - Starting Memory Read Line Multiple, at           5431035000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5431635000
 test master 2 - Starting Memory Read Line Multiple, at           5431875000
 test master 2 - Starting Memory Read Line Multiple, at           5432115000
 test master 2 - Starting Memory Read Line Multiple, at           5432355000
 test master 2 - Starting Memory Read Line Multiple, at           5432595000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5433195000
 test master 2 - Starting Memory Read Line Multiple, at           5433435000
 test master 2 - Starting Memory Read Line Multiple, at           5433675000
 test master 2 - Starting Memory Read Line Multiple, at           5433915000
 test master 2 - Starting Memory Read Line Multiple, at           5434155000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5434755000
 test master 2 - Starting Memory Read Line Multiple, at           5434995000
 test master 2 - Starting Memory Read Line Multiple, at           5435235000
 test master 2 - Starting Memory Read Line Multiple, at           5435475000
 test master 2 - Starting Memory Read Line Multiple, at           5435715000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5436315000
 test master 2 - Starting Memory Read Line Multiple, at           5436555000
 test master 2 - Starting Memory Read Line Multiple, at           5436795000
 test master 2 - Starting Memory Read Line Multiple, at           5437035000
 test master 2 - Starting Memory Read Line Multiple, at           5437275000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           5437875000
 test master 2 - Starting Memory Read Line Multiple, at           5438115000
 test master 2 - Starting Memory Read Line Multiple, at           5438355000
 test master 2 - Starting Memory Read Line Multiple, at           5438595000
 test master 2 - Starting Memory Read Line Multiple, at           5438835000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           5439435000
 test master 2 - Starting Memory Read Line, at           5439675000
 test master 2 - Starting Memory Read Line, at           5439915000
 test master 2 - Starting Memory Read Line, at           5440155000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           5440575000
 test master 2 - Starting Memory Read Line, at           5440815000
 test master 2 - Starting Memory Read Line, at           5441265000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5442405000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5443995000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5446845000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           5448705000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           5453475000
 test master 2 - Starting Memory Write, at           5453835000
 test master 2 - Starting Memory Write, at           5454195000
 test master 2 - Starting Memory Write, at           5454555000
 test master 2 - Starting Memory Write, at           5454915000
 test master 1 - Starting Memory Read, at           5455395000
 test master 1 - Starting Memory Read, at           5455815000
 test master 1 - Starting Memory Read, at           5456355000
 test master 1 - Starting Memory Read, at           5456775000
 test master 1 - Starting Memory Read, at           5457315000
 test master 1 - Starting Memory Read, at           5457735000
 test master 2 - Starting Memory Write, at           5458995000
 test master 2 - Starting Memory Write, at           5459355000
 test master 2 - Starting Memory Write, at           5459715000
 test master 2 - Starting Memory Write, at           5460075000
 test master 2 - Starting Memory Write, at           5460435000
 test master 1 - Starting Memory Read, at           5460915000
 test master 1 - Starting Memory Read, at           5461335000
 test master 1 - Starting Memory Read, at           5461875000
 test master 1 - Starting Memory Read, at           5462295000
 test master 1 - Starting Memory Read, at           5462835000
 test master 1 - Starting Memory Read, at           5463255000
 test master 2 - Starting Memory Write, at           5464995000
 test master 2 - Starting Memory Write, at           5466165000
 test master 2 - Starting Memory Write, at           5467365000
 test master 2 - Starting Memory Write, at           5468565000
 test master 2 - Starting Memory Write, at           5470845000
 test master 2 - Starting Memory Write, at           5472045000
 test master 2 - Starting Memory Write, at           5473245000
 test master 2 - Starting Memory Write, at           5474445000
 test master 2 - Starting Memory Write, at           5476725000
 test master 2 - Starting Memory Write, at           5478855000
 test master 2 - Starting Memory Write, at           5480955000
 test master 2 - Starting Memory Write, at           5483055000
 test master 2 - Starting Memory Write, at           5486235000
 test master 2 - Starting Memory Write, at           5488575000
 test master 2 - Starting Memory Write, at           5490915000
 test master 2 - Starting Memory Write, at           5493255000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           5497725000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5497755000
 test master 1 - Starting Memory Read, at           5499825000
 test master 1 - Starting Memory Read, at           5500275000
 test master 1 - Starting Memory Read, at           5501505000
 test master 1 - Starting Memory Read, at           5501955000
 test master 1 - Starting Memory Read Line, at           5503185000
 test master 1 - Starting Memory Read Line, at           5503635000
 test master 1 - Starting Memory Read Line, at           5504865000
 test master 1 - Starting Memory Read Line, at           5505405000
 test master 1 - Starting Memory Read Line, at           5506725000
 test master 1 - Starting Memory Read Line, at           5507415000
 test master 1 - Starting Memory Read Line, at           5508825000
 test master 1 - Starting Memory Read Line, at           5509515000
 test master 1 - Starting Memory Read Line Multiple, at           5510925000
 test master 1 - Starting Memory Read Line Multiple, at           5511855000
 test master 1 - Starting Memory Read Line Multiple, at           5513445000
 test master 1 - Starting Memory Read Line Multiple, at           5514375000
 test master 1 - Starting Memory Read Line, at           5515965000
 test master 1 - Starting Memory Read Line, at           5516655000
 test master 1 - Starting Memory Read, at           5519055000
 test master 1 - Starting Memory Read, at           5519505000
 test target 1 - Starting Config Write, at           5522655000
 test master 1 - Starting Memory Write, at           5523345000
 test master 1 - Starting Memory Write, at           5527185000
 test master 1 - Starting Memory Write, at           5532255000
 test master 1 - Starting Memory Write, at           5535855000
 test master 1 - Starting Memory Write, at           5540775000
 test master 1 - Starting Memory Read Line, at           5544615000
 test master 1 - Starting Memory Write, at           5550075000
 test master 1 - Starting Memory Read Line, at           5553915000
 test target 1 - Starting Config Write, at           5560875000
 test master 1 - Starting Memory Write, at           5561565000
 test master 1 - Starting Memory Write, at           5561745000
 test master 1 - Starting Memory Write, at           5562105000
 test master 1 - Starting Memory Read, at           5562285000
 test master 1 - Starting Memory Write, at           5562735000
 test master 1 - Starting Memory Read, at           5562915000
 test master 1 - Starting Memory Write, at           5564565000
 test master 1 - Starting Memory Write, at           5573475000
 test master 2 - Starting Memory Read Line, at           5582475000
 test master 2 - Starting Memory Read Line, at           5583135000
 test master 2 - Starting Memory Read Line, at           5583585000
 test master 2 - Starting Memory Read Line, at           5584245000
 test master 1 - Starting Memory Write, at           5584785000
 test master 1 - Starting Memory Write, at           5585145000
 test master 1 - Starting Memory Write, at           5585505000
 test master 2 - Starting Memory Read Line, at           5585985000
 test master 2 - Starting Memory Read Line, at           5586435000
 test master 2 - Starting Memory Read Line, at           5586735000
 test master 2 - Starting Memory Read Line, at           5587185000
 test master 2 - Starting Memory Read Line Multiple, at           5587515000
 test master 2 - Starting Memory Read Line Multiple, at           5587965000
 test master 1 - Starting Memory Write, at           5589855000
 test master 1 - Starting Memory Write, at           5590215000
 test master 2 - Starting Memory Read, at           5590695000
 test master 2 - Starting Memory Read, at           5591145000
 test master 2 - Starting Memory Read, at           5591445000
 test master 2 - Starting Memory Read, at           5591895000
 test master 1 - Starting Memory Write, at           5593545000
 test master 1 - Starting Memory Read, at           5593755000
 test master 1 - Starting Memory Write, at           5593965000
 test master 1 - Starting Memory Read, at           5594175000
 test master 1 - Starting Memory Write, at           5594385000
 test master 1 - Starting Memory Read, at           5594595000
 test master 1 - Starting Memory Read, at           5594805000
 test master 1 - Starting Memory Write, at           5595015000
 test master 1 - Starting Memory Write, at           5595225000
 test master 1 - Starting Memory Read, at           5595435000
 test master 1 - Starting Memory Write, at           5595645000
 test master 1 - Starting Memory Write, at           5595855000
 test master 1 - Starting Memory Write, at           5596065000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at           5600385000
 test target 1 - Starting Memory Write, at           5600715000
 test master 1 - Starting Memory Write, at           5601015000
 test target 1 - Starting Memory Write, at           5601255000
 test target 1 - Starting Memory Write, at           5601585000
 test target 1 - Starting Memory Write, at           5601915000
 test master 1 - Starting Memory Write, at           5602335000
 test target 1 - Starting Memory Write, at           5602965000
 test target 1 - Starting Memory Write, at           5603715000
 test target 1 - Starting Memory Write, at           5604075000
 test master 1 - Starting Memory Write, at           5604405000
 test target 1 - Starting Memory Write, at           5604765000
 test target 1 - Starting Memory Write, at           5605125000
 test target 1 - Starting Memory Write, at           5605485000
 test master 1 - Starting Memory Write, at           5606025000
 test target 1 - Starting Memory Write, at           5606925000
 test target 1 - Starting Memory Write, at           5607885000
 test target 1 - Starting Memory Write, at           5608215000
 test master 1 - Starting Memory Read, at           5608515000
 test target 1 - Starting Memory Write, at           5608755000
 test master 1 - Starting Memory Read, at           5609055000
 test target 1 - Starting Memory Write, at           5609295000
 test master 1 - Starting Memory Read, at           5609595000
 test target 1 - Starting Memory Write, at           5609835000
 test master 1 - Starting Memory Read, at           5610135000
 test target 1 - Starting Memory Write, at           5610375000
 test master 1 - Starting Memory Read, at           5610675000
 test target 1 - Starting Memory Write, at           5610915000
 test master 1 - Starting Memory Write, at           5611215000
 test target 1 - Starting Memory Write, at           5611455000
 test target 1 - Starting Memory Write, at           5611785000
 test target 1 - Starting Memory Write, at           5612115000
 test target 1 - Starting Memory Read, at           5612505000
 test master 1 - Starting Memory Write, at           5612925000
 test master 1 - Starting Memory Read, at           5613195000
 test target 1 - Starting Memory Write, at           5613765000
 test master 1 - Starting Memory Write, at           5614275000
 test target 1 - Starting Memory Read, at           5614785000
 test target 1 - Starting Memory Write, at           5615715000
 test master 1 - Starting Memory Read, at           5616135000
 test master 1 - Starting Memory Write, at           5616585000
 test master 1 - Starting Memory Write, at           5617005000
 test master 1 - Starting Memory Read, at           5617365000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           5619885000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           5620965000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           5645955000
 test target 1 - Starting Config Write, at           5646945000
 test target 1 - Starting Config Write, at           5647965000
 test target 2 - Starting Config Write, at           5648955000
 test target 2 - Starting Config Write, at           5649945000
 test target 2 - Starting Config Write, at           5650965000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           5652945000
 test target 1 - Starting Memory Read, at           5653245000
 test target 1 - Starting Memory Write, at           5654025000
 test target 1 - Starting Memory Read, at           5654325000
 test target 1 - Starting Memory Write, at           5655735000
 test target 1 - Starting Memory Read, at           5656515000
 test target 1 - Starting Memory Read, at           5657235000
 test target 1 - Starting Memory Read, at           5657925000
 test target 1 - Starting Memory Read, at           5658615000
 test target 1 - Starting Memory Read, at           5659515000
 test target 1 - Starting Memory Read, at           5660565000
 test target 1 - Starting Memory Read, at           5661495000
 test target 1 - Starting Memory Read, at           5662545000
 test target 1 - Starting Memory Read, at           5663475000
 test target 1 - Starting Memory Read, at           5664945000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           5671545000
 test target 1 - Starting Memory Read, at           5671845000
 test target 1 - Starting Memory Write, at           5672625000
 test target 1 - Starting Memory Read, at           5672925000
 test target 1 - Starting Memory Write, at           5674335000
 test target 1 - Starting Memory Read, at           5675115000
 test target 1 - Starting Memory Read, at           5675835000
 test target 1 - Starting Memory Read, at           5676525000
 test target 1 - Starting Memory Read, at           5677215000
 test target 1 - Starting Memory Read, at           5678115000
 test target 1 - Starting Memory Read, at           5679165000
 test target 1 - Starting Memory Read, at           5680095000
 test target 1 - Starting Memory Read, at           5681145000
 test target 1 - Starting Memory Read, at           5682075000
 test target 1 - Starting Memory Read, at           5683545000
 test target 1 - Starting Memory Write, at           5690145000
 test target 1 - Starting Memory Read, at           5690445000
 test target 1 - Starting Memory Write, at           5691225000
 test target 1 - Starting Memory Read, at           5691525000
 test target 1 - Starting Memory Write, at           5692935000
 test target 1 - Starting Memory Read, at           5693715000
 test target 1 - Starting Memory Read, at           5694435000
 test target 1 - Starting Memory Read, at           5695125000
 test target 1 - Starting Memory Read, at           5695815000
 test target 1 - Starting Memory Read, at           5696715000
 test target 1 - Starting Memory Read, at           5697765000
 test target 1 - Starting Memory Read, at           5698695000
 test target 1 - Starting Memory Read, at           5699745000
 test target 1 - Starting Memory Read, at           5700675000
 test target 1 - Starting Memory Read, at           5702145000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           5714325000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           5720895000
 test target 1 - Starting Memory Write, at           5721915000
 test target 1 - Starting Memory Read, at           5722275000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           5723475000
 test target 1 - Starting Config Write, at           5725545000
 test target 1 - Starting Memory Read, at           5726295000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           5727885000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           5730135000
 test target 1 - Starting Memory Write, at           5731425000
 test target 1 - Starting Memory Write, at           5731755000
 test target 1 - Starting Memory Read, at           5732055000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           5734635000
 test target 1 - Starting Memory Write, at           5737815000
 test target 1 - Starting Memory Write, at           5738175000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           5742165000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           5744235000
 test target 1 - Starting Memory Read, at           5745615000
 test target 1 - Starting Memory Read, at           5746755000
 test target 1 - Starting Memory Read, at           5748435000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           5754345000
 test target 2 - Starting Config Write, at           5755335000
 test target 1 - Starting Memory Write, at           5756115000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           5756325000
 test target 1 - Starting Memory Write, at           5757315000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           5757525000
 test target 1 - Starting Memory Write, at           5758515000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           5759955000
 test target 1 - Starting Memory Read, at           5762295000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           5762505000
 test target 1 - Starting Memory Read, at           5764635000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           5766495000
 test master 2 - Starting Memory Write, at           5766495000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           5766555000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5767455000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5767485000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5767785000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5767815000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5768715000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5768745000
 test target 1 - Starting Memory Write, at           5770575000
 test master 2 - Starting Memory Write, at           5770575000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5772375000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5772405000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5774115000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5774145000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5775855000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5775885000
 test target 1 - Starting Memory Write, at           5777955000
 test master 2 - Starting Memory Write, at           5777955000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           5778015000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5779725000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5779755000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5780055000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5780085000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5780985000
*** monitor - CBE Bus Changed when TRDY Desserted, at           5781015000
 test target 1 - Starting Memory Write, at           5782215000
 test master 2 - Starting Memory Write, at           5782215000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           5785215000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           5786925000
 test master 1 - Starting Memory Read, at           5787345000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           5787555000
 test target 1 - Starting Config Write, at           5790105000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           5792505000
 test target 1 - Starting Memory Write, at           5792745000
 test target 1 - Starting Memory Write, at           5792985000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           5793555000
 test target 1 - Starting Memory Write, at           5793825000
 test target 1 - Starting Memory Write, at           5794095000
 test target 1 - Starting Memory Write, at           5794665000
 test target 1 - Starting Memory Write, at           5794935000
 test target 1 - Starting Memory Write, at           5795505000
 test target 1 - Starting Memory Write, at           5796225000
 test target 1 - Starting Memory Write, at           5796495000
 test target 1 - Starting Memory Write, at           5797215000
 test target 1 - Starting Memory Write, at           5797515000
 test target 1 - Starting Memory Write, at           5798205000
 test target 1 - Starting Memory Write, at           5806095000
 test target 1 - Starting Memory Write, at           5806365000
 test target 1 - Starting Memory Write, at           5806635000
 test target 1 - Starting Memory Write, at           5806935000
 test target 1 - Starting Memory Write, at           5807235000
 test target 1 - Starting Memory Read, at           5809245000
 test target 1 - Starting Memory Read, at           5810325000
 test target 1 - Starting Memory Read, at           5811375000
 test target 1 - Starting Memory Read, at           5812455000
 test target 1 - Starting Memory Read, at           5813685000
 test target 1 - Starting Memory Read, at           5814735000
 test target 1 - Starting Memory Read, at           5815815000
 test target 1 - Starting Memory Read, at           5817045000
 test target 1 - Starting Memory Read, at           5818095000
 test target 1 - Starting Memory Read, at           5819175000
 test target 1 - Starting Memory Read, at           5820405000
 test target 1 - Starting Memory Read, at           5821455000
 test target 1 - Starting Memory Read, at           5822535000
 test target 1 - Starting Memory Read, at           5823765000
 test target 1 - Starting Memory Read, at           5824815000
 test target 1 - Starting Memory Read, at           5825895000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           5826915000
 test target 1 - Starting Memory Read, at           5827155000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           5829735000
 test target 1 - Starting Memory Read, at           5830485000
 test target 1 - Starting Memory Read, at           5831235000
 test target 1 - Starting Memory Read, at           5832015000
 test target 1 - Starting Memory Read, at           5832795000
 test target 1 - Starting Memory Read, at           5833515000
 test target 1 - Starting Memory Read, at           5834535000
 test target 1 - Starting Memory Read, at           5835585000
 test target 1 - Starting Memory Read, at           5836515000
 test target 1 - Starting Memory Read, at           5839275000
 test target 1 - Starting Memory Read, at           5840835000
 test target 1 - Starting Memory Read, at           5841735000
 test target 1 - Starting Memory Read, at           5842635000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           5844195000
 test master 1 - Starting Memory Write, at           5844435000
 test target 1 - Starting Memory Write, at           5844435000
 test target 1 - Starting Memory Write, at           5844675000
 test target 1 - Starting Memory Read, at           5845065000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           5846865000
 test master 1 - Starting Memory Write, at           5847105000
 test target 1 - Starting Memory Write, at           5847105000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           5852265000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           5853465000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           5878575000
 test target 1 - Starting Config Write, at           5879565000
 test target 1 - Starting Config Write, at           5880585000
 test target 2 - Starting Config Write, at           5881575000
 test target 2 - Starting Config Write, at           5882565000
 test target 2 - Starting Config Write, at           5883585000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           5885565000
 test target 1 - Starting Memory Read, at           5885895000
 test target 1 - Starting Memory Write, at           5886645000
 test target 1 - Starting Memory Read, at           5886975000
 test target 1 - Starting Memory Write, at           5888355000
 test target 1 - Starting Memory Read, at           5889195000
 test target 1 - Starting Memory Read, at           5889915000
 test target 1 - Starting Memory Read, at           5890605000
 test target 1 - Starting Memory Read, at           5891295000
 test target 1 - Starting Memory Read, at           5892195000
 test target 1 - Starting Memory Read, at           5893425000
 test target 1 - Starting Memory Read, at           5894355000
 test target 1 - Starting Memory Read, at           5895585000
 test target 1 - Starting Memory Read, at           5896515000
 test target 1 - Starting Memory Read, at           5897985000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           5904585000
 test target 1 - Starting Memory Read, at           5904915000
 test target 1 - Starting Memory Write, at           5905665000
 test target 1 - Starting Memory Read, at           5905995000
 test target 1 - Starting Memory Write, at           5907375000
 test target 1 - Starting Memory Read, at           5908215000
 test target 1 - Starting Memory Read, at           5908935000
 test target 1 - Starting Memory Read, at           5909625000
 test target 1 - Starting Memory Read, at           5910315000
 test target 1 - Starting Memory Read, at           5911215000
 test target 1 - Starting Memory Read, at           5912445000
 test target 1 - Starting Memory Read, at           5913375000
 test target 1 - Starting Memory Read, at           5914605000
 test target 1 - Starting Memory Read, at           5915535000
 test target 1 - Starting Memory Read, at           5917005000
 test target 1 - Starting Memory Write, at           5923605000
 test target 1 - Starting Memory Read, at           5923935000
 test target 1 - Starting Memory Write, at           5924685000
 test target 1 - Starting Memory Read, at           5925015000
 test target 1 - Starting Memory Write, at           5926395000
 test target 1 - Starting Memory Read, at           5927235000
 test target 1 - Starting Memory Read, at           5927955000
 test target 1 - Starting Memory Read, at           5928645000
 test target 1 - Starting Memory Read, at           5929335000
 test target 1 - Starting Memory Read, at           5930235000
 test target 1 - Starting Memory Read, at           5931465000
 test target 1 - Starting Memory Read, at           5932395000
 test target 1 - Starting Memory Read, at           5933625000
 test target 1 - Starting Memory Read, at           5934555000
 test target 1 - Starting Memory Read, at           5936025000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           5948205000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           5954775000
 test target 1 - Starting Memory Write, at           5955795000
 test target 1 - Starting Memory Read, at           5956185000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           5957355000
 test target 1 - Starting Config Write, at           5959425000
 test target 1 - Starting Memory Read, at           5960175000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           5961765000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           5964015000
 test target 1 - Starting Memory Write, at           5965305000
 test target 1 - Starting Memory Write, at           5965665000
 test target 1 - Starting Memory Read, at           5965995000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           5968695000
 test target 1 - Starting Memory Write, at           5971875000
 test target 1 - Starting Memory Write, at           5972265000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           5976285000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           5978355000
 test target 1 - Starting Memory Read, at           5979735000
 test target 1 - Starting Memory Read, at           5980875000
 test target 1 - Starting Memory Read, at           5982555000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           5988645000
 test target 2 - Starting Config Write, at           5989635000
 test target 1 - Starting Memory Write, at           5990415000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           5990655000
 test target 1 - Starting Memory Write, at           5991645000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           5991885000
 test target 1 - Starting Memory Write, at           5992875000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           5994315000
 test target 1 - Starting Memory Read, at           5996655000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           5996895000
 test target 1 - Starting Memory Read, at           5998995000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           6000855000
 test master 2 - Starting Memory Write, at           6000855000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           6000915000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6001845000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6001875000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6002175000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6002205000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6003105000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6003135000
 test target 1 - Starting Memory Write, at           6004965000
 test master 2 - Starting Memory Write, at           6004965000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6006795000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6006825000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6008535000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6008565000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6010275000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6010305000
 test target 1 - Starting Memory Write, at           6012375000
 test master 2 - Starting Memory Write, at           6012375000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           6012435000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6014175000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6014205000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6014505000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6014535000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6015435000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6015465000
 test target 1 - Starting Memory Write, at           6016665000
 test master 2 - Starting Memory Write, at           6016665000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           6019695000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           6021405000
 test master 1 - Starting Memory Read, at           6021825000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           6022035000
 test target 1 - Starting Config Write, at           6024585000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           6026985000
 test target 1 - Starting Memory Write, at           6027255000
 test target 1 - Starting Memory Write, at           6027525000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           6028125000
 test target 1 - Starting Memory Write, at           6028425000
 test target 1 - Starting Memory Write, at           6028725000
 test target 1 - Starting Memory Write, at           6029325000
 test target 1 - Starting Memory Write, at           6029625000
 test target 1 - Starting Memory Write, at           6030225000
 test target 1 - Starting Memory Write, at           6030975000
 test target 1 - Starting Memory Write, at           6031275000
 test target 1 - Starting Memory Write, at           6032025000
 test target 1 - Starting Memory Write, at           6032355000
 test target 1 - Starting Memory Write, at           6033075000
 test target 1 - Starting Memory Write, at           6040995000
 test target 1 - Starting Memory Write, at           6041295000
 test target 1 - Starting Memory Write, at           6041595000
 test target 1 - Starting Memory Write, at           6041925000
 test target 1 - Starting Memory Write, at           6042255000
 test target 1 - Starting Memory Read, at           6044295000
 test target 1 - Starting Memory Read, at           6045405000
 test target 1 - Starting Memory Read, at           6046635000
 test target 1 - Starting Memory Read, at           6047895000
 test target 1 - Starting Memory Read, at           6049125000
 test target 1 - Starting Memory Read, at           6050355000
 test target 1 - Starting Memory Read, at           6051615000
 test target 1 - Starting Memory Read, at           6052845000
 test target 1 - Starting Memory Read, at           6054075000
 test target 1 - Starting Memory Read, at           6055335000
 test target 1 - Starting Memory Read, at           6056565000
 test target 1 - Starting Memory Read, at           6057795000
 test target 1 - Starting Memory Read, at           6059055000
 test target 1 - Starting Memory Read, at           6060285000
 test target 1 - Starting Memory Read, at           6061515000
 test target 1 - Starting Memory Read, at           6062775000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           6063795000
 test target 1 - Starting Memory Read, at           6064065000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           6066615000
 test target 1 - Starting Memory Read, at           6067395000
 test target 1 - Starting Memory Read, at           6068115000
 test target 1 - Starting Memory Read, at           6068895000
 test target 1 - Starting Memory Read, at           6069675000
 test target 1 - Starting Memory Read, at           6070395000
 test target 1 - Starting Memory Read, at           6071595000
 test target 1 - Starting Memory Read, at           6072825000
 test target 1 - Starting Memory Read, at           6073755000
 test target 1 - Starting Memory Read, at           6076515000
 test target 1 - Starting Memory Read, at           6078075000
 test target 1 - Starting Memory Read, at           6078975000
 test target 1 - Starting Memory Read, at           6079875000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           6081435000
 test master 1 - Starting Memory Write, at           6081705000
 test target 1 - Starting Memory Write, at           6081705000
 test target 1 - Starting Memory Write, at           6081975000
 test target 1 - Starting Memory Read, at           6082395000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           6084135000
 test master 1 - Starting Memory Write, at           6084405000
 test target 1 - Starting Memory Write, at           6084405000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           6089505000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           6090705000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           6115815000
 test target 1 - Starting Config Write, at           6116805000
 test target 1 - Starting Config Write, at           6117825000
 test target 2 - Starting Config Write, at           6118815000
 test target 2 - Starting Config Write, at           6119805000
 test target 2 - Starting Config Write, at           6120825000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           6122805000
 test target 1 - Starting Memory Read, at           6123165000
 test target 1 - Starting Memory Write, at           6123885000
 test target 1 - Starting Memory Read, at           6124245000
 test target 1 - Starting Memory Write, at           6125595000
 test target 1 - Starting Memory Read, at           6126435000
 test target 1 - Starting Memory Read, at           6127155000
 test target 1 - Starting Memory Read, at           6127845000
 test target 1 - Starting Memory Read, at           6128535000
 test target 1 - Starting Memory Read, at           6129435000
 test target 1 - Starting Memory Read, at           6130665000
 test target 1 - Starting Memory Read, at           6131775000
 test target 1 - Starting Memory Read, at           6133005000
 test target 1 - Starting Memory Read, at           6134115000
 test target 1 - Starting Memory Read, at           6135765000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           6142365000
 test target 1 - Starting Memory Read, at           6142725000
 test target 1 - Starting Memory Write, at           6143445000
 test target 1 - Starting Memory Read, at           6143805000
 test target 1 - Starting Memory Write, at           6145155000
 test target 1 - Starting Memory Read, at           6145995000
 test target 1 - Starting Memory Read, at           6146715000
 test target 1 - Starting Memory Read, at           6147405000
 test target 1 - Starting Memory Read, at           6148095000
 test target 1 - Starting Memory Read, at           6148995000
 test target 1 - Starting Memory Read, at           6150225000
 test target 1 - Starting Memory Read, at           6151335000
 test target 1 - Starting Memory Read, at           6152565000
 test target 1 - Starting Memory Read, at           6153675000
 test target 1 - Starting Memory Read, at           6155325000
 test target 1 - Starting Memory Write, at           6161925000
 test target 1 - Starting Memory Read, at           6162285000
 test target 1 - Starting Memory Write, at           6163005000
 test target 1 - Starting Memory Read, at           6163365000
 test target 1 - Starting Memory Write, at           6164715000
 test target 1 - Starting Memory Read, at           6165555000
 test target 1 - Starting Memory Read, at           6166275000
 test target 1 - Starting Memory Read, at           6166965000
 test target 1 - Starting Memory Read, at           6167655000
 test target 1 - Starting Memory Read, at           6168555000
 test target 1 - Starting Memory Read, at           6169785000
 test target 1 - Starting Memory Read, at           6170895000
 test target 1 - Starting Memory Read, at           6172125000
 test target 1 - Starting Memory Read, at           6173235000
 test target 1 - Starting Memory Read, at           6174885000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           6187065000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           6193635000
 test target 1 - Starting Memory Write, at           6194655000
 test target 1 - Starting Memory Read, at           6195075000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           6196395000
 test target 1 - Starting Config Write, at           6198465000
 test target 1 - Starting Memory Read, at           6199215000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           6200805000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           6203055000
 test target 1 - Starting Memory Write, at           6204345000
 test target 1 - Starting Memory Write, at           6204735000
 test target 1 - Starting Memory Read, at           6205095000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           6207735000
 test target 1 - Starting Memory Write, at           6210975000
 test target 1 - Starting Memory Write, at           6211395000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           6215445000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           6217515000
 test target 1 - Starting Memory Read, at           6218895000
 test target 1 - Starting Memory Read, at           6220035000
 test target 1 - Starting Memory Read, at           6221715000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           6227805000
 test target 2 - Starting Config Write, at           6228795000
 test target 1 - Starting Memory Write, at           6229575000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           6229845000
 test target 1 - Starting Memory Write, at           6230835000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           6231105000
 test target 1 - Starting Memory Write, at           6232095000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           6233595000
 test target 1 - Starting Memory Read, at           6235935000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           6236205000
 test target 1 - Starting Memory Read, at           6238275000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           6240135000
 test master 2 - Starting Memory Write, at           6240135000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           6240195000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6241155000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6241185000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6241485000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6241515000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6242415000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6242445000
 test target 1 - Starting Memory Write, at           6244275000
 test master 2 - Starting Memory Write, at           6244275000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6246135000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6246165000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6247875000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6247905000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6249615000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6249645000
 test target 1 - Starting Memory Write, at           6251715000
 test master 2 - Starting Memory Write, at           6251715000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           6251775000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6253545000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6253575000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6253875000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6253905000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6254805000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6254835000
 test target 1 - Starting Memory Write, at           6256035000
 test master 2 - Starting Memory Write, at           6256035000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           6259095000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           6260805000
 test master 1 - Starting Memory Read, at           6261225000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           6261435000
 test target 1 - Starting Config Write, at           6263985000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           6266565000
 test target 1 - Starting Memory Write, at           6266865000
 test target 1 - Starting Memory Write, at           6267165000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           6267795000
 test target 1 - Starting Memory Write, at           6268125000
 test target 1 - Starting Memory Write, at           6268455000
 test target 1 - Starting Memory Write, at           6269085000
 test target 1 - Starting Memory Write, at           6269415000
 test target 1 - Starting Memory Write, at           6270045000
 test target 1 - Starting Memory Write, at           6270825000
 test target 1 - Starting Memory Write, at           6271155000
 test target 1 - Starting Memory Write, at           6271935000
 test target 1 - Starting Memory Write, at           6272295000
 test target 1 - Starting Memory Write, at           6273045000
 test target 1 - Starting Memory Write, at           6280995000
 test target 1 - Starting Memory Write, at           6281325000
 test target 1 - Starting Memory Write, at           6281655000
 test target 1 - Starting Memory Write, at           6282015000
 test target 1 - Starting Memory Write, at           6282375000
 test target 1 - Starting Memory Read, at           6284445000
 test target 1 - Starting Memory Read, at           6285585000
 test target 1 - Starting Memory Read, at           6286815000
 test target 1 - Starting Memory Read, at           6288075000
 test target 1 - Starting Memory Read, at           6289305000
 test target 1 - Starting Memory Read, at           6290535000
 test target 1 - Starting Memory Read, at           6291795000
 test target 1 - Starting Memory Read, at           6293025000
 test target 1 - Starting Memory Read, at           6294255000
 test target 1 - Starting Memory Read, at           6295515000
 test target 1 - Starting Memory Read, at           6296745000
 test target 1 - Starting Memory Read, at           6297975000
 test target 1 - Starting Memory Read, at           6299235000
 test target 1 - Starting Memory Read, at           6300465000
 test target 1 - Starting Memory Read, at           6301695000
 test target 1 - Starting Memory Read, at           6302955000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           6303975000
 test target 1 - Starting Memory Read, at           6304275000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           6306795000
 test target 1 - Starting Memory Read, at           6307605000
 test target 1 - Starting Memory Read, at           6308295000
 test target 1 - Starting Memory Read, at           6309075000
 test target 1 - Starting Memory Read, at           6309945000
 test target 1 - Starting Memory Read, at           6310695000
 test target 1 - Starting Memory Read, at           6311895000
 test target 1 - Starting Memory Read, at           6313125000
 test target 1 - Starting Memory Read, at           6314235000
 test target 1 - Starting Memory Read, at           6317055000
 test target 1 - Starting Memory Read, at           6318675000
 test target 1 - Starting Memory Read, at           6319575000
 test target 1 - Starting Memory Read, at           6320475000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           6322035000
 test master 1 - Starting Memory Write, at           6322335000
 test target 1 - Starting Memory Write, at           6322335000
 test target 1 - Starting Memory Write, at           6322635000
 test target 1 - Starting Memory Read, at           6323085000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           6324945000
 test master 1 - Starting Memory Write, at           6325245000
 test target 1 - Starting Memory Write, at           6325245000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           6330345000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           6331545000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           6356655000
 test target 1 - Starting Config Write, at           6357645000
 test target 1 - Starting Config Write, at           6358665000
 test target 2 - Starting Config Write, at           6359655000
 test target 2 - Starting Config Write, at           6360645000
 test target 2 - Starting Config Write, at           6361665000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           6363645000
 test target 1 - Starting Memory Read, at           6364035000
 test target 1 - Starting Memory Write, at           6364905000
 test target 1 - Starting Memory Read, at           6365295000
 test target 1 - Starting Memory Write, at           6366795000
 test target 1 - Starting Memory Read, at           6367695000
 test target 1 - Starting Memory Read, at           6368415000
 test target 1 - Starting Memory Read, at           6369285000
 test target 1 - Starting Memory Read, at           6369975000
 test target 1 - Starting Memory Read, at           6370875000
 test target 1 - Starting Memory Read, at           6372105000
 test target 1 - Starting Memory Read, at           6373215000
 test target 1 - Starting Memory Read, at           6374445000
 test target 1 - Starting Memory Read, at           6375555000
 test target 1 - Starting Memory Read, at           6377205000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           6383805000
 test target 1 - Starting Memory Read, at           6384195000
 test target 1 - Starting Memory Write, at           6385065000
 test target 1 - Starting Memory Read, at           6385455000
 test target 1 - Starting Memory Write, at           6386955000
 test target 1 - Starting Memory Read, at           6387855000
 test target 1 - Starting Memory Read, at           6388575000
 test target 1 - Starting Memory Read, at           6389445000
 test target 1 - Starting Memory Read, at           6390135000
 test target 1 - Starting Memory Read, at           6391035000
 test target 1 - Starting Memory Read, at           6392265000
 test target 1 - Starting Memory Read, at           6393375000
 test target 1 - Starting Memory Read, at           6394605000
 test target 1 - Starting Memory Read, at           6395715000
 test target 1 - Starting Memory Read, at           6397365000
 test target 1 - Starting Memory Write, at           6403965000
 test target 1 - Starting Memory Read, at           6404355000
 test target 1 - Starting Memory Write, at           6405225000
 test target 1 - Starting Memory Read, at           6405615000
 test target 1 - Starting Memory Write, at           6407115000
 test target 1 - Starting Memory Read, at           6408015000
 test target 1 - Starting Memory Read, at           6408735000
 test target 1 - Starting Memory Read, at           6409605000
 test target 1 - Starting Memory Read, at           6410295000
 test target 1 - Starting Memory Read, at           6411195000
 test target 1 - Starting Memory Read, at           6412425000
 test target 1 - Starting Memory Read, at           6413535000
 test target 1 - Starting Memory Read, at           6414765000
 test target 1 - Starting Memory Read, at           6415875000
 test target 1 - Starting Memory Read, at           6417525000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           6429705000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           6436275000
 test target 1 - Starting Memory Write, at           6437295000
 test target 1 - Starting Memory Read, at           6437745000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           6439035000
 test target 1 - Starting Config Write, at           6441105000
 test target 1 - Starting Memory Read, at           6441855000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           6443445000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           6445695000
 test target 1 - Starting Memory Write, at           6446985000
 test target 1 - Starting Memory Write, at           6447405000
 test target 1 - Starting Memory Read, at           6447795000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           6450555000
 test target 1 - Starting Memory Write, at           6453795000
 test target 1 - Starting Memory Write, at           6454245000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           6458325000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           6460395000
 test target 1 - Starting Memory Read, at           6461955000
 test target 1 - Starting Memory Read, at           6463095000
 test target 1 - Starting Memory Read, at           6464775000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           6470865000
 test target 2 - Starting Config Write, at           6471855000
 test target 1 - Starting Memory Write, at           6472635000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           6472935000
 test target 1 - Starting Memory Write, at           6473925000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           6474225000
 test target 1 - Starting Memory Write, at           6475215000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           6476715000
 test target 1 - Starting Memory Read, at           6479055000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           6479355000
 test target 1 - Starting Memory Read, at           6481575000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           6483435000
 test master 2 - Starting Memory Write, at           6483435000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           6483495000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6484485000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6484515000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6484815000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6484845000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6485745000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6485775000
 test target 1 - Starting Memory Write, at           6487605000
 test master 2 - Starting Memory Write, at           6487605000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6489495000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6489525000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6491235000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6491265000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6492975000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6493005000
 test target 1 - Starting Memory Write, at           6495075000
 test master 2 - Starting Memory Write, at           6495075000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           6495135000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6496935000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6496965000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6497265000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6497295000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6498195000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6498225000
 test target 1 - Starting Memory Write, at           6499425000
 test master 2 - Starting Memory Write, at           6499425000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           6502515000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           6504225000
 test master 1 - Starting Memory Read, at           6504645000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           6504855000
 test target 1 - Starting Config Write, at           6507405000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           6509985000
 test target 1 - Starting Memory Write, at           6510315000
 test target 1 - Starting Memory Write, at           6510645000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           6511305000
 test target 1 - Starting Memory Write, at           6511665000
 test target 1 - Starting Memory Write, at           6512025000
 test target 1 - Starting Memory Write, at           6512685000
 test target 1 - Starting Memory Write, at           6513045000
 test target 1 - Starting Memory Write, at           6513705000
 test target 1 - Starting Memory Write, at           6514515000
 test target 1 - Starting Memory Write, at           6514875000
 test target 1 - Starting Memory Write, at           6515685000
 test target 1 - Starting Memory Write, at           6516075000
 test target 1 - Starting Memory Write, at           6516855000
 test target 1 - Starting Memory Write, at           6524835000
 test target 1 - Starting Memory Write, at           6525195000
 test target 1 - Starting Memory Write, at           6525555000
 test target 1 - Starting Memory Write, at           6525945000
 test target 1 - Starting Memory Write, at           6526335000
 test target 1 - Starting Memory Read, at           6528435000
 test target 1 - Starting Memory Read, at           6529605000
 test target 1 - Starting Memory Read, at           6530835000
 test target 1 - Starting Memory Read, at           6532095000
 test target 1 - Starting Memory Read, at           6533325000
 test target 1 - Starting Memory Read, at           6534555000
 test target 1 - Starting Memory Read, at           6535815000
 test target 1 - Starting Memory Read, at           6537045000
 test target 1 - Starting Memory Read, at           6538275000
 test target 1 - Starting Memory Read, at           6539535000
 test target 1 - Starting Memory Read, at           6540765000
 test target 1 - Starting Memory Read, at           6541995000
 test target 1 - Starting Memory Read, at           6543255000
 test target 1 - Starting Memory Read, at           6544485000
 test target 1 - Starting Memory Read, at           6545715000
 test target 1 - Starting Memory Read, at           6546975000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           6547995000
 test target 1 - Starting Memory Read, at           6548325000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           6550995000
 test target 1 - Starting Memory Read, at           6551835000
 test target 1 - Starting Memory Read, at           6552675000
 test target 1 - Starting Memory Read, at           6553545000
 test target 1 - Starting Memory Read, at           6554445000
 test target 1 - Starting Memory Read, at           6555345000
 test target 1 - Starting Memory Read, at           6556515000
 test target 1 - Starting Memory Read, at           6557745000
 test target 1 - Starting Memory Read, at           6558855000
 test target 1 - Starting Memory Read, at           6561705000
 test target 1 - Starting Memory Read, at           6563295000
 test target 1 - Starting Memory Read, at           6564195000
 test target 1 - Starting Memory Read, at           6565095000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           6566655000
 test master 1 - Starting Memory Write, at           6566985000
 test target 1 - Starting Memory Write, at           6566985000
 test target 1 - Starting Memory Write, at           6567315000
 test target 1 - Starting Memory Read, at           6567795000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           6569595000
 test master 1 - Starting Memory Write, at           6569925000
 test target 1 - Starting Memory Write, at           6569925000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6575235000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           6575535000
 test master 2 - Starting Memory Read, at           6575775000
 test master 2 - Starting Memory Read, at           6576015000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6577455000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           6577815000
 test master 2 - Starting Memory Read, at           6578055000
 test master 2 - Starting Memory Read, at           6578295000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6579675000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6580065000
 test master 2 - Starting Memory Read Line Multiple, at           6580305000
 test master 2 - Starting Memory Read Line Multiple, at           6580575000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6582135000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6585495000
 test master 2 - Starting Memory Read Line Multiple, at           6585735000
 test master 2 - Starting Memory Read Line Multiple, at           6586005000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6586425000
 test master 2 - Starting Memory Read Line Multiple, at           6586665000
 test master 2 - Starting Memory Read Line Multiple, at           6586965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6587385000
 test master 2 - Starting Memory Read Line Multiple, at           6587625000
 test master 2 - Starting Memory Read Line Multiple, at           6587925000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6588345000
 test master 2 - Starting Memory Read Line Multiple, at           6588585000
 test master 2 - Starting Memory Read Line Multiple, at           6588885000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6589305000
 test master 2 - Starting Memory Read Line Multiple, at           6589545000
 test master 2 - Starting Memory Read Line Multiple, at           6589845000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6590265000
 test master 2 - Starting Memory Read Line Multiple, at           6590505000
 test master 2 - Starting Memory Read Line Multiple, at           6590805000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6591225000
 test master 2 - Starting Memory Read Line Multiple, at           6591465000
 test master 2 - Starting Memory Read Line Multiple, at           6591765000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6592185000
 test master 2 - Starting Memory Read Line Multiple, at           6592425000
 test master 2 - Starting Memory Read Line Multiple, at           6592725000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           6593145000
 test master 2 - Starting Memory Read Line, at           6593385000
 test master 2 - Starting Memory Read Line, at           6593625000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           6593955000
 test master 2 - Starting Memory Read Line, at           6594195000
 test master 2 - Starting Memory Read Line, at           6594435000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6595575000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6597195000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6600075000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6601755000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           6606045000
 test master 2 - Starting Memory Write, at           6606345000
 test master 2 - Starting Memory Write, at           6606645000
 test master 2 - Starting Memory Write, at           6606945000
 test master 2 - Starting Memory Write, at           6607245000
 test master 1 - Starting Memory Read, at           6607665000
 test master 1 - Starting Memory Read, at           6608025000
 test master 1 - Starting Memory Read, at           6608565000
 test master 1 - Starting Memory Read, at           6608925000
 test master 1 - Starting Memory Read, at           6609465000
 test master 1 - Starting Memory Read, at           6609825000
 test master 2 - Starting Memory Write, at           6611115000
 test master 2 - Starting Memory Write, at           6611415000
 test master 2 - Starting Memory Write, at           6611715000
 test master 2 - Starting Memory Write, at           6612015000
 test master 2 - Starting Memory Write, at           6612315000
 test master 1 - Starting Memory Read, at           6612735000
 test master 1 - Starting Memory Read, at           6613095000
 test master 1 - Starting Memory Read, at           6613635000
 test master 1 - Starting Memory Read, at           6613995000
 test master 1 - Starting Memory Read, at           6614535000
 test master 1 - Starting Memory Read, at           6614895000
 test master 2 - Starting Memory Write, at           6616695000
 test master 2 - Starting Memory Write, at           6617835000
 test master 2 - Starting Memory Write, at           6618975000
 test master 2 - Starting Memory Write, at           6620115000
 test master 2 - Starting Memory Write, at           6622395000
 test master 2 - Starting Memory Write, at           6623535000
 test master 2 - Starting Memory Write, at           6624675000
 test master 2 - Starting Memory Write, at           6625815000
 test master 2 - Starting Memory Write, at           6628095000
 test master 2 - Starting Memory Write, at           6630255000
 test master 2 - Starting Memory Write, at           6632415000
 test master 2 - Starting Memory Write, at           6634575000
 test master 2 - Starting Memory Write, at           6637875000
 test master 2 - Starting Memory Write, at           6640275000
 test master 2 - Starting Memory Write, at           6642675000
 test master 2 - Starting Memory Write, at           6645075000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           6649605000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6649635000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6651735000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           6652035000
 test master 2 - Starting Memory Read, at           6652275000
 test master 2 - Starting Memory Read, at           6652515000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6653955000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           6654315000
 test master 2 - Starting Memory Read, at           6654555000
 test master 2 - Starting Memory Read, at           6654795000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6656175000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6656565000
 test master 2 - Starting Memory Read Line Multiple, at           6656805000
 test master 2 - Starting Memory Read Line Multiple, at           6657075000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6658635000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6661995000
 test master 2 - Starting Memory Read Line Multiple, at           6662235000
 test master 2 - Starting Memory Read Line Multiple, at           6662505000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6662925000
 test master 2 - Starting Memory Read Line Multiple, at           6663165000
 test master 2 - Starting Memory Read Line Multiple, at           6663465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6663885000
 test master 2 - Starting Memory Read Line Multiple, at           6664125000
 test master 2 - Starting Memory Read Line Multiple, at           6664425000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6664845000
 test master 2 - Starting Memory Read Line Multiple, at           6665085000
 test master 2 - Starting Memory Read Line Multiple, at           6665385000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6665805000
 test master 2 - Starting Memory Read Line Multiple, at           6666045000
 test master 2 - Starting Memory Read Line Multiple, at           6666345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6666765000
 test master 2 - Starting Memory Read Line Multiple, at           6667005000
 test master 2 - Starting Memory Read Line Multiple, at           6667305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6667725000
 test master 2 - Starting Memory Read Line Multiple, at           6667965000
 test master 2 - Starting Memory Read Line Multiple, at           6668265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6668685000
 test master 2 - Starting Memory Read Line Multiple, at           6668925000
 test master 2 - Starting Memory Read Line Multiple, at           6669225000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           6669645000
 test master 2 - Starting Memory Read Line, at           6669885000
 test master 2 - Starting Memory Read Line, at           6670125000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           6670455000
 test master 2 - Starting Memory Read Line, at           6670695000
 test master 2 - Starting Memory Read Line, at           6670935000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6672075000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6673695000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6676575000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6678255000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           6682545000
 test master 2 - Starting Memory Write, at           6682845000
 test master 2 - Starting Memory Write, at           6683145000
 test master 2 - Starting Memory Write, at           6683445000
 test master 2 - Starting Memory Write, at           6683745000
 test master 1 - Starting Memory Read, at           6684165000
 test master 1 - Starting Memory Read, at           6684525000
 test master 1 - Starting Memory Read, at           6685065000
 test master 1 - Starting Memory Read, at           6685425000
 test master 1 - Starting Memory Read, at           6685965000
 test master 1 - Starting Memory Read, at           6686325000
 test master 2 - Starting Memory Write, at           6687615000
 test master 2 - Starting Memory Write, at           6687915000
 test master 2 - Starting Memory Write, at           6688215000
 test master 2 - Starting Memory Write, at           6688515000
 test master 2 - Starting Memory Write, at           6688815000
 test master 1 - Starting Memory Read, at           6689235000
 test master 1 - Starting Memory Read, at           6689595000
 test master 1 - Starting Memory Read, at           6690135000
 test master 1 - Starting Memory Read, at           6690495000
 test master 1 - Starting Memory Read, at           6691035000
 test master 1 - Starting Memory Read, at           6691395000
 test master 2 - Starting Memory Write, at           6693195000
 test master 2 - Starting Memory Write, at           6694335000
 test master 2 - Starting Memory Write, at           6695475000
 test master 2 - Starting Memory Write, at           6696615000
 test master 2 - Starting Memory Write, at           6698895000
 test master 2 - Starting Memory Write, at           6700035000
 test master 2 - Starting Memory Write, at           6701175000
 test master 2 - Starting Memory Write, at           6702315000
 test master 2 - Starting Memory Write, at           6704595000
 test master 2 - Starting Memory Write, at           6706755000
 test master 2 - Starting Memory Write, at           6708915000
 test master 2 - Starting Memory Write, at           6711075000
 test master 2 - Starting Memory Write, at           6714375000
 test master 2 - Starting Memory Write, at           6716775000
 test master 2 - Starting Memory Write, at           6719175000
 test master 2 - Starting Memory Write, at           6721575000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           6726105000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6726135000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6728235000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           6728535000
 test master 2 - Starting Memory Read, at           6728775000
 test master 2 - Starting Memory Read, at           6729015000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6730455000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           6730815000
 test master 2 - Starting Memory Read, at           6731055000
 test master 2 - Starting Memory Read, at           6731295000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6732675000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6733065000
 test master 2 - Starting Memory Read Line Multiple, at           6733305000
 test master 2 - Starting Memory Read Line Multiple, at           6733575000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6735135000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6738495000
 test master 2 - Starting Memory Read Line Multiple, at           6738735000
 test master 2 - Starting Memory Read Line Multiple, at           6739005000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6739425000
 test master 2 - Starting Memory Read Line Multiple, at           6739665000
 test master 2 - Starting Memory Read Line Multiple, at           6739965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6740385000
 test master 2 - Starting Memory Read Line Multiple, at           6740625000
 test master 2 - Starting Memory Read Line Multiple, at           6740925000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6741345000
 test master 2 - Starting Memory Read Line Multiple, at           6741585000
 test master 2 - Starting Memory Read Line Multiple, at           6741885000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6742305000
 test master 2 - Starting Memory Read Line Multiple, at           6742545000
 test master 2 - Starting Memory Read Line Multiple, at           6742845000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6743265000
 test master 2 - Starting Memory Read Line Multiple, at           6743505000
 test master 2 - Starting Memory Read Line Multiple, at           6743805000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6744225000
 test master 2 - Starting Memory Read Line Multiple, at           6744465000
 test master 2 - Starting Memory Read Line Multiple, at           6744765000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6745185000
 test master 2 - Starting Memory Read Line Multiple, at           6745425000
 test master 2 - Starting Memory Read Line Multiple, at           6745725000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           6746145000
 test master 2 - Starting Memory Read Line, at           6746385000
 test master 2 - Starting Memory Read Line, at           6746625000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           6746955000
 test master 2 - Starting Memory Read Line, at           6747195000
 test master 2 - Starting Memory Read Line, at           6747435000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6748575000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6750195000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6753075000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6754755000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           6759045000
 test master 2 - Starting Memory Write, at           6759345000
 test master 2 - Starting Memory Write, at           6759645000
 test master 2 - Starting Memory Write, at           6759945000
 test master 2 - Starting Memory Write, at           6760245000
 test master 1 - Starting Memory Read, at           6760665000
 test master 1 - Starting Memory Read, at           6761025000
 test master 1 - Starting Memory Read, at           6761565000
 test master 1 - Starting Memory Read, at           6761925000
 test master 1 - Starting Memory Read, at           6762465000
 test master 1 - Starting Memory Read, at           6762825000
 test master 2 - Starting Memory Write, at           6764115000
 test master 2 - Starting Memory Write, at           6764415000
 test master 2 - Starting Memory Write, at           6764715000
 test master 2 - Starting Memory Write, at           6765015000
 test master 2 - Starting Memory Write, at           6765315000
 test master 1 - Starting Memory Read, at           6765735000
 test master 1 - Starting Memory Read, at           6766095000
 test master 1 - Starting Memory Read, at           6766635000
 test master 1 - Starting Memory Read, at           6766995000
 test master 1 - Starting Memory Read, at           6767535000
 test master 1 - Starting Memory Read, at           6767895000
 test master 2 - Starting Memory Write, at           6769695000
 test master 2 - Starting Memory Write, at           6770835000
 test master 2 - Starting Memory Write, at           6771975000
 test master 2 - Starting Memory Write, at           6773115000
 test master 2 - Starting Memory Write, at           6775395000
 test master 2 - Starting Memory Write, at           6776535000
 test master 2 - Starting Memory Write, at           6777675000
 test master 2 - Starting Memory Write, at           6778815000
 test master 2 - Starting Memory Write, at           6781095000
 test master 2 - Starting Memory Write, at           6783255000
 test master 2 - Starting Memory Write, at           6785415000
 test master 2 - Starting Memory Write, at           6787575000
 test master 2 - Starting Memory Write, at           6790875000
 test master 2 - Starting Memory Write, at           6793275000
 test master 2 - Starting Memory Write, at           6795675000
 test master 2 - Starting Memory Write, at           6798075000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           6802605000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6802635000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6804735000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           6805035000
 test master 2 - Starting Memory Read, at           6805275000
 test master 2 - Starting Memory Read, at           6805515000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6806955000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           6807315000
 test master 2 - Starting Memory Read, at           6807555000
 test master 2 - Starting Memory Read, at           6807795000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6809175000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6809565000
 test master 2 - Starting Memory Read Line Multiple, at           6809805000
 test master 2 - Starting Memory Read Line Multiple, at           6810075000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6811635000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6814995000
 test master 2 - Starting Memory Read Line Multiple, at           6815235000
 test master 2 - Starting Memory Read Line Multiple, at           6815505000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6815925000
 test master 2 - Starting Memory Read Line Multiple, at           6816165000
 test master 2 - Starting Memory Read Line Multiple, at           6816465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6816885000
 test master 2 - Starting Memory Read Line Multiple, at           6817125000
 test master 2 - Starting Memory Read Line Multiple, at           6817425000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6817845000
 test master 2 - Starting Memory Read Line Multiple, at           6818085000
 test master 2 - Starting Memory Read Line Multiple, at           6818385000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6818805000
 test master 2 - Starting Memory Read Line Multiple, at           6819045000
 test master 2 - Starting Memory Read Line Multiple, at           6819345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6819765000
 test master 2 - Starting Memory Read Line Multiple, at           6820005000
 test master 2 - Starting Memory Read Line Multiple, at           6820305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6820725000
 test master 2 - Starting Memory Read Line Multiple, at           6820965000
 test master 2 - Starting Memory Read Line Multiple, at           6821265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           6821685000
 test master 2 - Starting Memory Read Line Multiple, at           6821925000
 test master 2 - Starting Memory Read Line Multiple, at           6822225000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           6822645000
 test master 2 - Starting Memory Read Line, at           6822885000
 test master 2 - Starting Memory Read Line, at           6823125000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           6823455000
 test master 2 - Starting Memory Read Line, at           6823695000
 test master 2 - Starting Memory Read Line, at           6823935000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6825075000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6826695000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6829575000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           6831255000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           6835545000
 test master 2 - Starting Memory Write, at           6835845000
 test master 2 - Starting Memory Write, at           6836145000
 test master 2 - Starting Memory Write, at           6836445000
 test master 2 - Starting Memory Write, at           6836745000
 test master 1 - Starting Memory Read, at           6837165000
 test master 1 - Starting Memory Read, at           6837525000
 test master 1 - Starting Memory Read, at           6838065000
 test master 1 - Starting Memory Read, at           6838425000
 test master 1 - Starting Memory Read, at           6838965000
 test master 1 - Starting Memory Read, at           6839325000
 test master 2 - Starting Memory Write, at           6840615000
 test master 2 - Starting Memory Write, at           6840915000
 test master 2 - Starting Memory Write, at           6841215000
 test master 2 - Starting Memory Write, at           6841515000
 test master 2 - Starting Memory Write, at           6841815000
 test master 1 - Starting Memory Read, at           6842235000
 test master 1 - Starting Memory Read, at           6842595000
 test master 1 - Starting Memory Read, at           6843135000
 test master 1 - Starting Memory Read, at           6843495000
 test master 1 - Starting Memory Read, at           6844035000
 test master 1 - Starting Memory Read, at           6844395000
 test master 2 - Starting Memory Write, at           6846195000
 test master 2 - Starting Memory Write, at           6847335000
 test master 2 - Starting Memory Write, at           6848475000
 test master 2 - Starting Memory Write, at           6849615000
 test master 2 - Starting Memory Write, at           6851895000
 test master 2 - Starting Memory Write, at           6853035000
 test master 2 - Starting Memory Write, at           6854175000
 test master 2 - Starting Memory Write, at           6855315000
 test master 2 - Starting Memory Write, at           6857595000
 test master 2 - Starting Memory Write, at           6859755000
 test master 2 - Starting Memory Write, at           6861915000
 test master 2 - Starting Memory Write, at           6864075000
 test master 2 - Starting Memory Write, at           6867375000
 test master 2 - Starting Memory Write, at           6869775000
 test master 2 - Starting Memory Write, at           6872175000
 test master 2 - Starting Memory Write, at           6874575000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           6879105000
*** monitor - CBE Bus Changed when TRDY Desserted, at           6879135000
 test master 1 - Starting Memory Read, at           6881235000
 test master 1 - Starting Memory Read, at           6881625000
 test master 1 - Starting Memory Read, at           6882885000
 test master 1 - Starting Memory Read, at           6883275000
 test master 1 - Starting Memory Read Line, at           6884565000
 test master 1 - Starting Memory Read Line, at           6884955000
 test master 1 - Starting Memory Read Line, at           6886245000
 test master 1 - Starting Memory Read Line, at           6886665000
 test master 1 - Starting Memory Read Line, at           6888045000
 test master 1 - Starting Memory Read Line, at           6888495000
 test master 1 - Starting Memory Read Line, at           6889905000
 test master 1 - Starting Memory Read Line, at           6890355000
 test master 1 - Starting Memory Read Line Multiple, at           6891765000
 test master 1 - Starting Memory Read Line Multiple, at           6892275000
 test master 1 - Starting Memory Read Line Multiple, at           6893745000
 test master 1 - Starting Memory Read Line Multiple, at           6894255000
 test master 1 - Starting Memory Read Line, at           6895785000
 test master 1 - Starting Memory Read Line, at           6896235000
 test master 1 - Starting Memory Read, at           6898635000
 test master 1 - Starting Memory Read, at           6899025000
 test target 1 - Starting Config Write, at           6902265000
 test master 1 - Starting Memory Write, at           6903045000
 test master 1 - Starting Memory Write, at           6905055000
 test master 1 - Starting Memory Write, at           6906375000
 test master 1 - Starting Memory Write, at           6908265000
 test master 1 - Starting Memory Write, at           6909615000
 test master 1 - Starting Memory Read Line, at           6911625000
 test master 1 - Starting Memory Write, at           6913125000
 test master 1 - Starting Memory Read Line, at           6915135000
 test target 1 - Starting Config Write, at           6918465000
 test master 1 - Starting Memory Write, at           6919245000
 test master 1 - Starting Memory Write, at           6919425000
 test master 1 - Starting Memory Write, at           6919725000
 test master 1 - Starting Memory Read, at           6919905000
 test master 1 - Starting Memory Write, at           6920295000
 test master 1 - Starting Memory Read, at           6920475000
 test master 1 - Starting Memory Write, at           6922155000
 test master 1 - Starting Memory Write, at           6925515000
 test master 2 - Starting Memory Read Line, at           6928995000
 test master 2 - Starting Memory Read Line, at           6929415000
 test master 2 - Starting Memory Read Line, at           6929775000
 test master 2 - Starting Memory Read Line, at           6930195000
 test master 1 - Starting Memory Write, at           6930645000
 test master 1 - Starting Memory Write, at           6930945000
 test master 1 - Starting Memory Write, at           6931245000
 test master 2 - Starting Memory Read Line, at           6931665000
 test master 2 - Starting Memory Read Line, at           6932055000
 test master 2 - Starting Memory Read Line, at           6932325000
 test master 2 - Starting Memory Read Line, at           6932715000
 test master 2 - Starting Memory Read Line Multiple, at           6933015000
 test master 2 - Starting Memory Read Line Multiple, at           6933405000
 test master 1 - Starting Memory Write, at           6935295000
 test master 1 - Starting Memory Write, at           6935595000
 test master 2 - Starting Memory Read, at           6936015000
 test master 2 - Starting Memory Read, at           6936405000
 test master 2 - Starting Memory Read, at           6936675000
 test master 2 - Starting Memory Read, at           6937065000
 test master 1 - Starting Memory Write, at           6938715000
 test master 1 - Starting Memory Read, at           6938925000
 test master 1 - Starting Memory Write, at           6939135000
 test master 1 - Starting Memory Read, at           6939345000
 test master 1 - Starting Memory Write, at           6939555000
 test master 1 - Starting Memory Read, at           6939765000
 test master 1 - Starting Memory Read, at           6939975000
 test master 1 - Starting Memory Write, at           6940185000
 test master 1 - Starting Memory Write, at           6940395000
 test master 1 - Starting Memory Read, at           6940605000
 test master 1 - Starting Memory Write, at           6940815000
 test master 1 - Starting Memory Write, at           6941025000
 test master 1 - Starting Memory Write, at           6941235000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at           6945645000
 test target 1 - Starting Memory Write, at           6945975000
 test master 1 - Starting Memory Write, at           6946275000
 test target 1 - Starting Memory Write, at           6946515000
 test target 1 - Starting Memory Write, at           6946845000
 test target 1 - Starting Memory Write, at           6947175000
 test master 1 - Starting Memory Write, at           6947595000
 test target 1 - Starting Memory Write, at           6948165000
 test target 1 - Starting Memory Write, at           6948855000
 test target 1 - Starting Memory Write, at           6949215000
 test master 1 - Starting Memory Write, at           6949545000
 test target 1 - Starting Memory Write, at           6949845000
 test target 1 - Starting Memory Write, at           6950205000
 test target 1 - Starting Memory Write, at           6950565000
 test master 1 - Starting Memory Write, at           6951045000
 test target 1 - Starting Memory Write, at           6951825000
 test target 1 - Starting Memory Write, at           6952515000
 test target 1 - Starting Memory Write, at           6952845000
 test master 1 - Starting Memory Read, at           6953145000
 test target 1 - Starting Memory Write, at           6953385000
 test master 1 - Starting Memory Read, at           6953685000
 test target 1 - Starting Memory Write, at           6953925000
 test master 1 - Starting Memory Read, at           6954225000
 test target 1 - Starting Memory Write, at           6954465000
 test master 1 - Starting Memory Read, at           6954765000
 test target 1 - Starting Memory Write, at           6955005000
 test master 1 - Starting Memory Read, at           6955305000
 test target 1 - Starting Memory Write, at           6955545000
 test master 1 - Starting Memory Write, at           6955845000
 test target 1 - Starting Memory Write, at           6956085000
 test target 1 - Starting Memory Write, at           6956415000
 test target 1 - Starting Memory Write, at           6956745000
 test target 1 - Starting Memory Read, at           6957135000
 test master 1 - Starting Memory Write, at           6957555000
 test master 1 - Starting Memory Read, at           6957855000
 test target 1 - Starting Memory Write, at           6958425000
 test master 1 - Starting Memory Write, at           6958935000
 test target 1 - Starting Memory Read, at           6959445000
 test target 1 - Starting Memory Write, at           6960375000
 test master 1 - Starting Memory Read, at           6960795000
 test master 1 - Starting Memory Write, at           6961185000
 test master 1 - Starting Memory Write, at           6961605000
 test master 1 - Starting Memory Read, at           6961905000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           6964125000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           6965145000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           6987885000
 test target 1 - Starting Config Write, at           6988725000
 test target 1 - Starting Config Write, at           6989565000
 test target 2 - Starting Config Write, at           6990405000
 test target 2 - Starting Config Write, at           6991245000
 test target 2 - Starting Config Write, at           6992085000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           6993675000
 test target 1 - Starting Memory Read, at           6993945000
 test target 1 - Starting Memory Write, at           6994515000
 test target 1 - Starting Memory Read, at           6994785000
 test target 1 - Starting Memory Write, at           6995565000
 test target 1 - Starting Memory Read, at           6996885000
 test target 1 - Starting Memory Read, at           6997545000
 test target 1 - Starting Memory Read, at           6998115000
 test target 1 - Starting Memory Read, at           6998685000
 test target 1 - Starting Memory Read, at           6999435000
 test target 1 - Starting Memory Read, at           7000605000
 test target 1 - Starting Memory Read, at           7001385000
 test target 1 - Starting Memory Read, at           7002555000
 test target 1 - Starting Memory Read, at           7003305000
 test target 1 - Starting Memory Read, at           7006215000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           7011675000
 test target 1 - Starting Memory Read, at           7011945000
 test target 1 - Starting Memory Write, at           7012515000
 test target 1 - Starting Memory Read, at           7012785000
 test target 1 - Starting Memory Write, at           7013565000
 test target 1 - Starting Memory Read, at           7014885000
 test target 1 - Starting Memory Read, at           7015545000
 test target 1 - Starting Memory Read, at           7016115000
 test target 1 - Starting Memory Read, at           7016685000
 test target 1 - Starting Memory Read, at           7017435000
 test target 1 - Starting Memory Read, at           7018605000
 test target 1 - Starting Memory Read, at           7019385000
 test target 1 - Starting Memory Read, at           7020555000
 test target 1 - Starting Memory Read, at           7021305000
 test target 1 - Starting Memory Read, at           7024215000
 test target 1 - Starting Memory Write, at           7029675000
 test target 1 - Starting Memory Read, at           7029945000
 test target 1 - Starting Memory Write, at           7030515000
 test target 1 - Starting Memory Read, at           7030785000
 test target 1 - Starting Memory Write, at           7031565000
 test target 1 - Starting Memory Read, at           7032885000
 test target 1 - Starting Memory Read, at           7033545000
 test target 1 - Starting Memory Read, at           7034115000
 test target 1 - Starting Memory Read, at           7034685000
 test target 1 - Starting Memory Read, at           7035435000
 test target 1 - Starting Memory Read, at           7036605000
 test target 1 - Starting Memory Read, at           7037385000
 test target 1 - Starting Memory Read, at           7038555000
 test target 1 - Starting Memory Read, at           7039305000
 test target 1 - Starting Memory Read, at           7042215000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           7051845000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           7057425000
 test target 1 - Starting Memory Write, at           7058175000
 test target 1 - Starting Memory Read, at           7058745000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           7060065000
 test target 1 - Starting Config Write, at           7061775000
 test target 1 - Starting Memory Read, at           7062465000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           7063725000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           7065645000
 test target 1 - Starting Memory Write, at           7066695000
 test target 1 - Starting Memory Write, at           7066995000
 test target 1 - Starting Memory Read, at           7067265000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           7069245000
 test target 1 - Starting Memory Write, at           7071855000
 test target 1 - Starting Memory Write, at           7072305000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           7075935000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           7077645000
 test target 1 - Starting Memory Read, at           7078875000
 test target 1 - Starting Memory Read, at           7080045000
 test target 1 - Starting Memory Read, at           7081695000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           7086885000
 test target 2 - Starting Config Write, at           7087725000
 test target 1 - Starting Memory Write, at           7088415000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           7088595000
 test target 1 - Starting Memory Write, at           7089495000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           7089675000
 test target 1 - Starting Memory Write, at           7090575000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           7091805000
 test target 1 - Starting Memory Read, at           7093755000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           7093935000
 test target 1 - Starting Memory Read, at           7095705000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           7097175000
 test master 2 - Starting Memory Write, at           7097175000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           7097235000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7097985000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7098015000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7098315000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7098345000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7099125000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7099155000
 test target 1 - Starting Memory Write, at           7100745000
 test master 2 - Starting Memory Write, at           7100745000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7102275000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7102305000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7103775000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7103805000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7105275000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7105305000
 test target 1 - Starting Memory Write, at           7107075000
 test master 2 - Starting Memory Write, at           7107075000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           7107135000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7108575000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7108605000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7108905000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7108935000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7109715000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7109745000
 test target 1 - Starting Memory Write, at           7110825000
 test master 2 - Starting Memory Write, at           7110825000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           7113255000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           7114695000
 test master 1 - Starting Memory Read, at           7115085000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           7115265000
 test target 1 - Starting Config Write, at           7117365000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           7119255000
 test target 1 - Starting Memory Write, at           7119465000
 test target 1 - Starting Memory Write, at           7119675000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           7120155000
 test target 1 - Starting Memory Write, at           7120395000
 test target 1 - Starting Memory Write, at           7120635000
 test target 1 - Starting Memory Write, at           7121115000
 test target 1 - Starting Memory Write, at           7121475000
 test target 1 - Starting Memory Write, at           7121955000
 test target 1 - Starting Memory Write, at           7122615000
 test target 1 - Starting Memory Write, at           7122855000
 test target 1 - Starting Memory Write, at           7123515000
 test target 1 - Starting Memory Write, at           7123905000
 test target 1 - Starting Memory Write, at           7124415000
 test target 1 - Starting Memory Write, at           7127595000
 test target 1 - Starting Memory Write, at           7127835000
 test target 1 - Starting Memory Write, at           7128075000
 test target 1 - Starting Memory Write, at           7128465000
 test target 1 - Starting Memory Write, at           7128855000
 test target 1 - Starting Memory Read, at           7137675000
 test target 1 - Starting Memory Read, at           7138875000
 test target 1 - Starting Memory Read, at           7140075000
 test target 1 - Starting Memory Read, at           7141275000
 test target 1 - Starting Memory Read, at           7142475000
 test target 1 - Starting Memory Read, at           7143675000
 test target 1 - Starting Memory Read, at           7144875000
 test target 1 - Starting Memory Read, at           7146075000
 test target 1 - Starting Memory Read, at           7147275000
 test target 1 - Starting Memory Read, at           7148475000
 test target 1 - Starting Memory Read, at           7149675000
 test target 1 - Starting Memory Read, at           7150875000
 test target 1 - Starting Memory Read, at           7152075000
 test target 1 - Starting Memory Read, at           7153275000
 test target 1 - Starting Memory Read, at           7154475000
 test target 1 - Starting Memory Read, at           7155675000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           7156845000
 test target 1 - Starting Memory Read, at           7157055000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           7158255000
 test target 1 - Starting Memory Read, at           7160775000
 test target 1 - Starting Memory Read, at           7161345000
 test target 1 - Starting Memory Read, at           7162005000
 test target 1 - Starting Memory Read, at           7162815000
 test target 1 - Starting Memory Read, at           7163625000
 test target 1 - Starting Memory Read, at           7164915000
 test target 1 - Starting Memory Read, at           7166085000
 test target 1 - Starting Memory Read, at           7166865000
 test target 1 - Starting Memory Read, at           7170105000
 test target 1 - Starting Memory Read, at           7173165000
 test target 1 - Starting Memory Read, at           7173975000
 test target 1 - Starting Memory Read, at           7174785000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           7175835000
 test master 1 - Starting Memory Write, at           7176165000
 test target 1 - Starting Memory Write, at           7176165000
 test target 1 - Starting Memory Write, at           7176375000
 test target 1 - Starting Memory Read, at           7177095000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           7180065000
 test master 1 - Starting Memory Write, at           7180395000
 test target 1 - Starting Memory Write, at           7180395000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           7184985000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           7186005000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           7208745000
 test target 1 - Starting Config Write, at           7209585000
 test target 1 - Starting Config Write, at           7210425000
 test target 2 - Starting Config Write, at           7211265000
 test target 2 - Starting Config Write, at           7212105000
 test target 2 - Starting Config Write, at           7212945000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           7214535000
 test target 1 - Starting Memory Read, at           7214835000
 test target 1 - Starting Memory Write, at           7215495000
 test target 1 - Starting Memory Read, at           7215795000
 test target 1 - Starting Memory Write, at           7216665000
 test target 1 - Starting Memory Read, at           7218045000
 test target 1 - Starting Memory Read, at           7218705000
 test target 1 - Starting Memory Read, at           7219365000
 test target 1 - Starting Memory Read, at           7220055000
 test target 1 - Starting Memory Read, at           7220895000
 test target 1 - Starting Memory Read, at           7222065000
 test target 1 - Starting Memory Read, at           7222845000
 test target 1 - Starting Memory Read, at           7224015000
 test target 1 - Starting Memory Read, at           7224765000
 test target 1 - Starting Memory Read, at           7227675000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           7233135000
 test target 1 - Starting Memory Read, at           7233435000
 test target 1 - Starting Memory Write, at           7234095000
 test target 1 - Starting Memory Read, at           7234395000
 test target 1 - Starting Memory Write, at           7235265000
 test target 1 - Starting Memory Read, at           7236645000
 test target 1 - Starting Memory Read, at           7237305000
 test target 1 - Starting Memory Read, at           7237965000
 test target 1 - Starting Memory Read, at           7238655000
 test target 1 - Starting Memory Read, at           7239495000
 test target 1 - Starting Memory Read, at           7240665000
 test target 1 - Starting Memory Read, at           7241445000
 test target 1 - Starting Memory Read, at           7242615000
 test target 1 - Starting Memory Read, at           7243365000
 test target 1 - Starting Memory Read, at           7246275000
 test target 1 - Starting Memory Write, at           7251735000
 test target 1 - Starting Memory Read, at           7252035000
 test target 1 - Starting Memory Write, at           7252695000
 test target 1 - Starting Memory Read, at           7252995000
 test target 1 - Starting Memory Write, at           7253865000
 test target 1 - Starting Memory Read, at           7255245000
 test target 1 - Starting Memory Read, at           7255905000
 test target 1 - Starting Memory Read, at           7256565000
 test target 1 - Starting Memory Read, at           7257255000
 test target 1 - Starting Memory Read, at           7258095000
 test target 1 - Starting Memory Read, at           7259265000
 test target 1 - Starting Memory Read, at           7260045000
 test target 1 - Starting Memory Read, at           7261215000
 test target 1 - Starting Memory Read, at           7261965000
 test target 1 - Starting Memory Read, at           7264875000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           7274505000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           7280085000
 test target 1 - Starting Memory Write, at           7280835000
 test target 1 - Starting Memory Read, at           7281435000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           7282815000
 test target 1 - Starting Config Write, at           7284555000
 test target 1 - Starting Memory Read, at           7285245000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           7286625000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           7288545000
 test target 1 - Starting Memory Write, at           7289595000
 test target 1 - Starting Memory Write, at           7289925000
 test target 1 - Starting Memory Read, at           7290225000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           7292265000
 test target 1 - Starting Memory Write, at           7294875000
 test target 1 - Starting Memory Write, at           7295355000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           7299015000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           7300725000
 test target 1 - Starting Memory Read, at           7301955000
 test target 1 - Starting Memory Read, at           7303125000
 test target 1 - Starting Memory Read, at           7304775000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           7309965000
 test target 2 - Starting Config Write, at           7310805000
 test target 1 - Starting Memory Write, at           7311495000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           7311705000
 test target 1 - Starting Memory Write, at           7312605000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           7312815000
 test target 1 - Starting Memory Write, at           7313715000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           7315005000
 test target 1 - Starting Memory Read, at           7316955000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           7317165000
 test target 1 - Starting Memory Read, at           7318905000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           7320375000
 test master 2 - Starting Memory Write, at           7320375000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           7320435000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7321215000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7321245000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7321545000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7321575000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7322355000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7322385000
 test target 1 - Starting Memory Write, at           7323975000
 test master 2 - Starting Memory Write, at           7323975000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7325535000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7325565000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7327035000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7327065000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7328535000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7328565000
 test target 1 - Starting Memory Write, at           7330335000
 test master 2 - Starting Memory Write, at           7330335000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           7330395000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7331865000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7331895000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7332195000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7332225000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7333005000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7333035000
 test target 1 - Starting Memory Write, at           7334115000
 test master 2 - Starting Memory Write, at           7334115000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           7336575000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           7338015000
 test master 1 - Starting Memory Read, at           7338405000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           7338585000
 test target 1 - Starting Config Write, at           7340685000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           7342575000
 test target 1 - Starting Memory Write, at           7342815000
 test target 1 - Starting Memory Write, at           7343055000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           7343565000
 test target 1 - Starting Memory Write, at           7343835000
 test target 1 - Starting Memory Write, at           7344105000
 test target 1 - Starting Memory Write, at           7344615000
 test target 1 - Starting Memory Write, at           7345005000
 test target 1 - Starting Memory Write, at           7345515000
 test target 1 - Starting Memory Write, at           7346205000
 test target 1 - Starting Memory Write, at           7346475000
 test target 1 - Starting Memory Write, at           7347165000
 test target 1 - Starting Memory Write, at           7347585000
 test target 1 - Starting Memory Write, at           7348125000
 test target 1 - Starting Memory Write, at           7351335000
 test target 1 - Starting Memory Write, at           7351605000
 test target 1 - Starting Memory Write, at           7351875000
 test target 1 - Starting Memory Write, at           7352295000
 test target 1 - Starting Memory Write, at           7352715000
 test target 1 - Starting Memory Read, at           7361565000
 test target 1 - Starting Memory Read, at           7362825000
 test target 1 - Starting Memory Read, at           7364025000
 test target 1 - Starting Memory Read, at           7365225000
 test target 1 - Starting Memory Read, at           7366425000
 test target 1 - Starting Memory Read, at           7367625000
 test target 1 - Starting Memory Read, at           7368825000
 test target 1 - Starting Memory Read, at           7370025000
 test target 1 - Starting Memory Read, at           7371225000
 test target 1 - Starting Memory Read, at           7372425000
 test target 1 - Starting Memory Read, at           7373625000
 test target 1 - Starting Memory Read, at           7374825000
 test target 1 - Starting Memory Read, at           7376025000
 test target 1 - Starting Memory Read, at           7377225000
 test target 1 - Starting Memory Read, at           7378425000
 test target 1 - Starting Memory Read, at           7379625000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           7380765000
 test target 1 - Starting Memory Read, at           7381005000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           7382295000
 test target 1 - Starting Memory Read, at           7384845000
 test target 1 - Starting Memory Read, at           7385535000
 test target 1 - Starting Memory Read, at           7386165000
 test target 1 - Starting Memory Read, at           7387005000
 test target 1 - Starting Memory Read, at           7387785000
 test target 1 - Starting Memory Read, at           7389105000
 test target 1 - Starting Memory Read, at           7390275000
 test target 1 - Starting Memory Read, at           7391025000
 test target 1 - Starting Memory Read, at           7394385000
 test target 1 - Starting Memory Read, at           7397505000
 test target 1 - Starting Memory Read, at           7398315000
 test target 1 - Starting Memory Read, at           7399125000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           7400175000
 test master 1 - Starting Memory Write, at           7400535000
 test target 1 - Starting Memory Write, at           7400535000
 test target 1 - Starting Memory Write, at           7400775000
 test target 1 - Starting Memory Read, at           7401525000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           7404525000
 test master 1 - Starting Memory Write, at           7404885000
 test target 1 - Starting Memory Write, at           7404885000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           7409445000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           7410585000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           7433445000
 test target 1 - Starting Config Write, at           7434285000
 test target 1 - Starting Config Write, at           7435125000
 test target 2 - Starting Config Write, at           7435965000
 test target 2 - Starting Config Write, at           7436805000
 test target 2 - Starting Config Write, at           7437645000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           7439235000
 test target 1 - Starting Memory Read, at           7439565000
 test target 1 - Starting Memory Write, at           7440195000
 test target 1 - Starting Memory Read, at           7440525000
 test target 1 - Starting Memory Write, at           7441365000
 test target 1 - Starting Memory Read, at           7442745000
 test target 1 - Starting Memory Read, at           7443405000
 test target 1 - Starting Memory Read, at           7444065000
 test target 1 - Starting Memory Read, at           7444755000
 test target 1 - Starting Memory Read, at           7445595000
 test target 1 - Starting Memory Read, at           7446885000
 test target 1 - Starting Memory Read, at           7447755000
 test target 1 - Starting Memory Read, at           7449045000
 test target 1 - Starting Memory Read, at           7449915000
 test target 1 - Starting Memory Read, at           7452825000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           7458255000
 test target 1 - Starting Memory Read, at           7458585000
 test target 1 - Starting Memory Write, at           7459215000
 test target 1 - Starting Memory Read, at           7459545000
 test target 1 - Starting Memory Write, at           7460385000
 test target 1 - Starting Memory Read, at           7461765000
 test target 1 - Starting Memory Read, at           7462425000
 test target 1 - Starting Memory Read, at           7463085000
 test target 1 - Starting Memory Read, at           7463775000
 test target 1 - Starting Memory Read, at           7464615000
 test target 1 - Starting Memory Read, at           7465905000
 test target 1 - Starting Memory Read, at           7466775000
 test target 1 - Starting Memory Read, at           7468065000
 test target 1 - Starting Memory Read, at           7468935000
 test target 1 - Starting Memory Read, at           7471845000
 test target 1 - Starting Memory Write, at           7477275000
 test target 1 - Starting Memory Read, at           7477605000
 test target 1 - Starting Memory Write, at           7478235000
 test target 1 - Starting Memory Read, at           7478565000
 test target 1 - Starting Memory Write, at           7479405000
 test target 1 - Starting Memory Read, at           7480785000
 test target 1 - Starting Memory Read, at           7481445000
 test target 1 - Starting Memory Read, at           7482105000
 test target 1 - Starting Memory Read, at           7482795000
 test target 1 - Starting Memory Read, at           7483635000
 test target 1 - Starting Memory Read, at           7484925000
 test target 1 - Starting Memory Read, at           7485795000
 test target 1 - Starting Memory Read, at           7487085000
 test target 1 - Starting Memory Read, at           7487955000
 test target 1 - Starting Memory Read, at           7490865000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           7500465000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           7506045000
 test target 1 - Starting Memory Write, at           7506795000
 test target 1 - Starting Memory Read, at           7507425000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           7508775000
 test target 1 - Starting Config Write, at           7510515000
 test target 1 - Starting Memory Read, at           7511205000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           7512585000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           7514505000
 test target 1 - Starting Memory Write, at           7515555000
 test target 1 - Starting Memory Write, at           7515915000
 test target 1 - Starting Memory Read, at           7516245000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           7518345000
 test target 1 - Starting Memory Write, at           7521015000
 test target 1 - Starting Memory Write, at           7521525000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           7525215000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           7527045000
 test target 1 - Starting Memory Read, at           7528395000
 test target 1 - Starting Memory Read, at           7529685000
 test target 1 - Starting Memory Read, at           7531425000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           7536705000
 test target 2 - Starting Config Write, at           7537545000
 test target 1 - Starting Memory Write, at           7538235000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           7538475000
 test target 1 - Starting Memory Write, at           7539375000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           7539615000
 test target 1 - Starting Memory Write, at           7540515000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           7541805000
 test target 1 - Starting Memory Read, at           7543755000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           7543995000
 test target 1 - Starting Memory Read, at           7545705000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           7547175000
 test master 2 - Starting Memory Write, at           7547175000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           7547235000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7548045000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7548075000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7548375000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7548405000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7549185000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7549215000
 test target 1 - Starting Memory Write, at           7550805000
 test master 2 - Starting Memory Write, at           7550805000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7552395000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7552425000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7553895000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7553925000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7555395000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7555425000
 test target 1 - Starting Memory Write, at           7557195000
 test master 2 - Starting Memory Write, at           7557195000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           7557255000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7558755000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7558785000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7559085000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7559115000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7559895000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7559925000
 test target 1 - Starting Memory Write, at           7561005000
 test master 2 - Starting Memory Write, at           7561005000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           7563495000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           7564935000
 test master 1 - Starting Memory Read, at           7565325000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           7565505000
 test target 1 - Starting Config Write, at           7567605000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           7569675000
 test target 1 - Starting Memory Write, at           7569945000
 test target 1 - Starting Memory Write, at           7570215000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           7570755000
 test target 1 - Starting Memory Write, at           7571055000
 test target 1 - Starting Memory Write, at           7571355000
 test target 1 - Starting Memory Write, at           7571895000
 test target 1 - Starting Memory Write, at           7572315000
 test target 1 - Starting Memory Write, at           7572855000
 test target 1 - Starting Memory Write, at           7573575000
 test target 1 - Starting Memory Write, at           7573875000
 test target 1 - Starting Memory Write, at           7574595000
 test target 1 - Starting Memory Write, at           7575045000
 test target 1 - Starting Memory Write, at           7575615000
 test target 1 - Starting Memory Write, at           7578855000
 test target 1 - Starting Memory Write, at           7579155000
 test target 1 - Starting Memory Write, at           7579455000
 test target 1 - Starting Memory Write, at           7579905000
 test target 1 - Starting Memory Write, at           7580355000
 test target 1 - Starting Memory Read, at           7589235000
 test target 1 - Starting Memory Read, at           7590435000
 test target 1 - Starting Memory Read, at           7591635000
 test target 1 - Starting Memory Read, at           7592835000
 test target 1 - Starting Memory Read, at           7594035000
 test target 1 - Starting Memory Read, at           7595235000
 test target 1 - Starting Memory Read, at           7596435000
 test target 1 - Starting Memory Read, at           7597635000
 test target 1 - Starting Memory Read, at           7598835000
 test target 1 - Starting Memory Read, at           7600035000
 test target 1 - Starting Memory Read, at           7601235000
 test target 1 - Starting Memory Read, at           7602435000
 test target 1 - Starting Memory Read, at           7603635000
 test target 1 - Starting Memory Read, at           7604835000
 test target 1 - Starting Memory Read, at           7606035000
 test target 1 - Starting Memory Read, at           7607235000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           7608405000
 test target 1 - Starting Memory Read, at           7608675000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           7609935000
 test target 1 - Starting Memory Read, at           7612515000
 test target 1 - Starting Memory Read, at           7613145000
 test target 1 - Starting Memory Read, at           7613925000
 test target 1 - Starting Memory Read, at           7614855000
 test target 1 - Starting Memory Read, at           7615665000
 test target 1 - Starting Memory Read, at           7616955000
 test target 1 - Starting Memory Read, at           7618245000
 test target 1 - Starting Memory Read, at           7619115000
 test target 1 - Starting Memory Read, at           7622475000
 test target 1 - Starting Memory Read, at           7625625000
 test target 1 - Starting Memory Read, at           7626435000
 test target 1 - Starting Memory Read, at           7627245000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           7628295000
 test master 1 - Starting Memory Write, at           7628685000
 test target 1 - Starting Memory Write, at           7628685000
 test target 1 - Starting Memory Write, at           7628955000
 test target 1 - Starting Memory Read, at           7629735000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           7632795000
 test master 1 - Starting Memory Write, at           7633185000
 test target 1 - Starting Memory Write, at           7633185000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           7637685000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           7638825000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           7661685000
 test target 1 - Starting Config Write, at           7662645000
 test target 1 - Starting Config Write, at           7663485000
 test target 2 - Starting Config Write, at           7664325000
 test target 2 - Starting Config Write, at           7665165000
 test target 2 - Starting Config Write, at           7666005000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           7667595000
 test target 1 - Starting Memory Read, at           7667955000
 test target 1 - Starting Memory Write, at           7668675000
 test target 1 - Starting Memory Read, at           7669035000
 test target 1 - Starting Memory Write, at           7669965000
 test target 1 - Starting Memory Read, at           7671405000
 test target 1 - Starting Memory Read, at           7672155000
 test target 1 - Starting Memory Read, at           7672845000
 test target 1 - Starting Memory Read, at           7673505000
 test target 1 - Starting Memory Read, at           7674345000
 test target 1 - Starting Memory Read, at           7675605000
 test target 1 - Starting Memory Read, at           7676505000
 test target 1 - Starting Memory Read, at           7677765000
 test target 1 - Starting Memory Read, at           7678665000
 test target 1 - Starting Memory Read, at           7681665000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           7687095000
 test target 1 - Starting Memory Read, at           7687455000
 test target 1 - Starting Memory Write, at           7688175000
 test target 1 - Starting Memory Read, at           7688535000
 test target 1 - Starting Memory Write, at           7689465000
 test target 1 - Starting Memory Read, at           7690905000
 test target 1 - Starting Memory Read, at           7691655000
 test target 1 - Starting Memory Read, at           7692345000
 test target 1 - Starting Memory Read, at           7693005000
 test target 1 - Starting Memory Read, at           7693845000
 test target 1 - Starting Memory Read, at           7695105000
 test target 1 - Starting Memory Read, at           7696005000
 test target 1 - Starting Memory Read, at           7697265000
 test target 1 - Starting Memory Read, at           7698165000
 test target 1 - Starting Memory Read, at           7701165000
 test target 1 - Starting Memory Write, at           7706595000
 test target 1 - Starting Memory Read, at           7706955000
 test target 1 - Starting Memory Write, at           7707675000
 test target 1 - Starting Memory Read, at           7708035000
 test target 1 - Starting Memory Write, at           7708965000
 test target 1 - Starting Memory Read, at           7710405000
 test target 1 - Starting Memory Read, at           7711155000
 test target 1 - Starting Memory Read, at           7711845000
 test target 1 - Starting Memory Read, at           7712505000
 test target 1 - Starting Memory Read, at           7713345000
 test target 1 - Starting Memory Read, at           7714605000
 test target 1 - Starting Memory Read, at           7715505000
 test target 1 - Starting Memory Read, at           7716765000
 test target 1 - Starting Memory Read, at           7717665000
 test target 1 - Starting Memory Read, at           7720665000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           7730265000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           7735845000
 test target 1 - Starting Memory Write, at           7736745000
 test target 1 - Starting Memory Read, at           7737405000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           7738815000
 test target 1 - Starting Config Write, at           7740555000
 test target 1 - Starting Memory Read, at           7741245000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           7742625000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           7744725000
 test target 1 - Starting Memory Write, at           7745895000
 test target 1 - Starting Memory Write, at           7746285000
 test target 1 - Starting Memory Read, at           7746645000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           7748805000
 test target 1 - Starting Memory Write, at           7751475000
 test target 1 - Starting Memory Write, at           7752015000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           7755735000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           7757565000
 test target 1 - Starting Memory Read, at           7758915000
 test target 1 - Starting Memory Read, at           7760205000
 test target 1 - Starting Memory Read, at           7761945000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           7767225000
 test target 2 - Starting Config Write, at           7768065000
 test target 1 - Starting Memory Write, at           7768755000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           7769025000
 test target 1 - Starting Memory Write, at           7769925000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           7770195000
 test target 1 - Starting Memory Write, at           7771095000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           7772445000
 test target 1 - Starting Memory Read, at           7774515000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           7774785000
 test target 1 - Starting Memory Read, at           7776585000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           7778175000
 test master 2 - Starting Memory Write, at           7778175000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           7778235000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7779075000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7779105000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7779405000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7779435000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7780215000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7780245000
 test target 1 - Starting Memory Write, at           7781835000
 test master 2 - Starting Memory Write, at           7781835000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7783455000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7783485000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7784955000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7784985000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7786455000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7786485000
 test target 1 - Starting Memory Write, at           7788255000
 test master 2 - Starting Memory Write, at           7788255000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           7788315000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7789845000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7789875000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7790175000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7790205000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7790985000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7791015000
 test target 1 - Starting Memory Write, at           7792095000
 test master 2 - Starting Memory Write, at           7792095000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           7794615000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           7796055000
 test master 1 - Starting Memory Read, at           7796445000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           7796625000
 test target 1 - Starting Config Write, at           7798725000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           7800795000
 test target 1 - Starting Memory Write, at           7801095000
 test target 1 - Starting Memory Write, at           7801395000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           7801965000
 test target 1 - Starting Memory Write, at           7802295000
 test target 1 - Starting Memory Write, at           7802625000
 test target 1 - Starting Memory Write, at           7803195000
 test target 1 - Starting Memory Write, at           7803645000
 test target 1 - Starting Memory Write, at           7804215000
 test target 1 - Starting Memory Write, at           7804965000
 test target 1 - Starting Memory Write, at           7805295000
 test target 1 - Starting Memory Write, at           7806045000
 test target 1 - Starting Memory Write, at           7806525000
 test target 1 - Starting Memory Write, at           7807125000
 test target 1 - Starting Memory Write, at           7810395000
 test target 1 - Starting Memory Write, at           7810725000
 test target 1 - Starting Memory Write, at           7811055000
 test target 1 - Starting Memory Write, at           7811535000
 test target 1 - Starting Memory Write, at           7812015000
 test target 1 - Starting Memory Read, at           7820925000
 test target 1 - Starting Memory Read, at           7822185000
 test target 1 - Starting Memory Read, at           7823475000
 test target 1 - Starting Memory Read, at           7824765000
 test target 1 - Starting Memory Read, at           7826085000
 test target 1 - Starting Memory Read, at           7827375000
 test target 1 - Starting Memory Read, at           7828665000
 test target 1 - Starting Memory Read, at           7829985000
 test target 1 - Starting Memory Read, at           7831275000
 test target 1 - Starting Memory Read, at           7832565000
 test target 1 - Starting Memory Read, at           7833885000
 test target 1 - Starting Memory Read, at           7835175000
 test target 1 - Starting Memory Read, at           7836465000
 test target 1 - Starting Memory Read, at           7837785000
 test target 1 - Starting Memory Read, at           7839075000
 test target 1 - Starting Memory Read, at           7840365000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           7841625000
 test target 1 - Starting Memory Read, at           7841925000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           7843275000
 test target 1 - Starting Memory Read, at           7845885000
 test target 1 - Starting Memory Read, at           7846635000
 test target 1 - Starting Memory Read, at           7847385000
 test target 1 - Starting Memory Read, at           7848345000
 test target 1 - Starting Memory Read, at           7849245000
 test target 1 - Starting Memory Read, at           7850565000
 test target 1 - Starting Memory Read, at           7851825000
 test target 1 - Starting Memory Read, at           7852725000
 test target 1 - Starting Memory Read, at           7856085000
 test target 1 - Starting Memory Read, at           7859205000
 test target 1 - Starting Memory Read, at           7860105000
 test target 1 - Starting Memory Read, at           7861005000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           7862145000
 test master 1 - Starting Memory Write, at           7862565000
 test target 1 - Starting Memory Write, at           7862565000
 test target 1 - Starting Memory Write, at           7862865000
 test target 1 - Starting Memory Read, at           7863675000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           7866675000
 test master 1 - Starting Memory Write, at           7867095000
 test target 1 - Starting Memory Write, at           7867095000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7871595000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           7871865000
 test master 2 - Starting Memory Read, at           7872075000
 test master 2 - Starting Memory Read, at           7872285000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7873815000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           7874235000
 test master 2 - Starting Memory Read, at           7874445000
 test master 2 - Starting Memory Read, at           7874655000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7875915000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7876515000
 test master 2 - Starting Memory Read Line Multiple, at           7876725000
 test master 2 - Starting Memory Read Line Multiple, at           7876995000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7878975000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7889595000
 test master 2 - Starting Memory Read Line Multiple, at           7889805000
 test master 2 - Starting Memory Read Line Multiple, at           7890105000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7891215000
 test master 2 - Starting Memory Read Line Multiple, at           7891425000
 test master 2 - Starting Memory Read Line Multiple, at           7891725000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7892835000
 test master 2 - Starting Memory Read Line Multiple, at           7893045000
 test master 2 - Starting Memory Read Line Multiple, at           7893345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7894455000
 test master 2 - Starting Memory Read Line Multiple, at           7894665000
 test master 2 - Starting Memory Read Line Multiple, at           7894965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7896075000
 test master 2 - Starting Memory Read Line Multiple, at           7896285000
 test master 2 - Starting Memory Read Line Multiple, at           7896585000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7897695000
 test master 2 - Starting Memory Read Line Multiple, at           7897905000
 test master 2 - Starting Memory Read Line Multiple, at           7898205000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7899315000
 test master 2 - Starting Memory Read Line Multiple, at           7899525000
 test master 2 - Starting Memory Read Line Multiple, at           7899825000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7900935000
 test master 2 - Starting Memory Read Line Multiple, at           7901145000
 test master 2 - Starting Memory Read Line Multiple, at           7901445000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           7902555000
 test master 2 - Starting Memory Read Line, at           7902765000
 test master 2 - Starting Memory Read Line, at           7903005000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           7903665000
 test master 2 - Starting Memory Read Line, at           7903875000
 test master 2 - Starting Memory Read Line, at           7904085000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7905135000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7906455000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7908975000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7910655000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           7915065000
 test master 2 - Starting Memory Write, at           7915335000
 test master 2 - Starting Memory Write, at           7915605000
 test master 2 - Starting Memory Write, at           7915875000
 test master 2 - Starting Memory Write, at           7916145000
 test master 1 - Starting Memory Read, at           7916535000
 test master 1 - Starting Memory Read, at           7916865000
 test master 1 - Starting Memory Read, at           7917405000
 test master 1 - Starting Memory Read, at           7917735000
 test master 1 - Starting Memory Read, at           7918275000
 test master 1 - Starting Memory Read, at           7918605000
 test master 2 - Starting Memory Write, at           7919775000
 test master 2 - Starting Memory Write, at           7920045000
 test master 2 - Starting Memory Write, at           7920315000
 test master 2 - Starting Memory Write, at           7920585000
 test master 2 - Starting Memory Write, at           7920855000
 test master 1 - Starting Memory Read, at           7921245000
 test master 1 - Starting Memory Read, at           7921575000
 test master 1 - Starting Memory Read, at           7922115000
 test master 1 - Starting Memory Read, at           7922445000
 test master 1 - Starting Memory Read, at           7922985000
 test master 1 - Starting Memory Read, at           7923315000
 test master 2 - Starting Memory Write, at           7924875000
 test master 2 - Starting Memory Write, at           7925895000
 test master 2 - Starting Memory Write, at           7926915000
 test master 2 - Starting Memory Write, at           7927935000
 test master 2 - Starting Memory Write, at           7929855000
 test master 2 - Starting Memory Write, at           7930875000
 test master 2 - Starting Memory Write, at           7931895000
 test master 2 - Starting Memory Write, at           7932915000
 test master 2 - Starting Memory Write, at           7934835000
 test master 2 - Starting Memory Write, at           7936695000
 test master 2 - Starting Memory Write, at           7938555000
 test master 2 - Starting Memory Write, at           7940415000
 test master 2 - Starting Memory Write, at           7943175000
 test master 2 - Starting Memory Write, at           7945215000
 test master 2 - Starting Memory Write, at           7947255000
 test master 2 - Starting Memory Write, at           7949295000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           7953465000
*** monitor - CBE Bus Changed when TRDY Desserted, at           7953495000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7955175000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           7955445000
 test master 2 - Starting Memory Read, at           7955655000
 test master 2 - Starting Memory Read, at           7955865000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7957395000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           7957815000
 test master 2 - Starting Memory Read, at           7958025000
 test master 2 - Starting Memory Read, at           7958235000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7959495000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7960095000
 test master 2 - Starting Memory Read Line Multiple, at           7960305000
 test master 2 - Starting Memory Read Line Multiple, at           7960575000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7962555000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7973175000
 test master 2 - Starting Memory Read Line Multiple, at           7973385000
 test master 2 - Starting Memory Read Line Multiple, at           7973685000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7974795000
 test master 2 - Starting Memory Read Line Multiple, at           7975005000
 test master 2 - Starting Memory Read Line Multiple, at           7975305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7976415000
 test master 2 - Starting Memory Read Line Multiple, at           7976625000
 test master 2 - Starting Memory Read Line Multiple, at           7976925000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7978035000
 test master 2 - Starting Memory Read Line Multiple, at           7978245000
 test master 2 - Starting Memory Read Line Multiple, at           7978545000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7979655000
 test master 2 - Starting Memory Read Line Multiple, at           7979865000
 test master 2 - Starting Memory Read Line Multiple, at           7980165000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7981275000
 test master 2 - Starting Memory Read Line Multiple, at           7981485000
 test master 2 - Starting Memory Read Line Multiple, at           7981785000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7982895000
 test master 2 - Starting Memory Read Line Multiple, at           7983105000
 test master 2 - Starting Memory Read Line Multiple, at           7983405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           7984515000
 test master 2 - Starting Memory Read Line Multiple, at           7984725000
 test master 2 - Starting Memory Read Line Multiple, at           7985025000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           7986135000
 test master 2 - Starting Memory Read Line, at           7986345000
 test master 2 - Starting Memory Read Line, at           7986585000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           7987245000
 test master 2 - Starting Memory Read Line, at           7987455000
 test master 2 - Starting Memory Read Line, at           7987665000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7988715000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7990035000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7992555000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           7994235000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           7998645000
 test master 2 - Starting Memory Write, at           7998915000
 test master 2 - Starting Memory Write, at           7999185000
 test master 2 - Starting Memory Write, at           7999455000
 test master 2 - Starting Memory Write, at           7999725000
 test master 1 - Starting Memory Read, at           8000115000
 test master 1 - Starting Memory Read, at           8000445000
 test master 1 - Starting Memory Read, at           8000985000
 test master 1 - Starting Memory Read, at           8001315000
 test master 1 - Starting Memory Read, at           8001855000
 test master 1 - Starting Memory Read, at           8002185000
 test master 2 - Starting Memory Write, at           8003355000
 test master 2 - Starting Memory Write, at           8003625000
 test master 2 - Starting Memory Write, at           8003895000
 test master 2 - Starting Memory Write, at           8004165000
 test master 2 - Starting Memory Write, at           8004435000
 test master 1 - Starting Memory Read, at           8004825000
 test master 1 - Starting Memory Read, at           8005155000
 test master 1 - Starting Memory Read, at           8005695000
 test master 1 - Starting Memory Read, at           8006025000
 test master 1 - Starting Memory Read, at           8006565000
 test master 1 - Starting Memory Read, at           8006895000
 test master 2 - Starting Memory Write, at           8008455000
 test master 2 - Starting Memory Write, at           8009475000
 test master 2 - Starting Memory Write, at           8010495000
 test master 2 - Starting Memory Write, at           8011515000
 test master 2 - Starting Memory Write, at           8013435000
 test master 2 - Starting Memory Write, at           8014455000
 test master 2 - Starting Memory Write, at           8015475000
 test master 2 - Starting Memory Write, at           8016495000
 test master 2 - Starting Memory Write, at           8018415000
 test master 2 - Starting Memory Write, at           8020275000
 test master 2 - Starting Memory Write, at           8022135000
 test master 2 - Starting Memory Write, at           8023995000
 test master 2 - Starting Memory Write, at           8026755000
 test master 2 - Starting Memory Write, at           8028795000
 test master 2 - Starting Memory Write, at           8030835000
 test master 2 - Starting Memory Write, at           8032875000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           8037045000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8037075000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8038755000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           8039025000
 test master 2 - Starting Memory Read, at           8039235000
 test master 2 - Starting Memory Read, at           8039445000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8040975000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           8041395000
 test master 2 - Starting Memory Read, at           8041605000
 test master 2 - Starting Memory Read, at           8041815000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8043075000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8043675000
 test master 2 - Starting Memory Read Line Multiple, at           8043885000
 test master 2 - Starting Memory Read Line Multiple, at           8044155000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8046135000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8056755000
 test master 2 - Starting Memory Read Line Multiple, at           8056965000
 test master 2 - Starting Memory Read Line Multiple, at           8057265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8058375000
 test master 2 - Starting Memory Read Line Multiple, at           8058585000
 test master 2 - Starting Memory Read Line Multiple, at           8058885000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8059995000
 test master 2 - Starting Memory Read Line Multiple, at           8060205000
 test master 2 - Starting Memory Read Line Multiple, at           8060505000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8061615000
 test master 2 - Starting Memory Read Line Multiple, at           8061825000
 test master 2 - Starting Memory Read Line Multiple, at           8062125000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8063235000
 test master 2 - Starting Memory Read Line Multiple, at           8063445000
 test master 2 - Starting Memory Read Line Multiple, at           8063745000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8064855000
 test master 2 - Starting Memory Read Line Multiple, at           8065065000
 test master 2 - Starting Memory Read Line Multiple, at           8065365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8066475000
 test master 2 - Starting Memory Read Line Multiple, at           8066685000
 test master 2 - Starting Memory Read Line Multiple, at           8066985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8068095000
 test master 2 - Starting Memory Read Line Multiple, at           8068305000
 test master 2 - Starting Memory Read Line Multiple, at           8068605000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           8069715000
 test master 2 - Starting Memory Read Line, at           8069925000
 test master 2 - Starting Memory Read Line, at           8070165000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           8070825000
 test master 2 - Starting Memory Read Line, at           8071035000
 test master 2 - Starting Memory Read Line, at           8071245000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8072295000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8073615000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8076135000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8077815000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           8082225000
 test master 2 - Starting Memory Write, at           8082495000
 test master 2 - Starting Memory Write, at           8082765000
 test master 2 - Starting Memory Write, at           8083035000
 test master 2 - Starting Memory Write, at           8083305000
 test master 1 - Starting Memory Read, at           8083695000
 test master 1 - Starting Memory Read, at           8084025000
 test master 1 - Starting Memory Read, at           8084565000
 test master 1 - Starting Memory Read, at           8084895000
 test master 1 - Starting Memory Read, at           8085435000
 test master 1 - Starting Memory Read, at           8085765000
 test master 2 - Starting Memory Write, at           8086935000
 test master 2 - Starting Memory Write, at           8087205000
 test master 2 - Starting Memory Write, at           8087475000
 test master 2 - Starting Memory Write, at           8087745000
 test master 2 - Starting Memory Write, at           8088015000
 test master 1 - Starting Memory Read, at           8088405000
 test master 1 - Starting Memory Read, at           8088735000
 test master 1 - Starting Memory Read, at           8089275000
 test master 1 - Starting Memory Read, at           8089605000
 test master 1 - Starting Memory Read, at           8090145000
 test master 1 - Starting Memory Read, at           8090475000
 test master 2 - Starting Memory Write, at           8092035000
 test master 2 - Starting Memory Write, at           8093055000
 test master 2 - Starting Memory Write, at           8094075000
 test master 2 - Starting Memory Write, at           8095095000
 test master 2 - Starting Memory Write, at           8097015000
 test master 2 - Starting Memory Write, at           8098035000
 test master 2 - Starting Memory Write, at           8099055000
 test master 2 - Starting Memory Write, at           8100075000
 test master 2 - Starting Memory Write, at           8101995000
 test master 2 - Starting Memory Write, at           8103855000
 test master 2 - Starting Memory Write, at           8105715000
 test master 2 - Starting Memory Write, at           8107575000
 test master 2 - Starting Memory Write, at           8110335000
 test master 2 - Starting Memory Write, at           8112375000
 test master 2 - Starting Memory Write, at           8114415000
 test master 2 - Starting Memory Write, at           8116455000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           8120625000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8120655000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8122335000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           8122605000
 test master 2 - Starting Memory Read, at           8122815000
 test master 2 - Starting Memory Read, at           8123025000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8124555000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           8124975000
 test master 2 - Starting Memory Read, at           8125185000
 test master 2 - Starting Memory Read, at           8125395000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8126655000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8127255000
 test master 2 - Starting Memory Read Line Multiple, at           8127465000
 test master 2 - Starting Memory Read Line Multiple, at           8127735000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8129715000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8140335000
 test master 2 - Starting Memory Read Line Multiple, at           8140545000
 test master 2 - Starting Memory Read Line Multiple, at           8140845000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8141955000
 test master 2 - Starting Memory Read Line Multiple, at           8142165000
 test master 2 - Starting Memory Read Line Multiple, at           8142465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8143575000
 test master 2 - Starting Memory Read Line Multiple, at           8143785000
 test master 2 - Starting Memory Read Line Multiple, at           8144085000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8145195000
 test master 2 - Starting Memory Read Line Multiple, at           8145405000
 test master 2 - Starting Memory Read Line Multiple, at           8145705000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8146815000
 test master 2 - Starting Memory Read Line Multiple, at           8147025000
 test master 2 - Starting Memory Read Line Multiple, at           8147325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8148435000
 test master 2 - Starting Memory Read Line Multiple, at           8148645000
 test master 2 - Starting Memory Read Line Multiple, at           8148945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8150055000
 test master 2 - Starting Memory Read Line Multiple, at           8150265000
 test master 2 - Starting Memory Read Line Multiple, at           8150565000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           8151675000
 test master 2 - Starting Memory Read Line Multiple, at           8151885000
 test master 2 - Starting Memory Read Line Multiple, at           8152185000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           8153295000
 test master 2 - Starting Memory Read Line, at           8153505000
 test master 2 - Starting Memory Read Line, at           8153745000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           8154405000
 test master 2 - Starting Memory Read Line, at           8154615000
 test master 2 - Starting Memory Read Line, at           8154825000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8155875000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8157195000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8159715000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           8161395000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           8165805000
 test master 2 - Starting Memory Write, at           8166075000
 test master 2 - Starting Memory Write, at           8166345000
 test master 2 - Starting Memory Write, at           8166615000
 test master 2 - Starting Memory Write, at           8166885000
 test master 1 - Starting Memory Read, at           8167275000
 test master 1 - Starting Memory Read, at           8167605000
 test master 1 - Starting Memory Read, at           8168145000
 test master 1 - Starting Memory Read, at           8168475000
 test master 1 - Starting Memory Read, at           8169015000
 test master 1 - Starting Memory Read, at           8169345000
 test master 2 - Starting Memory Write, at           8170515000
 test master 2 - Starting Memory Write, at           8170785000
 test master 2 - Starting Memory Write, at           8171055000
 test master 2 - Starting Memory Write, at           8171325000
 test master 2 - Starting Memory Write, at           8171595000
 test master 1 - Starting Memory Read, at           8171985000
 test master 1 - Starting Memory Read, at           8172315000
 test master 1 - Starting Memory Read, at           8172855000
 test master 1 - Starting Memory Read, at           8173185000
 test master 1 - Starting Memory Read, at           8173725000
 test master 1 - Starting Memory Read, at           8174055000
 test master 2 - Starting Memory Write, at           8175615000
 test master 2 - Starting Memory Write, at           8176635000
 test master 2 - Starting Memory Write, at           8177655000
 test master 2 - Starting Memory Write, at           8178675000
 test master 2 - Starting Memory Write, at           8180595000
 test master 2 - Starting Memory Write, at           8181615000
 test master 2 - Starting Memory Write, at           8182635000
 test master 2 - Starting Memory Write, at           8183655000
 test master 2 - Starting Memory Write, at           8185575000
 test master 2 - Starting Memory Write, at           8187435000
 test master 2 - Starting Memory Write, at           8189295000
 test master 2 - Starting Memory Write, at           8191155000
 test master 2 - Starting Memory Write, at           8193915000
 test master 2 - Starting Memory Write, at           8195955000
 test master 2 - Starting Memory Write, at           8197995000
 test master 2 - Starting Memory Write, at           8200035000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           8204205000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8204235000
 test master 1 - Starting Memory Read, at           8205915000
 test master 1 - Starting Memory Read, at           8206275000
 test master 1 - Starting Memory Read, at           8207385000
 test master 1 - Starting Memory Read, at           8207745000
 test master 1 - Starting Memory Read Line, at           8208825000
 test master 1 - Starting Memory Read Line, at           8209185000
 test master 1 - Starting Memory Read Line, at           8210265000
 test master 1 - Starting Memory Read Line, at           8210625000
 test master 1 - Starting Memory Read Line, at           8211765000
 test master 1 - Starting Memory Read Line, at           8212185000
 test master 1 - Starting Memory Read Line, at           8213625000
 test master 1 - Starting Memory Read Line, at           8214045000
 test master 1 - Starting Memory Read Line Multiple, at           8215485000
 test master 1 - Starting Memory Read Line Multiple, at           8215965000
 test master 1 - Starting Memory Read Line Multiple, at           8217885000
 test master 1 - Starting Memory Read Line Multiple, at           8218365000
 test master 1 - Starting Memory Read Line, at           8220285000
 test master 1 - Starting Memory Read Line, at           8220705000
 test master 1 - Starting Memory Read, at           8222835000
 test master 1 - Starting Memory Read, at           8223195000
 test target 1 - Starting Config Write, at           8225865000
 test master 1 - Starting Memory Write, at           8226495000
 test master 1 - Starting Memory Write, at           8235795000
 test master 1 - Starting Memory Write, at           8237115000
 test master 1 - Starting Memory Write, at           8245815000
 test master 1 - Starting Memory Write, at           8247135000
 test master 1 - Starting Memory Read Line, at           8256435000
 test master 1 - Starting Memory Write, at           8257935000
 test master 1 - Starting Memory Read Line, at           8267235000
 test target 1 - Starting Config Write, at           8270145000
 test master 1 - Starting Memory Write, at           8270775000
 test master 1 - Starting Memory Write, at           8270925000
 test master 1 - Starting Memory Write, at           8271195000
 test master 1 - Starting Memory Read, at           8271345000
 test master 1 - Starting Memory Write, at           8271705000
 test master 1 - Starting Memory Read, at           8271855000
 test master 1 - Starting Memory Write, at           8273115000
 test master 1 - Starting Memory Write, at           8283735000
 test master 2 - Starting Memory Read Line, at           8294475000
 test master 2 - Starting Memory Read Line, at           8294865000
 test master 2 - Starting Memory Read Line, at           8295555000
 test master 2 - Starting Memory Read Line, at           8295945000
 test master 1 - Starting Memory Write, at           8296725000
 test master 1 - Starting Memory Write, at           8297085000
 test master 1 - Starting Memory Write, at           8297475000
 test master 2 - Starting Memory Read Line, at           8297985000
 test master 2 - Starting Memory Read Line, at           8298345000
 test master 2 - Starting Memory Read Line, at           8298705000
 test master 2 - Starting Memory Read Line, at           8299065000
 test master 2 - Starting Memory Read Line Multiple, at           8299455000
 test master 2 - Starting Memory Read Line Multiple, at           8299815000
 test master 1 - Starting Memory Write, at           8301435000
 test master 1 - Starting Memory Write, at           8301795000
 test master 2 - Starting Memory Read, at           8302305000
 test master 2 - Starting Memory Read, at           8302665000
 test master 2 - Starting Memory Read, at           8303025000
 test master 2 - Starting Memory Read, at           8303385000
 test master 1 - Starting Memory Write, at           8304795000
 test master 1 - Starting Memory Read, at           8305005000
 test master 1 - Starting Memory Write, at           8305215000
 test master 1 - Starting Memory Read, at           8305425000
 test master 1 - Starting Memory Write, at           8305635000
 test master 1 - Starting Memory Read, at           8305845000
 test master 1 - Starting Memory Read, at           8306055000
 test master 1 - Starting Memory Write, at           8306265000
 test master 1 - Starting Memory Write, at           8306475000
 test master 1 - Starting Memory Read, at           8306685000
 test master 1 - Starting Memory Write, at           8306895000
 test master 1 - Starting Memory Write, at           8307105000
 test master 1 - Starting Memory Write, at           8307315000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at           8310825000
 test target 1 - Starting Memory Write, at           8311125000
 test master 1 - Starting Memory Write, at           8311395000
 test target 1 - Starting Memory Write, at           8311605000
 test target 1 - Starting Memory Write, at           8311905000
 test target 1 - Starting Memory Write, at           8312205000
 test master 1 - Starting Memory Write, at           8312595000
 test target 1 - Starting Memory Write, at           8313135000
 test target 1 - Starting Memory Write, at           8313795000
 test target 1 - Starting Memory Write, at           8314125000
 test master 1 - Starting Memory Write, at           8314425000
 test target 1 - Starting Memory Write, at           8314935000
 test target 1 - Starting Memory Write, at           8315265000
 test target 1 - Starting Memory Write, at           8315595000
 test master 1 - Starting Memory Write, at           8316285000
 test target 1 - Starting Memory Write, at           8317275000
 test target 1 - Starting Memory Write, at           8318295000
 test target 1 - Starting Memory Write, at           8318595000
 test master 1 - Starting Memory Read, at           8318865000
 test target 1 - Starting Memory Write, at           8319075000
 test master 1 - Starting Memory Read, at           8319345000
 test target 1 - Starting Memory Write, at           8319555000
 test master 1 - Starting Memory Read, at           8319825000
 test target 1 - Starting Memory Write, at           8320035000
 test master 1 - Starting Memory Read, at           8320305000
 test target 1 - Starting Memory Write, at           8320515000
 test master 1 - Starting Memory Read, at           8320785000
 test target 1 - Starting Memory Write, at           8320995000
 test master 1 - Starting Memory Write, at           8321265000
 test target 1 - Starting Memory Write, at           8321475000
 test target 1 - Starting Memory Write, at           8321775000
 test target 1 - Starting Memory Write, at           8322075000
 test target 1 - Starting Memory Read, at           8322435000
 test master 1 - Starting Memory Write, at           8322825000
 test master 1 - Starting Memory Read, at           8323095000
 test target 1 - Starting Memory Write, at           8323635000
 test master 1 - Starting Memory Write, at           8324115000
 test target 1 - Starting Memory Read, at           8324565000
 test target 1 - Starting Memory Write, at           8325435000
 test master 1 - Starting Memory Read, at           8325825000
 test master 1 - Starting Memory Write, at           8326185000
 test master 1 - Starting Memory Write, at           8326575000
 test master 1 - Starting Memory Read, at           8326845000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           8329185000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           8330235000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           8354025000
 test target 1 - Starting Config Write, at           8354835000
 test target 1 - Starting Config Write, at           8355645000
 test target 2 - Starting Config Write, at           8356425000
 test target 2 - Starting Config Write, at           8357235000
 test target 2 - Starting Config Write, at           8358045000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           8359695000
 test target 1 - Starting Memory Read, at           8359965000
 test target 1 - Starting Memory Write, at           8360655000
 test target 1 - Starting Memory Read, at           8360925000
 test target 1 - Starting Memory Write, at           8361825000
 test target 1 - Starting Memory Read, at           8363025000
 test target 1 - Starting Memory Read, at           8363655000
 test target 1 - Starting Memory Read, at           8364225000
 test target 1 - Starting Memory Read, at           8364825000
 test target 1 - Starting Memory Read, at           8365575000
 test target 1 - Starting Memory Read, at           8366745000
 test target 1 - Starting Memory Read, at           8367645000
 test target 1 - Starting Memory Read, at           8368815000
 test target 1 - Starting Memory Read, at           8369685000
 test target 1 - Starting Memory Read, at           8372205000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           8377965000
 test target 1 - Starting Memory Read, at           8378235000
 test target 1 - Starting Memory Write, at           8378955000
 test target 1 - Starting Memory Read, at           8379225000
 test target 1 - Starting Memory Write, at           8380245000
 test target 1 - Starting Memory Read, at           8381445000
 test target 1 - Starting Memory Read, at           8382075000
 test target 1 - Starting Memory Read, at           8382645000
 test target 1 - Starting Memory Read, at           8383245000
 test target 1 - Starting Memory Read, at           8383995000
 test target 1 - Starting Memory Read, at           8385165000
 test target 1 - Starting Memory Read, at           8386065000
 test target 1 - Starting Memory Read, at           8387235000
 test target 1 - Starting Memory Read, at           8388105000
 test target 1 - Starting Memory Read, at           8390625000
 test target 1 - Starting Memory Write, at           8396385000
 test target 1 - Starting Memory Read, at           8396655000
 test target 1 - Starting Memory Write, at           8397375000
 test target 1 - Starting Memory Read, at           8397645000
 test target 1 - Starting Memory Write, at           8398665000
 test target 1 - Starting Memory Read, at           8399865000
 test target 1 - Starting Memory Read, at           8400495000
 test target 1 - Starting Memory Read, at           8401065000
 test target 1 - Starting Memory Read, at           8401665000
 test target 1 - Starting Memory Read, at           8402415000
 test target 1 - Starting Memory Read, at           8403585000
 test target 1 - Starting Memory Read, at           8404485000
 test target 1 - Starting Memory Read, at           8405655000
 test target 1 - Starting Memory Read, at           8406525000
 test target 1 - Starting Memory Read, at           8409045000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           8419545000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           8425275000
 test target 1 - Starting Memory Write, at           8426025000
 test target 1 - Starting Memory Read, at           8426535000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           8427885000
 test target 1 - Starting Config Write, at           8429685000
 test target 1 - Starting Memory Read, at           8430285000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           8431575000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           8433495000
 test target 1 - Starting Memory Write, at           8434545000
 test target 1 - Starting Memory Write, at           8434845000
 test target 1 - Starting Memory Read, at           8435115000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           8437215000
 test target 1 - Starting Memory Write, at           8439975000
 test target 1 - Starting Memory Write, at           8440395000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           8444055000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           8445795000
 test target 1 - Starting Memory Read, at           8447085000
 test target 1 - Starting Memory Read, at           8448225000
 test target 1 - Starting Memory Read, at           8449845000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           8455335000
 test target 2 - Starting Config Write, at           8456145000
 test target 1 - Starting Memory Write, at           8456745000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           8456925000
 test target 1 - Starting Memory Write, at           8457855000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           8458035000
 test target 1 - Starting Memory Write, at           8458995000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           8460315000
 test target 1 - Starting Memory Read, at           8462325000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           8462505000
 test target 1 - Starting Memory Read, at           8464335000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           8465865000
 test master 2 - Starting Memory Write, at           8465865000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           8465925000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8466735000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8466765000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8467065000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8467095000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8467935000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8467965000
 test target 1 - Starting Memory Write, at           8469615000
 test master 2 - Starting Memory Write, at           8469615000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8471235000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8471265000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8472795000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8472825000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8474355000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8474385000
 test target 1 - Starting Memory Write, at           8476245000
 test master 2 - Starting Memory Write, at           8476245000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           8476305000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8477835000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8477865000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8478165000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8478195000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8479035000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8479065000
 test target 1 - Starting Memory Write, at           8480175000
 test master 2 - Starting Memory Write, at           8480175000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           8482785000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           8484315000
 test master 1 - Starting Memory Read, at           8484765000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           8484945000
 test target 1 - Starting Config Write, at           8487195000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           8489385000
 test target 1 - Starting Memory Write, at           8489595000
 test target 1 - Starting Memory Write, at           8489805000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           8490315000
 test target 1 - Starting Memory Write, at           8490555000
 test target 1 - Starting Memory Write, at           8490795000
 test target 1 - Starting Memory Write, at           8491275000
 test target 1 - Starting Memory Write, at           8491605000
 test target 1 - Starting Memory Write, at           8492115000
 test target 1 - Starting Memory Write, at           8492775000
 test target 1 - Starting Memory Write, at           8493015000
 test target 1 - Starting Memory Write, at           8493675000
 test target 1 - Starting Memory Write, at           8494035000
 test target 1 - Starting Memory Write, at           8494575000
 test target 1 - Starting Memory Write, at           8498925000
 test target 1 - Starting Memory Write, at           8499165000
 test target 1 - Starting Memory Write, at           8499405000
 test target 1 - Starting Memory Write, at           8499765000
 test target 1 - Starting Memory Write, at           8500125000
 test target 1 - Starting Memory Read, at           8507235000
 test target 1 - Starting Memory Read, at           8508375000
 test target 1 - Starting Memory Read, at           8509485000
 test target 1 - Starting Memory Read, at           8510625000
 test target 1 - Starting Memory Read, at           8511735000
 test target 1 - Starting Memory Read, at           8512845000
 test target 1 - Starting Memory Read, at           8513985000
 test target 1 - Starting Memory Read, at           8515095000
 test target 1 - Starting Memory Read, at           8516205000
 test target 1 - Starting Memory Read, at           8517345000
 test target 1 - Starting Memory Read, at           8518455000
 test target 1 - Starting Memory Read, at           8519565000
 test target 1 - Starting Memory Read, at           8520705000
 test target 1 - Starting Memory Read, at           8521815000
 test target 1 - Starting Memory Read, at           8522925000
 test target 1 - Starting Memory Read, at           8524065000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           8525085000
 test target 1 - Starting Memory Read, at           8525295000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           8526795000
 test target 1 - Starting Memory Read, at           8528865000
 test target 1 - Starting Memory Read, at           8529555000
 test target 1 - Starting Memory Read, at           8530245000
 test target 1 - Starting Memory Read, at           8531085000
 test target 1 - Starting Memory Read, at           8531835000
 test target 1 - Starting Memory Read, at           8533035000
 test target 1 - Starting Memory Read, at           8534205000
 test target 1 - Starting Memory Read, at           8535105000
 test target 1 - Starting Memory Read, at           8538255000
 test target 1 - Starting Memory Read, at           8540895000
 test target 1 - Starting Memory Read, at           8541705000
 test target 1 - Starting Memory Read, at           8542515000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           8543655000
 test master 1 - Starting Memory Write, at           8543955000
 test target 1 - Starting Memory Write, at           8543955000
 test target 1 - Starting Memory Write, at           8544165000
 test target 1 - Starting Memory Read, at           8544795000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           8547405000
 test master 1 - Starting Memory Write, at           8547705000
 test target 1 - Starting Memory Write, at           8547705000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           8552385000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           8553435000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           8577225000
 test target 1 - Starting Config Write, at           8578185000
 test target 1 - Starting Config Write, at           8579145000
 test target 2 - Starting Config Write, at           8580105000
 test target 2 - Starting Config Write, at           8581065000
 test target 2 - Starting Config Write, at           8582025000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           8583855000
 test target 1 - Starting Memory Read, at           8584155000
 test target 1 - Starting Memory Write, at           8584815000
 test target 1 - Starting Memory Read, at           8585115000
 test target 1 - Starting Memory Write, at           8586135000
 test target 1 - Starting Memory Read, at           8587365000
 test target 1 - Starting Memory Read, at           8587995000
 test target 1 - Starting Memory Read, at           8588685000
 test target 1 - Starting Memory Read, at           8589405000
 test target 1 - Starting Memory Read, at           8590275000
 test target 1 - Starting Memory Read, at           8591445000
 test target 1 - Starting Memory Read, at           8592345000
 test target 1 - Starting Memory Read, at           8593515000
 test target 1 - Starting Memory Read, at           8594385000
 test target 1 - Starting Memory Read, at           8596905000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           8602665000
 test target 1 - Starting Memory Read, at           8602965000
 test target 1 - Starting Memory Write, at           8603655000
 test target 1 - Starting Memory Read, at           8603955000
 test target 1 - Starting Memory Write, at           8604945000
 test target 1 - Starting Memory Read, at           8606175000
 test target 1 - Starting Memory Read, at           8606805000
 test target 1 - Starting Memory Read, at           8607525000
 test target 1 - Starting Memory Read, at           8608215000
 test target 1 - Starting Memory Read, at           8609085000
 test target 1 - Starting Memory Read, at           8610255000
 test target 1 - Starting Memory Read, at           8611125000
 test target 1 - Starting Memory Read, at           8612295000
 test target 1 - Starting Memory Read, at           8613165000
 test target 1 - Starting Memory Read, at           8615685000
 test target 1 - Starting Memory Write, at           8621445000
 test target 1 - Starting Memory Read, at           8621745000
 test target 1 - Starting Memory Write, at           8622435000
 test target 1 - Starting Memory Read, at           8622735000
 test target 1 - Starting Memory Write, at           8623725000
 test target 1 - Starting Memory Read, at           8624955000
 test target 1 - Starting Memory Read, at           8625585000
 test target 1 - Starting Memory Read, at           8626305000
 test target 1 - Starting Memory Read, at           8626995000
 test target 1 - Starting Memory Read, at           8627865000
 test target 1 - Starting Memory Read, at           8629035000
 test target 1 - Starting Memory Read, at           8629905000
 test target 1 - Starting Memory Read, at           8631075000
 test target 1 - Starting Memory Read, at           8631945000
 test target 1 - Starting Memory Read, at           8634465000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           8644965000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           8650815000
 test target 1 - Starting Memory Write, at           8651715000
 test target 1 - Starting Memory Read, at           8652255000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           8653575000
 test target 1 - Starting Config Write, at           8655405000
 test target 1 - Starting Memory Read, at           8656185000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           8657595000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           8659695000
 test target 1 - Starting Memory Write, at           8660895000
 test target 1 - Starting Memory Write, at           8661225000
 test target 1 - Starting Memory Read, at           8661525000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           8663715000
 test target 1 - Starting Memory Write, at           8666475000
 test target 1 - Starting Memory Write, at           8666925000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           8670615000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           8672475000
 test target 1 - Starting Memory Read, at           8673765000
 test target 1 - Starting Memory Read, at           8674905000
 test target 1 - Starting Memory Read, at           8676645000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           8682135000
 test target 2 - Starting Config Write, at           8683095000
 test target 1 - Starting Memory Write, at           8683875000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           8684085000
 test target 1 - Starting Memory Write, at           8685015000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           8685225000
 test target 1 - Starting Memory Write, at           8686155000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           8687475000
 test target 1 - Starting Memory Read, at           8689605000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           8689815000
 test target 1 - Starting Memory Read, at           8691735000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           8693385000
 test master 2 - Starting Memory Write, at           8693385000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           8693445000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8694255000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8694285000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8694585000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8694615000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8695455000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8695485000
 test target 1 - Starting Memory Write, at           8697135000
 test master 2 - Starting Memory Write, at           8697135000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8698755000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8698785000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8700315000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8700345000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8701875000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8701905000
 test target 1 - Starting Memory Write, at           8703765000
 test master 2 - Starting Memory Write, at           8703765000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           8703825000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8705355000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8705385000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8705685000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8705715000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8706555000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8706585000
 test target 1 - Starting Memory Write, at           8707695000
 test master 2 - Starting Memory Write, at           8707695000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           8710365000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           8711895000
 test master 1 - Starting Memory Read, at           8712345000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           8712525000
 test target 1 - Starting Config Write, at           8714775000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           8716965000
 test target 1 - Starting Memory Write, at           8717205000
 test target 1 - Starting Memory Write, at           8717445000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           8717955000
 test target 1 - Starting Memory Write, at           8718225000
 test target 1 - Starting Memory Write, at           8718495000
 test target 1 - Starting Memory Write, at           8719035000
 test target 1 - Starting Memory Write, at           8719395000
 test target 1 - Starting Memory Write, at           8719935000
 test target 1 - Starting Memory Write, at           8720655000
 test target 1 - Starting Memory Write, at           8720925000
 test target 1 - Starting Memory Write, at           8721615000
 test target 1 - Starting Memory Write, at           8722005000
 test target 1 - Starting Memory Write, at           8722575000
 test target 1 - Starting Memory Write, at           8726955000
 test target 1 - Starting Memory Write, at           8727225000
 test target 1 - Starting Memory Write, at           8727495000
 test target 1 - Starting Memory Write, at           8727885000
 test target 1 - Starting Memory Write, at           8728275000
 test target 1 - Starting Memory Read, at           8735415000
 test target 1 - Starting Memory Read, at           8736645000
 test target 1 - Starting Memory Read, at           8737905000
 test target 1 - Starting Memory Read, at           8739135000
 test target 1 - Starting Memory Read, at           8740365000
 test target 1 - Starting Memory Read, at           8741625000
 test target 1 - Starting Memory Read, at           8742855000
 test target 1 - Starting Memory Read, at           8744085000
 test target 1 - Starting Memory Read, at           8745345000
 test target 1 - Starting Memory Read, at           8746575000
 test target 1 - Starting Memory Read, at           8747805000
 test target 1 - Starting Memory Read, at           8749065000
 test target 1 - Starting Memory Read, at           8750295000
 test target 1 - Starting Memory Read, at           8751525000
 test target 1 - Starting Memory Read, at           8752785000
 test target 1 - Starting Memory Read, at           8754015000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           8755185000
 test target 1 - Starting Memory Read, at           8755425000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           8757015000
 test target 1 - Starting Memory Read, at           8759115000
 test target 1 - Starting Memory Read, at           8759775000
 test target 1 - Starting Memory Read, at           8760465000
 test target 1 - Starting Memory Read, at           8761305000
 test target 1 - Starting Memory Read, at           8762055000
 test target 1 - Starting Memory Read, at           8763255000
 test target 1 - Starting Memory Read, at           8764425000
 test target 1 - Starting Memory Read, at           8765325000
 test target 1 - Starting Memory Read, at           8768475000
 test target 1 - Starting Memory Read, at           8771235000
 test target 1 - Starting Memory Read, at           8772045000
 test target 1 - Starting Memory Read, at           8772855000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           8773995000
 test master 1 - Starting Memory Write, at           8774325000
 test target 1 - Starting Memory Write, at           8774325000
 test target 1 - Starting Memory Write, at           8774565000
 test target 1 - Starting Memory Read, at           8775225000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           8777925000
 test master 1 - Starting Memory Write, at           8778255000
 test target 1 - Starting Memory Write, at           8778255000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           8782965000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           8784135000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           8808045000
 test target 1 - Starting Config Write, at           8809005000
 test target 1 - Starting Config Write, at           8809965000
 test target 2 - Starting Config Write, at           8810925000
 test target 2 - Starting Config Write, at           8811885000
 test target 2 - Starting Config Write, at           8812845000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           8814675000
 test target 1 - Starting Memory Read, at           8815005000
 test target 1 - Starting Memory Write, at           8815635000
 test target 1 - Starting Memory Read, at           8815965000
 test target 1 - Starting Memory Write, at           8816955000
 test target 1 - Starting Memory Read, at           8818215000
 test target 1 - Starting Memory Read, at           8818845000
 test target 1 - Starting Memory Read, at           8819565000
 test target 1 - Starting Memory Read, at           8820255000
 test target 1 - Starting Memory Read, at           8821125000
 test target 1 - Starting Memory Read, at           8822295000
 test target 1 - Starting Memory Read, at           8823165000
 test target 1 - Starting Memory Read, at           8824335000
 test target 1 - Starting Memory Read, at           8825205000
 test target 1 - Starting Memory Read, at           8827725000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           8833485000
 test target 1 - Starting Memory Read, at           8833815000
 test target 1 - Starting Memory Write, at           8834475000
 test target 1 - Starting Memory Read, at           8834805000
 test target 1 - Starting Memory Write, at           8835765000
 test target 1 - Starting Memory Read, at           8837025000
 test target 1 - Starting Memory Read, at           8837655000
 test target 1 - Starting Memory Read, at           8838345000
 test target 1 - Starting Memory Read, at           8839065000
 test target 1 - Starting Memory Read, at           8839935000
 test target 1 - Starting Memory Read, at           8841105000
 test target 1 - Starting Memory Read, at           8842005000
 test target 1 - Starting Memory Read, at           8843175000
 test target 1 - Starting Memory Read, at           8844045000
 test target 1 - Starting Memory Read, at           8846565000
 test target 1 - Starting Memory Write, at           8852325000
 test target 1 - Starting Memory Read, at           8852655000
 test target 1 - Starting Memory Write, at           8853315000
 test target 1 - Starting Memory Read, at           8853645000
 test target 1 - Starting Memory Write, at           8854605000
 test target 1 - Starting Memory Read, at           8855865000
 test target 1 - Starting Memory Read, at           8856495000
 test target 1 - Starting Memory Read, at           8857185000
 test target 1 - Starting Memory Read, at           8857905000
 test target 1 - Starting Memory Read, at           8858775000
 test target 1 - Starting Memory Read, at           8859945000
 test target 1 - Starting Memory Read, at           8860845000
 test target 1 - Starting Memory Read, at           8862015000
 test target 1 - Starting Memory Read, at           8862885000
 test target 1 - Starting Memory Read, at           8865405000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           8875905000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           8881755000
 test target 1 - Starting Memory Write, at           8882655000
 test target 1 - Starting Memory Read, at           8883225000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           8884515000
 test target 1 - Starting Config Write, at           8886345000
 test target 1 - Starting Memory Read, at           8887125000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           8888535000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           8890635000
 test target 1 - Starting Memory Write, at           8891835000
 test target 1 - Starting Memory Write, at           8892195000
 test target 1 - Starting Memory Read, at           8892525000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           8894655000
 test target 1 - Starting Memory Write, at           8897475000
 test target 1 - Starting Memory Write, at           8897955000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           8901675000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           8903535000
 test target 1 - Starting Memory Read, at           8904825000
 test target 1 - Starting Memory Read, at           8905965000
 test target 1 - Starting Memory Read, at           8907705000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           8913195000
 test target 2 - Starting Config Write, at           8914155000
 test target 1 - Starting Memory Write, at           8914935000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           8915175000
 test target 1 - Starting Memory Write, at           8916135000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           8916375000
 test target 1 - Starting Memory Write, at           8917335000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           8918715000
 test target 1 - Starting Memory Read, at           8920845000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           8921085000
 test target 1 - Starting Memory Read, at           8922975000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           8924625000
 test master 2 - Starting Memory Write, at           8924625000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           8924685000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8925555000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8925585000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8925885000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8925915000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8926755000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8926785000
 test target 1 - Starting Memory Write, at           8928435000
 test master 2 - Starting Memory Write, at           8928435000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8930115000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8930145000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8931675000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8931705000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8933235000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8933265000
 test target 1 - Starting Memory Write, at           8935125000
 test master 2 - Starting Memory Write, at           8935125000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           8935185000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8936775000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8936805000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8937105000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8937135000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8937975000
*** monitor - CBE Bus Changed when TRDY Desserted, at           8938005000
 test target 1 - Starting Memory Write, at           8939115000
 test master 2 - Starting Memory Write, at           8939115000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           8941785000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           8943315000
 test master 1 - Starting Memory Read, at           8943765000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           8943945000
 test target 1 - Starting Config Write, at           8946195000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           8948385000
 test target 1 - Starting Memory Write, at           8948655000
 test target 1 - Starting Memory Write, at           8948925000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           8949495000
 test target 1 - Starting Memory Write, at           8949795000
 test target 1 - Starting Memory Write, at           8950095000
 test target 1 - Starting Memory Write, at           8950635000
 test target 1 - Starting Memory Write, at           8951025000
 test target 1 - Starting Memory Write, at           8951595000
 test target 1 - Starting Memory Write, at           8952315000
 test target 1 - Starting Memory Write, at           8952615000
 test target 1 - Starting Memory Write, at           8953335000
 test target 1 - Starting Memory Write, at           8953755000
 test target 1 - Starting Memory Write, at           8954355000
 test target 1 - Starting Memory Write, at           8958765000
 test target 1 - Starting Memory Write, at           8959065000
 test target 1 - Starting Memory Write, at           8959365000
 test target 1 - Starting Memory Write, at           8959785000
 test target 1 - Starting Memory Write, at           8960205000
 test target 1 - Starting Memory Read, at           8967375000
 test target 1 - Starting Memory Read, at           8968575000
 test target 1 - Starting Memory Read, at           8969805000
 test target 1 - Starting Memory Read, at           8971065000
 test target 1 - Starting Memory Read, at           8972295000
 test target 1 - Starting Memory Read, at           8973525000
 test target 1 - Starting Memory Read, at           8974785000
 test target 1 - Starting Memory Read, at           8976015000
 test target 1 - Starting Memory Read, at           8977245000
 test target 1 - Starting Memory Read, at           8978505000
 test target 1 - Starting Memory Read, at           8979735000
 test target 1 - Starting Memory Read, at           8980965000
 test target 1 - Starting Memory Read, at           8982225000
 test target 1 - Starting Memory Read, at           8983455000
 test target 1 - Starting Memory Read, at           8984685000
 test target 1 - Starting Memory Read, at           8985945000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           8987085000
 test target 1 - Starting Memory Read, at           8987355000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           8988945000
 test target 1 - Starting Memory Read, at           8991075000
 test target 1 - Starting Memory Read, at           8991825000
 test target 1 - Starting Memory Read, at           8992515000
 test target 1 - Starting Memory Read, at           8993355000
 test target 1 - Starting Memory Read, at           8994255000
 test target 1 - Starting Memory Read, at           8995575000
 test target 1 - Starting Memory Read, at           8996745000
 test target 1 - Starting Memory Read, at           8997645000
 test target 1 - Starting Memory Read, at           9000795000
 test target 1 - Starting Memory Read, at           9003555000
 test target 1 - Starting Memory Read, at           9004365000
 test target 1 - Starting Memory Read, at           9005175000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           9006315000
 test master 1 - Starting Memory Write, at           9006675000
 test target 1 - Starting Memory Write, at           9006675000
 test target 1 - Starting Memory Write, at           9006945000
 test target 1 - Starting Memory Read, at           9007635000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           9010365000
 test master 1 - Starting Memory Write, at           9010725000
 test target 1 - Starting Memory Write, at           9010725000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           9015465000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           9016635000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           9040545000
 test target 1 - Starting Config Write, at           9041505000
 test target 1 - Starting Config Write, at           9042465000
 test target 2 - Starting Config Write, at           9043425000
 test target 2 - Starting Config Write, at           9044385000
 test target 2 - Starting Config Write, at           9045345000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           9047175000
 test target 1 - Starting Memory Read, at           9047535000
 test target 1 - Starting Memory Write, at           9048285000
 test target 1 - Starting Memory Read, at           9048645000
 test target 1 - Starting Memory Write, at           9049725000
 test target 1 - Starting Memory Read, at           9051015000
 test target 1 - Starting Memory Read, at           9051765000
 test target 1 - Starting Memory Read, at           9052485000
 test target 1 - Starting Memory Read, at           9053175000
 test target 1 - Starting Memory Read, at           9054045000
 test target 1 - Starting Memory Read, at           9055335000
 test target 1 - Starting Memory Read, at           9056205000
 test target 1 - Starting Memory Read, at           9057495000
 test target 1 - Starting Memory Read, at           9058365000
 test target 1 - Starting Memory Read, at           9061005000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           9066795000
 test target 1 - Starting Memory Read, at           9067155000
 test target 1 - Starting Memory Write, at           9067905000
 test target 1 - Starting Memory Read, at           9068265000
 test target 1 - Starting Memory Write, at           9069345000
 test target 1 - Starting Memory Read, at           9070635000
 test target 1 - Starting Memory Read, at           9071385000
 test target 1 - Starting Memory Read, at           9072105000
 test target 1 - Starting Memory Read, at           9072795000
 test target 1 - Starting Memory Read, at           9073665000
 test target 1 - Starting Memory Read, at           9074955000
 test target 1 - Starting Memory Read, at           9075825000
 test target 1 - Starting Memory Read, at           9077115000
 test target 1 - Starting Memory Read, at           9077985000
 test target 1 - Starting Memory Read, at           9080625000
 test target 1 - Starting Memory Write, at           9086415000
 test target 1 - Starting Memory Read, at           9086775000
 test target 1 - Starting Memory Write, at           9087525000
 test target 1 - Starting Memory Read, at           9087885000
 test target 1 - Starting Memory Write, at           9088965000
 test target 1 - Starting Memory Read, at           9090255000
 test target 1 - Starting Memory Read, at           9091005000
 test target 1 - Starting Memory Read, at           9091725000
 test target 1 - Starting Memory Read, at           9092415000
 test target 1 - Starting Memory Read, at           9093285000
 test target 1 - Starting Memory Read, at           9094575000
 test target 1 - Starting Memory Read, at           9095445000
 test target 1 - Starting Memory Read, at           9096735000
 test target 1 - Starting Memory Read, at           9097605000
 test target 1 - Starting Memory Read, at           9100245000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           9110775000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           9116655000
 test target 1 - Starting Memory Write, at           9117555000
 test target 1 - Starting Memory Read, at           9118155000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           9119535000
 test target 1 - Starting Config Write, at           9121365000
 test target 1 - Starting Memory Read, at           9122145000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           9123555000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           9125655000
 test target 1 - Starting Memory Write, at           9126855000
 test target 1 - Starting Memory Write, at           9127245000
 test target 1 - Starting Memory Read, at           9127605000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           9129795000
 test target 1 - Starting Memory Write, at           9132615000
 test target 1 - Starting Memory Write, at           9133125000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           9136875000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           9138735000
 test target 1 - Starting Memory Read, at           9140145000
 test target 1 - Starting Memory Read, at           9141405000
 test target 1 - Starting Memory Read, at           9143145000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           9148755000
 test target 2 - Starting Config Write, at           9149715000
 test target 1 - Starting Memory Write, at           9150495000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           9150765000
 test target 1 - Starting Memory Write, at           9151695000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           9151965000
 test target 1 - Starting Memory Write, at           9152895000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           9154275000
 test target 1 - Starting Memory Read, at           9156405000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           9156675000
 test target 1 - Starting Memory Read, at           9158535000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           9160185000
 test master 2 - Starting Memory Write, at           9160185000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           9160245000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9161115000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9161145000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9161445000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9161475000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9162315000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9162345000
 test target 1 - Starting Memory Write, at           9163995000
 test master 2 - Starting Memory Write, at           9163995000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9165675000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9165705000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9167235000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9167265000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9168795000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9168825000
 test target 1 - Starting Memory Write, at           9170685000
 test master 2 - Starting Memory Write, at           9170685000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           9170745000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9172335000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9172365000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9172665000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9172695000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9173535000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9173565000
 test target 1 - Starting Memory Write, at           9174675000
 test master 2 - Starting Memory Write, at           9174675000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           9177405000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           9178935000
 test master 1 - Starting Memory Read, at           9179385000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           9179565000
 test target 1 - Starting Config Write, at           9181815000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           9184005000
 test target 1 - Starting Memory Write, at           9184305000
 test target 1 - Starting Memory Write, at           9184605000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           9185175000
 test target 1 - Starting Memory Write, at           9185505000
 test target 1 - Starting Memory Write, at           9185835000
 test target 1 - Starting Memory Write, at           9186435000
 test target 1 - Starting Memory Write, at           9186855000
 test target 1 - Starting Memory Write, at           9187455000
 test target 1 - Starting Memory Write, at           9188235000
 test target 1 - Starting Memory Write, at           9188565000
 test target 1 - Starting Memory Write, at           9189315000
 test target 1 - Starting Memory Write, at           9189765000
 test target 1 - Starting Memory Write, at           9190395000
 test target 1 - Starting Memory Write, at           9194835000
 test target 1 - Starting Memory Write, at           9195165000
 test target 1 - Starting Memory Write, at           9195495000
 test target 1 - Starting Memory Write, at           9195945000
 test target 1 - Starting Memory Write, at           9196395000
 test target 1 - Starting Memory Read, at           9203595000
 test target 1 - Starting Memory Read, at           9204885000
 test target 1 - Starting Memory Read, at           9206145000
 test target 1 - Starting Memory Read, at           9207375000
 test target 1 - Starting Memory Read, at           9208605000
 test target 1 - Starting Memory Read, at           9209865000
 test target 1 - Starting Memory Read, at           9211095000
 test target 1 - Starting Memory Read, at           9212325000
 test target 1 - Starting Memory Read, at           9213585000
 test target 1 - Starting Memory Read, at           9214815000
 test target 1 - Starting Memory Read, at           9216045000
 test target 1 - Starting Memory Read, at           9217305000
 test target 1 - Starting Memory Read, at           9218535000
 test target 1 - Starting Memory Read, at           9219765000
 test target 1 - Starting Memory Read, at           9221025000
 test target 1 - Starting Memory Read, at           9222255000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           9223425000
 test target 1 - Starting Memory Read, at           9223725000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           9225405000
 test target 1 - Starting Memory Read, at           9227565000
 test target 1 - Starting Memory Read, at           9228285000
 test target 1 - Starting Memory Read, at           9229095000
 test target 1 - Starting Memory Read, at           9229935000
 test target 1 - Starting Memory Read, at           9230835000
 test target 1 - Starting Memory Read, at           9232155000
 test target 1 - Starting Memory Read, at           9233445000
 test target 1 - Starting Memory Read, at           9234345000
 test target 1 - Starting Memory Read, at           9237615000
 test target 1 - Starting Memory Read, at           9240375000
 test target 1 - Starting Memory Read, at           9241305000
 test target 1 - Starting Memory Read, at           9242235000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           9243495000
 test master 1 - Starting Memory Write, at           9243885000
 test target 1 - Starting Memory Write, at           9243885000
 test target 1 - Starting Memory Write, at           9244185000
 test target 1 - Starting Memory Read, at           9244905000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           9247605000
 test master 1 - Starting Memory Write, at           9247995000
 test target 1 - Starting Memory Write, at           9247995000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9252735000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           9253065000
 test master 2 - Starting Memory Read, at           9253275000
 test master 2 - Starting Memory Read, at           9253485000
 test master 2 - Starting Memory Read, at           9253725000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9255255000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           9255795000
 test master 2 - Starting Memory Read, at           9256005000
 test master 2 - Starting Memory Read, at           9256455000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9257775000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9258495000
 test master 2 - Starting Memory Read Line Multiple, at           9258705000
 test master 2 - Starting Memory Read Line Multiple, at           9258915000
 test master 2 - Starting Memory Read Line Multiple, at           9259125000
 test master 2 - Starting Memory Read Line Multiple, at           9259395000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9261315000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9273855000
 test master 2 - Starting Memory Read Line Multiple, at           9274065000
 test master 2 - Starting Memory Read Line Multiple, at           9274275000
 test master 2 - Starting Memory Read Line Multiple, at           9274485000
 test master 2 - Starting Memory Read Line Multiple, at           9274785000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9275715000
 test master 2 - Starting Memory Read Line Multiple, at           9275925000
 test master 2 - Starting Memory Read Line Multiple, at           9276135000
 test master 2 - Starting Memory Read Line Multiple, at           9276345000
 test master 2 - Starting Memory Read Line Multiple, at           9276645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9277575000
 test master 2 - Starting Memory Read Line Multiple, at           9277785000
 test master 2 - Starting Memory Read Line Multiple, at           9277995000
 test master 2 - Starting Memory Read Line Multiple, at           9278205000
 test master 2 - Starting Memory Read Line Multiple, at           9278505000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9279435000
 test master 2 - Starting Memory Read Line Multiple, at           9279645000
 test master 2 - Starting Memory Read Line Multiple, at           9279855000
 test master 2 - Starting Memory Read Line Multiple, at           9280065000
 test master 2 - Starting Memory Read Line Multiple, at           9280365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9281295000
 test master 2 - Starting Memory Read Line Multiple, at           9281505000
 test master 2 - Starting Memory Read Line Multiple, at           9281715000
 test master 2 - Starting Memory Read Line Multiple, at           9281925000
 test master 2 - Starting Memory Read Line Multiple, at           9282225000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9283155000
 test master 2 - Starting Memory Read Line Multiple, at           9283365000
 test master 2 - Starting Memory Read Line Multiple, at           9283575000
 test master 2 - Starting Memory Read Line Multiple, at           9283785000
 test master 2 - Starting Memory Read Line Multiple, at           9284085000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9285015000
 test master 2 - Starting Memory Read Line Multiple, at           9285225000
 test master 2 - Starting Memory Read Line Multiple, at           9285435000
 test master 2 - Starting Memory Read Line Multiple, at           9285645000
 test master 2 - Starting Memory Read Line Multiple, at           9285945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9286875000
 test master 2 - Starting Memory Read Line Multiple, at           9287085000
 test master 2 - Starting Memory Read Line Multiple, at           9287295000
 test master 2 - Starting Memory Read Line Multiple, at           9287505000
 test master 2 - Starting Memory Read Line Multiple, at           9287805000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           9288735000
 test master 2 - Starting Memory Read Line, at           9288945000
 test master 2 - Starting Memory Read Line, at           9289155000
 test master 2 - Starting Memory Read Line, at           9289425000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           9289995000
 test master 2 - Starting Memory Read Line, at           9290205000
 test master 2 - Starting Memory Read Line, at           9290655000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9291765000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9293205000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9295845000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9297705000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           9302535000
 test master 2 - Starting Memory Write, at           9302865000
 test master 2 - Starting Memory Write, at           9303195000
 test master 2 - Starting Memory Write, at           9303525000
 test master 2 - Starting Memory Write, at           9303855000
 test master 1 - Starting Memory Read, at           9304305000
 test master 1 - Starting Memory Read, at           9304695000
 test master 1 - Starting Memory Read, at           9305235000
 test master 1 - Starting Memory Read, at           9305625000
 test master 1 - Starting Memory Read, at           9306165000
 test master 1 - Starting Memory Read, at           9306555000
 test master 2 - Starting Memory Write, at           9307755000
 test master 2 - Starting Memory Write, at           9308085000
 test master 2 - Starting Memory Write, at           9308415000
 test master 2 - Starting Memory Write, at           9308745000
 test master 2 - Starting Memory Write, at           9309075000
 test master 1 - Starting Memory Read, at           9309525000
 test master 1 - Starting Memory Read, at           9309915000
 test master 1 - Starting Memory Read, at           9310455000
 test master 1 - Starting Memory Read, at           9310845000
 test master 1 - Starting Memory Read, at           9311385000
 test master 1 - Starting Memory Read, at           9311775000
 test master 2 - Starting Memory Write, at           9313395000
 test master 2 - Starting Memory Write, at           9314505000
 test master 2 - Starting Memory Write, at           9315585000
 test master 2 - Starting Memory Write, at           9316665000
 test master 2 - Starting Memory Write, at           9318735000
 test master 2 - Starting Memory Write, at           9319845000
 test master 2 - Starting Memory Write, at           9320925000
 test master 2 - Starting Memory Write, at           9322005000
 test master 2 - Starting Memory Write, at           9324075000
 test master 2 - Starting Memory Write, at           9326025000
 test master 2 - Starting Memory Write, at           9327945000
 test master 2 - Starting Memory Write, at           9329865000
 test master 2 - Starting Memory Write, at           9332775000
 test master 2 - Starting Memory Write, at           9334935000
 test master 2 - Starting Memory Write, at           9337095000
 test master 2 - Starting Memory Write, at           9339255000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           9343545000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9343575000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9345435000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           9345765000
 test master 2 - Starting Memory Read, at           9345975000
 test master 2 - Starting Memory Read, at           9346185000
 test master 2 - Starting Memory Read, at           9346425000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9347955000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           9348495000
 test master 2 - Starting Memory Read, at           9348705000
 test master 2 - Starting Memory Read, at           9349155000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9350475000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9351195000
 test master 2 - Starting Memory Read Line Multiple, at           9351405000
 test master 2 - Starting Memory Read Line Multiple, at           9351615000
 test master 2 - Starting Memory Read Line Multiple, at           9351825000
 test master 2 - Starting Memory Read Line Multiple, at           9352095000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9354015000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9366555000
 test master 2 - Starting Memory Read Line Multiple, at           9366765000
 test master 2 - Starting Memory Read Line Multiple, at           9366975000
 test master 2 - Starting Memory Read Line Multiple, at           9367185000
 test master 2 - Starting Memory Read Line Multiple, at           9367485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9368415000
 test master 2 - Starting Memory Read Line Multiple, at           9368625000
 test master 2 - Starting Memory Read Line Multiple, at           9368835000
 test master 2 - Starting Memory Read Line Multiple, at           9369045000
 test master 2 - Starting Memory Read Line Multiple, at           9369345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9370275000
 test master 2 - Starting Memory Read Line Multiple, at           9370485000
 test master 2 - Starting Memory Read Line Multiple, at           9370695000
 test master 2 - Starting Memory Read Line Multiple, at           9370905000
 test master 2 - Starting Memory Read Line Multiple, at           9371205000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9372135000
 test master 2 - Starting Memory Read Line Multiple, at           9372345000
 test master 2 - Starting Memory Read Line Multiple, at           9372555000
 test master 2 - Starting Memory Read Line Multiple, at           9372765000
 test master 2 - Starting Memory Read Line Multiple, at           9373065000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9373995000
 test master 2 - Starting Memory Read Line Multiple, at           9374205000
 test master 2 - Starting Memory Read Line Multiple, at           9374415000
 test master 2 - Starting Memory Read Line Multiple, at           9374625000
 test master 2 - Starting Memory Read Line Multiple, at           9374925000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9375855000
 test master 2 - Starting Memory Read Line Multiple, at           9376065000
 test master 2 - Starting Memory Read Line Multiple, at           9376275000
 test master 2 - Starting Memory Read Line Multiple, at           9376485000
 test master 2 - Starting Memory Read Line Multiple, at           9376785000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9377715000
 test master 2 - Starting Memory Read Line Multiple, at           9377925000
 test master 2 - Starting Memory Read Line Multiple, at           9378135000
 test master 2 - Starting Memory Read Line Multiple, at           9378345000
 test master 2 - Starting Memory Read Line Multiple, at           9378645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9379575000
 test master 2 - Starting Memory Read Line Multiple, at           9379785000
 test master 2 - Starting Memory Read Line Multiple, at           9379995000
 test master 2 - Starting Memory Read Line Multiple, at           9380205000
 test master 2 - Starting Memory Read Line Multiple, at           9380505000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           9381435000
 test master 2 - Starting Memory Read Line, at           9381645000
 test master 2 - Starting Memory Read Line, at           9381855000
 test master 2 - Starting Memory Read Line, at           9382125000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           9382695000
 test master 2 - Starting Memory Read Line, at           9382905000
 test master 2 - Starting Memory Read Line, at           9383355000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9384465000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9385905000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9388545000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9390405000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           9395235000
 test master 2 - Starting Memory Write, at           9395565000
 test master 2 - Starting Memory Write, at           9395895000
 test master 2 - Starting Memory Write, at           9396225000
 test master 2 - Starting Memory Write, at           9396555000
 test master 1 - Starting Memory Read, at           9397005000
 test master 1 - Starting Memory Read, at           9397395000
 test master 1 - Starting Memory Read, at           9397935000
 test master 1 - Starting Memory Read, at           9398325000
 test master 1 - Starting Memory Read, at           9398865000
 test master 1 - Starting Memory Read, at           9399255000
 test master 2 - Starting Memory Write, at           9400455000
 test master 2 - Starting Memory Write, at           9400785000
 test master 2 - Starting Memory Write, at           9401115000
 test master 2 - Starting Memory Write, at           9401445000
 test master 2 - Starting Memory Write, at           9401775000
 test master 1 - Starting Memory Read, at           9402225000
 test master 1 - Starting Memory Read, at           9402615000
 test master 1 - Starting Memory Read, at           9403155000
 test master 1 - Starting Memory Read, at           9403545000
 test master 1 - Starting Memory Read, at           9404085000
 test master 1 - Starting Memory Read, at           9404475000
 test master 2 - Starting Memory Write, at           9406095000
 test master 2 - Starting Memory Write, at           9407205000
 test master 2 - Starting Memory Write, at           9408285000
 test master 2 - Starting Memory Write, at           9409365000
 test master 2 - Starting Memory Write, at           9411435000
 test master 2 - Starting Memory Write, at           9412545000
 test master 2 - Starting Memory Write, at           9413625000
 test master 2 - Starting Memory Write, at           9414705000
 test master 2 - Starting Memory Write, at           9416775000
 test master 2 - Starting Memory Write, at           9418725000
 test master 2 - Starting Memory Write, at           9420645000
 test master 2 - Starting Memory Write, at           9422565000
 test master 2 - Starting Memory Write, at           9425475000
 test master 2 - Starting Memory Write, at           9427635000
 test master 2 - Starting Memory Write, at           9429795000
 test master 2 - Starting Memory Write, at           9431955000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           9436245000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9436275000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9438135000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           9438465000
 test master 2 - Starting Memory Read, at           9438675000
 test master 2 - Starting Memory Read, at           9438885000
 test master 2 - Starting Memory Read, at           9439125000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9440655000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           9441195000
 test master 2 - Starting Memory Read, at           9441405000
 test master 2 - Starting Memory Read, at           9441855000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9443175000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9443895000
 test master 2 - Starting Memory Read Line Multiple, at           9444105000
 test master 2 - Starting Memory Read Line Multiple, at           9444315000
 test master 2 - Starting Memory Read Line Multiple, at           9444525000
 test master 2 - Starting Memory Read Line Multiple, at           9444795000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9446715000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9459255000
 test master 2 - Starting Memory Read Line Multiple, at           9459465000
 test master 2 - Starting Memory Read Line Multiple, at           9459675000
 test master 2 - Starting Memory Read Line Multiple, at           9459885000
 test master 2 - Starting Memory Read Line Multiple, at           9460185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9461115000
 test master 2 - Starting Memory Read Line Multiple, at           9461325000
 test master 2 - Starting Memory Read Line Multiple, at           9461535000
 test master 2 - Starting Memory Read Line Multiple, at           9461745000
 test master 2 - Starting Memory Read Line Multiple, at           9462045000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9462975000
 test master 2 - Starting Memory Read Line Multiple, at           9463185000
 test master 2 - Starting Memory Read Line Multiple, at           9463395000
 test master 2 - Starting Memory Read Line Multiple, at           9463605000
 test master 2 - Starting Memory Read Line Multiple, at           9463905000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9464835000
 test master 2 - Starting Memory Read Line Multiple, at           9465045000
 test master 2 - Starting Memory Read Line Multiple, at           9465255000
 test master 2 - Starting Memory Read Line Multiple, at           9465465000
 test master 2 - Starting Memory Read Line Multiple, at           9465765000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9466695000
 test master 2 - Starting Memory Read Line Multiple, at           9466905000
 test master 2 - Starting Memory Read Line Multiple, at           9467115000
 test master 2 - Starting Memory Read Line Multiple, at           9467325000
 test master 2 - Starting Memory Read Line Multiple, at           9467625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9468555000
 test master 2 - Starting Memory Read Line Multiple, at           9468765000
 test master 2 - Starting Memory Read Line Multiple, at           9468975000
 test master 2 - Starting Memory Read Line Multiple, at           9469185000
 test master 2 - Starting Memory Read Line Multiple, at           9469485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9470415000
 test master 2 - Starting Memory Read Line Multiple, at           9470625000
 test master 2 - Starting Memory Read Line Multiple, at           9470835000
 test master 2 - Starting Memory Read Line Multiple, at           9471045000
 test master 2 - Starting Memory Read Line Multiple, at           9471345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9472275000
 test master 2 - Starting Memory Read Line Multiple, at           9472485000
 test master 2 - Starting Memory Read Line Multiple, at           9472695000
 test master 2 - Starting Memory Read Line Multiple, at           9472905000
 test master 2 - Starting Memory Read Line Multiple, at           9473205000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           9474135000
 test master 2 - Starting Memory Read Line, at           9474345000
 test master 2 - Starting Memory Read Line, at           9474555000
 test master 2 - Starting Memory Read Line, at           9474825000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           9475395000
 test master 2 - Starting Memory Read Line, at           9475605000
 test master 2 - Starting Memory Read Line, at           9476055000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9477165000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9478605000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9481245000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9483105000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           9487935000
 test master 2 - Starting Memory Write, at           9488265000
 test master 2 - Starting Memory Write, at           9488595000
 test master 2 - Starting Memory Write, at           9488925000
 test master 2 - Starting Memory Write, at           9489255000
 test master 1 - Starting Memory Read, at           9489705000
 test master 1 - Starting Memory Read, at           9490095000
 test master 1 - Starting Memory Read, at           9490635000
 test master 1 - Starting Memory Read, at           9491025000
 test master 1 - Starting Memory Read, at           9491565000
 test master 1 - Starting Memory Read, at           9491955000
 test master 2 - Starting Memory Write, at           9493155000
 test master 2 - Starting Memory Write, at           9493485000
 test master 2 - Starting Memory Write, at           9493815000
 test master 2 - Starting Memory Write, at           9494145000
 test master 2 - Starting Memory Write, at           9494475000
 test master 1 - Starting Memory Read, at           9494925000
 test master 1 - Starting Memory Read, at           9495315000
 test master 1 - Starting Memory Read, at           9495855000
 test master 1 - Starting Memory Read, at           9496245000
 test master 1 - Starting Memory Read, at           9496785000
 test master 1 - Starting Memory Read, at           9497175000
 test master 2 - Starting Memory Write, at           9498795000
 test master 2 - Starting Memory Write, at           9499905000
 test master 2 - Starting Memory Write, at           9500985000
 test master 2 - Starting Memory Write, at           9502065000
 test master 2 - Starting Memory Write, at           9504135000
 test master 2 - Starting Memory Write, at           9505245000
 test master 2 - Starting Memory Write, at           9506325000
 test master 2 - Starting Memory Write, at           9507405000
 test master 2 - Starting Memory Write, at           9509475000
 test master 2 - Starting Memory Write, at           9511425000
 test master 2 - Starting Memory Write, at           9513345000
 test master 2 - Starting Memory Write, at           9515265000
 test master 2 - Starting Memory Write, at           9518175000
 test master 2 - Starting Memory Write, at           9520335000
 test master 2 - Starting Memory Write, at           9522495000
 test master 2 - Starting Memory Write, at           9524655000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           9528945000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9528975000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9530835000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at           9531165000
 test master 2 - Starting Memory Read, at           9531375000
 test master 2 - Starting Memory Read, at           9531585000
 test master 2 - Starting Memory Read, at           9531825000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9533355000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at           9533895000
 test master 2 - Starting Memory Read, at           9534105000
 test master 2 - Starting Memory Read, at           9534555000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9535875000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9536595000
 test master 2 - Starting Memory Read Line Multiple, at           9536805000
 test master 2 - Starting Memory Read Line Multiple, at           9537015000
 test master 2 - Starting Memory Read Line Multiple, at           9537225000
 test master 2 - Starting Memory Read Line Multiple, at           9537495000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9539415000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9551955000
 test master 2 - Starting Memory Read Line Multiple, at           9552165000
 test master 2 - Starting Memory Read Line Multiple, at           9552375000
 test master 2 - Starting Memory Read Line Multiple, at           9552585000
 test master 2 - Starting Memory Read Line Multiple, at           9552885000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9553815000
 test master 2 - Starting Memory Read Line Multiple, at           9554025000
 test master 2 - Starting Memory Read Line Multiple, at           9554235000
 test master 2 - Starting Memory Read Line Multiple, at           9554445000
 test master 2 - Starting Memory Read Line Multiple, at           9554745000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9555675000
 test master 2 - Starting Memory Read Line Multiple, at           9555885000
 test master 2 - Starting Memory Read Line Multiple, at           9556095000
 test master 2 - Starting Memory Read Line Multiple, at           9556305000
 test master 2 - Starting Memory Read Line Multiple, at           9556605000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9557535000
 test master 2 - Starting Memory Read Line Multiple, at           9557745000
 test master 2 - Starting Memory Read Line Multiple, at           9557955000
 test master 2 - Starting Memory Read Line Multiple, at           9558165000
 test master 2 - Starting Memory Read Line Multiple, at           9558465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9559395000
 test master 2 - Starting Memory Read Line Multiple, at           9559605000
 test master 2 - Starting Memory Read Line Multiple, at           9559815000
 test master 2 - Starting Memory Read Line Multiple, at           9560025000
 test master 2 - Starting Memory Read Line Multiple, at           9560325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9561255000
 test master 2 - Starting Memory Read Line Multiple, at           9561465000
 test master 2 - Starting Memory Read Line Multiple, at           9561675000
 test master 2 - Starting Memory Read Line Multiple, at           9561885000
 test master 2 - Starting Memory Read Line Multiple, at           9562185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9563115000
 test master 2 - Starting Memory Read Line Multiple, at           9563325000
 test master 2 - Starting Memory Read Line Multiple, at           9563535000
 test master 2 - Starting Memory Read Line Multiple, at           9563745000
 test master 2 - Starting Memory Read Line Multiple, at           9564045000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at           9564975000
 test master 2 - Starting Memory Read Line Multiple, at           9565185000
 test master 2 - Starting Memory Read Line Multiple, at           9565395000
 test master 2 - Starting Memory Read Line Multiple, at           9565605000
 test master 2 - Starting Memory Read Line Multiple, at           9565905000
Read    4 words!
 test master 2 - Starting Memory Read Line, at           9566835000
 test master 2 - Starting Memory Read Line, at           9567045000
 test master 2 - Starting Memory Read Line, at           9567255000
 test master 2 - Starting Memory Read Line, at           9567525000
Read    2 words!
 test master 2 - Starting Memory Read Line, at           9568095000
 test master 2 - Starting Memory Read Line, at           9568305000
 test master 2 - Starting Memory Read Line, at           9568755000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9569865000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9571305000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9573945000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at           9575805000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at           9580635000
 test master 2 - Starting Memory Write, at           9580965000
 test master 2 - Starting Memory Write, at           9581295000
 test master 2 - Starting Memory Write, at           9581625000
 test master 2 - Starting Memory Write, at           9581955000
 test master 1 - Starting Memory Read, at           9582405000
 test master 1 - Starting Memory Read, at           9582795000
 test master 1 - Starting Memory Read, at           9583335000
 test master 1 - Starting Memory Read, at           9583725000
 test master 1 - Starting Memory Read, at           9584265000
 test master 1 - Starting Memory Read, at           9584655000
 test master 2 - Starting Memory Write, at           9585855000
 test master 2 - Starting Memory Write, at           9586185000
 test master 2 - Starting Memory Write, at           9586515000
 test master 2 - Starting Memory Write, at           9586845000
 test master 2 - Starting Memory Write, at           9587175000
 test master 1 - Starting Memory Read, at           9587625000
 test master 1 - Starting Memory Read, at           9588015000
 test master 1 - Starting Memory Read, at           9588555000
 test master 1 - Starting Memory Read, at           9588945000
 test master 1 - Starting Memory Read, at           9589485000
 test master 1 - Starting Memory Read, at           9589875000
 test master 2 - Starting Memory Write, at           9591495000
 test master 2 - Starting Memory Write, at           9592605000
 test master 2 - Starting Memory Write, at           9593685000
 test master 2 - Starting Memory Write, at           9594765000
 test master 2 - Starting Memory Write, at           9596835000
 test master 2 - Starting Memory Write, at           9597945000
 test master 2 - Starting Memory Write, at           9599025000
 test master 2 - Starting Memory Write, at           9600105000
 test master 2 - Starting Memory Write, at           9602175000
 test master 2 - Starting Memory Write, at           9604125000
 test master 2 - Starting Memory Write, at           9606045000
 test master 2 - Starting Memory Write, at           9607965000
 test master 2 - Starting Memory Write, at           9610875000
 test master 2 - Starting Memory Write, at           9613035000
 test master 2 - Starting Memory Write, at           9615195000
 test master 2 - Starting Memory Write, at           9617355000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at           9621645000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9621675000
 test master 1 - Starting Memory Read, at           9623535000
 test master 1 - Starting Memory Read, at           9623955000
 test master 1 - Starting Memory Read, at           9625095000
 test master 1 - Starting Memory Read, at           9625515000
 test master 1 - Starting Memory Read Line, at           9626655000
 test master 1 - Starting Memory Read Line, at           9627075000
 test master 1 - Starting Memory Read Line, at           9628215000
 test master 1 - Starting Memory Read Line, at           9628725000
 test master 1 - Starting Memory Read Line, at           9629895000
 test master 1 - Starting Memory Read Line, at           9630555000
 test master 1 - Starting Memory Read Line, at           9631995000
 test master 1 - Starting Memory Read Line, at           9632655000
 test master 1 - Starting Memory Read Line Multiple, at           9634095000
 test master 1 - Starting Memory Read Line Multiple, at           9634995000
 test master 1 - Starting Memory Read Line Multiple, at           9636795000
 test master 1 - Starting Memory Read Line Multiple, at           9637695000
 test master 1 - Starting Memory Read Line, at           9639495000
 test master 1 - Starting Memory Read Line, at           9640155000
 test master 1 - Starting Memory Read, at           9642435000
 test master 1 - Starting Memory Read, at           9642855000
 test target 1 - Starting Config Write, at           9645765000
 test master 1 - Starting Memory Write, at           9646335000
 test master 1 - Starting Memory Write, at           9653805000
 test master 1 - Starting Memory Write, at           9658875000
 test master 1 - Starting Memory Write, at           9665865000
 test master 1 - Starting Memory Write, at           9670815000
 test master 1 - Starting Memory Read Line, at           9678285000
 test master 1 - Starting Memory Write, at           9683745000
 test master 1 - Starting Memory Read Line, at           9691215000
 test target 1 - Starting Config Write, at           9698025000
 test master 1 - Starting Memory Write, at           9698595000
 test master 1 - Starting Memory Write, at           9698745000
 test master 1 - Starting Memory Write, at           9699075000
 test master 1 - Starting Memory Read, at           9699225000
 test master 1 - Starting Memory Write, at           9699645000
 test master 1 - Starting Memory Read, at           9699795000
 test master 1 - Starting Memory Write, at           9701235000
 test master 1 - Starting Memory Write, at           9713775000
 test master 2 - Starting Memory Read Line, at           9726435000
 test master 2 - Starting Memory Read Line, at           9727065000
 test master 2 - Starting Memory Read Line, at           9727665000
 test master 2 - Starting Memory Read Line, at           9728295000
 test master 1 - Starting Memory Write, at           9728985000
 test master 1 - Starting Memory Write, at           9729315000
 test master 1 - Starting Memory Write, at           9729675000
 test master 2 - Starting Memory Read Line, at           9730155000
 test master 2 - Starting Memory Read Line, at           9730575000
 test master 2 - Starting Memory Read Line, at           9730905000
 test master 2 - Starting Memory Read Line, at           9731325000
 test master 2 - Starting Memory Read Line Multiple, at           9731685000
 test master 2 - Starting Memory Read Line Multiple, at           9732105000
 test master 1 - Starting Memory Write, at           9733845000
 test master 1 - Starting Memory Write, at           9734175000
 test master 2 - Starting Memory Read, at           9734655000
 test master 2 - Starting Memory Read, at           9735075000
 test master 2 - Starting Memory Read, at           9735405000
 test master 2 - Starting Memory Read, at           9735825000
 test master 1 - Starting Memory Write, at           9737355000
 test master 1 - Starting Memory Read, at           9737565000
 test master 1 - Starting Memory Write, at           9737775000
 test master 1 - Starting Memory Read, at           9737985000
 test master 1 - Starting Memory Write, at           9738195000
 test master 1 - Starting Memory Read, at           9738405000
 test master 1 - Starting Memory Read, at           9738615000
 test master 1 - Starting Memory Write, at           9738825000
 test master 1 - Starting Memory Write, at           9739035000
 test master 1 - Starting Memory Read, at           9739245000
 test master 1 - Starting Memory Write, at           9739455000
 test master 1 - Starting Memory Write, at           9739665000
 test master 1 - Starting Memory Write, at           9739875000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at           9743775000
 test target 1 - Starting Memory Write, at           9744075000
 test master 1 - Starting Memory Write, at           9744345000
 test target 1 - Starting Memory Write, at           9744555000
 test target 1 - Starting Memory Write, at           9744855000
 test target 1 - Starting Memory Write, at           9745155000
 test master 1 - Starting Memory Write, at           9745545000
 test target 1 - Starting Memory Write, at           9746145000
 test target 1 - Starting Memory Write, at           9746895000
 test target 1 - Starting Memory Write, at           9747225000
 test master 1 - Starting Memory Write, at           9747525000
 test target 1 - Starting Memory Write, at           9747975000
 test target 1 - Starting Memory Write, at           9748305000
 test target 1 - Starting Memory Write, at           9748635000
 test master 1 - Starting Memory Write, at           9749265000
 test target 1 - Starting Memory Write, at           9750255000
 test target 1 - Starting Memory Write, at           9751395000
 test target 1 - Starting Memory Write, at           9751695000
 test master 1 - Starting Memory Read, at           9751965000
 test target 1 - Starting Memory Write, at           9752175000
 test master 1 - Starting Memory Read, at           9752445000
 test target 1 - Starting Memory Write, at           9752655000
 test master 1 - Starting Memory Read, at           9752925000
 test target 1 - Starting Memory Write, at           9753135000
 test master 1 - Starting Memory Read, at           9753405000
 test target 1 - Starting Memory Write, at           9753615000
 test master 1 - Starting Memory Read, at           9753885000
 test target 1 - Starting Memory Write, at           9754095000
 test master 1 - Starting Memory Write, at           9754365000
 test target 1 - Starting Memory Write, at           9754575000
 test target 1 - Starting Memory Write, at           9754875000
 test target 1 - Starting Memory Write, at           9755175000
 test target 1 - Starting Memory Read, at           9755535000
 test master 1 - Starting Memory Write, at           9755925000
 test master 1 - Starting Memory Read, at           9756195000
 test target 1 - Starting Memory Write, at           9756735000
 test master 1 - Starting Memory Write, at           9757215000
 test target 1 - Starting Memory Read, at           9757665000
 test target 1 - Starting Memory Write, at           9758535000
 test master 1 - Starting Memory Read, at           9758925000
 test master 1 - Starting Memory Write, at           9759345000
 test master 1 - Starting Memory Write, at           9759735000
 test master 1 - Starting Memory Read, at           9760065000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           9762495000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           9763545000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at           9787965000
 test target 1 - Starting Config Write, at           9788865000
 test target 1 - Starting Config Write, at           9789765000
 test target 2 - Starting Config Write, at           9790665000
 test target 2 - Starting Config Write, at           9791565000
 test target 2 - Starting Config Write, at           9792465000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at           9794355000
 test target 1 - Starting Memory Read, at           9794625000
 test target 1 - Starting Memory Write, at           9795315000
 test target 1 - Starting Memory Read, at           9795585000
 test target 1 - Starting Memory Write, at           9796695000
 test target 1 - Starting Memory Read, at           9797775000
 test target 1 - Starting Memory Read, at           9798345000
 test target 1 - Starting Memory Read, at           9799035000
 test target 1 - Starting Memory Read, at           9799725000
 test target 1 - Starting Memory Read, at           9800595000
 test target 1 - Starting Memory Read, at           9801705000
 test target 1 - Starting Memory Read, at           9802545000
 test target 1 - Starting Memory Read, at           9803625000
 test target 1 - Starting Memory Read, at           9804465000
 test target 1 - Starting Memory Read, at           9806565000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at           9812685000
 test target 1 - Starting Memory Read, at           9812955000
 test target 1 - Starting Memory Write, at           9813645000
 test target 1 - Starting Memory Read, at           9813915000
 test target 1 - Starting Memory Write, at           9815025000
 test target 1 - Starting Memory Read, at           9816105000
 test target 1 - Starting Memory Read, at           9816675000
 test target 1 - Starting Memory Read, at           9817365000
 test target 1 - Starting Memory Read, at           9818025000
 test target 1 - Starting Memory Read, at           9818925000
 test target 1 - Starting Memory Read, at           9820005000
 test target 1 - Starting Memory Read, at           9820845000
 test target 1 - Starting Memory Read, at           9821925000
 test target 1 - Starting Memory Read, at           9822765000
 test target 1 - Starting Memory Read, at           9824865000
 test target 1 - Starting Memory Write, at           9830985000
 test target 1 - Starting Memory Read, at           9831255000
 test target 1 - Starting Memory Write, at           9831945000
 test target 1 - Starting Memory Read, at           9832215000
 test target 1 - Starting Memory Write, at           9833325000
 test target 1 - Starting Memory Read, at           9834405000
 test target 1 - Starting Memory Read, at           9834975000
 test target 1 - Starting Memory Read, at           9835665000
 test target 1 - Starting Memory Read, at           9836325000
 test target 1 - Starting Memory Read, at           9837225000
 test target 1 - Starting Memory Read, at           9838305000
 test target 1 - Starting Memory Read, at           9839145000
 test target 1 - Starting Memory Read, at           9840225000
 test target 1 - Starting Memory Read, at           9841065000
 test target 1 - Starting Memory Read, at           9843165000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at           9854565000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at           9860775000
 test target 1 - Starting Memory Write, at           9861645000
 test target 1 - Starting Memory Read, at           9862095000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at           9863355000
 test target 1 - Starting Config Write, at           9865245000
 test target 1 - Starting Memory Read, at           9865905000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at           9867345000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at           9869355000
 test target 1 - Starting Memory Write, at           9870525000
 test target 1 - Starting Memory Write, at           9870825000
 test target 1 - Starting Memory Read, at           9871095000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at           9873375000
 test target 1 - Starting Memory Write, at           9876345000
 test target 1 - Starting Memory Write, at           9876735000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at           9880635000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at           9882555000
 test target 1 - Starting Memory Read, at           9883905000
 test target 1 - Starting Memory Read, at           9884955000
 test target 1 - Starting Memory Read, at           9886665000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at           9892455000
 test target 2 - Starting Config Write, at           9893355000
 test target 1 - Starting Memory Write, at           9894045000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           9894225000
 test target 1 - Starting Memory Write, at           9895215000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at           9895395000
 test target 1 - Starting Memory Write, at           9896385000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at           9897765000
 test target 1 - Starting Memory Read, at           9899925000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at           9900105000
 test target 1 - Starting Memory Read, at           9902145000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at           9903825000
 test master 2 - Starting Memory Write, at           9903825000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           9903885000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9904725000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9904755000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9905055000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9905085000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9905955000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9905985000
 test target 1 - Starting Memory Write, at           9907755000
 test master 2 - Starting Memory Write, at           9907755000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9909465000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9909495000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9911145000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9911175000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9912825000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9912855000
 test target 1 - Starting Memory Write, at           9914865000
 test master 2 - Starting Memory Write, at           9914865000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at           9914925000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9916545000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9916575000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9916875000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9916905000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9917775000
*** monitor - CBE Bus Changed when TRDY Desserted, at           9917805000
 test target 1 - Starting Memory Write, at           9918975000
 test master 2 - Starting Memory Write, at           9918975000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at           9921855000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at           9923475000
 test master 1 - Starting Memory Read, at           9923865000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at           9924045000
 test target 1 - Starting Config Write, at           9926505000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           9928815000
 test target 1 - Starting Memory Write, at           9929025000
 test target 1 - Starting Memory Write, at           9929235000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           9929745000
 test target 1 - Starting Memory Write, at           9929985000
 test target 1 - Starting Memory Write, at           9930225000
 test target 1 - Starting Memory Write, at           9930735000
 test target 1 - Starting Memory Write, at           9931035000
 test target 1 - Starting Memory Write, at           9931545000
 test target 1 - Starting Memory Write, at           9932235000
 test target 1 - Starting Memory Write, at           9932475000
 test target 1 - Starting Memory Write, at           9933165000
 test target 1 - Starting Memory Write, at           9933495000
 test target 1 - Starting Memory Write, at           9934095000
 test target 1 - Starting Memory Write, at           9939615000
 test target 1 - Starting Memory Write, at           9939855000
 test target 1 - Starting Memory Write, at           9940095000
 test target 1 - Starting Memory Write, at           9940425000
 test target 1 - Starting Memory Write, at           9940755000
 test target 1 - Starting Memory Read, at           9946155000
 test target 1 - Starting Memory Read, at           9947265000
 test target 1 - Starting Memory Read, at           9948465000
 test target 1 - Starting Memory Read, at           9949665000
 test target 1 - Starting Memory Read, at           9950865000
 test target 1 - Starting Memory Read, at           9952065000
 test target 1 - Starting Memory Read, at           9953265000
 test target 1 - Starting Memory Read, at           9954465000
 test target 1 - Starting Memory Read, at           9955665000
 test target 1 - Starting Memory Read, at           9956865000
 test target 1 - Starting Memory Read, at           9958065000
 test target 1 - Starting Memory Read, at           9959265000
 test target 1 - Starting Memory Read, at           9960465000
 test target 1 - Starting Memory Read, at           9961665000
 test target 1 - Starting Memory Read, at           9962865000
 test target 1 - Starting Memory Read, at           9964065000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at           9965145000
 test target 1 - Starting Memory Read, at           9965355000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at           9967275000
 test target 1 - Starting Memory Read, at           9968895000
 test target 1 - Starting Memory Read, at           9969615000
 test target 1 - Starting Memory Read, at           9970305000
 test target 1 - Starting Memory Read, at           9971055000
 test target 1 - Starting Memory Read, at           9971745000
 test target 1 - Starting Memory Read, at           9973005000
 test target 1 - Starting Memory Read, at           9974085000
 test target 1 - Starting Memory Read, at           9974925000
 test target 1 - Starting Memory Read, at           9977865000
 test target 1 - Starting Memory Read, at           9980235000
 test target 1 - Starting Memory Read, at           9981015000
 test target 1 - Starting Memory Read, at           9981795000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at           9983025000
 test master 1 - Starting Memory Write, at           9983295000
 test target 1 - Starting Memory Write, at           9983295000
 test target 1 - Starting Memory Write, at           9983505000
 test target 1 - Starting Memory Read, at           9984045000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at           9986325000
 test master 1 - Starting Memory Write, at           9986595000
 test target 1 - Starting Memory Write, at           9986595000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at           9991575000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at           9992625000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          10017045000
 test target 1 - Starting Config Write, at          10017945000
 test target 1 - Starting Config Write, at          10018845000
 test target 2 - Starting Config Write, at          10019745000
 test target 2 - Starting Config Write, at          10020645000
 test target 2 - Starting Config Write, at          10021545000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          10023435000
 test target 1 - Starting Memory Read, at          10023735000
 test target 1 - Starting Memory Write, at          10024395000
 test target 1 - Starting Memory Read, at          10024695000
 test target 1 - Starting Memory Write, at          10025775000
 test target 1 - Starting Memory Read, at          10026885000
 test target 1 - Starting Memory Read, at          10027605000
 test target 1 - Starting Memory Read, at          10028265000
 test target 1 - Starting Memory Read, at          10028955000
 test target 1 - Starting Memory Read, at          10029825000
 test target 1 - Starting Memory Read, at          10031055000
 test target 1 - Starting Memory Read, at          10031895000
 test target 1 - Starting Memory Read, at          10033125000
 test target 1 - Starting Memory Read, at          10033965000
 test target 1 - Starting Memory Read, at          10036215000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          10042485000
 test target 1 - Starting Memory Read, at          10042785000
 test target 1 - Starting Memory Write, at          10043445000
 test target 1 - Starting Memory Read, at          10043745000
 test target 1 - Starting Memory Write, at          10044825000
 test target 1 - Starting Memory Read, at          10045935000
 test target 1 - Starting Memory Read, at          10046655000
 test target 1 - Starting Memory Read, at          10047345000
 test target 1 - Starting Memory Read, at          10048005000
 test target 1 - Starting Memory Read, at          10048905000
 test target 1 - Starting Memory Read, at          10050135000
 test target 1 - Starting Memory Read, at          10050975000
 test target 1 - Starting Memory Read, at          10052205000
 test target 1 - Starting Memory Read, at          10053045000
 test target 1 - Starting Memory Read, at          10055295000
 test target 1 - Starting Memory Write, at          10061565000
 test target 1 - Starting Memory Read, at          10061865000
 test target 1 - Starting Memory Write, at          10062525000
 test target 1 - Starting Memory Read, at          10062825000
 test target 1 - Starting Memory Write, at          10063905000
 test target 1 - Starting Memory Read, at          10065015000
 test target 1 - Starting Memory Read, at          10065735000
 test target 1 - Starting Memory Read, at          10066425000
 test target 1 - Starting Memory Read, at          10067085000
 test target 1 - Starting Memory Read, at          10067985000
 test target 1 - Starting Memory Read, at          10069215000
 test target 1 - Starting Memory Read, at          10070055000
 test target 1 - Starting Memory Read, at          10071285000
 test target 1 - Starting Memory Read, at          10072125000
 test target 1 - Starting Memory Read, at          10074375000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          10085925000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          10092135000
 test target 1 - Starting Memory Write, at          10093005000
 test target 1 - Starting Memory Read, at          10093485000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          10094715000
 test target 1 - Starting Config Write, at          10096605000
 test target 1 - Starting Memory Read, at          10097265000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          10098705000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          10100715000
 test target 1 - Starting Memory Write, at          10101885000
 test target 1 - Starting Memory Write, at          10102215000
 test target 1 - Starting Memory Read, at          10102515000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          10104915000
 test target 1 - Starting Memory Write, at          10107915000
 test target 1 - Starting Memory Write, at          10108335000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          10112235000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          10114155000
 test target 1 - Starting Memory Read, at          10115505000
 test target 1 - Starting Memory Read, at          10116705000
 test target 1 - Starting Memory Read, at          10118385000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          10124325000
 test target 2 - Starting Config Write, at          10125225000
 test target 1 - Starting Memory Write, at          10125915000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          10126125000
 test target 1 - Starting Memory Write, at          10127115000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          10127325000
 test target 1 - Starting Memory Write, at          10128315000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          10129725000
 test target 1 - Starting Memory Read, at          10131885000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          10132095000
 test target 1 - Starting Memory Read, at          10134105000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          10135785000
 test master 2 - Starting Memory Write, at          10135785000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          10135845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10136715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10136745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10137045000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10137075000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10137945000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10137975000
 test target 1 - Starting Memory Write, at          10139745000
 test master 2 - Starting Memory Write, at          10139745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10141485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10141515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10143165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10143195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10144845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10144875000
 test target 1 - Starting Memory Write, at          10146885000
 test master 2 - Starting Memory Write, at          10146885000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          10146945000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10148595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10148625000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10148925000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10148955000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10149825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10149855000
 test target 1 - Starting Memory Write, at          10151025000
 test master 2 - Starting Memory Write, at          10151025000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          10153935000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          10155555000
 test master 1 - Starting Memory Read, at          10155945000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          10156125000
 test target 1 - Starting Config Write, at          10158585000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          10161075000
 test target 1 - Starting Memory Write, at          10161315000
 test target 1 - Starting Memory Write, at          10161555000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          10162095000
 test target 1 - Starting Memory Write, at          10162365000
 test target 1 - Starting Memory Write, at          10162635000
 test target 1 - Starting Memory Write, at          10163175000
 test target 1 - Starting Memory Write, at          10163505000
 test target 1 - Starting Memory Write, at          10164045000
 test target 1 - Starting Memory Write, at          10164765000
 test target 1 - Starting Memory Write, at          10165035000
 test target 1 - Starting Memory Write, at          10165755000
 test target 1 - Starting Memory Write, at          10166115000
 test target 1 - Starting Memory Write, at          10166745000
 test target 1 - Starting Memory Write, at          10172295000
 test target 1 - Starting Memory Write, at          10172565000
 test target 1 - Starting Memory Write, at          10172835000
 test target 1 - Starting Memory Write, at          10173195000
 test target 1 - Starting Memory Write, at          10173555000
 test target 1 - Starting Memory Read, at          10178985000
 test target 1 - Starting Memory Read, at          10180095000
 test target 1 - Starting Memory Read, at          10181295000
 test target 1 - Starting Memory Read, at          10182495000
 test target 1 - Starting Memory Read, at          10183695000
 test target 1 - Starting Memory Read, at          10184895000
 test target 1 - Starting Memory Read, at          10186095000
 test target 1 - Starting Memory Read, at          10187295000
 test target 1 - Starting Memory Read, at          10188495000
 test target 1 - Starting Memory Read, at          10189695000
 test target 1 - Starting Memory Read, at          10190895000
 test target 1 - Starting Memory Read, at          10192095000
 test target 1 - Starting Memory Read, at          10193295000
 test target 1 - Starting Memory Read, at          10194495000
 test target 1 - Starting Memory Read, at          10195695000
 test target 1 - Starting Memory Read, at          10196895000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          10197975000
 test target 1 - Starting Memory Read, at          10198215000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          10200105000
 test target 1 - Starting Memory Read, at          10201755000
 test target 1 - Starting Memory Read, at          10202415000
 test target 1 - Starting Memory Read, at          10203135000
 test target 1 - Starting Memory Read, at          10204005000
 test target 1 - Starting Memory Read, at          10204845000
 test target 1 - Starting Memory Read, at          10206105000
 test target 1 - Starting Memory Read, at          10207335000
 test target 1 - Starting Memory Read, at          10208175000
 test target 1 - Starting Memory Read, at          10211265000
 test target 1 - Starting Memory Read, at          10213605000
 test target 1 - Starting Memory Read, at          10214505000
 test target 1 - Starting Memory Read, at          10215405000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          10216755000
 test master 1 - Starting Memory Write, at          10217055000
 test target 1 - Starting Memory Write, at          10217055000
 test target 1 - Starting Memory Write, at          10217295000
 test target 1 - Starting Memory Read, at          10217865000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          10220235000
 test master 1 - Starting Memory Write, at          10220535000
 test target 1 - Starting Memory Write, at          10220535000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          10225455000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          10226625000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          10251165000
 test target 1 - Starting Config Write, at          10252065000
 test target 1 - Starting Config Write, at          10252965000
 test target 2 - Starting Config Write, at          10253865000
 test target 2 - Starting Config Write, at          10254765000
 test target 2 - Starting Config Write, at          10255665000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          10257555000
 test target 1 - Starting Memory Read, at          10257885000
 test target 1 - Starting Memory Write, at          10258665000
 test target 1 - Starting Memory Read, at          10258995000
 test target 1 - Starting Memory Write, at          10260195000
 test target 1 - Starting Memory Read, at          10261335000
 test target 1 - Starting Memory Read, at          10262055000
 test target 1 - Starting Memory Read, at          10262745000
 test target 1 - Starting Memory Read, at          10263405000
 test target 1 - Starting Memory Read, at          10264305000
 test target 1 - Starting Memory Read, at          10265535000
 test target 1 - Starting Memory Read, at          10266525000
 test target 1 - Starting Memory Read, at          10267755000
 test target 1 - Starting Memory Read, at          10268745000
 test target 1 - Starting Memory Read, at          10270995000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          10277265000
 test target 1 - Starting Memory Read, at          10277595000
 test target 1 - Starting Memory Write, at          10278375000
 test target 1 - Starting Memory Read, at          10278705000
 test target 1 - Starting Memory Write, at          10279935000
 test target 1 - Starting Memory Read, at          10281075000
 test target 1 - Starting Memory Read, at          10281795000
 test target 1 - Starting Memory Read, at          10282485000
 test target 1 - Starting Memory Read, at          10283145000
 test target 1 - Starting Memory Read, at          10284045000
 test target 1 - Starting Memory Read, at          10285275000
 test target 1 - Starting Memory Read, at          10286265000
 test target 1 - Starting Memory Read, at          10287495000
 test target 1 - Starting Memory Read, at          10288485000
 test target 1 - Starting Memory Read, at          10290735000
 test target 1 - Starting Memory Write, at          10297005000
 test target 1 - Starting Memory Read, at          10297335000
 test target 1 - Starting Memory Write, at          10298115000
 test target 1 - Starting Memory Read, at          10298445000
 test target 1 - Starting Memory Write, at          10299675000
 test target 1 - Starting Memory Read, at          10300815000
 test target 1 - Starting Memory Read, at          10301535000
 test target 1 - Starting Memory Read, at          10302225000
 test target 1 - Starting Memory Read, at          10302885000
 test target 1 - Starting Memory Read, at          10303785000
 test target 1 - Starting Memory Read, at          10305015000
 test target 1 - Starting Memory Read, at          10306005000
 test target 1 - Starting Memory Read, at          10307235000
 test target 1 - Starting Memory Read, at          10308225000
 test target 1 - Starting Memory Read, at          10310475000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          10322025000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          10328235000
 test target 1 - Starting Memory Write, at          10329105000
 test target 1 - Starting Memory Read, at          10329615000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          10330965000
 test target 1 - Starting Config Write, at          10332825000
 test target 1 - Starting Memory Read, at          10333485000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          10334925000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          10336935000
 test target 1 - Starting Memory Write, at          10338105000
 test target 1 - Starting Memory Write, at          10338465000
 test target 1 - Starting Memory Read, at          10338795000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          10341135000
 test target 1 - Starting Memory Write, at          10344165000
 test target 1 - Starting Memory Write, at          10344615000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          10348575000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          10350495000
 test target 1 - Starting Memory Read, at          10351845000
 test target 1 - Starting Memory Read, at          10353045000
 test target 1 - Starting Memory Read, at          10354725000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          10360665000
 test target 2 - Starting Config Write, at          10361565000
 test target 1 - Starting Memory Write, at          10362255000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          10362495000
 test target 1 - Starting Memory Write, at          10363485000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          10363725000
 test target 1 - Starting Memory Write, at          10364715000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          10366155000
 test target 1 - Starting Memory Read, at          10368345000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          10368585000
 test target 1 - Starting Memory Read, at          10370565000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          10372245000
 test master 2 - Starting Memory Write, at          10372245000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          10372305000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10373205000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10373235000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10373535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10373565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10374435000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10374465000
 test target 1 - Starting Memory Write, at          10376235000
 test master 2 - Starting Memory Write, at          10376235000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10378005000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10378035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10379685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10379715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10381365000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10381395000
 test target 1 - Starting Memory Write, at          10383405000
 test master 2 - Starting Memory Write, at          10383405000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          10383465000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10385145000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10385175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10385475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10385505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10386375000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10386405000
 test target 1 - Starting Memory Write, at          10387575000
 test master 2 - Starting Memory Write, at          10387575000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          10390515000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          10392135000
 test master 1 - Starting Memory Read, at          10392525000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          10392705000
 test target 1 - Starting Config Write, at          10395165000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          10397655000
 test target 1 - Starting Memory Write, at          10397925000
 test target 1 - Starting Memory Write, at          10398195000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          10398765000
 test target 1 - Starting Memory Write, at          10399065000
 test target 1 - Starting Memory Write, at          10399365000
 test target 1 - Starting Memory Write, at          10399935000
 test target 1 - Starting Memory Write, at          10400295000
 test target 1 - Starting Memory Write, at          10400865000
 test target 1 - Starting Memory Write, at          10401615000
 test target 1 - Starting Memory Write, at          10401915000
 test target 1 - Starting Memory Write, at          10402665000
 test target 1 - Starting Memory Write, at          10403055000
 test target 1 - Starting Memory Write, at          10403715000
 test target 1 - Starting Memory Write, at          10409295000
 test target 1 - Starting Memory Write, at          10409595000
 test target 1 - Starting Memory Write, at          10409895000
 test target 1 - Starting Memory Write, at          10410285000
 test target 1 - Starting Memory Write, at          10410675000
 test target 1 - Starting Memory Read, at          10416135000
 test target 1 - Starting Memory Read, at          10417365000
 test target 1 - Starting Memory Read, at          10418565000
 test target 1 - Starting Memory Read, at          10419765000
 test target 1 - Starting Memory Read, at          10420965000
 test target 1 - Starting Memory Read, at          10422165000
 test target 1 - Starting Memory Read, at          10423365000
 test target 1 - Starting Memory Read, at          10424565000
 test target 1 - Starting Memory Read, at          10425765000
 test target 1 - Starting Memory Read, at          10426965000
 test target 1 - Starting Memory Read, at          10428165000
 test target 1 - Starting Memory Read, at          10429365000
 test target 1 - Starting Memory Read, at          10430565000
 test target 1 - Starting Memory Read, at          10431765000
 test target 1 - Starting Memory Read, at          10432965000
 test target 1 - Starting Memory Read, at          10434165000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          10435245000
 test target 1 - Starting Memory Read, at          10435515000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          10437555000
 test target 1 - Starting Memory Read, at          10439235000
 test target 1 - Starting Memory Read, at          10440015000
 test target 1 - Starting Memory Read, at          10440735000
 test target 1 - Starting Memory Read, at          10441605000
 test target 1 - Starting Memory Read, at          10442445000
 test target 1 - Starting Memory Read, at          10443705000
 test target 1 - Starting Memory Read, at          10444935000
 test target 1 - Starting Memory Read, at          10445925000
 test target 1 - Starting Memory Read, at          10448985000
 test target 1 - Starting Memory Read, at          10451355000
 test target 1 - Starting Memory Read, at          10452285000
 test target 1 - Starting Memory Read, at          10453185000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          10454535000
 test master 1 - Starting Memory Write, at          10454865000
 test target 1 - Starting Memory Write, at          10454865000
 test target 1 - Starting Memory Write, at          10455135000
 test target 1 - Starting Memory Read, at          10455735000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          10458195000
 test master 1 - Starting Memory Write, at          10458525000
 test target 1 - Starting Memory Write, at          10458525000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          10463415000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          10464585000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          10489125000
 test target 1 - Starting Config Write, at          10490205000
 test target 1 - Starting Config Write, at          10491285000
 test target 2 - Starting Config Write, at          10492365000
 test target 2 - Starting Config Write, at          10493445000
 test target 2 - Starting Config Write, at          10494525000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          10496595000
 test target 1 - Starting Memory Read, at          10496955000
 test target 1 - Starting Memory Write, at          10497705000
 test target 1 - Starting Memory Read, at          10498065000
 test target 1 - Starting Memory Write, at          10499235000
 test target 1 - Starting Memory Read, at          10500405000
 test target 1 - Starting Memory Read, at          10501125000
 test target 1 - Starting Memory Read, at          10501785000
 test target 1 - Starting Memory Read, at          10502475000
 test target 1 - Starting Memory Read, at          10503345000
 test target 1 - Starting Memory Read, at          10504575000
 test target 1 - Starting Memory Read, at          10505565000
 test target 1 - Starting Memory Read, at          10506795000
 test target 1 - Starting Memory Read, at          10507785000
 test target 1 - Starting Memory Read, at          10510035000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          10516305000
 test target 1 - Starting Memory Read, at          10516665000
 test target 1 - Starting Memory Write, at          10517415000
 test target 1 - Starting Memory Read, at          10517775000
 test target 1 - Starting Memory Write, at          10518975000
 test target 1 - Starting Memory Read, at          10520145000
 test target 1 - Starting Memory Read, at          10520865000
 test target 1 - Starting Memory Read, at          10521525000
 test target 1 - Starting Memory Read, at          10522215000
 test target 1 - Starting Memory Read, at          10523085000
 test target 1 - Starting Memory Read, at          10524315000
 test target 1 - Starting Memory Read, at          10525305000
 test target 1 - Starting Memory Read, at          10526535000
 test target 1 - Starting Memory Read, at          10527525000
 test target 1 - Starting Memory Read, at          10529775000
 test target 1 - Starting Memory Write, at          10536045000
 test target 1 - Starting Memory Read, at          10536405000
 test target 1 - Starting Memory Write, at          10537155000
 test target 1 - Starting Memory Read, at          10537515000
 test target 1 - Starting Memory Write, at          10538715000
 test target 1 - Starting Memory Read, at          10539885000
 test target 1 - Starting Memory Read, at          10540605000
 test target 1 - Starting Memory Read, at          10541265000
 test target 1 - Starting Memory Read, at          10541955000
 test target 1 - Starting Memory Read, at          10542825000
 test target 1 - Starting Memory Read, at          10544055000
 test target 1 - Starting Memory Read, at          10545045000
 test target 1 - Starting Memory Read, at          10546275000
 test target 1 - Starting Memory Read, at          10547265000
 test target 1 - Starting Memory Read, at          10549515000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          10561065000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          10567455000
 test target 1 - Starting Memory Write, at          10568505000
 test target 1 - Starting Memory Read, at          10569045000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          10570365000
 test target 1 - Starting Config Write, at          10572405000
 test target 1 - Starting Memory Read, at          10573245000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          10574865000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          10577055000
 test target 1 - Starting Memory Write, at          10578405000
 test target 1 - Starting Memory Write, at          10578795000
 test target 1 - Starting Memory Read, at          10579155000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          10581585000
 test target 1 - Starting Memory Write, at          10584645000
 test target 1 - Starting Memory Write, at          10585125000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          10589115000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          10591185000
 test target 1 - Starting Memory Read, at          10592655000
 test target 1 - Starting Memory Read, at          10593855000
 test target 1 - Starting Memory Read, at          10595685000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          10601625000
 test target 2 - Starting Config Write, at          10602705000
 test target 1 - Starting Memory Write, at          10603575000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          10603845000
 test target 1 - Starting Memory Write, at          10604835000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          10605105000
 test target 1 - Starting Memory Write, at          10606095000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          10607565000
 test target 1 - Starting Memory Read, at          10609905000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          10610175000
 test target 1 - Starting Memory Read, at          10612305000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          10614165000
 test master 2 - Starting Memory Write, at          10614165000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          10614225000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10615155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10615185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10615485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10615515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10616385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10616415000
 test target 1 - Starting Memory Write, at          10618185000
 test master 2 - Starting Memory Write, at          10618185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10619985000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10620015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10621665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10621695000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10623345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10623375000
 test target 1 - Starting Memory Write, at          10625385000
 test master 2 - Starting Memory Write, at          10625385000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          10625445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10627155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10627185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10627485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10627515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10628385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10628415000
 test target 1 - Starting Memory Write, at          10629585000
 test master 2 - Starting Memory Write, at          10629585000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          10632555000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          10634175000
 test master 1 - Starting Memory Read, at          10634565000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          10634745000
 test target 1 - Starting Config Write, at          10637205000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          10639695000
 test target 1 - Starting Memory Write, at          10639995000
 test target 1 - Starting Memory Write, at          10640295000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          10640895000
 test target 1 - Starting Memory Write, at          10641225000
 test target 1 - Starting Memory Write, at          10641555000
 test target 1 - Starting Memory Write, at          10642155000
 test target 1 - Starting Memory Write, at          10642545000
 test target 1 - Starting Memory Write, at          10643145000
 test target 1 - Starting Memory Write, at          10643925000
 test target 1 - Starting Memory Write, at          10644255000
 test target 1 - Starting Memory Write, at          10645035000
 test target 1 - Starting Memory Write, at          10645455000
 test target 1 - Starting Memory Write, at          10646145000
 test target 1 - Starting Memory Write, at          10651755000
 test target 1 - Starting Memory Write, at          10652085000
 test target 1 - Starting Memory Write, at          10652415000
 test target 1 - Starting Memory Write, at          10652835000
 test target 1 - Starting Memory Write, at          10653255000
 test target 1 - Starting Memory Read, at          10658745000
 test target 1 - Starting Memory Read, at          10659975000
 test target 1 - Starting Memory Read, at          10661175000
 test target 1 - Starting Memory Read, at          10662375000
 test target 1 - Starting Memory Read, at          10663575000
 test target 1 - Starting Memory Read, at          10664775000
 test target 1 - Starting Memory Read, at          10665975000
 test target 1 - Starting Memory Read, at          10667175000
 test target 1 - Starting Memory Read, at          10668375000
 test target 1 - Starting Memory Read, at          10669575000
 test target 1 - Starting Memory Read, at          10670775000
 test target 1 - Starting Memory Read, at          10671975000
 test target 1 - Starting Memory Read, at          10673175000
 test target 1 - Starting Memory Read, at          10674375000
 test target 1 - Starting Memory Read, at          10675575000
 test target 1 - Starting Memory Read, at          10676775000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          10677855000
 test target 1 - Starting Memory Read, at          10678155000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          10680135000
 test target 1 - Starting Memory Read, at          10681845000
 test target 1 - Starting Memory Read, at          10682625000
 test target 1 - Starting Memory Read, at          10683465000
 test target 1 - Starting Memory Read, at          10684305000
 test target 1 - Starting Memory Read, at          10685145000
 test target 1 - Starting Memory Read, at          10686405000
 test target 1 - Starting Memory Read, at          10687635000
 test target 1 - Starting Memory Read, at          10688625000
 test target 1 - Starting Memory Read, at          10691685000
 test target 1 - Starting Memory Read, at          10694055000
 test target 1 - Starting Memory Read, at          10694985000
 test target 1 - Starting Memory Read, at          10695885000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          10697235000
 test master 1 - Starting Memory Write, at          10697595000
 test target 1 - Starting Memory Write, at          10697595000
 test target 1 - Starting Memory Write, at          10697895000
 test target 1 - Starting Memory Read, at          10698525000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          10700925000
 test master 1 - Starting Memory Write, at          10701285000
 test target 1 - Starting Memory Write, at          10701285000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10706385000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          10706655000
 test master 2 - Starting Memory Read, at          10706865000
 test master 2 - Starting Memory Read, at          10707075000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10708635000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          10708995000
 test master 2 - Starting Memory Read, at          10709205000
 test master 2 - Starting Memory Read, at          10709415000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10710795000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10711275000
 test master 2 - Starting Memory Read Line Multiple, at          10711485000
 test master 2 - Starting Memory Read Line Multiple, at          10711755000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10713585000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10720575000
 test master 2 - Starting Memory Read Line Multiple, at          10720785000
 test master 2 - Starting Memory Read Line Multiple, at          10721085000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10721835000
 test master 2 - Starting Memory Read Line Multiple, at          10722045000
 test master 2 - Starting Memory Read Line Multiple, at          10722345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10723095000
 test master 2 - Starting Memory Read Line Multiple, at          10723305000
 test master 2 - Starting Memory Read Line Multiple, at          10723605000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10724355000
 test master 2 - Starting Memory Read Line Multiple, at          10724565000
 test master 2 - Starting Memory Read Line Multiple, at          10724865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10725615000
 test master 2 - Starting Memory Read Line Multiple, at          10725825000
 test master 2 - Starting Memory Read Line Multiple, at          10726125000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10726875000
 test master 2 - Starting Memory Read Line Multiple, at          10727085000
 test master 2 - Starting Memory Read Line Multiple, at          10727385000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10728135000
 test master 2 - Starting Memory Read Line Multiple, at          10728345000
 test master 2 - Starting Memory Read Line Multiple, at          10728645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10729395000
 test master 2 - Starting Memory Read Line Multiple, at          10729605000
 test master 2 - Starting Memory Read Line Multiple, at          10729905000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          10730655000
 test master 2 - Starting Memory Read Line, at          10730865000
 test master 2 - Starting Memory Read Line, at          10731105000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          10731585000
 test master 2 - Starting Memory Read Line, at          10731795000
 test master 2 - Starting Memory Read Line, at          10732005000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10733145000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10734645000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10737435000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10739145000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          10743675000
 test master 2 - Starting Memory Write, at          10743945000
 test master 2 - Starting Memory Write, at          10744215000
 test master 2 - Starting Memory Write, at          10744485000
 test master 2 - Starting Memory Write, at          10744755000
 test master 1 - Starting Memory Read, at          10745145000
 test master 1 - Starting Memory Read, at          10745475000
 test master 1 - Starting Memory Read, at          10746015000
 test master 1 - Starting Memory Read, at          10746345000
 test master 1 - Starting Memory Read, at          10746885000
 test master 1 - Starting Memory Read, at          10747215000
 test master 2 - Starting Memory Write, at          10748475000
 test master 2 - Starting Memory Write, at          10748745000
 test master 2 - Starting Memory Write, at          10749015000
 test master 2 - Starting Memory Write, at          10749285000
 test master 2 - Starting Memory Write, at          10749555000
 test master 1 - Starting Memory Read, at          10749945000
 test master 1 - Starting Memory Read, at          10750275000
 test master 1 - Starting Memory Read, at          10750815000
 test master 1 - Starting Memory Read, at          10751145000
 test master 1 - Starting Memory Read, at          10751685000
 test master 1 - Starting Memory Read, at          10752015000
 test master 2 - Starting Memory Write, at          10753755000
 test master 2 - Starting Memory Write, at          10754865000
 test master 2 - Starting Memory Write, at          10755945000
 test master 2 - Starting Memory Write, at          10757025000
 test master 2 - Starting Memory Write, at          10759185000
 test master 2 - Starting Memory Write, at          10760265000
 test master 2 - Starting Memory Write, at          10761345000
 test master 2 - Starting Memory Write, at          10762425000
 test master 2 - Starting Memory Write, at          10764585000
 test master 2 - Starting Memory Write, at          10766595000
 test master 2 - Starting Memory Write, at          10768635000
 test master 2 - Starting Memory Write, at          10770675000
 test master 2 - Starting Memory Write, at          10773795000
 test master 2 - Starting Memory Write, at          10776075000
 test master 2 - Starting Memory Write, at          10778355000
 test master 2 - Starting Memory Write, at          10780635000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          10785045000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10785075000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10787145000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          10787415000
 test master 2 - Starting Memory Read, at          10787625000
 test master 2 - Starting Memory Read, at          10787835000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10789395000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          10789755000
 test master 2 - Starting Memory Read, at          10789965000
 test master 2 - Starting Memory Read, at          10790175000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10791555000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10792035000
 test master 2 - Starting Memory Read Line Multiple, at          10792245000
 test master 2 - Starting Memory Read Line Multiple, at          10792515000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10794345000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10801335000
 test master 2 - Starting Memory Read Line Multiple, at          10801545000
 test master 2 - Starting Memory Read Line Multiple, at          10801845000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10802595000
 test master 2 - Starting Memory Read Line Multiple, at          10802805000
 test master 2 - Starting Memory Read Line Multiple, at          10803105000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10803855000
 test master 2 - Starting Memory Read Line Multiple, at          10804065000
 test master 2 - Starting Memory Read Line Multiple, at          10804365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10805115000
 test master 2 - Starting Memory Read Line Multiple, at          10805325000
 test master 2 - Starting Memory Read Line Multiple, at          10805625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10806375000
 test master 2 - Starting Memory Read Line Multiple, at          10806585000
 test master 2 - Starting Memory Read Line Multiple, at          10806885000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10807635000
 test master 2 - Starting Memory Read Line Multiple, at          10807845000
 test master 2 - Starting Memory Read Line Multiple, at          10808145000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10808895000
 test master 2 - Starting Memory Read Line Multiple, at          10809105000
 test master 2 - Starting Memory Read Line Multiple, at          10809405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10810155000
 test master 2 - Starting Memory Read Line Multiple, at          10810365000
 test master 2 - Starting Memory Read Line Multiple, at          10810665000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          10811415000
 test master 2 - Starting Memory Read Line, at          10811625000
 test master 2 - Starting Memory Read Line, at          10811865000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          10812345000
 test master 2 - Starting Memory Read Line, at          10812555000
 test master 2 - Starting Memory Read Line, at          10812765000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10813905000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10815405000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10818195000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10819905000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          10824435000
 test master 2 - Starting Memory Write, at          10824705000
 test master 2 - Starting Memory Write, at          10824975000
 test master 2 - Starting Memory Write, at          10825245000
 test master 2 - Starting Memory Write, at          10825515000
 test master 1 - Starting Memory Read, at          10825905000
 test master 1 - Starting Memory Read, at          10826235000
 test master 1 - Starting Memory Read, at          10826775000
 test master 1 - Starting Memory Read, at          10827105000
 test master 1 - Starting Memory Read, at          10827645000
 test master 1 - Starting Memory Read, at          10827975000
 test master 2 - Starting Memory Write, at          10829235000
 test master 2 - Starting Memory Write, at          10829505000
 test master 2 - Starting Memory Write, at          10829775000
 test master 2 - Starting Memory Write, at          10830045000
 test master 2 - Starting Memory Write, at          10830315000
 test master 1 - Starting Memory Read, at          10830705000
 test master 1 - Starting Memory Read, at          10831035000
 test master 1 - Starting Memory Read, at          10831575000
 test master 1 - Starting Memory Read, at          10831905000
 test master 1 - Starting Memory Read, at          10832445000
 test master 1 - Starting Memory Read, at          10832775000
 test master 2 - Starting Memory Write, at          10834515000
 test master 2 - Starting Memory Write, at          10835625000
 test master 2 - Starting Memory Write, at          10836705000
 test master 2 - Starting Memory Write, at          10837785000
 test master 2 - Starting Memory Write, at          10839945000
 test master 2 - Starting Memory Write, at          10841025000
 test master 2 - Starting Memory Write, at          10842105000
 test master 2 - Starting Memory Write, at          10843185000
 test master 2 - Starting Memory Write, at          10845345000
 test master 2 - Starting Memory Write, at          10847355000
 test master 2 - Starting Memory Write, at          10849395000
 test master 2 - Starting Memory Write, at          10851435000
 test master 2 - Starting Memory Write, at          10854555000
 test master 2 - Starting Memory Write, at          10856835000
 test master 2 - Starting Memory Write, at          10859115000
 test master 2 - Starting Memory Write, at          10861395000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          10865805000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10865835000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10867905000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          10868175000
 test master 2 - Starting Memory Read, at          10868385000
 test master 2 - Starting Memory Read, at          10868595000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10870155000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          10870515000
 test master 2 - Starting Memory Read, at          10870725000
 test master 2 - Starting Memory Read, at          10870935000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10872315000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10872795000
 test master 2 - Starting Memory Read Line Multiple, at          10873005000
 test master 2 - Starting Memory Read Line Multiple, at          10873275000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10875105000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10882095000
 test master 2 - Starting Memory Read Line Multiple, at          10882305000
 test master 2 - Starting Memory Read Line Multiple, at          10882605000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10883355000
 test master 2 - Starting Memory Read Line Multiple, at          10883565000
 test master 2 - Starting Memory Read Line Multiple, at          10883865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10884615000
 test master 2 - Starting Memory Read Line Multiple, at          10884825000
 test master 2 - Starting Memory Read Line Multiple, at          10885125000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10885875000
 test master 2 - Starting Memory Read Line Multiple, at          10886085000
 test master 2 - Starting Memory Read Line Multiple, at          10886385000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10887135000
 test master 2 - Starting Memory Read Line Multiple, at          10887345000
 test master 2 - Starting Memory Read Line Multiple, at          10887645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10888395000
 test master 2 - Starting Memory Read Line Multiple, at          10888605000
 test master 2 - Starting Memory Read Line Multiple, at          10888905000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10889655000
 test master 2 - Starting Memory Read Line Multiple, at          10889865000
 test master 2 - Starting Memory Read Line Multiple, at          10890165000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10890915000
 test master 2 - Starting Memory Read Line Multiple, at          10891125000
 test master 2 - Starting Memory Read Line Multiple, at          10891425000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          10892175000
 test master 2 - Starting Memory Read Line, at          10892385000
 test master 2 - Starting Memory Read Line, at          10892625000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          10893105000
 test master 2 - Starting Memory Read Line, at          10893315000
 test master 2 - Starting Memory Read Line, at          10893525000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10894665000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10896165000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10898955000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10900665000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          10905195000
 test master 2 - Starting Memory Write, at          10905465000
 test master 2 - Starting Memory Write, at          10905735000
 test master 2 - Starting Memory Write, at          10906005000
 test master 2 - Starting Memory Write, at          10906275000
 test master 1 - Starting Memory Read, at          10906665000
 test master 1 - Starting Memory Read, at          10906995000
 test master 1 - Starting Memory Read, at          10907535000
 test master 1 - Starting Memory Read, at          10907865000
 test master 1 - Starting Memory Read, at          10908405000
 test master 1 - Starting Memory Read, at          10908735000
 test master 2 - Starting Memory Write, at          10909995000
 test master 2 - Starting Memory Write, at          10910265000
 test master 2 - Starting Memory Write, at          10910535000
 test master 2 - Starting Memory Write, at          10910805000
 test master 2 - Starting Memory Write, at          10911075000
 test master 1 - Starting Memory Read, at          10911465000
 test master 1 - Starting Memory Read, at          10911795000
 test master 1 - Starting Memory Read, at          10912335000
 test master 1 - Starting Memory Read, at          10912665000
 test master 1 - Starting Memory Read, at          10913205000
 test master 1 - Starting Memory Read, at          10913535000
 test master 2 - Starting Memory Write, at          10915275000
 test master 2 - Starting Memory Write, at          10916385000
 test master 2 - Starting Memory Write, at          10917465000
 test master 2 - Starting Memory Write, at          10918545000
 test master 2 - Starting Memory Write, at          10920705000
 test master 2 - Starting Memory Write, at          10921785000
 test master 2 - Starting Memory Write, at          10922865000
 test master 2 - Starting Memory Write, at          10923945000
 test master 2 - Starting Memory Write, at          10926105000
 test master 2 - Starting Memory Write, at          10928115000
 test master 2 - Starting Memory Write, at          10930155000
 test master 2 - Starting Memory Write, at          10932195000
 test master 2 - Starting Memory Write, at          10935315000
 test master 2 - Starting Memory Write, at          10937595000
 test master 2 - Starting Memory Write, at          10939875000
 test master 2 - Starting Memory Write, at          10942155000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          10946565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          10946595000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10948665000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          10948935000
 test master 2 - Starting Memory Read, at          10949145000
 test master 2 - Starting Memory Read, at          10949355000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10950915000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          10951275000
 test master 2 - Starting Memory Read, at          10951485000
 test master 2 - Starting Memory Read, at          10951695000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10953075000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10953555000
 test master 2 - Starting Memory Read Line Multiple, at          10953765000
 test master 2 - Starting Memory Read Line Multiple, at          10954035000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10955865000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10962855000
 test master 2 - Starting Memory Read Line Multiple, at          10963065000
 test master 2 - Starting Memory Read Line Multiple, at          10963365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10964115000
 test master 2 - Starting Memory Read Line Multiple, at          10964325000
 test master 2 - Starting Memory Read Line Multiple, at          10964625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10965375000
 test master 2 - Starting Memory Read Line Multiple, at          10965585000
 test master 2 - Starting Memory Read Line Multiple, at          10965885000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10966635000
 test master 2 - Starting Memory Read Line Multiple, at          10966845000
 test master 2 - Starting Memory Read Line Multiple, at          10967145000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10967895000
 test master 2 - Starting Memory Read Line Multiple, at          10968105000
 test master 2 - Starting Memory Read Line Multiple, at          10968405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10969155000
 test master 2 - Starting Memory Read Line Multiple, at          10969365000
 test master 2 - Starting Memory Read Line Multiple, at          10969665000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10970415000
 test master 2 - Starting Memory Read Line Multiple, at          10970625000
 test master 2 - Starting Memory Read Line Multiple, at          10970925000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          10971675000
 test master 2 - Starting Memory Read Line Multiple, at          10971885000
 test master 2 - Starting Memory Read Line Multiple, at          10972185000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          10972935000
 test master 2 - Starting Memory Read Line, at          10973145000
 test master 2 - Starting Memory Read Line, at          10973385000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          10973865000
 test master 2 - Starting Memory Read Line, at          10974075000
 test master 2 - Starting Memory Read Line, at          10974285000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10975425000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10976925000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10979715000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          10981425000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          10985955000
 test master 2 - Starting Memory Write, at          10986225000
 test master 2 - Starting Memory Write, at          10986495000
 test master 2 - Starting Memory Write, at          10986765000
 test master 2 - Starting Memory Write, at          10987035000
 test master 1 - Starting Memory Read, at          10987425000
 test master 1 - Starting Memory Read, at          10987755000
 test master 1 - Starting Memory Read, at          10988295000
 test master 1 - Starting Memory Read, at          10988625000
 test master 1 - Starting Memory Read, at          10989165000
 test master 1 - Starting Memory Read, at          10989495000
 test master 2 - Starting Memory Write, at          10990755000
 test master 2 - Starting Memory Write, at          10991025000
 test master 2 - Starting Memory Write, at          10991295000
 test master 2 - Starting Memory Write, at          10991565000
 test master 2 - Starting Memory Write, at          10991835000
 test master 1 - Starting Memory Read, at          10992225000
 test master 1 - Starting Memory Read, at          10992555000
 test master 1 - Starting Memory Read, at          10993095000
 test master 1 - Starting Memory Read, at          10993425000
 test master 1 - Starting Memory Read, at          10993965000
 test master 1 - Starting Memory Read, at          10994295000
 test master 2 - Starting Memory Write, at          10996035000
 test master 2 - Starting Memory Write, at          10997145000
 test master 2 - Starting Memory Write, at          10998225000
 test master 2 - Starting Memory Write, at          10999305000
 test master 2 - Starting Memory Write, at          11001465000
 test master 2 - Starting Memory Write, at          11002545000
 test master 2 - Starting Memory Write, at          11003625000
 test master 2 - Starting Memory Write, at          11004705000
 test master 2 - Starting Memory Write, at          11006865000
 test master 2 - Starting Memory Write, at          11008875000
 test master 2 - Starting Memory Write, at          11010915000
 test master 2 - Starting Memory Write, at          11012955000
 test master 2 - Starting Memory Write, at          11016075000
 test master 2 - Starting Memory Write, at          11018355000
 test master 2 - Starting Memory Write, at          11020635000
 test master 2 - Starting Memory Write, at          11022915000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          11027325000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11027355000
 test master 1 - Starting Memory Read, at          11029425000
 test master 1 - Starting Memory Read, at          11029785000
 test master 1 - Starting Memory Read, at          11030985000
 test master 1 - Starting Memory Read, at          11031345000
 test master 1 - Starting Memory Read Line, at          11032545000
 test master 1 - Starting Memory Read Line, at          11032905000
 test master 1 - Starting Memory Read Line, at          11034105000
 test master 1 - Starting Memory Read Line, at          11034465000
 test master 1 - Starting Memory Read Line, at          11035725000
 test master 1 - Starting Memory Read Line, at          11036145000
 test master 1 - Starting Memory Read Line, at          11037585000
 test master 1 - Starting Memory Read Line, at          11038005000
 test master 1 - Starting Memory Read Line Multiple, at          11039445000
 test master 1 - Starting Memory Read Line Multiple, at          11039925000
 test master 1 - Starting Memory Read Line Multiple, at          11041665000
 test master 1 - Starting Memory Read Line Multiple, at          11042145000
 test master 1 - Starting Memory Read Line, at          11043885000
 test master 1 - Starting Memory Read Line, at          11044305000
 test master 1 - Starting Memory Read, at          11046735000
 test master 1 - Starting Memory Read, at          11047095000
 test target 1 - Starting Config Write, at          11050305000
 test master 1 - Starting Memory Write, at          11050965000
 test master 1 - Starting Memory Write, at          11056605000
 test master 1 - Starting Memory Write, at          11057955000
 test master 1 - Starting Memory Write, at          11063235000
 test master 1 - Starting Memory Write, at          11064555000
 test master 1 - Starting Memory Read Line, at          11070195000
 test master 1 - Starting Memory Write, at          11071695000
 test master 1 - Starting Memory Read Line, at          11077335000
 test target 1 - Starting Config Write, at          11080605000
 test master 1 - Starting Memory Write, at          11081265000
 test master 1 - Starting Memory Write, at          11081415000
 test master 1 - Starting Memory Write, at          11081685000
 test master 1 - Starting Memory Read, at          11081835000
 test master 1 - Starting Memory Write, at          11082195000
 test master 1 - Starting Memory Read, at          11082345000
 test master 1 - Starting Memory Write, at          11083965000
 test master 1 - Starting Memory Write, at          11090955000
 test master 2 - Starting Memory Read Line, at          11098035000
 test master 2 - Starting Memory Read Line, at          11098425000
 test master 2 - Starting Memory Read Line, at          11098935000
 test master 2 - Starting Memory Read Line, at          11099325000
 test master 1 - Starting Memory Write, at          11099925000
 test master 1 - Starting Memory Write, at          11100225000
 test master 1 - Starting Memory Write, at          11100555000
 test master 2 - Starting Memory Read Line, at          11101005000
 test master 2 - Starting Memory Read Line, at          11101365000
 test master 2 - Starting Memory Read Line, at          11101665000
 test master 2 - Starting Memory Read Line, at          11102025000
 test master 2 - Starting Memory Read Line Multiple, at          11102355000
 test master 2 - Starting Memory Read Line Multiple, at          11102715000
 test master 1 - Starting Memory Write, at          11104605000
 test master 1 - Starting Memory Write, at          11104905000
 test master 2 - Starting Memory Read, at          11105355000
 test master 2 - Starting Memory Read, at          11105715000
 test master 2 - Starting Memory Read, at          11106015000
 test master 2 - Starting Memory Read, at          11106375000
 test master 1 - Starting Memory Write, at          11108025000
 test master 1 - Starting Memory Read, at          11108235000
 test master 1 - Starting Memory Write, at          11108445000
 test master 1 - Starting Memory Read, at          11108655000
 test master 1 - Starting Memory Write, at          11108865000
 test master 1 - Starting Memory Read, at          11109075000
 test master 1 - Starting Memory Read, at          11109285000
 test master 1 - Starting Memory Write, at          11109495000
 test master 1 - Starting Memory Write, at          11109705000
 test master 1 - Starting Memory Read, at          11109915000
 test master 1 - Starting Memory Write, at          11110125000
 test master 1 - Starting Memory Write, at          11110335000
 test master 1 - Starting Memory Write, at          11110545000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          11114865000
 test target 1 - Starting Memory Write, at          11115165000
 test master 1 - Starting Memory Write, at          11115435000
 test target 1 - Starting Memory Write, at          11115645000
 test target 1 - Starting Memory Write, at          11115945000
 test target 1 - Starting Memory Write, at          11116245000
 test master 1 - Starting Memory Write, at          11116635000
 test target 1 - Starting Memory Write, at          11117175000
 test target 1 - Starting Memory Write, at          11117835000
 test target 1 - Starting Memory Write, at          11118165000
 test master 1 - Starting Memory Write, at          11118465000
 test target 1 - Starting Memory Write, at          11118855000
 test target 1 - Starting Memory Write, at          11119185000
 test target 1 - Starting Memory Write, at          11119515000
 test master 1 - Starting Memory Write, at          11120085000
 test target 1 - Starting Memory Write, at          11120955000
 test target 1 - Starting Memory Write, at          11121795000
 test target 1 - Starting Memory Write, at          11122095000
 test master 1 - Starting Memory Read, at          11122365000
 test target 1 - Starting Memory Write, at          11122575000
 test master 1 - Starting Memory Read, at          11122845000
 test target 1 - Starting Memory Write, at          11123055000
 test master 1 - Starting Memory Read, at          11123325000
 test target 1 - Starting Memory Write, at          11123535000
 test master 1 - Starting Memory Read, at          11123805000
 test target 1 - Starting Memory Write, at          11124015000
 test master 1 - Starting Memory Read, at          11124285000
 test target 1 - Starting Memory Write, at          11124495000
 test master 1 - Starting Memory Write, at          11124765000
 test target 1 - Starting Memory Write, at          11124975000
 test target 1 - Starting Memory Write, at          11125275000
 test target 1 - Starting Memory Write, at          11125575000
 test target 1 - Starting Memory Read, at          11125935000
 test master 1 - Starting Memory Write, at          11126325000
 test master 1 - Starting Memory Read, at          11126595000
 test target 1 - Starting Memory Write, at          11127135000
 test master 1 - Starting Memory Write, at          11127615000
 test target 1 - Starting Memory Read, at          11128065000
 test target 1 - Starting Memory Write, at          11128935000
 test master 1 - Starting Memory Read, at          11129325000
 test master 1 - Starting Memory Write, at          11129685000
 test master 1 - Starting Memory Write, at          11130075000
 test master 1 - Starting Memory Read, at          11130345000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          11132865000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          11133945000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          11158965000
 test target 1 - Starting Config Write, at          11159955000
 test target 1 - Starting Config Write, at          11160945000
 test target 2 - Starting Config Write, at          11161965000
 test target 2 - Starting Config Write, at          11162955000
 test target 2 - Starting Config Write, at          11163945000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          11165955000
 test target 1 - Starting Memory Read, at          11166225000
 test target 1 - Starting Memory Write, at          11166855000
 test target 1 - Starting Memory Read, at          11167125000
 test target 1 - Starting Memory Write, at          11168265000
 test target 1 - Starting Memory Read, at          11169225000
 test target 1 - Starting Memory Read, at          11169855000
 test target 1 - Starting Memory Read, at          11170485000
 test target 1 - Starting Memory Read, at          11171085000
 test target 1 - Starting Memory Read, at          11171925000
 test target 1 - Starting Memory Read, at          11173005000
 test target 1 - Starting Memory Read, at          11173965000
 test target 1 - Starting Memory Read, at          11175045000
 test target 1 - Starting Memory Read, at          11176005000
 test target 1 - Starting Memory Read, at          11177775000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          11184255000
 test target 1 - Starting Memory Read, at          11184525000
 test target 1 - Starting Memory Write, at          11185155000
 test target 1 - Starting Memory Read, at          11185425000
 test target 1 - Starting Memory Write, at          11186565000
 test target 1 - Starting Memory Read, at          11187525000
 test target 1 - Starting Memory Read, at          11188155000
 test target 1 - Starting Memory Read, at          11188785000
 test target 1 - Starting Memory Read, at          11189385000
 test target 1 - Starting Memory Read, at          11190225000
 test target 1 - Starting Memory Read, at          11191305000
 test target 1 - Starting Memory Read, at          11192265000
 test target 1 - Starting Memory Read, at          11193345000
 test target 1 - Starting Memory Read, at          11194305000
 test target 1 - Starting Memory Read, at          11196075000
 test target 1 - Starting Memory Write, at          11202555000
 test target 1 - Starting Memory Read, at          11202825000
 test target 1 - Starting Memory Write, at          11203455000
 test target 1 - Starting Memory Read, at          11203725000
 test target 1 - Starting Memory Write, at          11204865000
 test target 1 - Starting Memory Read, at          11205825000
 test target 1 - Starting Memory Read, at          11206455000
 test target 1 - Starting Memory Read, at          11207085000
 test target 1 - Starting Memory Read, at          11207685000
 test target 1 - Starting Memory Read, at          11208525000
 test target 1 - Starting Memory Read, at          11209605000
 test target 1 - Starting Memory Read, at          11210565000
 test target 1 - Starting Memory Read, at          11211645000
 test target 1 - Starting Memory Read, at          11212605000
 test target 1 - Starting Memory Read, at          11214375000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          11226465000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          11233065000
 test target 1 - Starting Memory Write, at          11234055000
 test target 1 - Starting Memory Read, at          11234445000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          11235645000
 test target 1 - Starting Config Write, at          11237715000
 test target 1 - Starting Memory Read, at          11238465000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          11240025000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          11242245000
 test target 1 - Starting Memory Write, at          11243535000
 test target 1 - Starting Memory Write, at          11243835000
 test target 1 - Starting Memory Read, at          11244105000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          11246685000
 test target 1 - Starting Memory Write, at          11249835000
 test target 1 - Starting Memory Write, at          11250195000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          11254215000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          11256285000
 test target 1 - Starting Memory Read, at          11257575000
 test target 1 - Starting Memory Read, at          11258625000
 test target 1 - Starting Memory Read, at          11260365000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          11266365000
 test target 2 - Starting Config Write, at          11267385000
 test target 1 - Starting Memory Write, at          11268135000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          11268315000
 test target 1 - Starting Memory Write, at          11269335000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          11269515000
 test target 1 - Starting Memory Write, at          11270535000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          11271945000
 test target 1 - Starting Memory Read, at          11274255000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          11274435000
 test target 1 - Starting Memory Read, at          11276625000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          11278455000
 test master 2 - Starting Memory Write, at          11278455000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          11278515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11279385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11279415000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11279715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11279745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11280645000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11280675000
 test target 1 - Starting Memory Write, at          11282505000
 test master 2 - Starting Memory Write, at          11282505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11284275000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11284305000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11286015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11286045000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11287755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11287785000
 test target 1 - Starting Memory Write, at          11289855000
 test master 2 - Starting Memory Write, at          11289855000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          11289915000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11291595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11291625000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11291925000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11291955000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11292855000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11292885000
 test target 1 - Starting Memory Write, at          11294085000
 test master 2 - Starting Memory Write, at          11294085000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          11297055000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          11298735000
 test master 1 - Starting Memory Read, at          11299185000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          11299365000
 test target 1 - Starting Config Write, at          11301885000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          11304315000
 test target 1 - Starting Memory Write, at          11304525000
 test target 1 - Starting Memory Write, at          11304735000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          11305275000
 test target 1 - Starting Memory Write, at          11305515000
 test target 1 - Starting Memory Write, at          11305755000
 test target 1 - Starting Memory Write, at          11306295000
 test target 1 - Starting Memory Write, at          11306565000
 test target 1 - Starting Memory Write, at          11307105000
 test target 1 - Starting Memory Write, at          11307795000
 test target 1 - Starting Memory Write, at          11308035000
 test target 1 - Starting Memory Write, at          11308725000
 test target 1 - Starting Memory Write, at          11309025000
 test target 1 - Starting Memory Write, at          11309655000
 test target 1 - Starting Memory Write, at          11316375000
 test target 1 - Starting Memory Write, at          11316615000
 test target 1 - Starting Memory Write, at          11316855000
 test target 1 - Starting Memory Write, at          11317155000
 test target 1 - Starting Memory Write, at          11317455000
 test target 1 - Starting Memory Read, at          11321145000
 test target 1 - Starting Memory Read, at          11322225000
 test target 1 - Starting Memory Read, at          11323305000
 test target 1 - Starting Memory Read, at          11324385000
 test target 1 - Starting Memory Read, at          11325465000
 test target 1 - Starting Memory Read, at          11326545000
 test target 1 - Starting Memory Read, at          11327625000
 test target 1 - Starting Memory Read, at          11328705000
 test target 1 - Starting Memory Read, at          11329785000
 test target 1 - Starting Memory Read, at          11330865000
 test target 1 - Starting Memory Read, at          11331945000
 test target 1 - Starting Memory Read, at          11333025000
 test target 1 - Starting Memory Read, at          11334105000
 test target 1 - Starting Memory Read, at          11335185000
 test target 1 - Starting Memory Read, at          11336265000
 test target 1 - Starting Memory Read, at          11337345000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          11338245000
 test target 1 - Starting Memory Read, at          11338455000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          11340615000
 test target 1 - Starting Memory Read, at          11341785000
 test target 1 - Starting Memory Read, at          11342505000
 test target 1 - Starting Memory Read, at          11343225000
 test target 1 - Starting Memory Read, at          11344005000
 test target 1 - Starting Memory Read, at          11344755000
 test target 1 - Starting Memory Read, at          11345865000
 test target 1 - Starting Memory Read, at          11346945000
 test target 1 - Starting Memory Read, at          11347905000
 test target 1 - Starting Memory Read, at          11350785000
 test target 1 - Starting Memory Read, at          11352765000
 test target 1 - Starting Memory Read, at          11353605000
 test target 1 - Starting Memory Read, at          11354445000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          11355825000
 test master 1 - Starting Memory Write, at          11356065000
 test target 1 - Starting Memory Write, at          11356065000
 test target 1 - Starting Memory Write, at          11356275000
 test target 1 - Starting Memory Read, at          11356725000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          11358735000
 test master 1 - Starting Memory Write, at          11358975000
 test target 1 - Starting Memory Write, at          11358975000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          11364045000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          11365125000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          11390145000
 test target 1 - Starting Config Write, at          11391135000
 test target 1 - Starting Config Write, at          11392125000
 test target 2 - Starting Config Write, at          11393145000
 test target 2 - Starting Config Write, at          11394135000
 test target 2 - Starting Config Write, at          11395125000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          11397135000
 test target 1 - Starting Memory Read, at          11397435000
 test target 1 - Starting Memory Write, at          11398215000
 test target 1 - Starting Memory Read, at          11398515000
 test target 1 - Starting Memory Write, at          11399805000
 test target 1 - Starting Memory Read, at          11400765000
 test target 1 - Starting Memory Read, at          11401395000
 test target 1 - Starting Memory Read, at          11402025000
 test target 1 - Starting Memory Read, at          11402625000
 test target 1 - Starting Memory Read, at          11403465000
 test target 1 - Starting Memory Read, at          11404545000
 test target 1 - Starting Memory Read, at          11405505000
 test target 1 - Starting Memory Read, at          11406585000
 test target 1 - Starting Memory Read, at          11407545000
 test target 1 - Starting Memory Read, at          11409465000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          11415915000
 test target 1 - Starting Memory Read, at          11416215000
 test target 1 - Starting Memory Write, at          11416995000
 test target 1 - Starting Memory Read, at          11417295000
 test target 1 - Starting Memory Write, at          11418585000
 test target 1 - Starting Memory Read, at          11419545000
 test target 1 - Starting Memory Read, at          11420175000
 test target 1 - Starting Memory Read, at          11420805000
 test target 1 - Starting Memory Read, at          11421405000
 test target 1 - Starting Memory Read, at          11422245000
 test target 1 - Starting Memory Read, at          11423325000
 test target 1 - Starting Memory Read, at          11424285000
 test target 1 - Starting Memory Read, at          11425365000
 test target 1 - Starting Memory Read, at          11426325000
 test target 1 - Starting Memory Read, at          11428245000
 test target 1 - Starting Memory Write, at          11434695000
 test target 1 - Starting Memory Read, at          11434995000
 test target 1 - Starting Memory Write, at          11435775000
 test target 1 - Starting Memory Read, at          11436075000
 test target 1 - Starting Memory Write, at          11437365000
 test target 1 - Starting Memory Read, at          11438325000
 test target 1 - Starting Memory Read, at          11438955000
 test target 1 - Starting Memory Read, at          11439585000
 test target 1 - Starting Memory Read, at          11440185000
 test target 1 - Starting Memory Read, at          11441025000
 test target 1 - Starting Memory Read, at          11442105000
 test target 1 - Starting Memory Read, at          11443065000
 test target 1 - Starting Memory Read, at          11444145000
 test target 1 - Starting Memory Read, at          11445105000
 test target 1 - Starting Memory Read, at          11447025000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          11459085000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          11465685000
 test target 1 - Starting Memory Write, at          11466675000
 test target 1 - Starting Memory Read, at          11467095000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          11468445000
 test target 1 - Starting Config Write, at          11470515000
 test target 1 - Starting Memory Read, at          11471265000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          11472825000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          11475045000
 test target 1 - Starting Memory Write, at          11476335000
 test target 1 - Starting Memory Write, at          11476665000
 test target 1 - Starting Memory Read, at          11476965000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          11479485000
 test target 1 - Starting Memory Write, at          11482635000
 test target 1 - Starting Memory Write, at          11483025000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          11487075000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          11489145000
 test target 1 - Starting Memory Read, at          11490615000
 test target 1 - Starting Memory Read, at          11491665000
 test target 1 - Starting Memory Read, at          11493405000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          11499405000
 test target 2 - Starting Config Write, at          11500425000
 test target 1 - Starting Memory Write, at          11501175000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          11501385000
 test target 1 - Starting Memory Write, at          11502405000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          11502615000
 test target 1 - Starting Memory Write, at          11503635000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          11505105000
 test target 1 - Starting Memory Read, at          11507415000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          11507625000
 test target 1 - Starting Memory Read, at          11509785000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          11511615000
 test master 2 - Starting Memory Write, at          11511615000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          11511675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11512575000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11512605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11512905000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11512935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11513835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11513865000
 test target 1 - Starting Memory Write, at          11515695000
 test master 2 - Starting Memory Write, at          11515695000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11517495000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11517525000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11519235000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11519265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11520975000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11521005000
 test target 1 - Starting Memory Write, at          11523075000
 test master 2 - Starting Memory Write, at          11523075000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          11523135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11524845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11524875000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11525175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11525205000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11526105000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11526135000
 test target 1 - Starting Memory Write, at          11527335000
 test master 2 - Starting Memory Write, at          11527335000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          11530335000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          11532015000
 test master 1 - Starting Memory Read, at          11532465000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          11532645000
 test target 1 - Starting Config Write, at          11535165000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          11537595000
 test target 1 - Starting Memory Write, at          11537835000
 test target 1 - Starting Memory Write, at          11538075000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          11538645000
 test target 1 - Starting Memory Write, at          11538915000
 test target 1 - Starting Memory Write, at          11539185000
 test target 1 - Starting Memory Write, at          11539755000
 test target 1 - Starting Memory Write, at          11540055000
 test target 1 - Starting Memory Write, at          11540625000
 test target 1 - Starting Memory Write, at          11541345000
 test target 1 - Starting Memory Write, at          11541615000
 test target 1 - Starting Memory Write, at          11542335000
 test target 1 - Starting Memory Write, at          11542665000
 test target 1 - Starting Memory Write, at          11543325000
 test target 1 - Starting Memory Write, at          11550075000
 test target 1 - Starting Memory Write, at          11550345000
 test target 1 - Starting Memory Write, at          11550615000
 test target 1 - Starting Memory Write, at          11550945000
 test target 1 - Starting Memory Write, at          11551275000
 test target 1 - Starting Memory Read, at          11554995000
 test target 1 - Starting Memory Read, at          11556075000
 test target 1 - Starting Memory Read, at          11557155000
 test target 1 - Starting Memory Read, at          11558235000
 test target 1 - Starting Memory Read, at          11559315000
 test target 1 - Starting Memory Read, at          11560395000
 test target 1 - Starting Memory Read, at          11561475000
 test target 1 - Starting Memory Read, at          11562555000
 test target 1 - Starting Memory Read, at          11563635000
 test target 1 - Starting Memory Read, at          11564715000
 test target 1 - Starting Memory Read, at          11565795000
 test target 1 - Starting Memory Read, at          11566875000
 test target 1 - Starting Memory Read, at          11567955000
 test target 1 - Starting Memory Read, at          11569035000
 test target 1 - Starting Memory Read, at          11570115000
 test target 1 - Starting Memory Read, at          11571195000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          11572125000
 test target 1 - Starting Memory Read, at          11572365000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          11574675000
 test target 1 - Starting Memory Read, at          11575875000
 test target 1 - Starting Memory Read, at          11576535000
 test target 1 - Starting Memory Read, at          11577285000
 test target 1 - Starting Memory Read, at          11578155000
 test target 1 - Starting Memory Read, at          11578905000
 test target 1 - Starting Memory Read, at          11580015000
 test target 1 - Starting Memory Read, at          11581125000
 test target 1 - Starting Memory Read, at          11582055000
 test target 1 - Starting Memory Read, at          11584935000
 test target 1 - Starting Memory Read, at          11586945000
 test target 1 - Starting Memory Read, at          11587785000
 test target 1 - Starting Memory Read, at          11588625000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          11590005000
 test master 1 - Starting Memory Write, at          11590275000
 test target 1 - Starting Memory Write, at          11590275000
 test target 1 - Starting Memory Write, at          11590515000
 test target 1 - Starting Memory Read, at          11590995000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          11593095000
 test master 1 - Starting Memory Write, at          11593365000
 test target 1 - Starting Memory Write, at          11593365000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          11598405000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          11599605000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          11624745000
 test target 1 - Starting Config Write, at          11625735000
 test target 1 - Starting Config Write, at          11626725000
 test target 2 - Starting Config Write, at          11627745000
 test target 2 - Starting Config Write, at          11628735000
 test target 2 - Starting Config Write, at          11629725000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          11631735000
 test target 1 - Starting Memory Read, at          11632065000
 test target 1 - Starting Memory Write, at          11632815000
 test target 1 - Starting Memory Read, at          11633145000
 test target 1 - Starting Memory Write, at          11634405000
 test target 1 - Starting Memory Read, at          11635425000
 test target 1 - Starting Memory Read, at          11636055000
 test target 1 - Starting Memory Read, at          11636835000
 test target 1 - Starting Memory Read, at          11637615000
 test target 1 - Starting Memory Read, at          11638605000
 test target 1 - Starting Memory Read, at          11639865000
 test target 1 - Starting Memory Read, at          11640795000
 test target 1 - Starting Memory Read, at          11642055000
 test target 1 - Starting Memory Read, at          11642985000
 test target 1 - Starting Memory Read, at          11644905000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          11651355000
 test target 1 - Starting Memory Read, at          11651685000
 test target 1 - Starting Memory Write, at          11652435000
 test target 1 - Starting Memory Read, at          11652765000
 test target 1 - Starting Memory Write, at          11654025000
 test target 1 - Starting Memory Read, at          11655045000
 test target 1 - Starting Memory Read, at          11655675000
 test target 1 - Starting Memory Read, at          11656455000
 test target 1 - Starting Memory Read, at          11657235000
 test target 1 - Starting Memory Read, at          11658225000
 test target 1 - Starting Memory Read, at          11659485000
 test target 1 - Starting Memory Read, at          11660415000
 test target 1 - Starting Memory Read, at          11661675000
 test target 1 - Starting Memory Read, at          11662605000
 test target 1 - Starting Memory Read, at          11664525000
 test target 1 - Starting Memory Write, at          11670975000
 test target 1 - Starting Memory Read, at          11671305000
 test target 1 - Starting Memory Write, at          11672055000
 test target 1 - Starting Memory Read, at          11672385000
 test target 1 - Starting Memory Write, at          11673645000
 test target 1 - Starting Memory Read, at          11674665000
 test target 1 - Starting Memory Read, at          11675295000
 test target 1 - Starting Memory Read, at          11676075000
 test target 1 - Starting Memory Read, at          11676855000
 test target 1 - Starting Memory Read, at          11677845000
 test target 1 - Starting Memory Read, at          11679105000
 test target 1 - Starting Memory Read, at          11680035000
 test target 1 - Starting Memory Read, at          11681295000
 test target 1 - Starting Memory Read, at          11682225000
 test target 1 - Starting Memory Read, at          11684145000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          11696205000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          11702805000
 test target 1 - Starting Memory Write, at          11703795000
 test target 1 - Starting Memory Read, at          11704245000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          11705565000
 test target 1 - Starting Config Write, at          11707635000
 test target 1 - Starting Memory Read, at          11708385000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          11709945000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          11712165000
 test target 1 - Starting Memory Write, at          11713455000
 test target 1 - Starting Memory Write, at          11713815000
 test target 1 - Starting Memory Read, at          11714145000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          11716785000
 test target 1 - Starting Memory Write, at          11719995000
 test target 1 - Starting Memory Write, at          11720415000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          11724495000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          11726565000
 test target 1 - Starting Memory Read, at          11728035000
 test target 1 - Starting Memory Read, at          11729235000
 test target 1 - Starting Memory Read, at          11730975000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          11737125000
 test target 2 - Starting Config Write, at          11738145000
 test target 1 - Starting Memory Write, at          11738895000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          11739135000
 test target 1 - Starting Memory Write, at          11740155000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          11740395000
 test target 1 - Starting Memory Write, at          11741415000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          11742885000
 test target 1 - Starting Memory Read, at          11745195000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          11745435000
 test target 1 - Starting Memory Read, at          11747565000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          11749395000
 test master 2 - Starting Memory Write, at          11749395000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          11749455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11750385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11750415000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11750715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11750745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11751645000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11751675000
 test target 1 - Starting Memory Write, at          11753505000
 test master 2 - Starting Memory Write, at          11753505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11755335000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11755365000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11757075000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11757105000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11758815000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11758845000
 test target 1 - Starting Memory Write, at          11760915000
 test master 2 - Starting Memory Write, at          11760915000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          11760975000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11762715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11762745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11763045000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11763075000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11763975000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11764005000
 test target 1 - Starting Memory Write, at          11765205000
 test master 2 - Starting Memory Write, at          11765205000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          11768235000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          11769915000
 test master 1 - Starting Memory Read, at          11770365000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          11770545000
 test target 1 - Starting Config Write, at          11773065000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          11775495000
 test target 1 - Starting Memory Write, at          11775765000
 test target 1 - Starting Memory Write, at          11776035000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          11776635000
 test target 1 - Starting Memory Write, at          11776935000
 test target 1 - Starting Memory Write, at          11777235000
 test target 1 - Starting Memory Write, at          11777835000
 test target 1 - Starting Memory Write, at          11778165000
 test target 1 - Starting Memory Write, at          11778765000
 test target 1 - Starting Memory Write, at          11779515000
 test target 1 - Starting Memory Write, at          11779815000
 test target 1 - Starting Memory Write, at          11780565000
 test target 1 - Starting Memory Write, at          11780925000
 test target 1 - Starting Memory Write, at          11781615000
 test target 1 - Starting Memory Write, at          11788395000
 test target 1 - Starting Memory Write, at          11788695000
 test target 1 - Starting Memory Write, at          11788995000
 test target 1 - Starting Memory Write, at          11789355000
 test target 1 - Starting Memory Write, at          11789715000
 test target 1 - Starting Memory Read, at          11793465000
 test target 1 - Starting Memory Read, at          11794725000
 test target 1 - Starting Memory Read, at          11795955000
 test target 1 - Starting Memory Read, at          11797185000
 test target 1 - Starting Memory Read, at          11798445000
 test target 1 - Starting Memory Read, at          11799675000
 test target 1 - Starting Memory Read, at          11800905000
 test target 1 - Starting Memory Read, at          11802165000
 test target 1 - Starting Memory Read, at          11803395000
 test target 1 - Starting Memory Read, at          11804625000
 test target 1 - Starting Memory Read, at          11805885000
 test target 1 - Starting Memory Read, at          11807115000
 test target 1 - Starting Memory Read, at          11808345000
 test target 1 - Starting Memory Read, at          11809605000
 test target 1 - Starting Memory Read, at          11810835000
 test target 1 - Starting Memory Read, at          11812065000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          11813145000
 test target 1 - Starting Memory Read, at          11813415000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          11815695000
 test target 1 - Starting Memory Read, at          11816925000
 test target 1 - Starting Memory Read, at          11817585000
 test target 1 - Starting Memory Read, at          11818305000
 test target 1 - Starting Memory Read, at          11819205000
 test target 1 - Starting Memory Read, at          11819955000
 test target 1 - Starting Memory Read, at          11821215000
 test target 1 - Starting Memory Read, at          11822475000
 test target 1 - Starting Memory Read, at          11823405000
 test target 1 - Starting Memory Read, at          11826285000
 test target 1 - Starting Memory Read, at          11828265000
 test target 1 - Starting Memory Read, at          11829105000
 test target 1 - Starting Memory Read, at          11829945000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          11831325000
 test master 1 - Starting Memory Write, at          11831625000
 test target 1 - Starting Memory Write, at          11831625000
 test target 1 - Starting Memory Write, at          11831895000
 test target 1 - Starting Memory Read, at          11832405000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          11834445000
 test master 1 - Starting Memory Write, at          11834745000
 test target 1 - Starting Memory Write, at          11834745000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          11839785000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          11840985000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          11866125000
 test target 1 - Starting Config Write, at          11867115000
 test target 1 - Starting Config Write, at          11868105000
 test target 2 - Starting Config Write, at          11869125000
 test target 2 - Starting Config Write, at          11870115000
 test target 2 - Starting Config Write, at          11871105000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          11873115000
 test target 1 - Starting Memory Read, at          11873475000
 test target 1 - Starting Memory Write, at          11874195000
 test target 1 - Starting Memory Read, at          11874555000
 test target 1 - Starting Memory Write, at          11875785000
 test target 1 - Starting Memory Read, at          11876805000
 test target 1 - Starting Memory Read, at          11877585000
 test target 1 - Starting Memory Read, at          11878365000
 test target 1 - Starting Memory Read, at          11879145000
 test target 1 - Starting Memory Read, at          11880165000
 test target 1 - Starting Memory Read, at          11881425000
 test target 1 - Starting Memory Read, at          11882535000
 test target 1 - Starting Memory Read, at          11883795000
 test target 1 - Starting Memory Read, at          11884725000
 test target 1 - Starting Memory Read, at          11886645000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          11893275000
 test target 1 - Starting Memory Read, at          11893635000
 test target 1 - Starting Memory Write, at          11894355000
 test target 1 - Starting Memory Read, at          11894715000
 test target 1 - Starting Memory Write, at          11895945000
 test target 1 - Starting Memory Read, at          11896965000
 test target 1 - Starting Memory Read, at          11897745000
 test target 1 - Starting Memory Read, at          11898525000
 test target 1 - Starting Memory Read, at          11899305000
 test target 1 - Starting Memory Read, at          11900325000
 test target 1 - Starting Memory Read, at          11901585000
 test target 1 - Starting Memory Read, at          11902695000
 test target 1 - Starting Memory Read, at          11903955000
 test target 1 - Starting Memory Read, at          11904885000
 test target 1 - Starting Memory Read, at          11906805000
 test target 1 - Starting Memory Write, at          11913435000
 test target 1 - Starting Memory Read, at          11913795000
 test target 1 - Starting Memory Write, at          11914515000
 test target 1 - Starting Memory Read, at          11914875000
 test target 1 - Starting Memory Write, at          11916105000
 test target 1 - Starting Memory Read, at          11917125000
 test target 1 - Starting Memory Read, at          11917905000
 test target 1 - Starting Memory Read, at          11918685000
 test target 1 - Starting Memory Read, at          11919465000
 test target 1 - Starting Memory Read, at          11920485000
 test target 1 - Starting Memory Read, at          11921745000
 test target 1 - Starting Memory Read, at          11922855000
 test target 1 - Starting Memory Read, at          11924115000
 test target 1 - Starting Memory Read, at          11925045000
 test target 1 - Starting Memory Read, at          11926965000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          11939205000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          11945805000
 test target 1 - Starting Memory Write, at          11946795000
 test target 1 - Starting Memory Read, at          11947275000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          11948565000
 test target 1 - Starting Config Write, at          11950635000
 test target 1 - Starting Memory Read, at          11951385000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          11952945000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          11955165000
 test target 1 - Starting Memory Write, at          11956455000
 test target 1 - Starting Memory Write, at          11956845000
 test target 1 - Starting Memory Read, at          11957205000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          11959785000
 test target 1 - Starting Memory Write, at          11962995000
 test target 1 - Starting Memory Write, at          11963445000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          11967555000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          11969625000
 test target 1 - Starting Memory Read, at          11971095000
 test target 1 - Starting Memory Read, at          11972295000
 test target 1 - Starting Memory Read, at          11974035000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          11980185000
 test target 2 - Starting Config Write, at          11981205000
 test target 1 - Starting Memory Write, at          11981955000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          11982225000
 test target 1 - Starting Memory Write, at          11983245000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          11983515000
 test target 1 - Starting Memory Write, at          11984535000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          11986065000
 test target 1 - Starting Memory Read, at          11988375000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          11988645000
 test target 1 - Starting Memory Read, at          11990745000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          11992575000
 test master 2 - Starting Memory Write, at          11992575000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          11992635000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11993595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11993625000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11993925000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11993955000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11994855000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11994885000
 test target 1 - Starting Memory Write, at          11996715000
 test master 2 - Starting Memory Write, at          11996715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11998575000
*** monitor - CBE Bus Changed when TRDY Desserted, at          11998605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12000315000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12000345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12002055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12002085000
 test target 1 - Starting Memory Write, at          12004155000
 test master 2 - Starting Memory Write, at          12004155000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          12004215000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12005985000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12006015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12006315000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12006345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12007245000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12007275000
 test target 1 - Starting Memory Write, at          12008475000
 test master 2 - Starting Memory Write, at          12008475000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          12011535000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          12013215000
 test master 1 - Starting Memory Read, at          12013665000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          12013845000
 test target 1 - Starting Config Write, at          12016365000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          12018975000
 test target 1 - Starting Memory Write, at          12019275000
 test target 1 - Starting Memory Write, at          12019575000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          12020205000
 test target 1 - Starting Memory Write, at          12020535000
 test target 1 - Starting Memory Write, at          12020865000
 test target 1 - Starting Memory Write, at          12021495000
 test target 1 - Starting Memory Write, at          12021855000
 test target 1 - Starting Memory Write, at          12022485000
 test target 1 - Starting Memory Write, at          12023265000
 test target 1 - Starting Memory Write, at          12023595000
 test target 1 - Starting Memory Write, at          12024375000
 test target 1 - Starting Memory Write, at          12024765000
 test target 1 - Starting Memory Write, at          12025485000
 test target 1 - Starting Memory Write, at          12032295000
 test target 1 - Starting Memory Write, at          12032625000
 test target 1 - Starting Memory Write, at          12032955000
 test target 1 - Starting Memory Write, at          12033345000
 test target 1 - Starting Memory Write, at          12033735000
 test target 1 - Starting Memory Read, at          12037515000
 test target 1 - Starting Memory Read, at          12038775000
 test target 1 - Starting Memory Read, at          12040005000
 test target 1 - Starting Memory Read, at          12041265000
 test target 1 - Starting Memory Read, at          12042495000
 test target 1 - Starting Memory Read, at          12043725000
 test target 1 - Starting Memory Read, at          12044985000
 test target 1 - Starting Memory Read, at          12046215000
 test target 1 - Starting Memory Read, at          12047445000
 test target 1 - Starting Memory Read, at          12048705000
 test target 1 - Starting Memory Read, at          12049935000
 test target 1 - Starting Memory Read, at          12051165000
 test target 1 - Starting Memory Read, at          12052425000
 test target 1 - Starting Memory Read, at          12053655000
 test target 1 - Starting Memory Read, at          12054885000
 test target 1 - Starting Memory Read, at          12056145000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          12057225000
 test target 1 - Starting Memory Read, at          12057525000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          12059775000
 test target 1 - Starting Memory Read, at          12061035000
 test target 1 - Starting Memory Read, at          12061815000
 test target 1 - Starting Memory Read, at          12062685000
 test target 1 - Starting Memory Read, at          12063555000
 test target 1 - Starting Memory Read, at          12064305000
 test target 1 - Starting Memory Read, at          12065565000
 test target 1 - Starting Memory Read, at          12066825000
 test target 1 - Starting Memory Read, at          12067935000
 test target 1 - Starting Memory Read, at          12070935000
 test target 1 - Starting Memory Read, at          12072945000
 test target 1 - Starting Memory Read, at          12073965000
 test target 1 - Starting Memory Read, at          12074985000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          12076545000
 test master 1 - Starting Memory Write, at          12076875000
 test target 1 - Starting Memory Write, at          12076875000
 test target 1 - Starting Memory Write, at          12077175000
 test target 1 - Starting Memory Read, at          12077715000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          12079845000
 test master 1 - Starting Memory Write, at          12080175000
 test target 1 - Starting Memory Write, at          12080175000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12085455000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          12085785000
 test master 2 - Starting Memory Read, at          12085995000
 test master 2 - Starting Memory Read, at          12086205000
 test master 2 - Starting Memory Read, at          12086445000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12087975000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          12088455000
 test master 2 - Starting Memory Read, at          12088665000
 test master 2 - Starting Memory Read, at          12089115000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12090495000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12091095000
 test master 2 - Starting Memory Read Line Multiple, at          12091305000
 test master 2 - Starting Memory Read Line Multiple, at          12091515000
 test master 2 - Starting Memory Read Line Multiple, at          12091725000
 test master 2 - Starting Memory Read Line Multiple, at          12091995000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12093675000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12102555000
 test master 2 - Starting Memory Read Line Multiple, at          12102765000
 test master 2 - Starting Memory Read Line Multiple, at          12102975000
 test master 2 - Starting Memory Read Line Multiple, at          12103185000
 test master 2 - Starting Memory Read Line Multiple, at          12103485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12104055000
 test master 2 - Starting Memory Read Line Multiple, at          12104265000
 test master 2 - Starting Memory Read Line Multiple, at          12104475000
 test master 2 - Starting Memory Read Line Multiple, at          12104685000
 test master 2 - Starting Memory Read Line Multiple, at          12104985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12105555000
 test master 2 - Starting Memory Read Line Multiple, at          12105765000
 test master 2 - Starting Memory Read Line Multiple, at          12105975000
 test master 2 - Starting Memory Read Line Multiple, at          12106185000
 test master 2 - Starting Memory Read Line Multiple, at          12106485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12107055000
 test master 2 - Starting Memory Read Line Multiple, at          12107265000
 test master 2 - Starting Memory Read Line Multiple, at          12107475000
 test master 2 - Starting Memory Read Line Multiple, at          12107685000
 test master 2 - Starting Memory Read Line Multiple, at          12107985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12108555000
 test master 2 - Starting Memory Read Line Multiple, at          12108765000
 test master 2 - Starting Memory Read Line Multiple, at          12108975000
 test master 2 - Starting Memory Read Line Multiple, at          12109185000
 test master 2 - Starting Memory Read Line Multiple, at          12109485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12110055000
 test master 2 - Starting Memory Read Line Multiple, at          12110265000
 test master 2 - Starting Memory Read Line Multiple, at          12110475000
 test master 2 - Starting Memory Read Line Multiple, at          12110685000
 test master 2 - Starting Memory Read Line Multiple, at          12110985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12111555000
 test master 2 - Starting Memory Read Line Multiple, at          12111765000
 test master 2 - Starting Memory Read Line Multiple, at          12111975000
 test master 2 - Starting Memory Read Line Multiple, at          12112185000
 test master 2 - Starting Memory Read Line Multiple, at          12112485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12113055000
 test master 2 - Starting Memory Read Line Multiple, at          12113265000
 test master 2 - Starting Memory Read Line Multiple, at          12113475000
 test master 2 - Starting Memory Read Line Multiple, at          12113685000
 test master 2 - Starting Memory Read Line Multiple, at          12113985000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          12114555000
 test master 2 - Starting Memory Read Line, at          12114765000
 test master 2 - Starting Memory Read Line, at          12114975000
 test master 2 - Starting Memory Read Line, at          12115245000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          12115635000
 test master 2 - Starting Memory Read Line, at          12115845000
 test master 2 - Starting Memory Read Line, at          12116295000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12117435000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12119055000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12121995000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12123915000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          12128805000
 test master 2 - Starting Memory Write, at          12129135000
 test master 2 - Starting Memory Write, at          12129465000
 test master 2 - Starting Memory Write, at          12129795000
 test master 2 - Starting Memory Write, at          12130125000
 test master 1 - Starting Memory Read, at          12130575000
 test master 1 - Starting Memory Read, at          12130965000
 test master 1 - Starting Memory Read, at          12131505000
 test master 1 - Starting Memory Read, at          12131895000
 test master 1 - Starting Memory Read, at          12132435000
 test master 1 - Starting Memory Read, at          12132825000
 test master 2 - Starting Memory Write, at          12134115000
 test master 2 - Starting Memory Write, at          12134445000
 test master 2 - Starting Memory Write, at          12134775000
 test master 2 - Starting Memory Write, at          12135105000
 test master 2 - Starting Memory Write, at          12135435000
 test master 1 - Starting Memory Read, at          12135885000
 test master 1 - Starting Memory Read, at          12136275000
 test master 1 - Starting Memory Read, at          12136815000
 test master 1 - Starting Memory Read, at          12137205000
 test master 1 - Starting Memory Read, at          12137745000
 test master 1 - Starting Memory Read, at          12138135000
 test master 2 - Starting Memory Write, at          12139935000
 test master 2 - Starting Memory Write, at          12141135000
 test master 2 - Starting Memory Write, at          12142335000
 test master 2 - Starting Memory Write, at          12143535000
 test master 2 - Starting Memory Write, at          12145875000
 test master 2 - Starting Memory Write, at          12147075000
 test master 2 - Starting Memory Write, at          12148275000
 test master 2 - Starting Memory Write, at          12149475000
 test master 2 - Starting Memory Write, at          12151815000
 test master 2 - Starting Memory Write, at          12154035000
 test master 2 - Starting Memory Write, at          12156255000
 test master 2 - Starting Memory Write, at          12158475000
 test master 2 - Starting Memory Write, at          12161835000
 test master 2 - Starting Memory Write, at          12164295000
 test master 2 - Starting Memory Write, at          12166755000
 test master 2 - Starting Memory Write, at          12169215000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          12173805000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12173835000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12175935000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          12176265000
 test master 2 - Starting Memory Read, at          12176475000
 test master 2 - Starting Memory Read, at          12176685000
 test master 2 - Starting Memory Read, at          12176925000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12178455000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          12178935000
 test master 2 - Starting Memory Read, at          12179145000
 test master 2 - Starting Memory Read, at          12179595000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12180975000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12181575000
 test master 2 - Starting Memory Read Line Multiple, at          12181785000
 test master 2 - Starting Memory Read Line Multiple, at          12181995000
 test master 2 - Starting Memory Read Line Multiple, at          12182205000
 test master 2 - Starting Memory Read Line Multiple, at          12182475000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12184155000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12193035000
 test master 2 - Starting Memory Read Line Multiple, at          12193245000
 test master 2 - Starting Memory Read Line Multiple, at          12193455000
 test master 2 - Starting Memory Read Line Multiple, at          12193665000
 test master 2 - Starting Memory Read Line Multiple, at          12193965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12194535000
 test master 2 - Starting Memory Read Line Multiple, at          12194745000
 test master 2 - Starting Memory Read Line Multiple, at          12194955000
 test master 2 - Starting Memory Read Line Multiple, at          12195165000
 test master 2 - Starting Memory Read Line Multiple, at          12195465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12196035000
 test master 2 - Starting Memory Read Line Multiple, at          12196245000
 test master 2 - Starting Memory Read Line Multiple, at          12196455000
 test master 2 - Starting Memory Read Line Multiple, at          12196665000
 test master 2 - Starting Memory Read Line Multiple, at          12196965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12197535000
 test master 2 - Starting Memory Read Line Multiple, at          12197745000
 test master 2 - Starting Memory Read Line Multiple, at          12197955000
 test master 2 - Starting Memory Read Line Multiple, at          12198165000
 test master 2 - Starting Memory Read Line Multiple, at          12198465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12199035000
 test master 2 - Starting Memory Read Line Multiple, at          12199245000
 test master 2 - Starting Memory Read Line Multiple, at          12199455000
 test master 2 - Starting Memory Read Line Multiple, at          12199665000
 test master 2 - Starting Memory Read Line Multiple, at          12199965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12200535000
 test master 2 - Starting Memory Read Line Multiple, at          12200745000
 test master 2 - Starting Memory Read Line Multiple, at          12200955000
 test master 2 - Starting Memory Read Line Multiple, at          12201165000
 test master 2 - Starting Memory Read Line Multiple, at          12201465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12202035000
 test master 2 - Starting Memory Read Line Multiple, at          12202245000
 test master 2 - Starting Memory Read Line Multiple, at          12202455000
 test master 2 - Starting Memory Read Line Multiple, at          12202665000
 test master 2 - Starting Memory Read Line Multiple, at          12202965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12203535000
 test master 2 - Starting Memory Read Line Multiple, at          12203745000
 test master 2 - Starting Memory Read Line Multiple, at          12203955000
 test master 2 - Starting Memory Read Line Multiple, at          12204165000
 test master 2 - Starting Memory Read Line Multiple, at          12204465000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          12205035000
 test master 2 - Starting Memory Read Line, at          12205245000
 test master 2 - Starting Memory Read Line, at          12205455000
 test master 2 - Starting Memory Read Line, at          12205725000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          12206115000
 test master 2 - Starting Memory Read Line, at          12206325000
 test master 2 - Starting Memory Read Line, at          12206775000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12207915000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12209535000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12212475000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12214395000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          12219285000
 test master 2 - Starting Memory Write, at          12219615000
 test master 2 - Starting Memory Write, at          12219945000
 test master 2 - Starting Memory Write, at          12220275000
 test master 2 - Starting Memory Write, at          12220605000
 test master 1 - Starting Memory Read, at          12221055000
 test master 1 - Starting Memory Read, at          12221445000
 test master 1 - Starting Memory Read, at          12221985000
 test master 1 - Starting Memory Read, at          12222375000
 test master 1 - Starting Memory Read, at          12222915000
 test master 1 - Starting Memory Read, at          12223305000
 test master 2 - Starting Memory Write, at          12224595000
 test master 2 - Starting Memory Write, at          12224925000
 test master 2 - Starting Memory Write, at          12225255000
 test master 2 - Starting Memory Write, at          12225585000
 test master 2 - Starting Memory Write, at          12225915000
 test master 1 - Starting Memory Read, at          12226365000
 test master 1 - Starting Memory Read, at          12226755000
 test master 1 - Starting Memory Read, at          12227295000
 test master 1 - Starting Memory Read, at          12227685000
 test master 1 - Starting Memory Read, at          12228225000
 test master 1 - Starting Memory Read, at          12228615000
 test master 2 - Starting Memory Write, at          12230415000
 test master 2 - Starting Memory Write, at          12231615000
 test master 2 - Starting Memory Write, at          12232815000
 test master 2 - Starting Memory Write, at          12234015000
 test master 2 - Starting Memory Write, at          12236355000
 test master 2 - Starting Memory Write, at          12237555000
 test master 2 - Starting Memory Write, at          12238755000
 test master 2 - Starting Memory Write, at          12239955000
 test master 2 - Starting Memory Write, at          12242295000
 test master 2 - Starting Memory Write, at          12244515000
 test master 2 - Starting Memory Write, at          12246735000
 test master 2 - Starting Memory Write, at          12248955000
 test master 2 - Starting Memory Write, at          12252315000
 test master 2 - Starting Memory Write, at          12254775000
 test master 2 - Starting Memory Write, at          12257235000
 test master 2 - Starting Memory Write, at          12259695000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          12264285000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12264315000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12266415000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          12266745000
 test master 2 - Starting Memory Read, at          12266955000
 test master 2 - Starting Memory Read, at          12267165000
 test master 2 - Starting Memory Read, at          12267405000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12268935000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          12269415000
 test master 2 - Starting Memory Read, at          12269625000
 test master 2 - Starting Memory Read, at          12270075000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12271455000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12272055000
 test master 2 - Starting Memory Read Line Multiple, at          12272265000
 test master 2 - Starting Memory Read Line Multiple, at          12272475000
 test master 2 - Starting Memory Read Line Multiple, at          12272685000
 test master 2 - Starting Memory Read Line Multiple, at          12272955000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12274635000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12283515000
 test master 2 - Starting Memory Read Line Multiple, at          12283725000
 test master 2 - Starting Memory Read Line Multiple, at          12283935000
 test master 2 - Starting Memory Read Line Multiple, at          12284145000
 test master 2 - Starting Memory Read Line Multiple, at          12284445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12285015000
 test master 2 - Starting Memory Read Line Multiple, at          12285225000
 test master 2 - Starting Memory Read Line Multiple, at          12285435000
 test master 2 - Starting Memory Read Line Multiple, at          12285645000
 test master 2 - Starting Memory Read Line Multiple, at          12285945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12286515000
 test master 2 - Starting Memory Read Line Multiple, at          12286725000
 test master 2 - Starting Memory Read Line Multiple, at          12286935000
 test master 2 - Starting Memory Read Line Multiple, at          12287145000
 test master 2 - Starting Memory Read Line Multiple, at          12287445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12288015000
 test master 2 - Starting Memory Read Line Multiple, at          12288225000
 test master 2 - Starting Memory Read Line Multiple, at          12288435000
 test master 2 - Starting Memory Read Line Multiple, at          12288645000
 test master 2 - Starting Memory Read Line Multiple, at          12288945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12289515000
 test master 2 - Starting Memory Read Line Multiple, at          12289725000
 test master 2 - Starting Memory Read Line Multiple, at          12289935000
 test master 2 - Starting Memory Read Line Multiple, at          12290145000
 test master 2 - Starting Memory Read Line Multiple, at          12290445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12291015000
 test master 2 - Starting Memory Read Line Multiple, at          12291225000
 test master 2 - Starting Memory Read Line Multiple, at          12291435000
 test master 2 - Starting Memory Read Line Multiple, at          12291645000
 test master 2 - Starting Memory Read Line Multiple, at          12291945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12292515000
 test master 2 - Starting Memory Read Line Multiple, at          12292725000
 test master 2 - Starting Memory Read Line Multiple, at          12292935000
 test master 2 - Starting Memory Read Line Multiple, at          12293145000
 test master 2 - Starting Memory Read Line Multiple, at          12293445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12294015000
 test master 2 - Starting Memory Read Line Multiple, at          12294225000
 test master 2 - Starting Memory Read Line Multiple, at          12294435000
 test master 2 - Starting Memory Read Line Multiple, at          12294645000
 test master 2 - Starting Memory Read Line Multiple, at          12294945000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          12295515000
 test master 2 - Starting Memory Read Line, at          12295725000
 test master 2 - Starting Memory Read Line, at          12295935000
 test master 2 - Starting Memory Read Line, at          12296205000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          12296595000
 test master 2 - Starting Memory Read Line, at          12296805000
 test master 2 - Starting Memory Read Line, at          12297255000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12298395000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12300015000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12302955000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12304875000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          12309765000
 test master 2 - Starting Memory Write, at          12310095000
 test master 2 - Starting Memory Write, at          12310425000
 test master 2 - Starting Memory Write, at          12310755000
 test master 2 - Starting Memory Write, at          12311085000
 test master 1 - Starting Memory Read, at          12311535000
 test master 1 - Starting Memory Read, at          12311925000
 test master 1 - Starting Memory Read, at          12312465000
 test master 1 - Starting Memory Read, at          12312855000
 test master 1 - Starting Memory Read, at          12313395000
 test master 1 - Starting Memory Read, at          12313785000
 test master 2 - Starting Memory Write, at          12315075000
 test master 2 - Starting Memory Write, at          12315405000
 test master 2 - Starting Memory Write, at          12315735000
 test master 2 - Starting Memory Write, at          12316065000
 test master 2 - Starting Memory Write, at          12316395000
 test master 1 - Starting Memory Read, at          12316845000
 test master 1 - Starting Memory Read, at          12317235000
 test master 1 - Starting Memory Read, at          12317775000
 test master 1 - Starting Memory Read, at          12318165000
 test master 1 - Starting Memory Read, at          12318705000
 test master 1 - Starting Memory Read, at          12319095000
 test master 2 - Starting Memory Write, at          12320895000
 test master 2 - Starting Memory Write, at          12322095000
 test master 2 - Starting Memory Write, at          12323295000
 test master 2 - Starting Memory Write, at          12324495000
 test master 2 - Starting Memory Write, at          12326835000
 test master 2 - Starting Memory Write, at          12328035000
 test master 2 - Starting Memory Write, at          12329235000
 test master 2 - Starting Memory Write, at          12330435000
 test master 2 - Starting Memory Write, at          12332775000
 test master 2 - Starting Memory Write, at          12334995000
 test master 2 - Starting Memory Write, at          12337215000
 test master 2 - Starting Memory Write, at          12339435000
 test master 2 - Starting Memory Write, at          12342795000
 test master 2 - Starting Memory Write, at          12345255000
 test master 2 - Starting Memory Write, at          12347715000
 test master 2 - Starting Memory Write, at          12350175000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          12354765000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12354795000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12356895000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          12357225000
 test master 2 - Starting Memory Read, at          12357435000
 test master 2 - Starting Memory Read, at          12357645000
 test master 2 - Starting Memory Read, at          12357885000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12359415000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          12359895000
 test master 2 - Starting Memory Read, at          12360105000
 test master 2 - Starting Memory Read, at          12360555000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12361935000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12362535000
 test master 2 - Starting Memory Read Line Multiple, at          12362745000
 test master 2 - Starting Memory Read Line Multiple, at          12362955000
 test master 2 - Starting Memory Read Line Multiple, at          12363165000
 test master 2 - Starting Memory Read Line Multiple, at          12363435000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12365115000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12373995000
 test master 2 - Starting Memory Read Line Multiple, at          12374205000
 test master 2 - Starting Memory Read Line Multiple, at          12374415000
 test master 2 - Starting Memory Read Line Multiple, at          12374625000
 test master 2 - Starting Memory Read Line Multiple, at          12374925000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12375495000
 test master 2 - Starting Memory Read Line Multiple, at          12375705000
 test master 2 - Starting Memory Read Line Multiple, at          12375915000
 test master 2 - Starting Memory Read Line Multiple, at          12376125000
 test master 2 - Starting Memory Read Line Multiple, at          12376425000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12376995000
 test master 2 - Starting Memory Read Line Multiple, at          12377205000
 test master 2 - Starting Memory Read Line Multiple, at          12377415000
 test master 2 - Starting Memory Read Line Multiple, at          12377625000
 test master 2 - Starting Memory Read Line Multiple, at          12377925000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12378495000
 test master 2 - Starting Memory Read Line Multiple, at          12378705000
 test master 2 - Starting Memory Read Line Multiple, at          12378915000
 test master 2 - Starting Memory Read Line Multiple, at          12379125000
 test master 2 - Starting Memory Read Line Multiple, at          12379425000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12379995000
 test master 2 - Starting Memory Read Line Multiple, at          12380205000
 test master 2 - Starting Memory Read Line Multiple, at          12380415000
 test master 2 - Starting Memory Read Line Multiple, at          12380625000
 test master 2 - Starting Memory Read Line Multiple, at          12380925000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12381495000
 test master 2 - Starting Memory Read Line Multiple, at          12381705000
 test master 2 - Starting Memory Read Line Multiple, at          12381915000
 test master 2 - Starting Memory Read Line Multiple, at          12382125000
 test master 2 - Starting Memory Read Line Multiple, at          12382425000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12382995000
 test master 2 - Starting Memory Read Line Multiple, at          12383205000
 test master 2 - Starting Memory Read Line Multiple, at          12383415000
 test master 2 - Starting Memory Read Line Multiple, at          12383625000
 test master 2 - Starting Memory Read Line Multiple, at          12383925000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          12384495000
 test master 2 - Starting Memory Read Line Multiple, at          12384705000
 test master 2 - Starting Memory Read Line Multiple, at          12384915000
 test master 2 - Starting Memory Read Line Multiple, at          12385125000
 test master 2 - Starting Memory Read Line Multiple, at          12385425000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          12385995000
 test master 2 - Starting Memory Read Line, at          12386205000
 test master 2 - Starting Memory Read Line, at          12386415000
 test master 2 - Starting Memory Read Line, at          12386685000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          12387075000
 test master 2 - Starting Memory Read Line, at          12387285000
 test master 2 - Starting Memory Read Line, at          12387735000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12388875000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12390495000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12393435000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          12395355000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          12400245000
 test master 2 - Starting Memory Write, at          12400575000
 test master 2 - Starting Memory Write, at          12400905000
 test master 2 - Starting Memory Write, at          12401235000
 test master 2 - Starting Memory Write, at          12401565000
 test master 1 - Starting Memory Read, at          12402015000
 test master 1 - Starting Memory Read, at          12402405000
 test master 1 - Starting Memory Read, at          12402945000
 test master 1 - Starting Memory Read, at          12403335000
 test master 1 - Starting Memory Read, at          12403875000
 test master 1 - Starting Memory Read, at          12404265000
 test master 2 - Starting Memory Write, at          12405555000
 test master 2 - Starting Memory Write, at          12405885000
 test master 2 - Starting Memory Write, at          12406215000
 test master 2 - Starting Memory Write, at          12406545000
 test master 2 - Starting Memory Write, at          12406875000
 test master 1 - Starting Memory Read, at          12407325000
 test master 1 - Starting Memory Read, at          12407715000
 test master 1 - Starting Memory Read, at          12408255000
 test master 1 - Starting Memory Read, at          12408645000
 test master 1 - Starting Memory Read, at          12409185000
 test master 1 - Starting Memory Read, at          12409575000
 test master 2 - Starting Memory Write, at          12411375000
 test master 2 - Starting Memory Write, at          12412575000
 test master 2 - Starting Memory Write, at          12413775000
 test master 2 - Starting Memory Write, at          12414975000
 test master 2 - Starting Memory Write, at          12417315000
 test master 2 - Starting Memory Write, at          12418515000
 test master 2 - Starting Memory Write, at          12419715000
 test master 2 - Starting Memory Write, at          12420915000
 test master 2 - Starting Memory Write, at          12423255000
 test master 2 - Starting Memory Write, at          12425475000
 test master 2 - Starting Memory Write, at          12427695000
 test master 2 - Starting Memory Write, at          12429915000
 test master 2 - Starting Memory Write, at          12433275000
 test master 2 - Starting Memory Write, at          12435735000
 test master 2 - Starting Memory Write, at          12438195000
 test master 2 - Starting Memory Write, at          12440655000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          12445245000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12445275000
 test master 1 - Starting Memory Read, at          12447375000
 test master 1 - Starting Memory Read, at          12447795000
 test master 1 - Starting Memory Read, at          12449085000
 test master 1 - Starting Memory Read, at          12449505000
 test master 1 - Starting Memory Read Line, at          12450765000
 test master 1 - Starting Memory Read Line, at          12451185000
 test master 1 - Starting Memory Read Line, at          12452445000
 test master 1 - Starting Memory Read Line, at          12452925000
 test master 1 - Starting Memory Read Line, at          12454245000
 test master 1 - Starting Memory Read Line, at          12454905000
 test master 1 - Starting Memory Read Line, at          12456345000
 test master 1 - Starting Memory Read Line, at          12457005000
 test master 1 - Starting Memory Read Line Multiple, at          12458445000
 test master 1 - Starting Memory Read Line Multiple, at          12459345000
 test master 1 - Starting Memory Read Line Multiple, at          12460965000
 test master 1 - Starting Memory Read Line Multiple, at          12461865000
 test master 1 - Starting Memory Read Line, at          12463485000
 test master 1 - Starting Memory Read Line, at          12464145000
 test master 1 - Starting Memory Read, at          12466575000
 test master 1 - Starting Memory Read, at          12466995000
 test target 1 - Starting Config Write, at          12470265000
 test master 1 - Starting Memory Write, at          12471045000
 test master 1 - Starting Memory Write, at          12474855000
 test master 1 - Starting Memory Write, at          12479895000
 test master 1 - Starting Memory Write, at          12483465000
 test master 1 - Starting Memory Write, at          12488415000
 test master 1 - Starting Memory Read Line, at          12492225000
 test master 1 - Starting Memory Write, at          12497685000
 test master 1 - Starting Memory Read Line, at          12501495000
 test target 1 - Starting Config Write, at          12508545000
 test master 1 - Starting Memory Write, at          12509325000
 test master 1 - Starting Memory Write, at          12509475000
 test master 1 - Starting Memory Write, at          12509805000
 test master 1 - Starting Memory Read, at          12509955000
 test master 1 - Starting Memory Write, at          12510375000
 test master 1 - Starting Memory Read, at          12510525000
 test master 1 - Starting Memory Write, at          12512175000
 test master 1 - Starting Memory Write, at          12521055000
 test master 2 - Starting Memory Read Line, at          12530055000
 test master 2 - Starting Memory Read Line, at          12530685000
 test master 2 - Starting Memory Read Line, at          12531105000
 test master 2 - Starting Memory Read Line, at          12531735000
 test master 1 - Starting Memory Write, at          12532245000
 test master 1 - Starting Memory Write, at          12532575000
 test master 1 - Starting Memory Write, at          12532905000
 test master 2 - Starting Memory Read Line, at          12533355000
 test master 2 - Starting Memory Read Line, at          12533775000
 test master 2 - Starting Memory Read Line, at          12534045000
 test master 2 - Starting Memory Read Line, at          12534465000
 test master 2 - Starting Memory Read Line Multiple, at          12534765000
 test master 2 - Starting Memory Read Line Multiple, at          12535185000
 test master 1 - Starting Memory Write, at          12537075000
 test master 1 - Starting Memory Write, at          12537405000
 test master 2 - Starting Memory Read, at          12537855000
 test master 2 - Starting Memory Read, at          12538275000
 test master 2 - Starting Memory Read, at          12538545000
 test master 2 - Starting Memory Read, at          12538965000
 test master 1 - Starting Memory Write, at          12540615000
 test master 1 - Starting Memory Read, at          12540825000
 test master 1 - Starting Memory Write, at          12541035000
 test master 1 - Starting Memory Read, at          12541245000
 test master 1 - Starting Memory Write, at          12541455000
 test master 1 - Starting Memory Read, at          12541665000
 test master 1 - Starting Memory Read, at          12541875000
 test master 1 - Starting Memory Write, at          12542085000
 test master 1 - Starting Memory Write, at          12542295000
 test master 1 - Starting Memory Read, at          12542505000
 test master 1 - Starting Memory Write, at          12542715000
 test master 1 - Starting Memory Write, at          12542925000
 test master 1 - Starting Memory Write, at          12543135000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          12547545000
 test target 1 - Starting Memory Write, at          12547845000
 test master 1 - Starting Memory Write, at          12548115000
 test target 1 - Starting Memory Write, at          12548325000
 test target 1 - Starting Memory Write, at          12548625000
 test target 1 - Starting Memory Write, at          12548925000
 test master 1 - Starting Memory Write, at          12549315000
 test target 1 - Starting Memory Write, at          12549915000
 test target 1 - Starting Memory Write, at          12550665000
 test target 1 - Starting Memory Write, at          12550995000
 test master 1 - Starting Memory Write, at          12551295000
 test target 1 - Starting Memory Write, at          12551625000
 test target 1 - Starting Memory Write, at          12551955000
 test target 1 - Starting Memory Write, at          12552285000
 test master 1 - Starting Memory Write, at          12552795000
 test target 1 - Starting Memory Write, at          12553665000
 test target 1 - Starting Memory Write, at          12554625000
 test target 1 - Starting Memory Write, at          12554925000
 test master 1 - Starting Memory Read, at          12555195000
 test target 1 - Starting Memory Write, at          12555405000
 test master 1 - Starting Memory Read, at          12555675000
 test target 1 - Starting Memory Write, at          12555885000
 test master 1 - Starting Memory Read, at          12556155000
 test target 1 - Starting Memory Write, at          12556365000
 test master 1 - Starting Memory Read, at          12556635000
 test target 1 - Starting Memory Write, at          12556845000
 test master 1 - Starting Memory Read, at          12557115000
 test target 1 - Starting Memory Write, at          12557325000
 test master 1 - Starting Memory Write, at          12557595000
 test target 1 - Starting Memory Write, at          12557805000
 test target 1 - Starting Memory Write, at          12558105000
 test target 1 - Starting Memory Write, at          12558405000
 test target 1 - Starting Memory Read, at          12558765000
 test master 1 - Starting Memory Write, at          12559155000
 test master 1 - Starting Memory Read, at          12559395000
 test target 1 - Starting Memory Write, at          12559935000
 test master 1 - Starting Memory Write, at          12560415000
 test target 1 - Starting Memory Read, at          12560865000
 test target 1 - Starting Memory Write, at          12561735000
 test master 1 - Starting Memory Read, at          12562125000
 test master 1 - Starting Memory Write, at          12562545000
 test master 1 - Starting Memory Write, at          12562935000
 test master 1 - Starting Memory Read, at          12563265000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          12565905000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          12567015000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          12593085000
 test target 1 - Starting Config Write, at          12594195000
 test target 1 - Starting Config Write, at          12595305000
 test target 2 - Starting Config Write, at          12596385000
 test target 2 - Starting Config Write, at          12597495000
 test target 2 - Starting Config Write, at          12598605000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          12600795000
 test target 1 - Starting Memory Read, at          12601065000
 test target 1 - Starting Memory Write, at          12601785000
 test target 1 - Starting Memory Read, at          12602055000
 test target 1 - Starting Memory Write, at          12603405000
 test target 1 - Starting Memory Read, at          12604215000
 test target 1 - Starting Memory Read, at          12604935000
 test target 1 - Starting Memory Read, at          12605625000
 test target 1 - Starting Memory Read, at          12606315000
 test target 1 - Starting Memory Read, at          12607245000
 test target 1 - Starting Memory Read, at          12608295000
 test target 1 - Starting Memory Read, at          12609345000
 test target 1 - Starting Memory Read, at          12610395000
 test target 1 - Starting Memory Read, at          12611445000
 test target 1 - Starting Memory Read, at          12612885000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          12619995000
 test target 1 - Starting Memory Read, at          12620265000
 test target 1 - Starting Memory Write, at          12620985000
 test target 1 - Starting Memory Read, at          12621255000
 test target 1 - Starting Memory Write, at          12622605000
 test target 1 - Starting Memory Read, at          12623415000
 test target 1 - Starting Memory Read, at          12624135000
 test target 1 - Starting Memory Read, at          12624825000
 test target 1 - Starting Memory Read, at          12625515000
 test target 1 - Starting Memory Read, at          12626445000
 test target 1 - Starting Memory Read, at          12627495000
 test target 1 - Starting Memory Read, at          12628545000
 test target 1 - Starting Memory Read, at          12629595000
 test target 1 - Starting Memory Read, at          12630645000
 test target 1 - Starting Memory Read, at          12632085000
 test target 1 - Starting Memory Write, at          12639195000
 test target 1 - Starting Memory Read, at          12639465000
 test target 1 - Starting Memory Write, at          12640185000
 test target 1 - Starting Memory Read, at          12640455000
 test target 1 - Starting Memory Write, at          12641805000
 test target 1 - Starting Memory Read, at          12642615000
 test target 1 - Starting Memory Read, at          12643335000
 test target 1 - Starting Memory Read, at          12644025000
 test target 1 - Starting Memory Read, at          12644715000
 test target 1 - Starting Memory Read, at          12645645000
 test target 1 - Starting Memory Read, at          12646695000
 test target 1 - Starting Memory Read, at          12647745000
 test target 1 - Starting Memory Read, at          12648795000
 test target 1 - Starting Memory Read, at          12649845000
 test target 1 - Starting Memory Read, at          12651285000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          12664575000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          12671475000
 test target 1 - Starting Memory Write, at          12672585000
 test target 1 - Starting Memory Read, at          12672915000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          12674205000
 test target 1 - Starting Config Write, at          12676485000
 test target 1 - Starting Memory Read, at          12677295000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          12679035000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          12681435000
 test target 1 - Starting Memory Write, at          12682845000
 test target 1 - Starting Memory Write, at          12683145000
 test target 1 - Starting Memory Read, at          12683415000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          12686055000
 test target 1 - Starting Memory Write, at          12689355000
 test target 1 - Starting Memory Write, at          12689715000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          12693795000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          12696015000
 test target 1 - Starting Memory Read, at          12697425000
 test target 1 - Starting Memory Read, at          12698385000
 test target 1 - Starting Memory Read, at          12700185000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          12706455000
 test target 2 - Starting Config Write, at          12707565000
 test target 1 - Starting Memory Write, at          12708405000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          12708585000
 test target 1 - Starting Memory Write, at          12709635000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          12709815000
 test target 1 - Starting Memory Write, at          12710895000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          12712395000
 test target 1 - Starting Memory Read, at          12714885000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          12715065000
 test target 1 - Starting Memory Read, at          12717435000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          12719445000
 test master 2 - Starting Memory Write, at          12719445000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          12719505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12720435000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12720465000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12720765000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12720795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12721755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12721785000
 test target 1 - Starting Memory Write, at          12723675000
 test master 2 - Starting Memory Write, at          12723675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12725535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12725565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12727335000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12727365000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12729135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12729165000
 test target 1 - Starting Memory Write, at          12731325000
 test master 2 - Starting Memory Write, at          12731325000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          12731385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12733155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12733185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12733485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12733515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12734475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12734505000
 test target 1 - Starting Memory Write, at          12735735000
 test master 2 - Starting Memory Write, at          12735735000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          12738885000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          12740655000
 test master 1 - Starting Memory Read, at          12741045000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          12741225000
 test target 1 - Starting Config Write, at          12743895000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          12746595000
 test target 1 - Starting Memory Write, at          12746805000
 test target 1 - Starting Memory Write, at          12747015000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          12747555000
 test target 1 - Starting Memory Write, at          12747795000
 test target 1 - Starting Memory Write, at          12748035000
 test target 1 - Starting Memory Write, at          12748575000
 test target 1 - Starting Memory Write, at          12748815000
 test target 1 - Starting Memory Write, at          12749355000
 test target 1 - Starting Memory Write, at          12750075000
 test target 1 - Starting Memory Write, at          12750315000
 test target 1 - Starting Memory Write, at          12751035000
 test target 1 - Starting Memory Write, at          12751305000
 test target 1 - Starting Memory Write, at          12751995000
 test target 1 - Starting Memory Write, at          12759885000
 test target 1 - Starting Memory Write, at          12760125000
 test target 1 - Starting Memory Write, at          12760365000
 test target 1 - Starting Memory Write, at          12760635000
 test target 1 - Starting Memory Write, at          12760905000
 test target 1 - Starting Memory Read, at          12762885000
 test target 1 - Starting Memory Read, at          12763935000
 test target 1 - Starting Memory Read, at          12765015000
 test target 1 - Starting Memory Read, at          12766065000
 test target 1 - Starting Memory Read, at          12767115000
 test target 1 - Starting Memory Read, at          12768195000
 test target 1 - Starting Memory Read, at          12769245000
 test target 1 - Starting Memory Read, at          12770295000
 test target 1 - Starting Memory Read, at          12771375000
 test target 1 - Starting Memory Read, at          12772425000
 test target 1 - Starting Memory Read, at          12773475000
 test target 1 - Starting Memory Read, at          12774555000
 test target 1 - Starting Memory Read, at          12775605000
 test target 1 - Starting Memory Read, at          12776655000
 test target 1 - Starting Memory Read, at          12777735000
 test target 1 - Starting Memory Read, at          12778785000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          12779625000
 test target 1 - Starting Memory Read, at          12779835000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          12782415000
 test target 1 - Starting Memory Read, at          12783135000
 test target 1 - Starting Memory Read, at          12783885000
 test target 1 - Starting Memory Read, at          12784635000
 test target 1 - Starting Memory Read, at          12785415000
 test target 1 - Starting Memory Read, at          12786255000
 test target 1 - Starting Memory Read, at          12787305000
 test target 1 - Starting Memory Read, at          12788355000
 test target 1 - Starting Memory Read, at          12789405000
 test target 1 - Starting Memory Read, at          12792075000
 test target 1 - Starting Memory Read, at          12793575000
 test target 1 - Starting Memory Read, at          12794505000
 test target 1 - Starting Memory Read, at          12795435000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          12796995000
 test master 1 - Starting Memory Write, at          12797205000
 test target 1 - Starting Memory Write, at          12797205000
 test target 1 - Starting Memory Write, at          12797415000
 test target 1 - Starting Memory Read, at          12797775000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          12799485000
 test master 1 - Starting Memory Write, at          12799695000
 test target 1 - Starting Memory Write, at          12799695000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          12804825000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          12805935000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          12832005000
 test target 1 - Starting Config Write, at          12833115000
 test target 1 - Starting Config Write, at          12834225000
 test target 2 - Starting Config Write, at          12835305000
 test target 2 - Starting Config Write, at          12836415000
 test target 2 - Starting Config Write, at          12837525000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          12839715000
 test target 1 - Starting Memory Read, at          12840015000
 test target 1 - Starting Memory Write, at          12840705000
 test target 1 - Starting Memory Read, at          12841005000
 test target 1 - Starting Memory Write, at          12842325000
 test target 1 - Starting Memory Read, at          12843165000
 test target 1 - Starting Memory Read, at          12843855000
 test target 1 - Starting Memory Read, at          12844575000
 test target 1 - Starting Memory Read, at          12845265000
 test target 1 - Starting Memory Read, at          12846195000
 test target 1 - Starting Memory Read, at          12847245000
 test target 1 - Starting Memory Read, at          12848295000
 test target 1 - Starting Memory Read, at          12849345000
 test target 1 - Starting Memory Read, at          12850395000
 test target 1 - Starting Memory Read, at          12851865000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          12858975000
 test target 1 - Starting Memory Read, at          12859275000
 test target 1 - Starting Memory Write, at          12859965000
 test target 1 - Starting Memory Read, at          12860265000
 test target 1 - Starting Memory Write, at          12861585000
 test target 1 - Starting Memory Read, at          12862425000
 test target 1 - Starting Memory Read, at          12863115000
 test target 1 - Starting Memory Read, at          12863835000
 test target 1 - Starting Memory Read, at          12864525000
 test target 1 - Starting Memory Read, at          12865455000
 test target 1 - Starting Memory Read, at          12866505000
 test target 1 - Starting Memory Read, at          12867555000
 test target 1 - Starting Memory Read, at          12868605000
 test target 1 - Starting Memory Read, at          12869655000
 test target 1 - Starting Memory Read, at          12871125000
 test target 1 - Starting Memory Write, at          12878235000
 test target 1 - Starting Memory Read, at          12878535000
 test target 1 - Starting Memory Write, at          12879225000
 test target 1 - Starting Memory Read, at          12879525000
 test target 1 - Starting Memory Write, at          12880845000
 test target 1 - Starting Memory Read, at          12881685000
 test target 1 - Starting Memory Read, at          12882375000
 test target 1 - Starting Memory Read, at          12883095000
 test target 1 - Starting Memory Read, at          12883785000
 test target 1 - Starting Memory Read, at          12884715000
 test target 1 - Starting Memory Read, at          12885765000
 test target 1 - Starting Memory Read, at          12886815000
 test target 1 - Starting Memory Read, at          12887865000
 test target 1 - Starting Memory Read, at          12888915000
 test target 1 - Starting Memory Read, at          12890385000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          12903675000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          12910575000
 test target 1 - Starting Memory Write, at          12911685000
 test target 1 - Starting Memory Read, at          12912045000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          12913305000
 test target 1 - Starting Config Write, at          12915585000
 test target 1 - Starting Memory Read, at          12916395000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          12918135000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          12920535000
 test target 1 - Starting Memory Write, at          12921945000
 test target 1 - Starting Memory Write, at          12922275000
 test target 1 - Starting Memory Read, at          12922575000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          12925335000
 test target 1 - Starting Memory Write, at          12928635000
 test target 1 - Starting Memory Write, at          12928995000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          12933135000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          12935355000
 test target 1 - Starting Memory Read, at          12936765000
 test target 1 - Starting Memory Read, at          12937725000
 test target 1 - Starting Memory Read, at          12939525000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          12945795000
 test target 2 - Starting Config Write, at          12946905000
 test target 1 - Starting Memory Write, at          12947745000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          12947955000
 test target 1 - Starting Memory Write, at          12949035000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          12949245000
 test target 1 - Starting Memory Write, at          12950295000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          12951795000
 test target 1 - Starting Memory Read, at          12954285000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          12954495000
 test target 1 - Starting Memory Read, at          12956835000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          12958845000
 test master 2 - Starting Memory Write, at          12958845000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          12958905000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12959835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12959865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12960165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12960195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12961155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12961185000
 test target 1 - Starting Memory Write, at          12963075000
 test master 2 - Starting Memory Write, at          12963075000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12964935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12964965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12966735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12966765000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12968535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12968565000
 test target 1 - Starting Memory Write, at          12970725000
 test master 2 - Starting Memory Write, at          12970725000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          12970785000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12972555000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12972585000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12972885000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12972915000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12973875000
*** monitor - CBE Bus Changed when TRDY Desserted, at          12973905000
 test target 1 - Starting Memory Write, at          12975135000
 test master 2 - Starting Memory Write, at          12975135000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          12978345000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          12980115000
 test master 1 - Starting Memory Read, at          12980505000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          12980685000
 test target 1 - Starting Config Write, at          12983355000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          12986055000
 test target 1 - Starting Memory Write, at          12986295000
 test target 1 - Starting Memory Write, at          12986535000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          12987135000
 test target 1 - Starting Memory Write, at          12987405000
 test target 1 - Starting Memory Write, at          12987675000
 test target 1 - Starting Memory Write, at          12988275000
 test target 1 - Starting Memory Write, at          12988545000
 test target 1 - Starting Memory Write, at          12989115000
 test target 1 - Starting Memory Write, at          12989835000
 test target 1 - Starting Memory Write, at          12990105000
 test target 1 - Starting Memory Write, at          12990855000
 test target 1 - Starting Memory Write, at          12991155000
 test target 1 - Starting Memory Write, at          12991875000
 test target 1 - Starting Memory Write, at          12999795000
 test target 1 - Starting Memory Write, at          13000065000
 test target 1 - Starting Memory Write, at          13000335000
 test target 1 - Starting Memory Write, at          13000635000
 test target 1 - Starting Memory Write, at          13000935000
 test target 1 - Starting Memory Read, at          13002945000
 test target 1 - Starting Memory Read, at          13004055000
 test target 1 - Starting Memory Read, at          13005285000
 test target 1 - Starting Memory Read, at          13006335000
 test target 1 - Starting Memory Read, at          13007415000
 test target 1 - Starting Memory Read, at          13008645000
 test target 1 - Starting Memory Read, at          13009695000
 test target 1 - Starting Memory Read, at          13010775000
 test target 1 - Starting Memory Read, at          13012005000
 test target 1 - Starting Memory Read, at          13013055000
 test target 1 - Starting Memory Read, at          13014135000
 test target 1 - Starting Memory Read, at          13015365000
 test target 1 - Starting Memory Read, at          13016415000
 test target 1 - Starting Memory Read, at          13017495000
 test target 1 - Starting Memory Read, at          13018725000
 test target 1 - Starting Memory Read, at          13019775000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          13020645000
 test target 1 - Starting Memory Read, at          13020885000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          13023405000
 test target 1 - Starting Memory Read, at          13024155000
 test target 1 - Starting Memory Read, at          13024875000
 test target 1 - Starting Memory Read, at          13025625000
 test target 1 - Starting Memory Read, at          13026405000
 test target 1 - Starting Memory Read, at          13027245000
 test target 1 - Starting Memory Read, at          13028295000
 test target 1 - Starting Memory Read, at          13029345000
 test target 1 - Starting Memory Read, at          13030395000
 test target 1 - Starting Memory Read, at          13033215000
 test target 1 - Starting Memory Read, at          13034895000
 test target 1 - Starting Memory Read, at          13035825000
 test target 1 - Starting Memory Read, at          13036755000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          13038315000
 test master 1 - Starting Memory Write, at          13038555000
 test target 1 - Starting Memory Write, at          13038555000
 test target 1 - Starting Memory Write, at          13038795000
 test target 1 - Starting Memory Read, at          13039185000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          13040985000
 test master 1 - Starting Memory Write, at          13041225000
 test target 1 - Starting Memory Write, at          13041225000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          13046385000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          13047615000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          13073805000
 test target 1 - Starting Config Write, at          13074915000
 test target 1 - Starting Config Write, at          13076025000
 test target 2 - Starting Config Write, at          13077105000
 test target 2 - Starting Config Write, at          13078215000
 test target 2 - Starting Config Write, at          13079325000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          13081515000
 test target 1 - Starting Memory Read, at          13081845000
 test target 1 - Starting Memory Write, at          13082715000
 test target 1 - Starting Memory Read, at          13083045000
 test target 1 - Starting Memory Write, at          13084515000
 test target 1 - Starting Memory Read, at          13085385000
 test target 1 - Starting Memory Read, at          13086075000
 test target 1 - Starting Memory Read, at          13086795000
 test target 1 - Starting Memory Read, at          13087485000
 test target 1 - Starting Memory Read, at          13088415000
 test target 1 - Starting Memory Read, at          13089645000
 test target 1 - Starting Memory Read, at          13090695000
 test target 1 - Starting Memory Read, at          13091925000
 test target 1 - Starting Memory Read, at          13092975000
 test target 1 - Starting Memory Read, at          13094445000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          13101555000
 test target 1 - Starting Memory Read, at          13101885000
 test target 1 - Starting Memory Write, at          13102755000
 test target 1 - Starting Memory Read, at          13103085000
 test target 1 - Starting Memory Write, at          13104555000
 test target 1 - Starting Memory Read, at          13105425000
 test target 1 - Starting Memory Read, at          13106115000
 test target 1 - Starting Memory Read, at          13106835000
 test target 1 - Starting Memory Read, at          13107525000
 test target 1 - Starting Memory Read, at          13108455000
 test target 1 - Starting Memory Read, at          13109685000
 test target 1 - Starting Memory Read, at          13110735000
 test target 1 - Starting Memory Read, at          13111965000
 test target 1 - Starting Memory Read, at          13113015000
 test target 1 - Starting Memory Read, at          13114485000
 test target 1 - Starting Memory Write, at          13121595000
 test target 1 - Starting Memory Read, at          13121925000
 test target 1 - Starting Memory Write, at          13122795000
 test target 1 - Starting Memory Read, at          13123125000
 test target 1 - Starting Memory Write, at          13124595000
 test target 1 - Starting Memory Read, at          13125465000
 test target 1 - Starting Memory Read, at          13126155000
 test target 1 - Starting Memory Read, at          13126875000
 test target 1 - Starting Memory Read, at          13127565000
 test target 1 - Starting Memory Read, at          13128495000
 test target 1 - Starting Memory Read, at          13129725000
 test target 1 - Starting Memory Read, at          13130775000
 test target 1 - Starting Memory Read, at          13132005000
 test target 1 - Starting Memory Read, at          13133055000
 test target 1 - Starting Memory Read, at          13134525000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          13147815000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          13154715000
 test target 1 - Starting Memory Write, at          13155825000
 test target 1 - Starting Memory Read, at          13156215000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          13157445000
 test target 1 - Starting Config Write, at          13159725000
 test target 1 - Starting Memory Read, at          13160535000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          13162275000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          13164675000
 test target 1 - Starting Memory Write, at          13166085000
 test target 1 - Starting Memory Write, at          13166445000
 test target 1 - Starting Memory Read, at          13166775000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          13169475000
 test target 1 - Starting Memory Write, at          13172835000
 test target 1 - Starting Memory Write, at          13173225000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          13177395000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          13179615000
 test target 1 - Starting Memory Read, at          13181025000
 test target 1 - Starting Memory Read, at          13182165000
 test target 1 - Starting Memory Read, at          13183965000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          13190415000
 test target 2 - Starting Config Write, at          13191525000
 test target 1 - Starting Memory Write, at          13192365000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          13192605000
 test target 1 - Starting Memory Write, at          13193655000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          13193895000
 test target 1 - Starting Memory Write, at          13194975000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          13196535000
 test target 1 - Starting Memory Read, at          13199025000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          13199265000
 test target 1 - Starting Memory Read, at          13201575000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          13203585000
 test master 2 - Starting Memory Write, at          13203585000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          13203645000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13204635000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13204665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13204965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13204995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13205955000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13205985000
 test target 1 - Starting Memory Write, at          13207875000
 test master 2 - Starting Memory Write, at          13207875000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13209795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13209825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13211595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13211625000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13213395000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13213425000
 test target 1 - Starting Memory Write, at          13215585000
 test master 2 - Starting Memory Write, at          13215585000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          13215645000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13217475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13217505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13217805000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13217835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13218795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13218825000
 test target 1 - Starting Memory Write, at          13220055000
 test master 2 - Starting Memory Write, at          13220055000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          13223265000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          13225035000
 test master 1 - Starting Memory Read, at          13225425000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          13225605000
 test target 1 - Starting Config Write, at          13228275000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          13230975000
 test target 1 - Starting Memory Write, at          13231245000
 test target 1 - Starting Memory Write, at          13231515000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          13232115000
 test target 1 - Starting Memory Write, at          13232415000
 test target 1 - Starting Memory Write, at          13232715000
 test target 1 - Starting Memory Write, at          13233315000
 test target 1 - Starting Memory Write, at          13233615000
 test target 1 - Starting Memory Write, at          13234215000
 test target 1 - Starting Memory Write, at          13234995000
 test target 1 - Starting Memory Write, at          13235295000
 test target 1 - Starting Memory Write, at          13236075000
 test target 1 - Starting Memory Write, at          13236405000
 test target 1 - Starting Memory Write, at          13237155000
 test target 1 - Starting Memory Write, at          13245105000
 test target 1 - Starting Memory Write, at          13245405000
 test target 1 - Starting Memory Write, at          13245705000
 test target 1 - Starting Memory Write, at          13246035000
 test target 1 - Starting Memory Write, at          13246365000
 test target 1 - Starting Memory Read, at          13248405000
 test target 1 - Starting Memory Read, at          13249515000
 test target 1 - Starting Memory Read, at          13250775000
 test target 1 - Starting Memory Read, at          13252005000
 test target 1 - Starting Memory Read, at          13253235000
 test target 1 - Starting Memory Read, at          13254495000
 test target 1 - Starting Memory Read, at          13255725000
 test target 1 - Starting Memory Read, at          13256955000
 test target 1 - Starting Memory Read, at          13258215000
 test target 1 - Starting Memory Read, at          13259445000
 test target 1 - Starting Memory Read, at          13260675000
 test target 1 - Starting Memory Read, at          13261935000
 test target 1 - Starting Memory Read, at          13263165000
 test target 1 - Starting Memory Read, at          13264395000
 test target 1 - Starting Memory Read, at          13265655000
 test target 1 - Starting Memory Read, at          13266885000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          13267905000
 test target 1 - Starting Memory Read, at          13268175000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          13270875000
 test target 1 - Starting Memory Read, at          13271655000
 test target 1 - Starting Memory Read, at          13272375000
 test target 1 - Starting Memory Read, at          13273245000
 test target 1 - Starting Memory Read, at          13274145000
 test target 1 - Starting Memory Read, at          13274955000
 test target 1 - Starting Memory Read, at          13276185000
 test target 1 - Starting Memory Read, at          13277415000
 test target 1 - Starting Memory Read, at          13278465000
 test target 1 - Starting Memory Read, at          13281255000
 test target 1 - Starting Memory Read, at          13282935000
 test target 1 - Starting Memory Read, at          13283865000
 test target 1 - Starting Memory Read, at          13284795000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          13286355000
 test master 1 - Starting Memory Write, at          13286625000
 test target 1 - Starting Memory Write, at          13286625000
 test target 1 - Starting Memory Write, at          13286895000
 test target 1 - Starting Memory Read, at          13287315000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          13289085000
 test master 1 - Starting Memory Write, at          13289355000
 test target 1 - Starting Memory Write, at          13289355000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          13294605000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          13295835000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          13322025000
 test target 1 - Starting Config Write, at          13323135000
 test target 1 - Starting Config Write, at          13324245000
 test target 2 - Starting Config Write, at          13325325000
 test target 2 - Starting Config Write, at          13326435000
 test target 2 - Starting Config Write, at          13327545000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          13329735000
 test target 1 - Starting Memory Read, at          13330095000
 test target 1 - Starting Memory Write, at          13330935000
 test target 1 - Starting Memory Read, at          13331295000
 test target 1 - Starting Memory Write, at          13332735000
 test target 1 - Starting Memory Read, at          13333635000
 test target 1 - Starting Memory Read, at          13334355000
 test target 1 - Starting Memory Read, at          13335045000
 test target 1 - Starting Memory Read, at          13335735000
 test target 1 - Starting Memory Read, at          13336665000
 test target 1 - Starting Memory Read, at          13337895000
 test target 1 - Starting Memory Read, at          13338945000
 test target 1 - Starting Memory Read, at          13340175000
 test target 1 - Starting Memory Read, at          13341225000
 test target 1 - Starting Memory Read, at          13342845000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          13349955000
 test target 1 - Starting Memory Read, at          13350315000
 test target 1 - Starting Memory Write, at          13351155000
 test target 1 - Starting Memory Read, at          13351515000
 test target 1 - Starting Memory Write, at          13352955000
 test target 1 - Starting Memory Read, at          13353855000
 test target 1 - Starting Memory Read, at          13354575000
 test target 1 - Starting Memory Read, at          13355265000
 test target 1 - Starting Memory Read, at          13355955000
 test target 1 - Starting Memory Read, at          13356885000
 test target 1 - Starting Memory Read, at          13358115000
 test target 1 - Starting Memory Read, at          13359165000
 test target 1 - Starting Memory Read, at          13360395000
 test target 1 - Starting Memory Read, at          13361445000
 test target 1 - Starting Memory Read, at          13363065000
 test target 1 - Starting Memory Write, at          13370175000
 test target 1 - Starting Memory Read, at          13370535000
 test target 1 - Starting Memory Write, at          13371375000
 test target 1 - Starting Memory Read, at          13371735000
 test target 1 - Starting Memory Write, at          13373175000
 test target 1 - Starting Memory Read, at          13374075000
 test target 1 - Starting Memory Read, at          13374795000
 test target 1 - Starting Memory Read, at          13375485000
 test target 1 - Starting Memory Read, at          13376175000
 test target 1 - Starting Memory Read, at          13377105000
 test target 1 - Starting Memory Read, at          13378335000
 test target 1 - Starting Memory Read, at          13379385000
 test target 1 - Starting Memory Read, at          13380615000
 test target 1 - Starting Memory Read, at          13381665000
 test target 1 - Starting Memory Read, at          13383285000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          13396575000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          13403475000
 test target 1 - Starting Memory Write, at          13404585000
 test target 1 - Starting Memory Read, at          13405005000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          13406385000
 test target 1 - Starting Config Write, at          13408665000
 test target 1 - Starting Memory Read, at          13409475000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          13411215000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          13413615000
 test target 1 - Starting Memory Write, at          13415025000
 test target 1 - Starting Memory Write, at          13415415000
 test target 1 - Starting Memory Read, at          13415775000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          13418415000
 test target 1 - Starting Memory Write, at          13421775000
 test target 1 - Starting Memory Write, at          13422195000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          13426395000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          13428615000
 test target 1 - Starting Memory Read, at          13430025000
 test target 1 - Starting Memory Read, at          13431165000
 test target 1 - Starting Memory Read, at          13432965000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          13439415000
 test target 2 - Starting Config Write, at          13440525000
 test target 1 - Starting Memory Write, at          13441365000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          13441635000
 test target 1 - Starting Memory Write, at          13442715000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          13442985000
 test target 1 - Starting Memory Write, at          13444035000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          13445595000
 test target 1 - Starting Memory Read, at          13448085000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          13448355000
 test target 1 - Starting Memory Read, at          13450635000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          13452645000
 test master 2 - Starting Memory Write, at          13452645000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          13452705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13453695000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13453725000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13454025000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13454055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13455015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13455045000
 test target 1 - Starting Memory Write, at          13456935000
 test master 2 - Starting Memory Write, at          13456935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13458855000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13458885000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13460655000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13460685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13462455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13462485000
 test target 1 - Starting Memory Write, at          13464645000
 test master 2 - Starting Memory Write, at          13464645000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          13464705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13466535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13466565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13466865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13466895000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13467855000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13467885000
 test target 1 - Starting Memory Write, at          13469115000
 test master 2 - Starting Memory Write, at          13469115000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          13472385000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          13474155000
 test master 1 - Starting Memory Read, at          13474545000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          13474725000
 test target 1 - Starting Config Write, at          13477395000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          13480095000
 test target 1 - Starting Memory Write, at          13480395000
 test target 1 - Starting Memory Write, at          13480695000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          13481355000
 test target 1 - Starting Memory Write, at          13481685000
 test target 1 - Starting Memory Write, at          13482015000
 test target 1 - Starting Memory Write, at          13482675000
 test target 1 - Starting Memory Write, at          13483005000
 test target 1 - Starting Memory Write, at          13483635000
 test target 1 - Starting Memory Write, at          13484415000
 test target 1 - Starting Memory Write, at          13484745000
 test target 1 - Starting Memory Write, at          13485555000
 test target 1 - Starting Memory Write, at          13485915000
 test target 1 - Starting Memory Write, at          13486695000
 test target 1 - Starting Memory Write, at          13494675000
 test target 1 - Starting Memory Write, at          13495005000
 test target 1 - Starting Memory Write, at          13495335000
 test target 1 - Starting Memory Write, at          13495695000
 test target 1 - Starting Memory Write, at          13496055000
 test target 1 - Starting Memory Read, at          13498125000
 test target 1 - Starting Memory Read, at          13499295000
 test target 1 - Starting Memory Read, at          13500525000
 test target 1 - Starting Memory Read, at          13501755000
 test target 1 - Starting Memory Read, at          13503015000
 test target 1 - Starting Memory Read, at          13504245000
 test target 1 - Starting Memory Read, at          13505475000
 test target 1 - Starting Memory Read, at          13506735000
 test target 1 - Starting Memory Read, at          13507965000
 test target 1 - Starting Memory Read, at          13509195000
 test target 1 - Starting Memory Read, at          13510455000
 test target 1 - Starting Memory Read, at          13511685000
 test target 1 - Starting Memory Read, at          13512915000
 test target 1 - Starting Memory Read, at          13514175000
 test target 1 - Starting Memory Read, at          13515405000
 test target 1 - Starting Memory Read, at          13516635000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          13517685000
 test target 1 - Starting Memory Read, at          13517985000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          13520655000
 test target 1 - Starting Memory Read, at          13521465000
 test target 1 - Starting Memory Read, at          13522335000
 test target 1 - Starting Memory Read, at          13523205000
 test target 1 - Starting Memory Read, at          13524105000
 test target 1 - Starting Memory Read, at          13524915000
 test target 1 - Starting Memory Read, at          13526145000
 test target 1 - Starting Memory Read, at          13527375000
 test target 1 - Starting Memory Read, at          13528425000
 test target 1 - Starting Memory Read, at          13531215000
 test target 1 - Starting Memory Read, at          13532895000
 test target 1 - Starting Memory Read, at          13533825000
 test target 1 - Starting Memory Read, at          13534755000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          13536315000
 test master 1 - Starting Memory Write, at          13536615000
 test target 1 - Starting Memory Write, at          13536615000
 test target 1 - Starting Memory Write, at          13536915000
 test target 1 - Starting Memory Read, at          13537365000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          13539225000
 test master 1 - Starting Memory Write, at          13539525000
 test target 1 - Starting Memory Write, at          13539525000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13545225000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          13545495000
 test master 2 - Starting Memory Read, at          13545705000
 test master 2 - Starting Memory Read, at          13545915000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13547415000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          13547715000
 test master 2 - Starting Memory Read, at          13547925000
 test master 2 - Starting Memory Read, at          13548135000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13549575000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13549935000
 test master 2 - Starting Memory Read Line Multiple, at          13550145000
 test master 2 - Starting Memory Read Line Multiple, at          13550415000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13552035000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13555335000
 test master 2 - Starting Memory Read Line Multiple, at          13555545000
 test master 2 - Starting Memory Read Line Multiple, at          13555845000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13556235000
 test master 2 - Starting Memory Read Line Multiple, at          13556445000
 test master 2 - Starting Memory Read Line Multiple, at          13556745000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13557135000
 test master 2 - Starting Memory Read Line Multiple, at          13557345000
 test master 2 - Starting Memory Read Line Multiple, at          13557645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13558035000
 test master 2 - Starting Memory Read Line Multiple, at          13558245000
 test master 2 - Starting Memory Read Line Multiple, at          13558545000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13558935000
 test master 2 - Starting Memory Read Line Multiple, at          13559145000
 test master 2 - Starting Memory Read Line Multiple, at          13559445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13559835000
 test master 2 - Starting Memory Read Line Multiple, at          13560045000
 test master 2 - Starting Memory Read Line Multiple, at          13560345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13560735000
 test master 2 - Starting Memory Read Line Multiple, at          13560945000
 test master 2 - Starting Memory Read Line Multiple, at          13561245000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13561635000
 test master 2 - Starting Memory Read Line Multiple, at          13561845000
 test master 2 - Starting Memory Read Line Multiple, at          13562145000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          13562535000
 test master 2 - Starting Memory Read Line, at          13562745000
 test master 2 - Starting Memory Read Line, at          13562985000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          13563285000
 test master 2 - Starting Memory Read Line, at          13563495000
 test master 2 - Starting Memory Read Line, at          13563705000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13564905000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13566525000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13569525000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13571265000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          13575795000
 test master 2 - Starting Memory Write, at          13576065000
 test master 2 - Starting Memory Write, at          13576335000
 test master 2 - Starting Memory Write, at          13576605000
 test master 2 - Starting Memory Write, at          13576875000
 test master 1 - Starting Memory Read, at          13577265000
 test master 1 - Starting Memory Read, at          13577595000
 test master 1 - Starting Memory Read, at          13578135000
 test master 1 - Starting Memory Read, at          13578465000
 test master 1 - Starting Memory Read, at          13579005000
 test master 1 - Starting Memory Read, at          13579335000
 test master 2 - Starting Memory Write, at          13580655000
 test master 2 - Starting Memory Write, at          13580925000
 test master 2 - Starting Memory Write, at          13581195000
 test master 2 - Starting Memory Write, at          13581465000
 test master 2 - Starting Memory Write, at          13581735000
 test master 1 - Starting Memory Read, at          13582125000
 test master 1 - Starting Memory Read, at          13582455000
 test master 1 - Starting Memory Read, at          13582995000
 test master 1 - Starting Memory Read, at          13583325000
 test master 1 - Starting Memory Read, at          13583865000
 test master 1 - Starting Memory Read, at          13584195000
 test master 2 - Starting Memory Write, at          13586055000
 test master 2 - Starting Memory Write, at          13587225000
 test master 2 - Starting Memory Write, at          13588365000
 test master 2 - Starting Memory Write, at          13589505000
 test master 2 - Starting Memory Write, at          13591875000
 test master 2 - Starting Memory Write, at          13593045000
 test master 2 - Starting Memory Write, at          13594185000
 test master 2 - Starting Memory Write, at          13595325000
 test master 2 - Starting Memory Write, at          13597695000
 test master 2 - Starting Memory Write, at          13599885000
 test master 2 - Starting Memory Write, at          13602045000
 test master 2 - Starting Memory Write, at          13604205000
 test master 2 - Starting Memory Write, at          13607595000
 test master 2 - Starting Memory Write, at          13610055000
 test master 2 - Starting Memory Write, at          13612515000
 test master 2 - Starting Memory Write, at          13614975000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          13619565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13619595000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13621875000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          13622145000
 test master 2 - Starting Memory Read, at          13622355000
 test master 2 - Starting Memory Read, at          13622565000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13624095000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          13624395000
 test master 2 - Starting Memory Read, at          13624605000
 test master 2 - Starting Memory Read, at          13624815000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13626255000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13626615000
 test master 2 - Starting Memory Read Line Multiple, at          13626825000
 test master 2 - Starting Memory Read Line Multiple, at          13627095000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13628715000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13632015000
 test master 2 - Starting Memory Read Line Multiple, at          13632225000
 test master 2 - Starting Memory Read Line Multiple, at          13632525000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13632915000
 test master 2 - Starting Memory Read Line Multiple, at          13633125000
 test master 2 - Starting Memory Read Line Multiple, at          13633425000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13633815000
 test master 2 - Starting Memory Read Line Multiple, at          13634025000
 test master 2 - Starting Memory Read Line Multiple, at          13634325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13634715000
 test master 2 - Starting Memory Read Line Multiple, at          13634925000
 test master 2 - Starting Memory Read Line Multiple, at          13635225000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13635615000
 test master 2 - Starting Memory Read Line Multiple, at          13635825000
 test master 2 - Starting Memory Read Line Multiple, at          13636125000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13636515000
 test master 2 - Starting Memory Read Line Multiple, at          13636725000
 test master 2 - Starting Memory Read Line Multiple, at          13637025000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13637415000
 test master 2 - Starting Memory Read Line Multiple, at          13637625000
 test master 2 - Starting Memory Read Line Multiple, at          13637925000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13638315000
 test master 2 - Starting Memory Read Line Multiple, at          13638525000
 test master 2 - Starting Memory Read Line Multiple, at          13638825000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          13639215000
 test master 2 - Starting Memory Read Line, at          13639425000
 test master 2 - Starting Memory Read Line, at          13639665000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          13639965000
 test master 2 - Starting Memory Read Line, at          13640175000
 test master 2 - Starting Memory Read Line, at          13640385000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13641585000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13643205000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13646205000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13647945000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          13652475000
 test master 2 - Starting Memory Write, at          13652745000
 test master 2 - Starting Memory Write, at          13653015000
 test master 2 - Starting Memory Write, at          13653285000
 test master 2 - Starting Memory Write, at          13653555000
 test master 1 - Starting Memory Read, at          13653945000
 test master 1 - Starting Memory Read, at          13654275000
 test master 1 - Starting Memory Read, at          13654815000
 test master 1 - Starting Memory Read, at          13655145000
 test master 1 - Starting Memory Read, at          13655685000
 test master 1 - Starting Memory Read, at          13656015000
 test master 2 - Starting Memory Write, at          13657335000
 test master 2 - Starting Memory Write, at          13657605000
 test master 2 - Starting Memory Write, at          13657875000
 test master 2 - Starting Memory Write, at          13658145000
 test master 2 - Starting Memory Write, at          13658415000
 test master 1 - Starting Memory Read, at          13658805000
 test master 1 - Starting Memory Read, at          13659135000
 test master 1 - Starting Memory Read, at          13659675000
 test master 1 - Starting Memory Read, at          13660005000
 test master 1 - Starting Memory Read, at          13660545000
 test master 1 - Starting Memory Read, at          13660875000
 test master 2 - Starting Memory Write, at          13662735000
 test master 2 - Starting Memory Write, at          13663905000
 test master 2 - Starting Memory Write, at          13665045000
 test master 2 - Starting Memory Write, at          13666185000
 test master 2 - Starting Memory Write, at          13668555000
 test master 2 - Starting Memory Write, at          13669725000
 test master 2 - Starting Memory Write, at          13670865000
 test master 2 - Starting Memory Write, at          13672005000
 test master 2 - Starting Memory Write, at          13674375000
 test master 2 - Starting Memory Write, at          13676565000
 test master 2 - Starting Memory Write, at          13678725000
 test master 2 - Starting Memory Write, at          13680885000
 test master 2 - Starting Memory Write, at          13684275000
 test master 2 - Starting Memory Write, at          13686735000
 test master 2 - Starting Memory Write, at          13689195000
 test master 2 - Starting Memory Write, at          13691655000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          13696245000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13696275000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13698555000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          13698825000
 test master 2 - Starting Memory Read, at          13699035000
 test master 2 - Starting Memory Read, at          13699245000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13700775000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          13701075000
 test master 2 - Starting Memory Read, at          13701285000
 test master 2 - Starting Memory Read, at          13701495000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13702935000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13703295000
 test master 2 - Starting Memory Read Line Multiple, at          13703505000
 test master 2 - Starting Memory Read Line Multiple, at          13703775000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13705395000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13708695000
 test master 2 - Starting Memory Read Line Multiple, at          13708905000
 test master 2 - Starting Memory Read Line Multiple, at          13709205000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13709595000
 test master 2 - Starting Memory Read Line Multiple, at          13709805000
 test master 2 - Starting Memory Read Line Multiple, at          13710105000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13710495000
 test master 2 - Starting Memory Read Line Multiple, at          13710705000
 test master 2 - Starting Memory Read Line Multiple, at          13711005000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13711395000
 test master 2 - Starting Memory Read Line Multiple, at          13711605000
 test master 2 - Starting Memory Read Line Multiple, at          13711905000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13712295000
 test master 2 - Starting Memory Read Line Multiple, at          13712505000
 test master 2 - Starting Memory Read Line Multiple, at          13712805000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13713195000
 test master 2 - Starting Memory Read Line Multiple, at          13713405000
 test master 2 - Starting Memory Read Line Multiple, at          13713705000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13714095000
 test master 2 - Starting Memory Read Line Multiple, at          13714305000
 test master 2 - Starting Memory Read Line Multiple, at          13714605000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13714995000
 test master 2 - Starting Memory Read Line Multiple, at          13715205000
 test master 2 - Starting Memory Read Line Multiple, at          13715505000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          13715895000
 test master 2 - Starting Memory Read Line, at          13716105000
 test master 2 - Starting Memory Read Line, at          13716345000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          13716645000
 test master 2 - Starting Memory Read Line, at          13716855000
 test master 2 - Starting Memory Read Line, at          13717065000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13718265000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13719885000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13722885000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13724625000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          13729155000
 test master 2 - Starting Memory Write, at          13729425000
 test master 2 - Starting Memory Write, at          13729695000
 test master 2 - Starting Memory Write, at          13729965000
 test master 2 - Starting Memory Write, at          13730235000
 test master 1 - Starting Memory Read, at          13730625000
 test master 1 - Starting Memory Read, at          13730955000
 test master 1 - Starting Memory Read, at          13731495000
 test master 1 - Starting Memory Read, at          13731825000
 test master 1 - Starting Memory Read, at          13732365000
 test master 1 - Starting Memory Read, at          13732695000
 test master 2 - Starting Memory Write, at          13734015000
 test master 2 - Starting Memory Write, at          13734285000
 test master 2 - Starting Memory Write, at          13734555000
 test master 2 - Starting Memory Write, at          13734825000
 test master 2 - Starting Memory Write, at          13735095000
 test master 1 - Starting Memory Read, at          13735485000
 test master 1 - Starting Memory Read, at          13735815000
 test master 1 - Starting Memory Read, at          13736355000
 test master 1 - Starting Memory Read, at          13736685000
 test master 1 - Starting Memory Read, at          13737225000
 test master 1 - Starting Memory Read, at          13737555000
 test master 2 - Starting Memory Write, at          13739415000
 test master 2 - Starting Memory Write, at          13740585000
 test master 2 - Starting Memory Write, at          13741725000
 test master 2 - Starting Memory Write, at          13742865000
 test master 2 - Starting Memory Write, at          13745235000
 test master 2 - Starting Memory Write, at          13746405000
 test master 2 - Starting Memory Write, at          13747545000
 test master 2 - Starting Memory Write, at          13748685000
 test master 2 - Starting Memory Write, at          13751055000
 test master 2 - Starting Memory Write, at          13753245000
 test master 2 - Starting Memory Write, at          13755405000
 test master 2 - Starting Memory Write, at          13757565000
 test master 2 - Starting Memory Write, at          13760955000
 test master 2 - Starting Memory Write, at          13763415000
 test master 2 - Starting Memory Write, at          13765875000
 test master 2 - Starting Memory Write, at          13768335000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          13772925000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13772955000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13775235000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          13775505000
 test master 2 - Starting Memory Read, at          13775715000
 test master 2 - Starting Memory Read, at          13775925000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13777455000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          13777755000
 test master 2 - Starting Memory Read, at          13777965000
 test master 2 - Starting Memory Read, at          13778175000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13779615000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13779975000
 test master 2 - Starting Memory Read Line Multiple, at          13780185000
 test master 2 - Starting Memory Read Line Multiple, at          13780455000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13782075000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13785375000
 test master 2 - Starting Memory Read Line Multiple, at          13785585000
 test master 2 - Starting Memory Read Line Multiple, at          13785885000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13786275000
 test master 2 - Starting Memory Read Line Multiple, at          13786485000
 test master 2 - Starting Memory Read Line Multiple, at          13786785000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13787175000
 test master 2 - Starting Memory Read Line Multiple, at          13787385000
 test master 2 - Starting Memory Read Line Multiple, at          13787685000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13788075000
 test master 2 - Starting Memory Read Line Multiple, at          13788285000
 test master 2 - Starting Memory Read Line Multiple, at          13788585000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13788975000
 test master 2 - Starting Memory Read Line Multiple, at          13789185000
 test master 2 - Starting Memory Read Line Multiple, at          13789485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13789875000
 test master 2 - Starting Memory Read Line Multiple, at          13790085000
 test master 2 - Starting Memory Read Line Multiple, at          13790385000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13790775000
 test master 2 - Starting Memory Read Line Multiple, at          13790985000
 test master 2 - Starting Memory Read Line Multiple, at          13791285000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          13791675000
 test master 2 - Starting Memory Read Line Multiple, at          13791885000
 test master 2 - Starting Memory Read Line Multiple, at          13792185000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          13792575000
 test master 2 - Starting Memory Read Line, at          13792785000
 test master 2 - Starting Memory Read Line, at          13793025000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          13793325000
 test master 2 - Starting Memory Read Line, at          13793535000
 test master 2 - Starting Memory Read Line, at          13793745000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13794945000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13796565000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13799565000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          13801305000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          13805835000
 test master 2 - Starting Memory Write, at          13806105000
 test master 2 - Starting Memory Write, at          13806375000
 test master 2 - Starting Memory Write, at          13806645000
 test master 2 - Starting Memory Write, at          13806915000
 test master 1 - Starting Memory Read, at          13807305000
 test master 1 - Starting Memory Read, at          13807635000
 test master 1 - Starting Memory Read, at          13808175000
 test master 1 - Starting Memory Read, at          13808505000
 test master 1 - Starting Memory Read, at          13809045000
 test master 1 - Starting Memory Read, at          13809375000
 test master 2 - Starting Memory Write, at          13810695000
 test master 2 - Starting Memory Write, at          13810965000
 test master 2 - Starting Memory Write, at          13811235000
 test master 2 - Starting Memory Write, at          13811505000
 test master 2 - Starting Memory Write, at          13811775000
 test master 1 - Starting Memory Read, at          13812165000
 test master 1 - Starting Memory Read, at          13812495000
 test master 1 - Starting Memory Read, at          13813035000
 test master 1 - Starting Memory Read, at          13813365000
 test master 1 - Starting Memory Read, at          13813905000
 test master 1 - Starting Memory Read, at          13814235000
 test master 2 - Starting Memory Write, at          13816095000
 test master 2 - Starting Memory Write, at          13817265000
 test master 2 - Starting Memory Write, at          13818405000
 test master 2 - Starting Memory Write, at          13819545000
 test master 2 - Starting Memory Write, at          13821915000
 test master 2 - Starting Memory Write, at          13823085000
 test master 2 - Starting Memory Write, at          13824225000
 test master 2 - Starting Memory Write, at          13825365000
 test master 2 - Starting Memory Write, at          13827735000
 test master 2 - Starting Memory Write, at          13829925000
 test master 2 - Starting Memory Write, at          13832085000
 test master 2 - Starting Memory Write, at          13834245000
 test master 2 - Starting Memory Write, at          13837635000
 test master 2 - Starting Memory Write, at          13840095000
 test master 2 - Starting Memory Write, at          13842555000
 test master 2 - Starting Memory Write, at          13845015000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          13849605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          13849635000
 test master 1 - Starting Memory Read, at          13851915000
 test master 1 - Starting Memory Read, at          13852275000
 test master 1 - Starting Memory Read, at          13853595000
 test master 1 - Starting Memory Read, at          13853955000
 test master 1 - Starting Memory Read Line, at          13855275000
 test master 1 - Starting Memory Read Line, at          13855635000
 test master 1 - Starting Memory Read Line, at          13856955000
 test master 1 - Starting Memory Read Line, at          13857345000
 test master 1 - Starting Memory Read Line, at          13858695000
 test master 1 - Starting Memory Read Line, at          13859115000
 test master 1 - Starting Memory Read Line, at          13860495000
 test master 1 - Starting Memory Read Line, at          13860915000
 test master 1 - Starting Memory Read Line Multiple, at          13862355000
 test master 1 - Starting Memory Read Line Multiple, at          13862835000
 test master 1 - Starting Memory Read Line Multiple, at          13864335000
 test master 1 - Starting Memory Read Line Multiple, at          13864815000
 test master 1 - Starting Memory Read Line, at          13866315000
 test master 1 - Starting Memory Read Line, at          13866735000
 test master 1 - Starting Memory Read, at          13869315000
 test master 1 - Starting Memory Read, at          13869675000
 test target 1 - Starting Config Write, at          13873185000
 test master 1 - Starting Memory Write, at          13873845000
 test master 1 - Starting Memory Write, at          13875825000
 test master 1 - Starting Memory Write, at          13877175000
 test master 1 - Starting Memory Write, at          13879035000
 test master 1 - Starting Memory Write, at          13880355000
 test master 1 - Starting Memory Read Line, at          13882335000
 test master 1 - Starting Memory Write, at          13883835000
 test master 1 - Starting Memory Read Line, at          13885815000
 test target 1 - Starting Config Write, at          13889325000
 test master 1 - Starting Memory Write, at          13889985000
 test master 1 - Starting Memory Write, at          13890135000
 test master 1 - Starting Memory Write, at          13890405000
 test master 1 - Starting Memory Read, at          13890555000
 test master 1 - Starting Memory Write, at          13890915000
 test master 1 - Starting Memory Read, at          13891065000
 test master 1 - Starting Memory Write, at          13892865000
 test master 1 - Starting Memory Write, at          13896195000
 test master 2 - Starting Memory Read Line, at          13899615000
 test master 2 - Starting Memory Read Line, at          13900005000
 test master 2 - Starting Memory Read Line, at          13900335000
 test master 2 - Starting Memory Read Line, at          13900725000
 test master 1 - Starting Memory Write, at          13901145000
 test master 1 - Starting Memory Write, at          13901415000
 test master 1 - Starting Memory Write, at          13901685000
 test master 2 - Starting Memory Read Line, at          13902075000
 test master 2 - Starting Memory Read Line, at          13902435000
 test master 2 - Starting Memory Read Line, at          13902675000
 test master 2 - Starting Memory Read Line, at          13903035000
 test master 2 - Starting Memory Read Line Multiple, at          13903305000
 test master 2 - Starting Memory Read Line Multiple, at          13903665000
 test master 1 - Starting Memory Write, at          13905675000
 test master 1 - Starting Memory Write, at          13905945000
 test master 2 - Starting Memory Read, at          13906335000
 test master 2 - Starting Memory Read, at          13906695000
 test master 2 - Starting Memory Read, at          13906935000
 test master 2 - Starting Memory Read, at          13907295000
 test master 1 - Starting Memory Write, at          13909035000
 test master 1 - Starting Memory Read, at          13909245000
 test master 1 - Starting Memory Write, at          13909455000
 test master 1 - Starting Memory Read, at          13909665000
 test master 1 - Starting Memory Write, at          13909875000
 test master 1 - Starting Memory Read, at          13910085000
 test master 1 - Starting Memory Read, at          13910295000
 test master 1 - Starting Memory Write, at          13910505000
 test master 1 - Starting Memory Write, at          13910715000
 test master 1 - Starting Memory Read, at          13910925000
 test master 1 - Starting Memory Write, at          13911135000
 test master 1 - Starting Memory Write, at          13911345000
 test master 1 - Starting Memory Write, at          13911555000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          13916355000
 test target 1 - Starting Memory Write, at          13916655000
 test master 1 - Starting Memory Write, at          13916925000
 test target 1 - Starting Memory Write, at          13917135000
 test target 1 - Starting Memory Write, at          13917435000
 test target 1 - Starting Memory Write, at          13917735000
 test master 1 - Starting Memory Write, at          13918125000
 test target 1 - Starting Memory Write, at          13918665000
 test target 1 - Starting Memory Write, at          13919295000
 test target 1 - Starting Memory Write, at          13919625000
 test master 1 - Starting Memory Write, at          13919925000
 test target 1 - Starting Memory Write, at          13920195000
 test target 1 - Starting Memory Write, at          13920525000
 test target 1 - Starting Memory Write, at          13920855000
 test master 1 - Starting Memory Write, at          13921305000
 test target 1 - Starting Memory Write, at          13922055000
 test target 1 - Starting Memory Write, at          13922715000
 test target 1 - Starting Memory Write, at          13923015000
 test master 1 - Starting Memory Read, at          13923285000
 test target 1 - Starting Memory Write, at          13923495000
 test master 1 - Starting Memory Read, at          13923765000
 test target 1 - Starting Memory Write, at          13923975000
 test master 1 - Starting Memory Read, at          13924245000
 test target 1 - Starting Memory Write, at          13924455000
 test master 1 - Starting Memory Read, at          13924725000
 test target 1 - Starting Memory Write, at          13924935000
 test master 1 - Starting Memory Read, at          13925205000
 test target 1 - Starting Memory Write, at          13925415000
 test master 1 - Starting Memory Write, at          13925685000
 test target 1 - Starting Memory Write, at          13925895000
 test target 1 - Starting Memory Write, at          13926195000
 test target 1 - Starting Memory Write, at          13926495000
 test target 1 - Starting Memory Read, at          13926855000
 test master 1 - Starting Memory Write, at          13927245000
 test master 1 - Starting Memory Read, at          13927515000
 test target 1 - Starting Memory Write, at          13928055000
 test master 1 - Starting Memory Write, at          13928535000
 test target 1 - Starting Memory Read, at          13928985000
 test target 1 - Starting Memory Write, at          13929855000
 test master 1 - Starting Memory Read, at          13930245000
 test master 1 - Starting Memory Write, at          13930605000
 test master 1 - Starting Memory Write, at          13930995000
 test master 1 - Starting Memory Read, at          13931265000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          13933605000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          13934655000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          13958475000
 test target 1 - Starting Config Write, at          13959285000
 test target 1 - Starting Config Write, at          13960065000
 test target 2 - Starting Config Write, at          13960875000
 test target 2 - Starting Config Write, at          13961685000
 test target 2 - Starting Config Write, at          13962465000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          13964115000
 test target 1 - Starting Memory Read, at          13964355000
 test target 1 - Starting Memory Write, at          13964955000
 test target 1 - Starting Memory Read, at          13965195000
 test target 1 - Starting Memory Write, at          13966035000
 test target 1 - Starting Memory Read, at          13967385000
 test target 1 - Starting Memory Read, at          13967925000
 test target 1 - Starting Memory Read, at          13968525000
 test target 1 - Starting Memory Read, at          13969095000
 test target 1 - Starting Memory Read, at          13969875000
 test target 1 - Starting Memory Read, at          13971045000
 test target 1 - Starting Memory Read, at          13971795000
 test target 1 - Starting Memory Read, at          13972965000
 test target 1 - Starting Memory Read, at          13973715000
 test target 1 - Starting Memory Read, at          13976505000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          13982415000
 test target 1 - Starting Memory Read, at          13982655000
 test target 1 - Starting Memory Write, at          13983255000
 test target 1 - Starting Memory Read, at          13983495000
 test target 1 - Starting Memory Write, at          13984335000
 test target 1 - Starting Memory Read, at          13985685000
 test target 1 - Starting Memory Read, at          13986225000
 test target 1 - Starting Memory Read, at          13986825000
 test target 1 - Starting Memory Read, at          13987395000
 test target 1 - Starting Memory Read, at          13988175000
 test target 1 - Starting Memory Read, at          13989345000
 test target 1 - Starting Memory Read, at          13990095000
 test target 1 - Starting Memory Read, at          13991265000
 test target 1 - Starting Memory Read, at          13992015000
 test target 1 - Starting Memory Read, at          13994805000
 test target 1 - Starting Memory Write, at          14000715000
 test target 1 - Starting Memory Read, at          14000955000
 test target 1 - Starting Memory Write, at          14001555000
 test target 1 - Starting Memory Read, at          14001795000
 test target 1 - Starting Memory Write, at          14002635000
 test target 1 - Starting Memory Read, at          14003985000
 test target 1 - Starting Memory Read, at          14004525000
 test target 1 - Starting Memory Read, at          14005125000
 test target 1 - Starting Memory Read, at          14005695000
 test target 1 - Starting Memory Read, at          14006475000
 test target 1 - Starting Memory Read, at          14007645000
 test target 1 - Starting Memory Read, at          14008395000
 test target 1 - Starting Memory Read, at          14009565000
 test target 1 - Starting Memory Read, at          14010315000
 test target 1 - Starting Memory Read, at          14013105000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          14023905000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          14029605000
 test target 1 - Starting Memory Write, at          14030295000
 test target 1 - Starting Memory Read, at          14030835000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          14032125000
 test target 1 - Starting Config Write, at          14033805000
 test target 1 - Starting Memory Read, at          14034405000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          14035725000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          14037705000
 test target 1 - Starting Memory Write, at          14038755000
 test target 1 - Starting Memory Write, at          14039025000
 test target 1 - Starting Memory Read, at          14039265000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          14041365000
 test target 1 - Starting Memory Write, at          14044095000
 test target 1 - Starting Memory Write, at          14044515000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          14048265000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          14050005000
 test target 1 - Starting Memory Read, at          14051295000
 test target 1 - Starting Memory Read, at          14052465000
 test target 1 - Starting Memory Read, at          14054115000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          14059605000
 test target 2 - Starting Config Write, at          14060385000
 test target 1 - Starting Memory Write, at          14061015000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          14061165000
 test target 1 - Starting Memory Write, at          14062095000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          14062245000
 test target 1 - Starting Memory Write, at          14063175000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          14064465000
 test target 1 - Starting Memory Read, at          14066475000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          14066625000
 test target 1 - Starting Memory Read, at          14068485000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          14069985000
 test master 2 - Starting Memory Write, at          14069985000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          14070045000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14070795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14070825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14071125000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14071155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14071995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14072025000
 test target 1 - Starting Memory Write, at          14073675000
 test master 2 - Starting Memory Write, at          14073675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14075235000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14075265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14076795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14076825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14078355000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14078385000
 test target 1 - Starting Memory Write, at          14080245000
 test master 2 - Starting Memory Write, at          14080245000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          14080305000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14081775000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14081805000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14082105000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14082135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14082975000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14083005000
 test target 1 - Starting Memory Write, at          14084115000
 test master 2 - Starting Memory Write, at          14084115000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          14086725000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          14088195000
 test master 1 - Starting Memory Read, at          14088525000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          14088675000
 test target 1 - Starting Config Write, at          14090985000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          14093175000
 test target 1 - Starting Memory Write, at          14093355000
 test target 1 - Starting Memory Write, at          14093535000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          14094015000
 test target 1 - Starting Memory Write, at          14094225000
 test target 1 - Starting Memory Write, at          14094435000
 test target 1 - Starting Memory Write, at          14094915000
 test target 1 - Starting Memory Write, at          14095245000
 test target 1 - Starting Memory Write, at          14095695000
 test target 1 - Starting Memory Write, at          14096355000
 test target 1 - Starting Memory Write, at          14096565000
 test target 1 - Starting Memory Write, at          14097225000
 test target 1 - Starting Memory Write, at          14097585000
 test target 1 - Starting Memory Write, at          14098095000
 test target 1 - Starting Memory Write, at          14101275000
 test target 1 - Starting Memory Write, at          14101485000
 test target 1 - Starting Memory Write, at          14101695000
 test target 1 - Starting Memory Write, at          14102055000
 test target 1 - Starting Memory Write, at          14102415000
 test target 1 - Starting Memory Read, at          14111205000
 test target 1 - Starting Memory Read, at          14112375000
 test target 1 - Starting Memory Read, at          14113575000
 test target 1 - Starting Memory Read, at          14114775000
 test target 1 - Starting Memory Read, at          14115975000
 test target 1 - Starting Memory Read, at          14117175000
 test target 1 - Starting Memory Read, at          14118375000
 test target 1 - Starting Memory Read, at          14119575000
 test target 1 - Starting Memory Read, at          14120775000
 test target 1 - Starting Memory Read, at          14121975000
 test target 1 - Starting Memory Read, at          14123175000
 test target 1 - Starting Memory Read, at          14124375000
 test target 1 - Starting Memory Read, at          14125575000
 test target 1 - Starting Memory Read, at          14126775000
 test target 1 - Starting Memory Read, at          14127975000
 test target 1 - Starting Memory Read, at          14129175000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          14130345000
 test target 1 - Starting Memory Read, at          14130525000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          14131755000
 test target 1 - Starting Memory Read, at          14134245000
 test target 1 - Starting Memory Read, at          14134815000
 test target 1 - Starting Memory Read, at          14135415000
 test target 1 - Starting Memory Read, at          14136225000
 test target 1 - Starting Memory Read, at          14137005000
 test target 1 - Starting Memory Read, at          14138265000
 test target 1 - Starting Memory Read, at          14139435000
 test target 1 - Starting Memory Read, at          14140215000
 test target 1 - Starting Memory Read, at          14143425000
 test target 1 - Starting Memory Read, at          14146575000
 test target 1 - Starting Memory Read, at          14147325000
 test target 1 - Starting Memory Read, at          14148075000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          14149065000
 test master 1 - Starting Memory Write, at          14149515000
 test target 1 - Starting Memory Write, at          14149515000
 test target 1 - Starting Memory Write, at          14149695000
 test target 1 - Starting Memory Read, at          14150235000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          14153145000
 test master 1 - Starting Memory Write, at          14153595000
 test target 1 - Starting Memory Write, at          14153595000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          14158305000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          14159355000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          14183175000
 test target 1 - Starting Config Write, at          14183985000
 test target 1 - Starting Config Write, at          14184765000
 test target 2 - Starting Config Write, at          14185575000
 test target 2 - Starting Config Write, at          14186385000
 test target 2 - Starting Config Write, at          14187165000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          14188815000
 test target 1 - Starting Memory Read, at          14189085000
 test target 1 - Starting Memory Write, at          14189655000
 test target 1 - Starting Memory Read, at          14189925000
 test target 1 - Starting Memory Write, at          14190735000
 test target 1 - Starting Memory Read, at          14192115000
 test target 1 - Starting Memory Read, at          14192745000
 test target 1 - Starting Memory Read, at          14193345000
 test target 1 - Starting Memory Read, at          14193915000
 test target 1 - Starting Memory Read, at          14194695000
 test target 1 - Starting Memory Read, at          14195865000
 test target 1 - Starting Memory Read, at          14196765000
 test target 1 - Starting Memory Read, at          14197935000
 test target 1 - Starting Memory Read, at          14198835000
 test target 1 - Starting Memory Read, at          14201745000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          14207655000
 test target 1 - Starting Memory Read, at          14207925000
 test target 1 - Starting Memory Write, at          14208495000
 test target 1 - Starting Memory Read, at          14208765000
 test target 1 - Starting Memory Write, at          14209575000
 test target 1 - Starting Memory Read, at          14210955000
 test target 1 - Starting Memory Read, at          14211585000
 test target 1 - Starting Memory Read, at          14212185000
 test target 1 - Starting Memory Read, at          14212755000
 test target 1 - Starting Memory Read, at          14213535000
 test target 1 - Starting Memory Read, at          14214705000
 test target 1 - Starting Memory Read, at          14215605000
 test target 1 - Starting Memory Read, at          14216775000
 test target 1 - Starting Memory Read, at          14217675000
 test target 1 - Starting Memory Read, at          14220585000
 test target 1 - Starting Memory Write, at          14226495000
 test target 1 - Starting Memory Read, at          14226765000
 test target 1 - Starting Memory Write, at          14227335000
 test target 1 - Starting Memory Read, at          14227605000
 test target 1 - Starting Memory Write, at          14228415000
 test target 1 - Starting Memory Read, at          14229795000
 test target 1 - Starting Memory Read, at          14230425000
 test target 1 - Starting Memory Read, at          14231025000
 test target 1 - Starting Memory Read, at          14231595000
 test target 1 - Starting Memory Read, at          14232375000
 test target 1 - Starting Memory Read, at          14233545000
 test target 1 - Starting Memory Read, at          14234445000
 test target 1 - Starting Memory Read, at          14235615000
 test target 1 - Starting Memory Read, at          14236515000
 test target 1 - Starting Memory Read, at          14239425000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          14250225000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          14255925000
 test target 1 - Starting Memory Write, at          14256615000
 test target 1 - Starting Memory Read, at          14257185000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          14258565000
 test target 1 - Starting Config Write, at          14260365000
 test target 1 - Starting Memory Read, at          14260965000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          14262285000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          14264265000
 test target 1 - Starting Memory Write, at          14265315000
 test target 1 - Starting Memory Write, at          14265615000
 test target 1 - Starting Memory Read, at          14265885000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          14267925000
 test target 1 - Starting Memory Write, at          14270655000
 test target 1 - Starting Memory Write, at          14271105000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          14274885000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          14276625000
 test target 1 - Starting Memory Read, at          14277915000
 test target 1 - Starting Memory Read, at          14279085000
 test target 1 - Starting Memory Read, at          14280795000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          14286285000
 test target 2 - Starting Config Write, at          14287065000
 test target 1 - Starting Memory Write, at          14287695000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          14287875000
 test target 1 - Starting Memory Write, at          14288835000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          14289015000
 test target 1 - Starting Memory Write, at          14289975000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          14291325000
 test target 1 - Starting Memory Read, at          14293335000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          14293515000
 test target 1 - Starting Memory Read, at          14295465000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          14296965000
 test master 2 - Starting Memory Write, at          14296965000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          14297025000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14297835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14297865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14298165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14298195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14299035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14299065000
 test target 1 - Starting Memory Write, at          14300715000
 test master 2 - Starting Memory Write, at          14300715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14302335000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14302365000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14303895000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14303925000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14305455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14305485000
 test target 1 - Starting Memory Write, at          14307345000
 test master 2 - Starting Memory Write, at          14307345000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          14307405000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14308935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14308965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14309265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14309295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14310135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14310165000
 test target 1 - Starting Memory Write, at          14311275000
 test master 2 - Starting Memory Write, at          14311275000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          14313885000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          14315355000
 test master 1 - Starting Memory Read, at          14315685000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          14315835000
 test target 1 - Starting Config Write, at          14318145000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          14320335000
 test target 1 - Starting Memory Write, at          14320545000
 test target 1 - Starting Memory Write, at          14320755000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          14321235000
 test target 1 - Starting Memory Write, at          14321475000
 test target 1 - Starting Memory Write, at          14321715000
 test target 1 - Starting Memory Write, at          14322195000
 test target 1 - Starting Memory Write, at          14322555000
 test target 1 - Starting Memory Write, at          14323035000
 test target 1 - Starting Memory Write, at          14323725000
 test target 1 - Starting Memory Write, at          14323965000
 test target 1 - Starting Memory Write, at          14324655000
 test target 1 - Starting Memory Write, at          14325045000
 test target 1 - Starting Memory Write, at          14325585000
 test target 1 - Starting Memory Write, at          14328795000
 test target 1 - Starting Memory Write, at          14329035000
 test target 1 - Starting Memory Write, at          14329275000
 test target 1 - Starting Memory Write, at          14329665000
 test target 1 - Starting Memory Write, at          14330055000
 test target 1 - Starting Memory Read, at          14338875000
 test target 1 - Starting Memory Read, at          14340105000
 test target 1 - Starting Memory Read, at          14341305000
 test target 1 - Starting Memory Read, at          14342505000
 test target 1 - Starting Memory Read, at          14343705000
 test target 1 - Starting Memory Read, at          14344905000
 test target 1 - Starting Memory Read, at          14346105000
 test target 1 - Starting Memory Read, at          14347305000
 test target 1 - Starting Memory Read, at          14348505000
 test target 1 - Starting Memory Read, at          14349705000
 test target 1 - Starting Memory Read, at          14350905000
 test target 1 - Starting Memory Read, at          14352105000
 test target 1 - Starting Memory Read, at          14353305000
 test target 1 - Starting Memory Read, at          14354505000
 test target 1 - Starting Memory Read, at          14355705000
 test target 1 - Starting Memory Read, at          14356905000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          14358045000
 test target 1 - Starting Memory Read, at          14358255000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          14359485000
 test target 1 - Starting Memory Read, at          14362005000
 test target 1 - Starting Memory Read, at          14362665000
 test target 1 - Starting Memory Read, at          14363265000
 test target 1 - Starting Memory Read, at          14364075000
 test target 1 - Starting Memory Read, at          14364855000
 test target 1 - Starting Memory Read, at          14366115000
 test target 1 - Starting Memory Read, at          14367285000
 test target 1 - Starting Memory Read, at          14368185000
 test target 1 - Starting Memory Read, at          14371425000
 test target 1 - Starting Memory Read, at          14374545000
 test target 1 - Starting Memory Read, at          14375415000
 test target 1 - Starting Memory Read, at          14376255000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          14377335000
 test master 1 - Starting Memory Write, at          14377665000
 test target 1 - Starting Memory Write, at          14377665000
 test target 1 - Starting Memory Write, at          14377875000
 test target 1 - Starting Memory Read, at          14378595000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          14381595000
 test master 1 - Starting Memory Write, at          14381925000
 test target 1 - Starting Memory Write, at          14381925000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          14386665000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          14387715000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          14411535000
 test target 1 - Starting Config Write, at          14412495000
 test target 1 - Starting Config Write, at          14413455000
 test target 2 - Starting Config Write, at          14414415000
 test target 2 - Starting Config Write, at          14415375000
 test target 2 - Starting Config Write, at          14416335000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          14418135000
 test target 1 - Starting Memory Read, at          14418435000
 test target 1 - Starting Memory Write, at          14419125000
 test target 1 - Starting Memory Read, at          14419425000
 test target 1 - Starting Memory Write, at          14420325000
 test target 1 - Starting Memory Read, at          14421735000
 test target 1 - Starting Memory Read, at          14422365000
 test target 1 - Starting Memory Read, at          14423055000
 test target 1 - Starting Memory Read, at          14423745000
 test target 1 - Starting Memory Read, at          14424615000
 test target 1 - Starting Memory Read, at          14425875000
 test target 1 - Starting Memory Read, at          14426775000
 test target 1 - Starting Memory Read, at          14428035000
 test target 1 - Starting Memory Read, at          14428935000
 test target 1 - Starting Memory Read, at          14431845000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          14437755000
 test target 1 - Starting Memory Read, at          14438055000
 test target 1 - Starting Memory Write, at          14438745000
 test target 1 - Starting Memory Read, at          14439045000
 test target 1 - Starting Memory Write, at          14439945000
 test target 1 - Starting Memory Read, at          14441355000
 test target 1 - Starting Memory Read, at          14441985000
 test target 1 - Starting Memory Read, at          14442675000
 test target 1 - Starting Memory Read, at          14443365000
 test target 1 - Starting Memory Read, at          14444235000
 test target 1 - Starting Memory Read, at          14445495000
 test target 1 - Starting Memory Read, at          14446395000
 test target 1 - Starting Memory Read, at          14447655000
 test target 1 - Starting Memory Read, at          14448555000
 test target 1 - Starting Memory Read, at          14451465000
 test target 1 - Starting Memory Write, at          14457375000
 test target 1 - Starting Memory Read, at          14457675000
 test target 1 - Starting Memory Write, at          14458365000
 test target 1 - Starting Memory Read, at          14458665000
 test target 1 - Starting Memory Write, at          14459565000
 test target 1 - Starting Memory Read, at          14460975000
 test target 1 - Starting Memory Read, at          14461605000
 test target 1 - Starting Memory Read, at          14462295000
 test target 1 - Starting Memory Read, at          14462985000
 test target 1 - Starting Memory Read, at          14463855000
 test target 1 - Starting Memory Read, at          14465115000
 test target 1 - Starting Memory Read, at          14466015000
 test target 1 - Starting Memory Read, at          14467275000
 test target 1 - Starting Memory Read, at          14468175000
 test target 1 - Starting Memory Read, at          14471085000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          14481885000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          14487765000
 test target 1 - Starting Memory Write, at          14488635000
 test target 1 - Starting Memory Read, at          14489235000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          14490645000
 test target 1 - Starting Config Write, at          14492625000
 test target 1 - Starting Memory Read, at          14493405000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          14494845000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          14496945000
 test target 1 - Starting Memory Write, at          14498115000
 test target 1 - Starting Memory Write, at          14498445000
 test target 1 - Starting Memory Read, at          14498745000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          14500905000
 test target 1 - Starting Memory Write, at          14503695000
 test target 1 - Starting Memory Write, at          14504175000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          14507985000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          14509845000
 test target 1 - Starting Memory Read, at          14511135000
 test target 1 - Starting Memory Read, at          14512395000
 test target 1 - Starting Memory Read, at          14514135000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          14519745000
 test target 2 - Starting Config Write, at          14520705000
 test target 1 - Starting Memory Write, at          14521455000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          14521665000
 test target 1 - Starting Memory Write, at          14522595000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          14522805000
 test target 1 - Starting Memory Write, at          14523735000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          14525085000
 test target 1 - Starting Memory Read, at          14527215000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          14527425000
 test target 1 - Starting Memory Read, at          14529345000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          14530965000
 test master 2 - Starting Memory Write, at          14530965000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          14531025000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14531835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14531865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14532165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14532195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14533035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14533065000
 test target 1 - Starting Memory Write, at          14534715000
 test master 2 - Starting Memory Write, at          14534715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14536335000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14536365000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14537895000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14537925000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14539455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14539485000
 test target 1 - Starting Memory Write, at          14541345000
 test master 2 - Starting Memory Write, at          14541345000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          14541405000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14542935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14542965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14543265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14543295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14544135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14544165000
 test target 1 - Starting Memory Write, at          14545275000
 test master 2 - Starting Memory Write, at          14545275000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          14547945000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          14549415000
 test master 1 - Starting Memory Read, at          14549745000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          14549895000
 test target 1 - Starting Config Write, at          14552205000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          14554395000
 test target 1 - Starting Memory Write, at          14554635000
 test target 1 - Starting Memory Write, at          14554875000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          14555415000
 test target 1 - Starting Memory Write, at          14555685000
 test target 1 - Starting Memory Write, at          14555955000
 test target 1 - Starting Memory Write, at          14556495000
 test target 1 - Starting Memory Write, at          14556885000
 test target 1 - Starting Memory Write, at          14557395000
 test target 1 - Starting Memory Write, at          14558115000
 test target 1 - Starting Memory Write, at          14558385000
 test target 1 - Starting Memory Write, at          14559105000
 test target 1 - Starting Memory Write, at          14559525000
 test target 1 - Starting Memory Write, at          14560095000
 test target 1 - Starting Memory Write, at          14563335000
 test target 1 - Starting Memory Write, at          14563605000
 test target 1 - Starting Memory Write, at          14563875000
 test target 1 - Starting Memory Write, at          14564295000
 test target 1 - Starting Memory Write, at          14564715000
 test target 1 - Starting Memory Read, at          14573565000
 test target 1 - Starting Memory Read, at          14574735000
 test target 1 - Starting Memory Read, at          14575935000
 test target 1 - Starting Memory Read, at          14577135000
 test target 1 - Starting Memory Read, at          14578335000
 test target 1 - Starting Memory Read, at          14579535000
 test target 1 - Starting Memory Read, at          14580735000
 test target 1 - Starting Memory Read, at          14581935000
 test target 1 - Starting Memory Read, at          14583135000
 test target 1 - Starting Memory Read, at          14584335000
 test target 1 - Starting Memory Read, at          14585535000
 test target 1 - Starting Memory Read, at          14586735000
 test target 1 - Starting Memory Read, at          14587935000
 test target 1 - Starting Memory Read, at          14589135000
 test target 1 - Starting Memory Read, at          14590335000
 test target 1 - Starting Memory Read, at          14591535000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          14592705000
 test target 1 - Starting Memory Read, at          14592945000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          14594265000
 test target 1 - Starting Memory Read, at          14596815000
 test target 1 - Starting Memory Read, at          14597445000
 test target 1 - Starting Memory Read, at          14598195000
 test target 1 - Starting Memory Read, at          14599005000
 test target 1 - Starting Memory Read, at          14599785000
 test target 1 - Starting Memory Read, at          14601135000
 test target 1 - Starting Memory Read, at          14602395000
 test target 1 - Starting Memory Read, at          14603295000
 test target 1 - Starting Memory Read, at          14606655000
 test target 1 - Starting Memory Read, at          14609805000
 test target 1 - Starting Memory Read, at          14610675000
 test target 1 - Starting Memory Read, at          14611515000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          14612595000
 test master 1 - Starting Memory Write, at          14612955000
 test target 1 - Starting Memory Write, at          14612955000
 test target 1 - Starting Memory Write, at          14613195000
 test target 1 - Starting Memory Read, at          14613945000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          14616975000
 test master 1 - Starting Memory Write, at          14617335000
 test target 1 - Starting Memory Write, at          14617335000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          14622045000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          14623215000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          14647155000
 test target 1 - Starting Config Write, at          14648115000
 test target 1 - Starting Config Write, at          14649075000
 test target 2 - Starting Config Write, at          14650035000
 test target 2 - Starting Config Write, at          14650995000
 test target 2 - Starting Config Write, at          14651955000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          14653755000
 test target 1 - Starting Memory Read, at          14654085000
 test target 1 - Starting Memory Write, at          14654745000
 test target 1 - Starting Memory Read, at          14655075000
 test target 1 - Starting Memory Write, at          14655945000
 test target 1 - Starting Memory Read, at          14657385000
 test target 1 - Starting Memory Read, at          14658045000
 test target 1 - Starting Memory Read, at          14658705000
 test target 1 - Starting Memory Read, at          14659395000
 test target 1 - Starting Memory Read, at          14660295000
 test target 1 - Starting Memory Read, at          14661555000
 test target 1 - Starting Memory Read, at          14662455000
 test target 1 - Starting Memory Read, at          14663715000
 test target 1 - Starting Memory Read, at          14664615000
 test target 1 - Starting Memory Read, at          14667525000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          14673435000
 test target 1 - Starting Memory Read, at          14673765000
 test target 1 - Starting Memory Write, at          14674425000
 test target 1 - Starting Memory Read, at          14674755000
 test target 1 - Starting Memory Write, at          14675625000
 test target 1 - Starting Memory Read, at          14677065000
 test target 1 - Starting Memory Read, at          14677725000
 test target 1 - Starting Memory Read, at          14678385000
 test target 1 - Starting Memory Read, at          14679075000
 test target 1 - Starting Memory Read, at          14679975000
 test target 1 - Starting Memory Read, at          14681235000
 test target 1 - Starting Memory Read, at          14682135000
 test target 1 - Starting Memory Read, at          14683395000
 test target 1 - Starting Memory Read, at          14684295000
 test target 1 - Starting Memory Read, at          14687205000
 test target 1 - Starting Memory Write, at          14693115000
 test target 1 - Starting Memory Read, at          14693445000
 test target 1 - Starting Memory Write, at          14694105000
 test target 1 - Starting Memory Read, at          14694435000
 test target 1 - Starting Memory Write, at          14695305000
 test target 1 - Starting Memory Read, at          14696745000
 test target 1 - Starting Memory Read, at          14697405000
 test target 1 - Starting Memory Read, at          14698065000
 test target 1 - Starting Memory Read, at          14698755000
 test target 1 - Starting Memory Read, at          14699655000
 test target 1 - Starting Memory Read, at          14700915000
 test target 1 - Starting Memory Read, at          14701815000
 test target 1 - Starting Memory Read, at          14703075000
 test target 1 - Starting Memory Read, at          14703975000
 test target 1 - Starting Memory Read, at          14706885000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          14717685000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          14723565000
 test target 1 - Starting Memory Write, at          14724435000
 test target 1 - Starting Memory Read, at          14725065000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          14726445000
 test target 1 - Starting Config Write, at          14728425000
 test target 1 - Starting Memory Read, at          14729205000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          14730645000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          14732745000
 test target 1 - Starting Memory Write, at          14733915000
 test target 1 - Starting Memory Write, at          14734275000
 test target 1 - Starting Memory Read, at          14734605000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          14736705000
 test target 1 - Starting Memory Write, at          14739495000
 test target 1 - Starting Memory Write, at          14740005000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          14743845000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          14745705000
 test target 1 - Starting Memory Read, at          14747115000
 test target 1 - Starting Memory Read, at          14748375000
 test target 1 - Starting Memory Read, at          14750115000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          14755725000
 test target 2 - Starting Config Write, at          14756685000
 test target 1 - Starting Memory Write, at          14757435000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          14757675000
 test target 1 - Starting Memory Write, at          14758635000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          14758875000
 test target 1 - Starting Memory Write, at          14759835000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          14761245000
 test target 1 - Starting Memory Read, at          14763375000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          14763615000
 test target 1 - Starting Memory Read, at          14765505000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          14767125000
 test master 2 - Starting Memory Write, at          14767125000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          14767185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14768055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14768085000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14768385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14768415000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14769255000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14769285000
 test target 1 - Starting Memory Write, at          14770935000
 test master 2 - Starting Memory Write, at          14770935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14772615000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14772645000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14774175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14774205000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14775735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14775765000
 test target 1 - Starting Memory Write, at          14777625000
 test master 2 - Starting Memory Write, at          14777625000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          14777685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14779275000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14779305000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14779605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14779635000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14780475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14780505000
 test target 1 - Starting Memory Write, at          14781615000
 test master 2 - Starting Memory Write, at          14781615000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          14784285000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          14785755000
 test master 1 - Starting Memory Read, at          14786085000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          14786235000
 test target 1 - Starting Config Write, at          14788545000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          14790735000
 test target 1 - Starting Memory Write, at          14791005000
 test target 1 - Starting Memory Write, at          14791275000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          14791815000
 test target 1 - Starting Memory Write, at          14792115000
 test target 1 - Starting Memory Write, at          14792415000
 test target 1 - Starting Memory Write, at          14792955000
 test target 1 - Starting Memory Write, at          14793375000
 test target 1 - Starting Memory Write, at          14793915000
 test target 1 - Starting Memory Write, at          14794665000
 test target 1 - Starting Memory Write, at          14794965000
 test target 1 - Starting Memory Write, at          14795715000
 test target 1 - Starting Memory Write, at          14796165000
 test target 1 - Starting Memory Write, at          14796765000
 test target 1 - Starting Memory Write, at          14800035000
 test target 1 - Starting Memory Write, at          14800335000
 test target 1 - Starting Memory Write, at          14800635000
 test target 1 - Starting Memory Write, at          14801085000
 test target 1 - Starting Memory Write, at          14801535000
 test target 1 - Starting Memory Read, at          14810415000
 test target 1 - Starting Memory Read, at          14811645000
 test target 1 - Starting Memory Read, at          14812935000
 test target 1 - Starting Memory Read, at          14814135000
 test target 1 - Starting Memory Read, at          14815335000
 test target 1 - Starting Memory Read, at          14816535000
 test target 1 - Starting Memory Read, at          14817735000
 test target 1 - Starting Memory Read, at          14818935000
 test target 1 - Starting Memory Read, at          14820135000
 test target 1 - Starting Memory Read, at          14821335000
 test target 1 - Starting Memory Read, at          14822535000
 test target 1 - Starting Memory Read, at          14823735000
 test target 1 - Starting Memory Read, at          14824935000
 test target 1 - Starting Memory Read, at          14826135000
 test target 1 - Starting Memory Read, at          14827335000
 test target 1 - Starting Memory Read, at          14828535000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          14829705000
 test target 1 - Starting Memory Read, at          14829975000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          14831265000
 test target 1 - Starting Memory Read, at          14833845000
 test target 1 - Starting Memory Read, at          14834595000
 test target 1 - Starting Memory Read, at          14835345000
 test target 1 - Starting Memory Read, at          14836275000
 test target 1 - Starting Memory Read, at          14837205000
 test target 1 - Starting Memory Read, at          14838555000
 test target 1 - Starting Memory Read, at          14839815000
 test target 1 - Starting Memory Read, at          14840715000
 test target 1 - Starting Memory Read, at          14844075000
 test target 1 - Starting Memory Read, at          14847315000
 test target 1 - Starting Memory Read, at          14848155000
 test target 1 - Starting Memory Read, at          14848995000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          14850075000
 test master 1 - Starting Memory Write, at          14850465000
 test target 1 - Starting Memory Write, at          14850465000
 test target 1 - Starting Memory Write, at          14850735000
 test target 1 - Starting Memory Read, at          14851515000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          14854485000
 test master 1 - Starting Memory Write, at          14854875000
 test target 1 - Starting Memory Write, at          14854875000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14859615000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          14859855000
 test master 2 - Starting Memory Read, at          14860035000
 test master 2 - Starting Memory Read, at          14860245000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14861835000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          14862255000
 test master 2 - Starting Memory Read, at          14862435000
 test master 2 - Starting Memory Read, at          14862645000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14863935000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14864505000
 test master 2 - Starting Memory Read Line Multiple, at          14864685000
 test master 2 - Starting Memory Read Line Multiple, at          14864955000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14866995000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14877615000
 test master 2 - Starting Memory Read Line Multiple, at          14877795000
 test master 2 - Starting Memory Read Line Multiple, at          14878065000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14879145000
 test master 2 - Starting Memory Read Line Multiple, at          14879325000
 test master 2 - Starting Memory Read Line Multiple, at          14879625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14880705000
 test master 2 - Starting Memory Read Line Multiple, at          14880885000
 test master 2 - Starting Memory Read Line Multiple, at          14881185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14882265000
 test master 2 - Starting Memory Read Line Multiple, at          14882445000
 test master 2 - Starting Memory Read Line Multiple, at          14882745000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14883825000
 test master 2 - Starting Memory Read Line Multiple, at          14884005000
 test master 2 - Starting Memory Read Line Multiple, at          14884305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14885385000
 test master 2 - Starting Memory Read Line Multiple, at          14885565000
 test master 2 - Starting Memory Read Line Multiple, at          14885865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14886945000
 test master 2 - Starting Memory Read Line Multiple, at          14887125000
 test master 2 - Starting Memory Read Line Multiple, at          14887425000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14888505000
 test master 2 - Starting Memory Read Line Multiple, at          14888685000
 test master 2 - Starting Memory Read Line Multiple, at          14888985000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          14890065000
 test master 2 - Starting Memory Read Line, at          14890245000
 test master 2 - Starting Memory Read Line, at          14890485000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          14891115000
 test master 2 - Starting Memory Read Line, at          14891295000
 test master 2 - Starting Memory Read Line, at          14891505000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14892585000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14893965000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14896545000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14898225000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          14902815000
 test master 2 - Starting Memory Write, at          14903055000
 test master 2 - Starting Memory Write, at          14903295000
 test master 2 - Starting Memory Write, at          14903535000
 test master 2 - Starting Memory Write, at          14903775000
 test master 1 - Starting Memory Read, at          14904135000
 test master 1 - Starting Memory Read, at          14904435000
 test master 1 - Starting Memory Read, at          14904975000
 test master 1 - Starting Memory Read, at          14905275000
 test master 1 - Starting Memory Read, at          14905815000
 test master 1 - Starting Memory Read, at          14906115000
 test master 2 - Starting Memory Write, at          14907315000
 test master 2 - Starting Memory Write, at          14907555000
 test master 2 - Starting Memory Write, at          14907795000
 test master 2 - Starting Memory Write, at          14908035000
 test master 2 - Starting Memory Write, at          14908275000
 test master 1 - Starting Memory Read, at          14908635000
 test master 1 - Starting Memory Read, at          14908935000
 test master 1 - Starting Memory Read, at          14909475000
 test master 1 - Starting Memory Read, at          14909775000
 test master 1 - Starting Memory Read, at          14910315000
 test master 1 - Starting Memory Read, at          14910615000
 test master 2 - Starting Memory Write, at          14912235000
 test master 2 - Starting Memory Write, at          14913225000
 test master 2 - Starting Memory Write, at          14914245000
 test master 2 - Starting Memory Write, at          14915265000
 test master 2 - Starting Memory Write, at          14917275000
 test master 2 - Starting Memory Write, at          14918265000
 test master 2 - Starting Memory Write, at          14919285000
 test master 2 - Starting Memory Write, at          14920305000
 test master 2 - Starting Memory Write, at          14922315000
 test master 2 - Starting Memory Write, at          14924145000
 test master 2 - Starting Memory Write, at          14926005000
 test master 2 - Starting Memory Write, at          14927865000
 test master 2 - Starting Memory Write, at          14930715000
 test master 2 - Starting Memory Write, at          14932755000
 test master 2 - Starting Memory Write, at          14934795000
 test master 2 - Starting Memory Write, at          14936835000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          14941005000
*** monitor - CBE Bus Changed when TRDY Desserted, at          14941035000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14942895000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          14943135000
 test master 2 - Starting Memory Read, at          14943315000
 test master 2 - Starting Memory Read, at          14943525000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14945115000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          14945535000
 test master 2 - Starting Memory Read, at          14945715000
 test master 2 - Starting Memory Read, at          14945925000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14947215000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14947785000
 test master 2 - Starting Memory Read Line Multiple, at          14947965000
 test master 2 - Starting Memory Read Line Multiple, at          14948235000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14950275000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14960895000
 test master 2 - Starting Memory Read Line Multiple, at          14961075000
 test master 2 - Starting Memory Read Line Multiple, at          14961345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14962425000
 test master 2 - Starting Memory Read Line Multiple, at          14962605000
 test master 2 - Starting Memory Read Line Multiple, at          14962905000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14963985000
 test master 2 - Starting Memory Read Line Multiple, at          14964165000
 test master 2 - Starting Memory Read Line Multiple, at          14964465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14965545000
 test master 2 - Starting Memory Read Line Multiple, at          14965725000
 test master 2 - Starting Memory Read Line Multiple, at          14966025000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14967105000
 test master 2 - Starting Memory Read Line Multiple, at          14967285000
 test master 2 - Starting Memory Read Line Multiple, at          14967585000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14968665000
 test master 2 - Starting Memory Read Line Multiple, at          14968845000
 test master 2 - Starting Memory Read Line Multiple, at          14969145000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14970225000
 test master 2 - Starting Memory Read Line Multiple, at          14970405000
 test master 2 - Starting Memory Read Line Multiple, at          14970705000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          14971785000
 test master 2 - Starting Memory Read Line Multiple, at          14971965000
 test master 2 - Starting Memory Read Line Multiple, at          14972265000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          14973345000
 test master 2 - Starting Memory Read Line, at          14973525000
 test master 2 - Starting Memory Read Line, at          14973765000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          14974395000
 test master 2 - Starting Memory Read Line, at          14974575000
 test master 2 - Starting Memory Read Line, at          14974785000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14975865000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14977245000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14979825000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          14981505000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          14986095000
 test master 2 - Starting Memory Write, at          14986335000
 test master 2 - Starting Memory Write, at          14986575000
 test master 2 - Starting Memory Write, at          14986815000
 test master 2 - Starting Memory Write, at          14987055000
 test master 1 - Starting Memory Read, at          14987415000
 test master 1 - Starting Memory Read, at          14987715000
 test master 1 - Starting Memory Read, at          14988255000
 test master 1 - Starting Memory Read, at          14988555000
 test master 1 - Starting Memory Read, at          14989095000
 test master 1 - Starting Memory Read, at          14989395000
 test master 2 - Starting Memory Write, at          14990595000
 test master 2 - Starting Memory Write, at          14990835000
 test master 2 - Starting Memory Write, at          14991075000
 test master 2 - Starting Memory Write, at          14991315000
 test master 2 - Starting Memory Write, at          14991555000
 test master 1 - Starting Memory Read, at          14991915000
 test master 1 - Starting Memory Read, at          14992215000
 test master 1 - Starting Memory Read, at          14992755000
 test master 1 - Starting Memory Read, at          14993055000
 test master 1 - Starting Memory Read, at          14993595000
 test master 1 - Starting Memory Read, at          14993895000
 test master 2 - Starting Memory Write, at          14995515000
 test master 2 - Starting Memory Write, at          14996505000
 test master 2 - Starting Memory Write, at          14997525000
 test master 2 - Starting Memory Write, at          14998545000
 test master 2 - Starting Memory Write, at          15000555000
 test master 2 - Starting Memory Write, at          15001545000
 test master 2 - Starting Memory Write, at          15002565000
 test master 2 - Starting Memory Write, at          15003585000
 test master 2 - Starting Memory Write, at          15005595000
 test master 2 - Starting Memory Write, at          15007425000
 test master 2 - Starting Memory Write, at          15009285000
 test master 2 - Starting Memory Write, at          15011145000
 test master 2 - Starting Memory Write, at          15013995000
 test master 2 - Starting Memory Write, at          15016035000
 test master 2 - Starting Memory Write, at          15018075000
 test master 2 - Starting Memory Write, at          15020115000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          15024285000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15024315000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15026175000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          15026415000
 test master 2 - Starting Memory Read, at          15026595000
 test master 2 - Starting Memory Read, at          15026805000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15028395000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          15028815000
 test master 2 - Starting Memory Read, at          15028995000
 test master 2 - Starting Memory Read, at          15029205000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15030495000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15031065000
 test master 2 - Starting Memory Read Line Multiple, at          15031245000
 test master 2 - Starting Memory Read Line Multiple, at          15031515000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15033555000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15044175000
 test master 2 - Starting Memory Read Line Multiple, at          15044355000
 test master 2 - Starting Memory Read Line Multiple, at          15044625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15045705000
 test master 2 - Starting Memory Read Line Multiple, at          15045885000
 test master 2 - Starting Memory Read Line Multiple, at          15046185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15047265000
 test master 2 - Starting Memory Read Line Multiple, at          15047445000
 test master 2 - Starting Memory Read Line Multiple, at          15047745000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15048825000
 test master 2 - Starting Memory Read Line Multiple, at          15049005000
 test master 2 - Starting Memory Read Line Multiple, at          15049305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15050385000
 test master 2 - Starting Memory Read Line Multiple, at          15050565000
 test master 2 - Starting Memory Read Line Multiple, at          15050865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15051945000
 test master 2 - Starting Memory Read Line Multiple, at          15052125000
 test master 2 - Starting Memory Read Line Multiple, at          15052425000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15053505000
 test master 2 - Starting Memory Read Line Multiple, at          15053685000
 test master 2 - Starting Memory Read Line Multiple, at          15053985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15055065000
 test master 2 - Starting Memory Read Line Multiple, at          15055245000
 test master 2 - Starting Memory Read Line Multiple, at          15055545000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          15056625000
 test master 2 - Starting Memory Read Line, at          15056805000
 test master 2 - Starting Memory Read Line, at          15057045000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          15057675000
 test master 2 - Starting Memory Read Line, at          15057855000
 test master 2 - Starting Memory Read Line, at          15058065000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15059145000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15060525000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15063105000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15064785000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          15069375000
 test master 2 - Starting Memory Write, at          15069615000
 test master 2 - Starting Memory Write, at          15069855000
 test master 2 - Starting Memory Write, at          15070095000
 test master 2 - Starting Memory Write, at          15070335000
 test master 1 - Starting Memory Read, at          15070695000
 test master 1 - Starting Memory Read, at          15070995000
 test master 1 - Starting Memory Read, at          15071535000
 test master 1 - Starting Memory Read, at          15071835000
 test master 1 - Starting Memory Read, at          15072375000
 test master 1 - Starting Memory Read, at          15072675000
 test master 2 - Starting Memory Write, at          15073875000
 test master 2 - Starting Memory Write, at          15074115000
 test master 2 - Starting Memory Write, at          15074355000
 test master 2 - Starting Memory Write, at          15074595000
 test master 2 - Starting Memory Write, at          15074835000
 test master 1 - Starting Memory Read, at          15075195000
 test master 1 - Starting Memory Read, at          15075495000
 test master 1 - Starting Memory Read, at          15076035000
 test master 1 - Starting Memory Read, at          15076335000
 test master 1 - Starting Memory Read, at          15076875000
 test master 1 - Starting Memory Read, at          15077175000
 test master 2 - Starting Memory Write, at          15078795000
 test master 2 - Starting Memory Write, at          15079785000
 test master 2 - Starting Memory Write, at          15080805000
 test master 2 - Starting Memory Write, at          15081825000
 test master 2 - Starting Memory Write, at          15083835000
 test master 2 - Starting Memory Write, at          15084825000
 test master 2 - Starting Memory Write, at          15085845000
 test master 2 - Starting Memory Write, at          15086865000
 test master 2 - Starting Memory Write, at          15088875000
 test master 2 - Starting Memory Write, at          15090705000
 test master 2 - Starting Memory Write, at          15092565000
 test master 2 - Starting Memory Write, at          15094425000
 test master 2 - Starting Memory Write, at          15097275000
 test master 2 - Starting Memory Write, at          15099315000
 test master 2 - Starting Memory Write, at          15101355000
 test master 2 - Starting Memory Write, at          15103395000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          15107565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15107595000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15109455000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          15109695000
 test master 2 - Starting Memory Read, at          15109875000
 test master 2 - Starting Memory Read, at          15110085000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15111675000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          15112095000
 test master 2 - Starting Memory Read, at          15112275000
 test master 2 - Starting Memory Read, at          15112485000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15113775000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15114345000
 test master 2 - Starting Memory Read Line Multiple, at          15114525000
 test master 2 - Starting Memory Read Line Multiple, at          15114795000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15116835000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15127455000
 test master 2 - Starting Memory Read Line Multiple, at          15127635000
 test master 2 - Starting Memory Read Line Multiple, at          15127905000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15128985000
 test master 2 - Starting Memory Read Line Multiple, at          15129165000
 test master 2 - Starting Memory Read Line Multiple, at          15129465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15130545000
 test master 2 - Starting Memory Read Line Multiple, at          15130725000
 test master 2 - Starting Memory Read Line Multiple, at          15131025000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15132105000
 test master 2 - Starting Memory Read Line Multiple, at          15132285000
 test master 2 - Starting Memory Read Line Multiple, at          15132585000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15133665000
 test master 2 - Starting Memory Read Line Multiple, at          15133845000
 test master 2 - Starting Memory Read Line Multiple, at          15134145000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15135225000
 test master 2 - Starting Memory Read Line Multiple, at          15135405000
 test master 2 - Starting Memory Read Line Multiple, at          15135705000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15136785000
 test master 2 - Starting Memory Read Line Multiple, at          15136965000
 test master 2 - Starting Memory Read Line Multiple, at          15137265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          15138345000
 test master 2 - Starting Memory Read Line Multiple, at          15138525000
 test master 2 - Starting Memory Read Line Multiple, at          15138825000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          15139905000
 test master 2 - Starting Memory Read Line, at          15140085000
 test master 2 - Starting Memory Read Line, at          15140325000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          15140955000
 test master 2 - Starting Memory Read Line, at          15141135000
 test master 2 - Starting Memory Read Line, at          15141345000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15142425000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15143805000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15146385000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          15148065000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          15152655000
 test master 2 - Starting Memory Write, at          15152895000
 test master 2 - Starting Memory Write, at          15153135000
 test master 2 - Starting Memory Write, at          15153375000
 test master 2 - Starting Memory Write, at          15153615000
 test master 1 - Starting Memory Read, at          15153975000
 test master 1 - Starting Memory Read, at          15154275000
 test master 1 - Starting Memory Read, at          15154815000
 test master 1 - Starting Memory Read, at          15155115000
 test master 1 - Starting Memory Read, at          15155655000
 test master 1 - Starting Memory Read, at          15155955000
 test master 2 - Starting Memory Write, at          15157155000
 test master 2 - Starting Memory Write, at          15157395000
 test master 2 - Starting Memory Write, at          15157635000
 test master 2 - Starting Memory Write, at          15157875000
 test master 2 - Starting Memory Write, at          15158115000
 test master 1 - Starting Memory Read, at          15158475000
 test master 1 - Starting Memory Read, at          15158775000
 test master 1 - Starting Memory Read, at          15159315000
 test master 1 - Starting Memory Read, at          15159615000
 test master 1 - Starting Memory Read, at          15160155000
 test master 1 - Starting Memory Read, at          15160455000
 test master 2 - Starting Memory Write, at          15162075000
 test master 2 - Starting Memory Write, at          15163065000
 test master 2 - Starting Memory Write, at          15164085000
 test master 2 - Starting Memory Write, at          15165105000
 test master 2 - Starting Memory Write, at          15167115000
 test master 2 - Starting Memory Write, at          15168105000
 test master 2 - Starting Memory Write, at          15169125000
 test master 2 - Starting Memory Write, at          15170145000
 test master 2 - Starting Memory Write, at          15172155000
 test master 2 - Starting Memory Write, at          15173985000
 test master 2 - Starting Memory Write, at          15175845000
 test master 2 - Starting Memory Write, at          15177705000
 test master 2 - Starting Memory Write, at          15180555000
 test master 2 - Starting Memory Write, at          15182595000
 test master 2 - Starting Memory Write, at          15184635000
 test master 2 - Starting Memory Write, at          15186675000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          15190845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15190875000
 test master 1 - Starting Memory Read, at          15192735000
 test master 1 - Starting Memory Read, at          15193065000
 test master 1 - Starting Memory Read, at          15194175000
 test master 1 - Starting Memory Read, at          15194505000
 test master 1 - Starting Memory Read Line, at          15195615000
 test master 1 - Starting Memory Read Line, at          15195945000
 test master 1 - Starting Memory Read Line, at          15197055000
 test master 1 - Starting Memory Read Line, at          15197385000
 test master 1 - Starting Memory Read Line, at          15198555000
 test master 1 - Starting Memory Read Line, at          15198945000
 test master 1 - Starting Memory Read Line, at          15200415000
 test master 1 - Starting Memory Read Line, at          15200805000
 test master 1 - Starting Memory Read Line Multiple, at          15202275000
 test master 1 - Starting Memory Read Line Multiple, at          15202725000
 test master 1 - Starting Memory Read Line Multiple, at          15204615000
 test master 1 - Starting Memory Read Line Multiple, at          15205065000
 test master 1 - Starting Memory Read Line, at          15206955000
 test master 1 - Starting Memory Read Line, at          15207345000
 test master 1 - Starting Memory Read, at          15209655000
 test master 1 - Starting Memory Read, at          15209985000
 test target 1 - Starting Config Write, at          15212895000
 test master 1 - Starting Memory Write, at          15213435000
 test master 1 - Starting Memory Write, at          15222705000
 test master 1 - Starting Memory Write, at          15224055000
 test master 1 - Starting Memory Write, at          15232725000
 test master 1 - Starting Memory Write, at          15234075000
 test master 1 - Starting Memory Read Line, at          15243345000
 test master 1 - Starting Memory Write, at          15244845000
 test master 1 - Starting Memory Read Line, at          15254115000
 test target 1 - Starting Config Write, at          15257235000
 test master 1 - Starting Memory Write, at          15257775000
 test master 1 - Starting Memory Write, at          15257895000
 test master 1 - Starting Memory Write, at          15258135000
 test master 1 - Starting Memory Read, at          15258255000
 test master 1 - Starting Memory Write, at          15258585000
 test master 1 - Starting Memory Read, at          15258705000
 test master 1 - Starting Memory Write, at          15260115000
 test master 1 - Starting Memory Write, at          15270735000
 test master 2 - Starting Memory Read Line, at          15281475000
 test master 2 - Starting Memory Read Line, at          15281835000
 test master 2 - Starting Memory Read Line, at          15282495000
 test master 2 - Starting Memory Read Line, at          15282855000
 test master 1 - Starting Memory Write, at          15283605000
 test master 1 - Starting Memory Write, at          15283935000
 test master 1 - Starting Memory Write, at          15284295000
 test master 2 - Starting Memory Read Line, at          15284775000
 test master 2 - Starting Memory Read Line, at          15285105000
 test master 2 - Starting Memory Read Line, at          15285435000
 test master 2 - Starting Memory Read Line, at          15285765000
 test master 2 - Starting Memory Read Line Multiple, at          15286125000
 test master 2 - Starting Memory Read Line Multiple, at          15286455000
 test master 1 - Starting Memory Write, at          15288195000
 test master 1 - Starting Memory Write, at          15288525000
 test master 2 - Starting Memory Read, at          15289005000
 test master 2 - Starting Memory Read, at          15289335000
 test master 2 - Starting Memory Read, at          15289665000
 test master 2 - Starting Memory Read, at          15289995000
 test master 1 - Starting Memory Write, at          15291525000
 test master 1 - Starting Memory Read, at          15291705000
 test master 1 - Starting Memory Write, at          15291885000
 test master 1 - Starting Memory Read, at          15292095000
 test master 1 - Starting Memory Write, at          15292305000
 test master 1 - Starting Memory Read, at          15292485000
 test master 1 - Starting Memory Read, at          15292695000
 test master 1 - Starting Memory Write, at          15292905000
 test master 1 - Starting Memory Write, at          15293085000
 test master 1 - Starting Memory Read, at          15293265000
 test master 1 - Starting Memory Write, at          15293445000
 test master 1 - Starting Memory Write, at          15293655000
 test master 1 - Starting Memory Write, at          15293865000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          15297735000
 test target 1 - Starting Memory Write, at          15298005000
 test master 1 - Starting Memory Write, at          15298245000
 test target 1 - Starting Memory Write, at          15298425000
 test target 1 - Starting Memory Write, at          15298695000
 test target 1 - Starting Memory Write, at          15298965000
 test master 1 - Starting Memory Write, at          15299325000
 test target 1 - Starting Memory Write, at          15299835000
 test target 1 - Starting Memory Write, at          15300435000
 test target 1 - Starting Memory Write, at          15300735000
 test master 1 - Starting Memory Write, at          15301005000
 test target 1 - Starting Memory Write, at          15301485000
 test target 1 - Starting Memory Write, at          15301785000
 test target 1 - Starting Memory Write, at          15302085000
 test master 1 - Starting Memory Write, at          15302745000
 test target 1 - Starting Memory Write, at          15303705000
 test target 1 - Starting Memory Write, at          15304695000
 test target 1 - Starting Memory Write, at          15304965000
 test master 1 - Starting Memory Read, at          15305205000
 test target 1 - Starting Memory Write, at          15305385000
 test master 1 - Starting Memory Read, at          15305625000
 test target 1 - Starting Memory Write, at          15305805000
 test master 1 - Starting Memory Read, at          15306045000
 test target 1 - Starting Memory Write, at          15306225000
 test master 1 - Starting Memory Read, at          15306465000
 test target 1 - Starting Memory Write, at          15306645000
 test master 1 - Starting Memory Read, at          15306885000
 test target 1 - Starting Memory Write, at          15307065000
 test master 1 - Starting Memory Write, at          15307305000
 test target 1 - Starting Memory Write, at          15307485000
 test target 1 - Starting Memory Write, at          15307755000
 test target 1 - Starting Memory Write, at          15308025000
 test target 1 - Starting Memory Read, at          15308355000
 test master 1 - Starting Memory Write, at          15308715000
 test master 1 - Starting Memory Read, at          15308955000
 test target 1 - Starting Memory Write, at          15309465000
 test master 1 - Starting Memory Write, at          15309915000
 test target 1 - Starting Memory Read, at          15310365000
 test target 1 - Starting Memory Write, at          15311235000
 test master 1 - Starting Memory Read, at          15311595000
 test master 1 - Starting Memory Write, at          15311925000
 test master 1 - Starting Memory Write, at          15312285000
 test master 1 - Starting Memory Read, at          15312525000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          15314955000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          15316005000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          15340425000
 test target 1 - Starting Config Write, at          15341325000
 test target 1 - Starting Config Write, at          15342225000
 test target 2 - Starting Config Write, at          15343125000
 test target 2 - Starting Config Write, at          15344025000
 test target 2 - Starting Config Write, at          15344925000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          15346815000
 test target 1 - Starting Memory Read, at          15347055000
 test target 1 - Starting Memory Write, at          15347625000
 test target 1 - Starting Memory Read, at          15347865000
 test target 1 - Starting Memory Write, at          15348915000
 test target 1 - Starting Memory Read, at          15350145000
 test target 1 - Starting Memory Read, at          15350775000
 test target 1 - Starting Memory Read, at          15351345000
 test target 1 - Starting Memory Read, at          15351945000
 test target 1 - Starting Memory Read, at          15352755000
 test target 1 - Starting Memory Read, at          15353925000
 test target 1 - Starting Memory Read, at          15354795000
 test target 1 - Starting Memory Read, at          15355965000
 test target 1 - Starting Memory Read, at          15356835000
 test target 1 - Starting Memory Read, at          15359355000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          15365475000
 test target 1 - Starting Memory Read, at          15365715000
 test target 1 - Starting Memory Write, at          15366435000
 test target 1 - Starting Memory Read, at          15366675000
 test target 1 - Starting Memory Write, at          15367695000
 test target 1 - Starting Memory Read, at          15368925000
 test target 1 - Starting Memory Read, at          15369555000
 test target 1 - Starting Memory Read, at          15370125000
 test target 1 - Starting Memory Read, at          15370725000
 test target 1 - Starting Memory Read, at          15371535000
 test target 1 - Starting Memory Read, at          15372705000
 test target 1 - Starting Memory Read, at          15373575000
 test target 1 - Starting Memory Read, at          15374745000
 test target 1 - Starting Memory Read, at          15375615000
 test target 1 - Starting Memory Read, at          15378135000
 test target 1 - Starting Memory Write, at          15384255000
 test target 1 - Starting Memory Read, at          15384495000
 test target 1 - Starting Memory Write, at          15385215000
 test target 1 - Starting Memory Read, at          15385455000
 test target 1 - Starting Memory Write, at          15386475000
 test target 1 - Starting Memory Read, at          15387705000
 test target 1 - Starting Memory Read, at          15388335000
 test target 1 - Starting Memory Read, at          15388905000
 test target 1 - Starting Memory Read, at          15389505000
 test target 1 - Starting Memory Read, at          15390315000
 test target 1 - Starting Memory Read, at          15391485000
 test target 1 - Starting Memory Read, at          15392355000
 test target 1 - Starting Memory Read, at          15393525000
 test target 1 - Starting Memory Read, at          15394395000
 test target 1 - Starting Memory Read, at          15396915000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          15408405000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          15414645000
 test target 1 - Starting Memory Write, at          15415455000
 test target 1 - Starting Memory Read, at          15415935000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          15417255000
 test target 1 - Starting Config Write, at          15419145000
 test target 1 - Starting Memory Read, at          15419805000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          15421245000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          15423345000
 test target 1 - Starting Memory Write, at          15424515000
 test target 1 - Starting Memory Write, at          15424785000
 test target 1 - Starting Memory Read, at          15425025000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          15427335000
 test target 1 - Starting Memory Write, at          15430275000
 test target 1 - Starting Memory Write, at          15430665000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          15434625000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          15436545000
 test target 1 - Starting Memory Read, at          15437925000
 test target 1 - Starting Memory Read, at          15439065000
 test target 1 - Starting Memory Read, at          15440775000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          15446685000
 test target 2 - Starting Config Write, at          15447585000
 test target 1 - Starting Memory Write, at          15448275000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          15448425000
 test target 1 - Starting Memory Write, at          15449415000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          15449565000
 test target 1 - Starting Memory Write, at          15450555000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          15451935000
 test target 1 - Starting Memory Read, at          15454095000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          15454245000
 test target 1 - Starting Memory Read, at          15456315000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          15457965000
 test master 2 - Starting Memory Write, at          15457965000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          15458025000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15458835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15458865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15459165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15459195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15460065000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15460095000
 test target 1 - Starting Memory Write, at          15461865000
 test master 2 - Starting Memory Write, at          15461865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15463545000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15463575000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15465225000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15465255000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15466905000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15466935000
 test target 1 - Starting Memory Write, at          15468945000
 test master 2 - Starting Memory Write, at          15468945000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          15469005000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15470595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15470625000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15470925000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15470955000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15471825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15471855000
 test target 1 - Starting Memory Write, at          15473025000
 test master 2 - Starting Memory Write, at          15473025000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          15475875000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          15477465000
 test master 1 - Starting Memory Read, at          15477885000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          15478035000
 test target 1 - Starting Config Write, at          15480525000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          15482835000
 test target 1 - Starting Memory Write, at          15483015000
 test target 1 - Starting Memory Write, at          15483195000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          15483675000
 test target 1 - Starting Memory Write, at          15483885000
 test target 1 - Starting Memory Write, at          15484095000
 test target 1 - Starting Memory Write, at          15484575000
 test target 1 - Starting Memory Write, at          15484875000
 test target 1 - Starting Memory Write, at          15485355000
 test target 1 - Starting Memory Write, at          15486015000
 test target 1 - Starting Memory Write, at          15486225000
 test target 1 - Starting Memory Write, at          15486885000
 test target 1 - Starting Memory Write, at          15487215000
 test target 1 - Starting Memory Write, at          15487755000
 test target 1 - Starting Memory Write, at          15492105000
 test target 1 - Starting Memory Write, at          15492315000
 test target 1 - Starting Memory Write, at          15492525000
 test target 1 - Starting Memory Write, at          15492855000
 test target 1 - Starting Memory Write, at          15493185000
 test target 1 - Starting Memory Read, at          15500265000
 test target 1 - Starting Memory Read, at          15501465000
 test target 1 - Starting Memory Read, at          15502575000
 test target 1 - Starting Memory Read, at          15503685000
 test target 1 - Starting Memory Read, at          15504825000
 test target 1 - Starting Memory Read, at          15505935000
 test target 1 - Starting Memory Read, at          15507045000
 test target 1 - Starting Memory Read, at          15508185000
 test target 1 - Starting Memory Read, at          15509295000
 test target 1 - Starting Memory Read, at          15510405000
 test target 1 - Starting Memory Read, at          15511545000
 test target 1 - Starting Memory Read, at          15512655000
 test target 1 - Starting Memory Read, at          15513765000
 test target 1 - Starting Memory Read, at          15514905000
 test target 1 - Starting Memory Read, at          15516015000
 test target 1 - Starting Memory Read, at          15517125000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          15518175000
 test target 1 - Starting Memory Read, at          15518355000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          15519855000
 test target 1 - Starting Memory Read, at          15521895000
 test target 1 - Starting Memory Read, at          15522525000
 test target 1 - Starting Memory Read, at          15523155000
 test target 1 - Starting Memory Read, at          15523965000
 test target 1 - Starting Memory Read, at          15524685000
 test target 1 - Starting Memory Read, at          15525945000
 test target 1 - Starting Memory Read, at          15527115000
 test target 1 - Starting Memory Read, at          15527985000
 test target 1 - Starting Memory Read, at          15531075000
 test target 1 - Starting Memory Read, at          15533835000
 test target 1 - Starting Memory Read, at          15534675000
 test target 1 - Starting Memory Read, at          15535515000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          15536685000
 test master 1 - Starting Memory Write, at          15537075000
 test target 1 - Starting Memory Write, at          15537075000
 test target 1 - Starting Memory Write, at          15537255000
 test target 1 - Starting Memory Read, at          15537735000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          15540315000
 test master 1 - Starting Memory Write, at          15540705000
 test target 1 - Starting Memory Write, at          15540705000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          15545565000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          15546615000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          15571065000
 test target 1 - Starting Config Write, at          15571965000
 test target 1 - Starting Config Write, at          15572865000
 test target 2 - Starting Config Write, at          15573765000
 test target 2 - Starting Config Write, at          15574665000
 test target 2 - Starting Config Write, at          15575565000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          15577455000
 test target 1 - Starting Memory Read, at          15577725000
 test target 1 - Starting Memory Write, at          15578415000
 test target 1 - Starting Memory Read, at          15578685000
 test target 1 - Starting Memory Write, at          15579675000
 test target 1 - Starting Memory Read, at          15580935000
 test target 1 - Starting Memory Read, at          15581565000
 test target 1 - Starting Memory Read, at          15582135000
 test target 1 - Starting Memory Read, at          15582705000
 test target 1 - Starting Memory Read, at          15583515000
 test target 1 - Starting Memory Read, at          15584685000
 test target 1 - Starting Memory Read, at          15585555000
 test target 1 - Starting Memory Read, at          15586725000
 test target 1 - Starting Memory Read, at          15587595000
 test target 1 - Starting Memory Read, at          15590115000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          15596235000
 test target 1 - Starting Memory Read, at          15596505000
 test target 1 - Starting Memory Write, at          15597195000
 test target 1 - Starting Memory Read, at          15597465000
 test target 1 - Starting Memory Write, at          15598455000
 test target 1 - Starting Memory Read, at          15599715000
 test target 1 - Starting Memory Read, at          15600345000
 test target 1 - Starting Memory Read, at          15600915000
 test target 1 - Starting Memory Read, at          15601485000
 test target 1 - Starting Memory Read, at          15602295000
 test target 1 - Starting Memory Read, at          15603465000
 test target 1 - Starting Memory Read, at          15604335000
 test target 1 - Starting Memory Read, at          15605505000
 test target 1 - Starting Memory Read, at          15606375000
 test target 1 - Starting Memory Read, at          15608895000
 test target 1 - Starting Memory Write, at          15615015000
 test target 1 - Starting Memory Read, at          15615285000
 test target 1 - Starting Memory Write, at          15615975000
 test target 1 - Starting Memory Read, at          15616245000
 test target 1 - Starting Memory Write, at          15617235000
 test target 1 - Starting Memory Read, at          15618495000
 test target 1 - Starting Memory Read, at          15619125000
 test target 1 - Starting Memory Read, at          15619695000
 test target 1 - Starting Memory Read, at          15620265000
 test target 1 - Starting Memory Read, at          15621075000
 test target 1 - Starting Memory Read, at          15622245000
 test target 1 - Starting Memory Read, at          15623115000
 test target 1 - Starting Memory Read, at          15624285000
 test target 1 - Starting Memory Read, at          15625155000
 test target 1 - Starting Memory Read, at          15627675000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          15639165000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          15645405000
 test target 1 - Starting Memory Write, at          15646215000
 test target 1 - Starting Memory Read, at          15646725000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          15648015000
 test target 1 - Starting Config Write, at          15649905000
 test target 1 - Starting Memory Read, at          15650565000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          15652005000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          15654105000
 test target 1 - Starting Memory Write, at          15655275000
 test target 1 - Starting Memory Write, at          15655575000
 test target 1 - Starting Memory Read, at          15655845000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          15658095000
 test target 1 - Starting Memory Write, at          15661065000
 test target 1 - Starting Memory Write, at          15661485000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          15665445000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          15667365000
 test target 1 - Starting Memory Read, at          15668745000
 test target 1 - Starting Memory Read, at          15669885000
 test target 1 - Starting Memory Read, at          15671595000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          15677505000
 test target 2 - Starting Config Write, at          15678405000
 test target 1 - Starting Memory Write, at          15679095000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          15679275000
 test target 1 - Starting Memory Write, at          15680295000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          15680475000
 test target 1 - Starting Memory Write, at          15681495000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          15682905000
 test target 1 - Starting Memory Read, at          15685095000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          15685275000
 test target 1 - Starting Memory Read, at          15687315000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          15688965000
 test master 2 - Starting Memory Write, at          15688965000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          15689025000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15689865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15689895000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15690195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15690225000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15691095000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15691125000
 test target 1 - Starting Memory Write, at          15692895000
 test master 2 - Starting Memory Write, at          15692895000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15694605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15694635000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15696285000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15696315000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15697965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15697995000
 test target 1 - Starting Memory Write, at          15700005000
 test master 2 - Starting Memory Write, at          15700005000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          15700065000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15701685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15701715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15702015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15702045000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15702915000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15702945000
 test target 1 - Starting Memory Write, at          15704115000
 test master 2 - Starting Memory Write, at          15704115000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          15706995000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          15708585000
 test master 1 - Starting Memory Read, at          15709005000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          15709155000
 test target 1 - Starting Config Write, at          15711645000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          15713955000
 test target 1 - Starting Memory Write, at          15714165000
 test target 1 - Starting Memory Write, at          15714375000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          15714885000
 test target 1 - Starting Memory Write, at          15715125000
 test target 1 - Starting Memory Write, at          15715365000
 test target 1 - Starting Memory Write, at          15715875000
 test target 1 - Starting Memory Write, at          15716205000
 test target 1 - Starting Memory Write, at          15716715000
 test target 1 - Starting Memory Write, at          15717405000
 test target 1 - Starting Memory Write, at          15717645000
 test target 1 - Starting Memory Write, at          15718335000
 test target 1 - Starting Memory Write, at          15718695000
 test target 1 - Starting Memory Write, at          15719265000
 test target 1 - Starting Memory Write, at          15723645000
 test target 1 - Starting Memory Write, at          15723885000
 test target 1 - Starting Memory Write, at          15724125000
 test target 1 - Starting Memory Write, at          15724485000
 test target 1 - Starting Memory Write, at          15724845000
 test target 1 - Starting Memory Read, at          15731955000
 test target 1 - Starting Memory Read, at          15733125000
 test target 1 - Starting Memory Read, at          15734235000
 test target 1 - Starting Memory Read, at          15735345000
 test target 1 - Starting Memory Read, at          15736485000
 test target 1 - Starting Memory Read, at          15737595000
 test target 1 - Starting Memory Read, at          15738705000
 test target 1 - Starting Memory Read, at          15739845000
 test target 1 - Starting Memory Read, at          15740955000
 test target 1 - Starting Memory Read, at          15742065000
 test target 1 - Starting Memory Read, at          15743205000
 test target 1 - Starting Memory Read, at          15744315000
 test target 1 - Starting Memory Read, at          15745425000
 test target 1 - Starting Memory Read, at          15746565000
 test target 1 - Starting Memory Read, at          15747675000
 test target 1 - Starting Memory Read, at          15748785000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          15749835000
 test target 1 - Starting Memory Read, at          15750045000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          15751695000
 test target 1 - Starting Memory Read, at          15753765000
 test target 1 - Starting Memory Read, at          15754335000
 test target 1 - Starting Memory Read, at          15754965000
 test target 1 - Starting Memory Read, at          15755805000
 test target 1 - Starting Memory Read, at          15756645000
 test target 1 - Starting Memory Read, at          15757935000
 test target 1 - Starting Memory Read, at          15759105000
 test target 1 - Starting Memory Read, at          15759975000
 test target 1 - Starting Memory Read, at          15763185000
 test target 1 - Starting Memory Read, at          15765945000
 test target 1 - Starting Memory Read, at          15766815000
 test target 1 - Starting Memory Read, at          15767655000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          15768825000
 test master 1 - Starting Memory Write, at          15769125000
 test target 1 - Starting Memory Write, at          15769125000
 test target 1 - Starting Memory Write, at          15769335000
 test target 1 - Starting Memory Read, at          15769965000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          15772605000
 test master 1 - Starting Memory Write, at          15772905000
 test target 1 - Starting Memory Write, at          15772905000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          15777735000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          15778785000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          15803205000
 test target 1 - Starting Config Write, at          15804105000
 test target 1 - Starting Config Write, at          15805005000
 test target 2 - Starting Config Write, at          15805905000
 test target 2 - Starting Config Write, at          15806805000
 test target 2 - Starting Config Write, at          15807705000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          15809595000
 test target 1 - Starting Memory Read, at          15809895000
 test target 1 - Starting Memory Write, at          15810555000
 test target 1 - Starting Memory Read, at          15810855000
 test target 1 - Starting Memory Write, at          15811845000
 test target 1 - Starting Memory Read, at          15813135000
 test target 1 - Starting Memory Read, at          15813765000
 test target 1 - Starting Memory Read, at          15814455000
 test target 1 - Starting Memory Read, at          15815145000
 test target 1 - Starting Memory Read, at          15816075000
 test target 1 - Starting Memory Read, at          15817245000
 test target 1 - Starting Memory Read, at          15818115000
 test target 1 - Starting Memory Read, at          15819285000
 test target 1 - Starting Memory Read, at          15820155000
 test target 1 - Starting Memory Read, at          15822675000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          15828975000
 test target 1 - Starting Memory Read, at          15829275000
 test target 1 - Starting Memory Write, at          15829935000
 test target 1 - Starting Memory Read, at          15830235000
 test target 1 - Starting Memory Write, at          15831195000
 test target 1 - Starting Memory Read, at          15832485000
 test target 1 - Starting Memory Read, at          15833115000
 test target 1 - Starting Memory Read, at          15833805000
 test target 1 - Starting Memory Read, at          15834525000
 test target 1 - Starting Memory Read, at          15835455000
 test target 1 - Starting Memory Read, at          15836625000
 test target 1 - Starting Memory Read, at          15837495000
 test target 1 - Starting Memory Read, at          15838665000
 test target 1 - Starting Memory Read, at          15839535000
 test target 1 - Starting Memory Read, at          15842055000
 test target 1 - Starting Memory Write, at          15848355000
 test target 1 - Starting Memory Read, at          15848655000
 test target 1 - Starting Memory Write, at          15849315000
 test target 1 - Starting Memory Read, at          15849615000
 test target 1 - Starting Memory Write, at          15850575000
 test target 1 - Starting Memory Read, at          15851865000
 test target 1 - Starting Memory Read, at          15852495000
 test target 1 - Starting Memory Read, at          15853185000
 test target 1 - Starting Memory Read, at          15853905000
 test target 1 - Starting Memory Read, at          15854835000
 test target 1 - Starting Memory Read, at          15856005000
 test target 1 - Starting Memory Read, at          15856875000
 test target 1 - Starting Memory Read, at          15858045000
 test target 1 - Starting Memory Read, at          15858915000
 test target 1 - Starting Memory Read, at          15861435000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          15873105000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          15879345000
 test target 1 - Starting Memory Write, at          15880155000
 test target 1 - Starting Memory Read, at          15880695000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          15882075000
 test target 1 - Starting Config Write, at          15883965000
 test target 1 - Starting Memory Read, at          15884625000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          15886065000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          15888165000
 test target 1 - Starting Memory Write, at          15889335000
 test target 1 - Starting Memory Write, at          15889665000
 test target 1 - Starting Memory Read, at          15889965000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          15892305000
 test target 1 - Starting Memory Write, at          15895305000
 test target 1 - Starting Memory Write, at          15895755000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          15899745000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          15901665000
 test target 1 - Starting Memory Read, at          15903045000
 test target 1 - Starting Memory Read, at          15904185000
 test target 1 - Starting Memory Read, at          15906015000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          15911925000
 test target 2 - Starting Config Write, at          15912825000
 test target 1 - Starting Memory Write, at          15913515000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          15913725000
 test target 1 - Starting Memory Write, at          15914715000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          15914925000
 test target 1 - Starting Memory Write, at          15915915000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          15917355000
 test target 1 - Starting Memory Read, at          15919515000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          15919725000
 test target 1 - Starting Memory Read, at          15921735000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          15923385000
 test master 2 - Starting Memory Write, at          15923385000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          15923445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15924315000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15924345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15924645000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15924675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15925545000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15925575000
 test target 1 - Starting Memory Write, at          15927345000
 test master 2 - Starting Memory Write, at          15927345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15929085000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15929115000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15930765000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15930795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15932445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15932475000
 test target 1 - Starting Memory Write, at          15934485000
 test master 2 - Starting Memory Write, at          15934485000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          15934545000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15936195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15936225000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15936525000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15936555000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15937425000
*** monitor - CBE Bus Changed when TRDY Desserted, at          15937455000
 test target 1 - Starting Memory Write, at          15938625000
 test master 2 - Starting Memory Write, at          15938625000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          15941535000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          15943125000
 test master 1 - Starting Memory Read, at          15943545000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          15943695000
 test target 1 - Starting Config Write, at          15946185000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          15948675000
 test target 1 - Starting Memory Write, at          15948915000
 test target 1 - Starting Memory Write, at          15949155000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          15949695000
 test target 1 - Starting Memory Write, at          15949965000
 test target 1 - Starting Memory Write, at          15950235000
 test target 1 - Starting Memory Write, at          15950775000
 test target 1 - Starting Memory Write, at          15951135000
 test target 1 - Starting Memory Write, at          15951675000
 test target 1 - Starting Memory Write, at          15952395000
 test target 1 - Starting Memory Write, at          15952665000
 test target 1 - Starting Memory Write, at          15953385000
 test target 1 - Starting Memory Write, at          15953775000
 test target 1 - Starting Memory Write, at          15954375000
 test target 1 - Starting Memory Write, at          15958785000
 test target 1 - Starting Memory Write, at          15959055000
 test target 1 - Starting Memory Write, at          15959325000
 test target 1 - Starting Memory Write, at          15959715000
 test target 1 - Starting Memory Write, at          15960105000
 test target 1 - Starting Memory Read, at          15967245000
 test target 1 - Starting Memory Read, at          15968505000
 test target 1 - Starting Memory Read, at          15969735000
 test target 1 - Starting Memory Read, at          15970965000
 test target 1 - Starting Memory Read, at          15972225000
 test target 1 - Starting Memory Read, at          15973455000
 test target 1 - Starting Memory Read, at          15974685000
 test target 1 - Starting Memory Read, at          15975945000
 test target 1 - Starting Memory Read, at          15977175000
 test target 1 - Starting Memory Read, at          15978405000
 test target 1 - Starting Memory Read, at          15979665000
 test target 1 - Starting Memory Read, at          15980895000
 test target 1 - Starting Memory Read, at          15982125000
 test target 1 - Starting Memory Read, at          15983385000
 test target 1 - Starting Memory Read, at          15984615000
 test target 1 - Starting Memory Read, at          15985845000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          15987015000
 test target 1 - Starting Memory Read, at          15987255000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          15988875000
 test target 1 - Starting Memory Read, at          15990975000
 test target 1 - Starting Memory Read, at          15991695000
 test target 1 - Starting Memory Read, at          15992445000
 test target 1 - Starting Memory Read, at          15993285000
 test target 1 - Starting Memory Read, at          15994125000
 test target 1 - Starting Memory Read, at          15995415000
 test target 1 - Starting Memory Read, at          15996585000
 test target 1 - Starting Memory Read, at          15997455000
 test target 1 - Starting Memory Read, at          16000665000
 test target 1 - Starting Memory Read, at          16003425000
 test target 1 - Starting Memory Read, at          16004295000
 test target 1 - Starting Memory Read, at          16005135000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          16006305000
 test master 1 - Starting Memory Write, at          16006635000
 test target 1 - Starting Memory Write, at          16006635000
 test target 1 - Starting Memory Write, at          16006875000
 test target 1 - Starting Memory Read, at          16007535000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          16010235000
 test master 1 - Starting Memory Write, at          16010565000
 test target 1 - Starting Memory Write, at          16010565000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          16015485000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          16016655000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          16041225000
 test target 1 - Starting Config Write, at          16042125000
 test target 1 - Starting Config Write, at          16043025000
 test target 2 - Starting Config Write, at          16043925000
 test target 2 - Starting Config Write, at          16044825000
 test target 2 - Starting Config Write, at          16045725000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          16047615000
 test target 1 - Starting Memory Read, at          16047945000
 test target 1 - Starting Memory Write, at          16048725000
 test target 1 - Starting Memory Read, at          16049055000
 test target 1 - Starting Memory Write, at          16050165000
 test target 1 - Starting Memory Read, at          16051485000
 test target 1 - Starting Memory Read, at          16052115000
 test target 1 - Starting Memory Read, at          16052805000
 test target 1 - Starting Memory Read, at          16053525000
 test target 1 - Starting Memory Read, at          16054455000
 test target 1 - Starting Memory Read, at          16055745000
 test target 1 - Starting Memory Read, at          16056765000
 test target 1 - Starting Memory Read, at          16057935000
 test target 1 - Starting Memory Read, at          16058955000
 test target 1 - Starting Memory Read, at          16061595000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          16067895000
 test target 1 - Starting Memory Read, at          16068225000
 test target 1 - Starting Memory Write, at          16069005000
 test target 1 - Starting Memory Read, at          16069335000
 test target 1 - Starting Memory Write, at          16070445000
 test target 1 - Starting Memory Read, at          16071765000
 test target 1 - Starting Memory Read, at          16072395000
 test target 1 - Starting Memory Read, at          16073085000
 test target 1 - Starting Memory Read, at          16073805000
 test target 1 - Starting Memory Read, at          16074735000
 test target 1 - Starting Memory Read, at          16076025000
 test target 1 - Starting Memory Read, at          16077045000
 test target 1 - Starting Memory Read, at          16078215000
 test target 1 - Starting Memory Read, at          16079235000
 test target 1 - Starting Memory Read, at          16081875000
 test target 1 - Starting Memory Write, at          16088175000
 test target 1 - Starting Memory Read, at          16088505000
 test target 1 - Starting Memory Write, at          16089285000
 test target 1 - Starting Memory Read, at          16089615000
 test target 1 - Starting Memory Write, at          16090725000
 test target 1 - Starting Memory Read, at          16092045000
 test target 1 - Starting Memory Read, at          16092675000
 test target 1 - Starting Memory Read, at          16093365000
 test target 1 - Starting Memory Read, at          16094085000
 test target 1 - Starting Memory Read, at          16095015000
 test target 1 - Starting Memory Read, at          16096305000
 test target 1 - Starting Memory Read, at          16097325000
 test target 1 - Starting Memory Read, at          16098495000
 test target 1 - Starting Memory Read, at          16099515000
 test target 1 - Starting Memory Read, at          16102155000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          16113825000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          16120065000
 test target 1 - Starting Memory Write, at          16120875000
 test target 1 - Starting Memory Read, at          16121445000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          16122795000
 test target 1 - Starting Config Write, at          16124685000
 test target 1 - Starting Memory Read, at          16125345000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          16126785000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          16128885000
 test target 1 - Starting Memory Write, at          16130055000
 test target 1 - Starting Memory Write, at          16130415000
 test target 1 - Starting Memory Read, at          16130745000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          16133025000
 test target 1 - Starting Memory Write, at          16136055000
 test target 1 - Starting Memory Write, at          16136535000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          16140585000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          16142505000
 test target 1 - Starting Memory Read, at          16143885000
 test target 1 - Starting Memory Read, at          16145025000
 test target 1 - Starting Memory Read, at          16146855000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          16152885000
 test target 2 - Starting Config Write, at          16153785000
 test target 1 - Starting Memory Write, at          16154475000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          16154715000
 test target 1 - Starting Memory Write, at          16155735000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          16155975000
 test target 1 - Starting Memory Write, at          16156995000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          16158465000
 test target 1 - Starting Memory Read, at          16160655000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          16160895000
 test target 1 - Starting Memory Read, at          16163055000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          16164885000
 test master 2 - Starting Memory Write, at          16164885000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          16164945000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16165845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16165875000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16166175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16166205000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16167075000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16167105000
 test target 1 - Starting Memory Write, at          16168875000
 test master 2 - Starting Memory Write, at          16168875000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16170645000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16170675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16172325000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16172355000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16174005000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16174035000
 test target 1 - Starting Memory Write, at          16176045000
 test master 2 - Starting Memory Write, at          16176045000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          16176105000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16177785000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16177815000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16178115000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16178145000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16179015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16179045000
 test target 1 - Starting Memory Write, at          16180215000
 test master 2 - Starting Memory Write, at          16180215000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          16183155000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          16184745000
 test master 1 - Starting Memory Read, at          16185165000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          16185315000
 test target 1 - Starting Config Write, at          16187805000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          16190295000
 test target 1 - Starting Memory Write, at          16190565000
 test target 1 - Starting Memory Write, at          16190835000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          16191405000
 test target 1 - Starting Memory Write, at          16191705000
 test target 1 - Starting Memory Write, at          16192005000
 test target 1 - Starting Memory Write, at          16192575000
 test target 1 - Starting Memory Write, at          16192965000
 test target 1 - Starting Memory Write, at          16193535000
 test target 1 - Starting Memory Write, at          16194285000
 test target 1 - Starting Memory Write, at          16194585000
 test target 1 - Starting Memory Write, at          16195335000
 test target 1 - Starting Memory Write, at          16195755000
 test target 1 - Starting Memory Write, at          16196385000
 test target 1 - Starting Memory Write, at          16200825000
 test target 1 - Starting Memory Write, at          16201125000
 test target 1 - Starting Memory Write, at          16201425000
 test target 1 - Starting Memory Write, at          16201845000
 test target 1 - Starting Memory Write, at          16202265000
 test target 1 - Starting Memory Read, at          16209435000
 test target 1 - Starting Memory Read, at          16210665000
 test target 1 - Starting Memory Read, at          16211895000
 test target 1 - Starting Memory Read, at          16213125000
 test target 1 - Starting Memory Read, at          16214385000
 test target 1 - Starting Memory Read, at          16215615000
 test target 1 - Starting Memory Read, at          16216845000
 test target 1 - Starting Memory Read, at          16218105000
 test target 1 - Starting Memory Read, at          16219335000
 test target 1 - Starting Memory Read, at          16220565000
 test target 1 - Starting Memory Read, at          16221825000
 test target 1 - Starting Memory Read, at          16223055000
 test target 1 - Starting Memory Read, at          16224285000
 test target 1 - Starting Memory Read, at          16225545000
 test target 1 - Starting Memory Read, at          16226775000
 test target 1 - Starting Memory Read, at          16228005000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          16229175000
 test target 1 - Starting Memory Read, at          16229445000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          16231035000
 test target 1 - Starting Memory Read, at          16233165000
 test target 1 - Starting Memory Read, at          16233855000
 test target 1 - Starting Memory Read, at          16234605000
 test target 1 - Starting Memory Read, at          16235445000
 test target 1 - Starting Memory Read, at          16236285000
 test target 1 - Starting Memory Read, at          16237575000
 test target 1 - Starting Memory Read, at          16238865000
 test target 1 - Starting Memory Read, at          16239885000
 test target 1 - Starting Memory Read, at          16243125000
 test target 1 - Starting Memory Read, at          16245975000
 test target 1 - Starting Memory Read, at          16246935000
 test target 1 - Starting Memory Read, at          16247895000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          16249185000
 test master 1 - Starting Memory Write, at          16249545000
 test target 1 - Starting Memory Write, at          16249545000
 test target 1 - Starting Memory Write, at          16249815000
 test target 1 - Starting Memory Read, at          16250505000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          16253145000
 test master 1 - Starting Memory Write, at          16253505000
 test target 1 - Starting Memory Write, at          16253505000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16258635000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          16258935000
 test master 2 - Starting Memory Read, at          16259115000
 test master 2 - Starting Memory Read, at          16259295000
 test master 2 - Starting Memory Read, at          16259565000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16261185000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          16261695000
 test master 2 - Starting Memory Read, at          16261875000
 test master 2 - Starting Memory Read, at          16262325000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16263705000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16264395000
 test master 2 - Starting Memory Read Line Multiple, at          16264575000
 test master 2 - Starting Memory Read Line Multiple, at          16264755000
 test master 2 - Starting Memory Read Line Multiple, at          16264935000
 test master 2 - Starting Memory Read Line Multiple, at          16265265000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16267245000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16279755000
 test master 2 - Starting Memory Read Line Multiple, at          16279935000
 test master 2 - Starting Memory Read Line Multiple, at          16280115000
 test master 2 - Starting Memory Read Line Multiple, at          16280295000
 test master 2 - Starting Memory Read Line Multiple, at          16280625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16281525000
 test master 2 - Starting Memory Read Line Multiple, at          16281705000
 test master 2 - Starting Memory Read Line Multiple, at          16281885000
 test master 2 - Starting Memory Read Line Multiple, at          16282065000
 test master 2 - Starting Memory Read Line Multiple, at          16282425000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16283325000
 test master 2 - Starting Memory Read Line Multiple, at          16283505000
 test master 2 - Starting Memory Read Line Multiple, at          16283685000
 test master 2 - Starting Memory Read Line Multiple, at          16283865000
 test master 2 - Starting Memory Read Line Multiple, at          16284225000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16285125000
 test master 2 - Starting Memory Read Line Multiple, at          16285305000
 test master 2 - Starting Memory Read Line Multiple, at          16285485000
 test master 2 - Starting Memory Read Line Multiple, at          16285665000
 test master 2 - Starting Memory Read Line Multiple, at          16286025000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16286925000
 test master 2 - Starting Memory Read Line Multiple, at          16287105000
 test master 2 - Starting Memory Read Line Multiple, at          16287285000
 test master 2 - Starting Memory Read Line Multiple, at          16287465000
 test master 2 - Starting Memory Read Line Multiple, at          16287825000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16288725000
 test master 2 - Starting Memory Read Line Multiple, at          16288905000
 test master 2 - Starting Memory Read Line Multiple, at          16289085000
 test master 2 - Starting Memory Read Line Multiple, at          16289265000
 test master 2 - Starting Memory Read Line Multiple, at          16289625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16290525000
 test master 2 - Starting Memory Read Line Multiple, at          16290705000
 test master 2 - Starting Memory Read Line Multiple, at          16290885000
 test master 2 - Starting Memory Read Line Multiple, at          16291065000
 test master 2 - Starting Memory Read Line Multiple, at          16291425000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16292325000
 test master 2 - Starting Memory Read Line Multiple, at          16292505000
 test master 2 - Starting Memory Read Line Multiple, at          16292685000
 test master 2 - Starting Memory Read Line Multiple, at          16292865000
 test master 2 - Starting Memory Read Line Multiple, at          16293225000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          16294125000
 test master 2 - Starting Memory Read Line, at          16294305000
 test master 2 - Starting Memory Read Line, at          16294485000
 test master 2 - Starting Memory Read Line, at          16294785000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          16295325000
 test master 2 - Starting Memory Read Line, at          16295505000
 test master 2 - Starting Memory Read Line, at          16295955000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16297095000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16298625000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16301475000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16303395000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          16308525000
 test master 2 - Starting Memory Write, at          16308825000
 test master 2 - Starting Memory Write, at          16309125000
 test master 2 - Starting Memory Write, at          16309425000
 test master 2 - Starting Memory Write, at          16309725000
 test master 1 - Starting Memory Read, at          16310145000
 test master 1 - Starting Memory Read, at          16310505000
 test master 1 - Starting Memory Read, at          16311045000
 test master 1 - Starting Memory Read, at          16311405000
 test master 1 - Starting Memory Read, at          16311945000
 test master 1 - Starting Memory Read, at          16312305000
 test master 2 - Starting Memory Write, at          16313565000
 test master 2 - Starting Memory Write, at          16313865000
 test master 2 - Starting Memory Write, at          16314165000
 test master 2 - Starting Memory Write, at          16314465000
 test master 2 - Starting Memory Write, at          16314765000
 test master 1 - Starting Memory Read, at          16315185000
 test master 1 - Starting Memory Read, at          16315545000
 test master 1 - Starting Memory Read, at          16316085000
 test master 1 - Starting Memory Read, at          16316445000
 test master 1 - Starting Memory Read, at          16316985000
 test master 1 - Starting Memory Read, at          16317345000
 test master 2 - Starting Memory Write, at          16319085000
 test master 2 - Starting Memory Write, at          16320225000
 test master 2 - Starting Memory Write, at          16321365000
 test master 2 - Starting Memory Write, at          16322505000
 test master 2 - Starting Memory Write, at          16324725000
 test master 2 - Starting Memory Write, at          16325865000
 test master 2 - Starting Memory Write, at          16327005000
 test master 2 - Starting Memory Write, at          16328145000
 test master 2 - Starting Memory Write, at          16330365000
 test master 2 - Starting Memory Write, at          16332435000
 test master 2 - Starting Memory Write, at          16334475000
 test master 2 - Starting Memory Write, at          16336515000
 test master 2 - Starting Memory Write, at          16339635000
 test master 2 - Starting Memory Write, at          16341915000
 test master 2 - Starting Memory Write, at          16344195000
 test master 2 - Starting Memory Write, at          16346475000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          16350885000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16350915000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16352985000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          16353285000
 test master 2 - Starting Memory Read, at          16353465000
 test master 2 - Starting Memory Read, at          16353645000
 test master 2 - Starting Memory Read, at          16353915000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16355535000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          16356015000
 test master 2 - Starting Memory Read, at          16356195000
 test master 2 - Starting Memory Read, at          16356645000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16358025000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16358715000
 test master 2 - Starting Memory Read Line Multiple, at          16358895000
 test master 2 - Starting Memory Read Line Multiple, at          16359075000
 test master 2 - Starting Memory Read Line Multiple, at          16359255000
 test master 2 - Starting Memory Read Line Multiple, at          16359585000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16361565000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16374075000
 test master 2 - Starting Memory Read Line Multiple, at          16374255000
 test master 2 - Starting Memory Read Line Multiple, at          16374435000
 test master 2 - Starting Memory Read Line Multiple, at          16374615000
 test master 2 - Starting Memory Read Line Multiple, at          16374945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16375845000
 test master 2 - Starting Memory Read Line Multiple, at          16376025000
 test master 2 - Starting Memory Read Line Multiple, at          16376205000
 test master 2 - Starting Memory Read Line Multiple, at          16376385000
 test master 2 - Starting Memory Read Line Multiple, at          16376745000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16377645000
 test master 2 - Starting Memory Read Line Multiple, at          16377825000
 test master 2 - Starting Memory Read Line Multiple, at          16378005000
 test master 2 - Starting Memory Read Line Multiple, at          16378185000
 test master 2 - Starting Memory Read Line Multiple, at          16378545000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16379445000
 test master 2 - Starting Memory Read Line Multiple, at          16379625000
 test master 2 - Starting Memory Read Line Multiple, at          16379805000
 test master 2 - Starting Memory Read Line Multiple, at          16379985000
 test master 2 - Starting Memory Read Line Multiple, at          16380345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16381245000
 test master 2 - Starting Memory Read Line Multiple, at          16381425000
 test master 2 - Starting Memory Read Line Multiple, at          16381605000
 test master 2 - Starting Memory Read Line Multiple, at          16381785000
 test master 2 - Starting Memory Read Line Multiple, at          16382145000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16383045000
 test master 2 - Starting Memory Read Line Multiple, at          16383225000
 test master 2 - Starting Memory Read Line Multiple, at          16383405000
 test master 2 - Starting Memory Read Line Multiple, at          16383585000
 test master 2 - Starting Memory Read Line Multiple, at          16383945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16384845000
 test master 2 - Starting Memory Read Line Multiple, at          16385025000
 test master 2 - Starting Memory Read Line Multiple, at          16385205000
 test master 2 - Starting Memory Read Line Multiple, at          16385385000
 test master 2 - Starting Memory Read Line Multiple, at          16385745000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16386645000
 test master 2 - Starting Memory Read Line Multiple, at          16386825000
 test master 2 - Starting Memory Read Line Multiple, at          16387005000
 test master 2 - Starting Memory Read Line Multiple, at          16387185000
 test master 2 - Starting Memory Read Line Multiple, at          16387545000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          16388445000
 test master 2 - Starting Memory Read Line, at          16388625000
 test master 2 - Starting Memory Read Line, at          16388805000
 test master 2 - Starting Memory Read Line, at          16389105000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          16389645000
 test master 2 - Starting Memory Read Line, at          16389825000
 test master 2 - Starting Memory Read Line, at          16390275000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16391415000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16392945000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16395795000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16397715000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          16402845000
 test master 2 - Starting Memory Write, at          16403145000
 test master 2 - Starting Memory Write, at          16403445000
 test master 2 - Starting Memory Write, at          16403745000
 test master 2 - Starting Memory Write, at          16404045000
 test master 1 - Starting Memory Read, at          16404465000
 test master 1 - Starting Memory Read, at          16404825000
 test master 1 - Starting Memory Read, at          16405365000
 test master 1 - Starting Memory Read, at          16405725000
 test master 1 - Starting Memory Read, at          16406265000
 test master 1 - Starting Memory Read, at          16406625000
 test master 2 - Starting Memory Write, at          16407885000
 test master 2 - Starting Memory Write, at          16408185000
 test master 2 - Starting Memory Write, at          16408485000
 test master 2 - Starting Memory Write, at          16408785000
 test master 2 - Starting Memory Write, at          16409085000
 test master 1 - Starting Memory Read, at          16409505000
 test master 1 - Starting Memory Read, at          16409865000
 test master 1 - Starting Memory Read, at          16410405000
 test master 1 - Starting Memory Read, at          16410765000
 test master 1 - Starting Memory Read, at          16411305000
 test master 1 - Starting Memory Read, at          16411665000
 test master 2 - Starting Memory Write, at          16413405000
 test master 2 - Starting Memory Write, at          16414545000
 test master 2 - Starting Memory Write, at          16415685000
 test master 2 - Starting Memory Write, at          16416825000
 test master 2 - Starting Memory Write, at          16419045000
 test master 2 - Starting Memory Write, at          16420185000
 test master 2 - Starting Memory Write, at          16421325000
 test master 2 - Starting Memory Write, at          16422465000
 test master 2 - Starting Memory Write, at          16424685000
 test master 2 - Starting Memory Write, at          16426755000
 test master 2 - Starting Memory Write, at          16428795000
 test master 2 - Starting Memory Write, at          16430835000
 test master 2 - Starting Memory Write, at          16433955000
 test master 2 - Starting Memory Write, at          16436235000
 test master 2 - Starting Memory Write, at          16438515000
 test master 2 - Starting Memory Write, at          16440795000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          16445205000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16445235000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16447305000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          16447605000
 test master 2 - Starting Memory Read, at          16447785000
 test master 2 - Starting Memory Read, at          16447965000
 test master 2 - Starting Memory Read, at          16448235000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16449855000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          16450335000
 test master 2 - Starting Memory Read, at          16450515000
 test master 2 - Starting Memory Read, at          16450965000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16452345000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16453035000
 test master 2 - Starting Memory Read Line Multiple, at          16453215000
 test master 2 - Starting Memory Read Line Multiple, at          16453395000
 test master 2 - Starting Memory Read Line Multiple, at          16453575000
 test master 2 - Starting Memory Read Line Multiple, at          16453905000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16455885000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16468395000
 test master 2 - Starting Memory Read Line Multiple, at          16468575000
 test master 2 - Starting Memory Read Line Multiple, at          16468755000
 test master 2 - Starting Memory Read Line Multiple, at          16468935000
 test master 2 - Starting Memory Read Line Multiple, at          16469265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16470165000
 test master 2 - Starting Memory Read Line Multiple, at          16470345000
 test master 2 - Starting Memory Read Line Multiple, at          16470525000
 test master 2 - Starting Memory Read Line Multiple, at          16470705000
 test master 2 - Starting Memory Read Line Multiple, at          16471065000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16471965000
 test master 2 - Starting Memory Read Line Multiple, at          16472145000
 test master 2 - Starting Memory Read Line Multiple, at          16472325000
 test master 2 - Starting Memory Read Line Multiple, at          16472505000
 test master 2 - Starting Memory Read Line Multiple, at          16472865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16473765000
 test master 2 - Starting Memory Read Line Multiple, at          16473945000
 test master 2 - Starting Memory Read Line Multiple, at          16474125000
 test master 2 - Starting Memory Read Line Multiple, at          16474305000
 test master 2 - Starting Memory Read Line Multiple, at          16474665000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16475565000
 test master 2 - Starting Memory Read Line Multiple, at          16475745000
 test master 2 - Starting Memory Read Line Multiple, at          16475925000
 test master 2 - Starting Memory Read Line Multiple, at          16476105000
 test master 2 - Starting Memory Read Line Multiple, at          16476465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16477365000
 test master 2 - Starting Memory Read Line Multiple, at          16477545000
 test master 2 - Starting Memory Read Line Multiple, at          16477725000
 test master 2 - Starting Memory Read Line Multiple, at          16477905000
 test master 2 - Starting Memory Read Line Multiple, at          16478265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16479165000
 test master 2 - Starting Memory Read Line Multiple, at          16479345000
 test master 2 - Starting Memory Read Line Multiple, at          16479525000
 test master 2 - Starting Memory Read Line Multiple, at          16479705000
 test master 2 - Starting Memory Read Line Multiple, at          16480065000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16480965000
 test master 2 - Starting Memory Read Line Multiple, at          16481145000
 test master 2 - Starting Memory Read Line Multiple, at          16481325000
 test master 2 - Starting Memory Read Line Multiple, at          16481505000
 test master 2 - Starting Memory Read Line Multiple, at          16481865000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          16482765000
 test master 2 - Starting Memory Read Line, at          16482945000
 test master 2 - Starting Memory Read Line, at          16483125000
 test master 2 - Starting Memory Read Line, at          16483425000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          16483965000
 test master 2 - Starting Memory Read Line, at          16484145000
 test master 2 - Starting Memory Read Line, at          16484595000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16485735000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16487265000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16490115000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16492035000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          16497165000
 test master 2 - Starting Memory Write, at          16497465000
 test master 2 - Starting Memory Write, at          16497765000
 test master 2 - Starting Memory Write, at          16498065000
 test master 2 - Starting Memory Write, at          16498365000
 test master 1 - Starting Memory Read, at          16498785000
 test master 1 - Starting Memory Read, at          16499145000
 test master 1 - Starting Memory Read, at          16499685000
 test master 1 - Starting Memory Read, at          16500045000
 test master 1 - Starting Memory Read, at          16500585000
 test master 1 - Starting Memory Read, at          16500945000
 test master 2 - Starting Memory Write, at          16502205000
 test master 2 - Starting Memory Write, at          16502505000
 test master 2 - Starting Memory Write, at          16502805000
 test master 2 - Starting Memory Write, at          16503105000
 test master 2 - Starting Memory Write, at          16503405000
 test master 1 - Starting Memory Read, at          16503825000
 test master 1 - Starting Memory Read, at          16504185000
 test master 1 - Starting Memory Read, at          16504725000
 test master 1 - Starting Memory Read, at          16505085000
 test master 1 - Starting Memory Read, at          16505625000
 test master 1 - Starting Memory Read, at          16505985000
 test master 2 - Starting Memory Write, at          16507725000
 test master 2 - Starting Memory Write, at          16508865000
 test master 2 - Starting Memory Write, at          16510005000
 test master 2 - Starting Memory Write, at          16511145000
 test master 2 - Starting Memory Write, at          16513365000
 test master 2 - Starting Memory Write, at          16514505000
 test master 2 - Starting Memory Write, at          16515645000
 test master 2 - Starting Memory Write, at          16516785000
 test master 2 - Starting Memory Write, at          16519005000
 test master 2 - Starting Memory Write, at          16521075000
 test master 2 - Starting Memory Write, at          16523115000
 test master 2 - Starting Memory Write, at          16525155000
 test master 2 - Starting Memory Write, at          16528275000
 test master 2 - Starting Memory Write, at          16530555000
 test master 2 - Starting Memory Write, at          16532835000
 test master 2 - Starting Memory Write, at          16535115000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          16539525000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16539555000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16541625000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          16541925000
 test master 2 - Starting Memory Read, at          16542105000
 test master 2 - Starting Memory Read, at          16542285000
 test master 2 - Starting Memory Read, at          16542555000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16544175000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          16544655000
 test master 2 - Starting Memory Read, at          16544835000
 test master 2 - Starting Memory Read, at          16545285000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16546665000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16547355000
 test master 2 - Starting Memory Read Line Multiple, at          16547535000
 test master 2 - Starting Memory Read Line Multiple, at          16547715000
 test master 2 - Starting Memory Read Line Multiple, at          16547895000
 test master 2 - Starting Memory Read Line Multiple, at          16548225000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16550205000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16562715000
 test master 2 - Starting Memory Read Line Multiple, at          16562895000
 test master 2 - Starting Memory Read Line Multiple, at          16563075000
 test master 2 - Starting Memory Read Line Multiple, at          16563255000
 test master 2 - Starting Memory Read Line Multiple, at          16563585000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16564485000
 test master 2 - Starting Memory Read Line Multiple, at          16564665000
 test master 2 - Starting Memory Read Line Multiple, at          16564845000
 test master 2 - Starting Memory Read Line Multiple, at          16565025000
 test master 2 - Starting Memory Read Line Multiple, at          16565385000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16566285000
 test master 2 - Starting Memory Read Line Multiple, at          16566465000
 test master 2 - Starting Memory Read Line Multiple, at          16566645000
 test master 2 - Starting Memory Read Line Multiple, at          16566825000
 test master 2 - Starting Memory Read Line Multiple, at          16567185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16568085000
 test master 2 - Starting Memory Read Line Multiple, at          16568265000
 test master 2 - Starting Memory Read Line Multiple, at          16568445000
 test master 2 - Starting Memory Read Line Multiple, at          16568625000
 test master 2 - Starting Memory Read Line Multiple, at          16568985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16569885000
 test master 2 - Starting Memory Read Line Multiple, at          16570065000
 test master 2 - Starting Memory Read Line Multiple, at          16570245000
 test master 2 - Starting Memory Read Line Multiple, at          16570425000
 test master 2 - Starting Memory Read Line Multiple, at          16570785000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16571685000
 test master 2 - Starting Memory Read Line Multiple, at          16571865000
 test master 2 - Starting Memory Read Line Multiple, at          16572045000
 test master 2 - Starting Memory Read Line Multiple, at          16572225000
 test master 2 - Starting Memory Read Line Multiple, at          16572585000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16573485000
 test master 2 - Starting Memory Read Line Multiple, at          16573665000
 test master 2 - Starting Memory Read Line Multiple, at          16573845000
 test master 2 - Starting Memory Read Line Multiple, at          16574025000
 test master 2 - Starting Memory Read Line Multiple, at          16574385000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          16575285000
 test master 2 - Starting Memory Read Line Multiple, at          16575465000
 test master 2 - Starting Memory Read Line Multiple, at          16575645000
 test master 2 - Starting Memory Read Line Multiple, at          16575825000
 test master 2 - Starting Memory Read Line Multiple, at          16576185000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          16577085000
 test master 2 - Starting Memory Read Line, at          16577265000
 test master 2 - Starting Memory Read Line, at          16577445000
 test master 2 - Starting Memory Read Line, at          16577745000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          16578285000
 test master 2 - Starting Memory Read Line, at          16578465000
 test master 2 - Starting Memory Read Line, at          16578915000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16580055000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16581585000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16584435000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          16586355000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          16591485000
 test master 2 - Starting Memory Write, at          16591785000
 test master 2 - Starting Memory Write, at          16592085000
 test master 2 - Starting Memory Write, at          16592385000
 test master 2 - Starting Memory Write, at          16592685000
 test master 1 - Starting Memory Read, at          16593105000
 test master 1 - Starting Memory Read, at          16593465000
 test master 1 - Starting Memory Read, at          16594005000
 test master 1 - Starting Memory Read, at          16594365000
 test master 1 - Starting Memory Read, at          16594905000
 test master 1 - Starting Memory Read, at          16595265000
 test master 2 - Starting Memory Write, at          16596525000
 test master 2 - Starting Memory Write, at          16596825000
 test master 2 - Starting Memory Write, at          16597125000
 test master 2 - Starting Memory Write, at          16597425000
 test master 2 - Starting Memory Write, at          16597725000
 test master 1 - Starting Memory Read, at          16598145000
 test master 1 - Starting Memory Read, at          16598505000
 test master 1 - Starting Memory Read, at          16599045000
 test master 1 - Starting Memory Read, at          16599405000
 test master 1 - Starting Memory Read, at          16599945000
 test master 1 - Starting Memory Read, at          16600305000
 test master 2 - Starting Memory Write, at          16602045000
 test master 2 - Starting Memory Write, at          16603185000
 test master 2 - Starting Memory Write, at          16604325000
 test master 2 - Starting Memory Write, at          16605465000
 test master 2 - Starting Memory Write, at          16607685000
 test master 2 - Starting Memory Write, at          16608825000
 test master 2 - Starting Memory Write, at          16609965000
 test master 2 - Starting Memory Write, at          16611105000
 test master 2 - Starting Memory Write, at          16613325000
 test master 2 - Starting Memory Write, at          16615395000
 test master 2 - Starting Memory Write, at          16617435000
 test master 2 - Starting Memory Write, at          16619475000
 test master 2 - Starting Memory Write, at          16622595000
 test master 2 - Starting Memory Write, at          16624875000
 test master 2 - Starting Memory Write, at          16627155000
 test master 2 - Starting Memory Write, at          16629435000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          16633845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16633875000
 test master 1 - Starting Memory Read, at          16635945000
 test master 1 - Starting Memory Read, at          16636335000
 test master 1 - Starting Memory Read, at          16637505000
 test master 1 - Starting Memory Read, at          16637895000
 test master 1 - Starting Memory Read Line, at          16639125000
 test master 1 - Starting Memory Read Line, at          16639515000
 test master 1 - Starting Memory Read Line, at          16640745000
 test master 1 - Starting Memory Read Line, at          16641225000
 test master 1 - Starting Memory Read Line, at          16642485000
 test master 1 - Starting Memory Read Line, at          16643115000
 test master 1 - Starting Memory Read Line, at          16644585000
 test master 1 - Starting Memory Read Line, at          16645215000
 test master 1 - Starting Memory Read Line Multiple, at          16646685000
 test master 1 - Starting Memory Read Line Multiple, at          16647555000
 test master 1 - Starting Memory Read Line Multiple, at          16649385000
 test master 1 - Starting Memory Read Line Multiple, at          16650255000
 test master 1 - Starting Memory Read Line, at          16652085000
 test master 1 - Starting Memory Read Line, at          16652715000
 test master 1 - Starting Memory Read, at          16655175000
 test master 1 - Starting Memory Read, at          16655565000
 test target 1 - Starting Config Write, at          16658745000
 test master 1 - Starting Memory Write, at          16659405000
 test master 1 - Starting Memory Write, at          16666845000
 test master 1 - Starting Memory Write, at          16671915000
 test master 1 - Starting Memory Write, at          16678875000
 test master 1 - Starting Memory Write, at          16683795000
 test master 1 - Starting Memory Read Line, at          16691235000
 test master 1 - Starting Memory Write, at          16696695000
 test master 1 - Starting Memory Read Line, at          16704135000
 test target 1 - Starting Config Write, at          16711125000
 test master 1 - Starting Memory Write, at          16711785000
 test master 1 - Starting Memory Write, at          16711905000
 test master 1 - Starting Memory Write, at          16712205000
 test master 1 - Starting Memory Read, at          16712325000
 test master 1 - Starting Memory Write, at          16712715000
 test master 1 - Starting Memory Read, at          16712835000
 test master 1 - Starting Memory Write, at          16714425000
 test master 1 - Starting Memory Write, at          16726935000
 test master 2 - Starting Memory Read Line, at          16739535000
 test master 2 - Starting Memory Read Line, at          16740135000
 test master 2 - Starting Memory Read Line, at          16740705000
 test master 2 - Starting Memory Read Line, at          16741305000
 test master 1 - Starting Memory Write, at          16741965000
 test master 1 - Starting Memory Write, at          16742265000
 test master 1 - Starting Memory Write, at          16742595000
 test master 2 - Starting Memory Read Line, at          16743045000
 test master 2 - Starting Memory Read Line, at          16743435000
 test master 2 - Starting Memory Read Line, at          16743735000
 test master 2 - Starting Memory Read Line, at          16744125000
 test master 2 - Starting Memory Read Line Multiple, at          16744455000
 test master 2 - Starting Memory Read Line Multiple, at          16744845000
 test master 1 - Starting Memory Write, at          16746735000
 test master 1 - Starting Memory Write, at          16747035000
 test master 2 - Starting Memory Read, at          16747485000
 test master 2 - Starting Memory Read, at          16747875000
 test master 2 - Starting Memory Read, at          16748175000
 test master 2 - Starting Memory Read, at          16748565000
 test master 1 - Starting Memory Write, at          16750215000
 test master 1 - Starting Memory Read, at          16750395000
 test master 1 - Starting Memory Write, at          16750575000
 test master 1 - Starting Memory Read, at          16750785000
 test master 1 - Starting Memory Write, at          16750995000
 test master 1 - Starting Memory Read, at          16751175000
 test master 1 - Starting Memory Read, at          16751385000
 test master 1 - Starting Memory Write, at          16751595000
 test master 1 - Starting Memory Write, at          16751775000
 test master 1 - Starting Memory Read, at          16751955000
 test master 1 - Starting Memory Write, at          16752135000
 test master 1 - Starting Memory Write, at          16752345000
 test master 1 - Starting Memory Write, at          16752555000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          16756875000
 test target 1 - Starting Memory Write, at          16757145000
 test master 1 - Starting Memory Write, at          16757385000
 test target 1 - Starting Memory Write, at          16757565000
 test target 1 - Starting Memory Write, at          16757835000
 test target 1 - Starting Memory Write, at          16758105000
 test master 1 - Starting Memory Write, at          16758465000
 test target 1 - Starting Memory Write, at          16759035000
 test target 1 - Starting Memory Write, at          16759695000
 test target 1 - Starting Memory Write, at          16759995000
 test master 1 - Starting Memory Write, at          16760265000
 test target 1 - Starting Memory Write, at          16760685000
 test target 1 - Starting Memory Write, at          16760985000
 test target 1 - Starting Memory Write, at          16761285000
 test master 1 - Starting Memory Write, at          16761885000
 test target 1 - Starting Memory Write, at          16762845000
 test target 1 - Starting Memory Write, at          16764015000
 test target 1 - Starting Memory Write, at          16764285000
 test master 1 - Starting Memory Read, at          16764525000
 test target 1 - Starting Memory Write, at          16764705000
 test master 1 - Starting Memory Read, at          16764945000
 test target 1 - Starting Memory Write, at          16765125000
 test master 1 - Starting Memory Read, at          16765365000
 test target 1 - Starting Memory Write, at          16765545000
 test master 1 - Starting Memory Read, at          16765785000
 test target 1 - Starting Memory Write, at          16765965000
 test master 1 - Starting Memory Read, at          16766205000
 test target 1 - Starting Memory Write, at          16766385000
 test master 1 - Starting Memory Write, at          16766625000
 test target 1 - Starting Memory Write, at          16766805000
 test target 1 - Starting Memory Write, at          16767075000
 test target 1 - Starting Memory Write, at          16767345000
 test target 1 - Starting Memory Read, at          16767675000
 test master 1 - Starting Memory Write, at          16768035000
 test master 1 - Starting Memory Read, at          16768275000
 test target 1 - Starting Memory Write, at          16768785000
 test master 1 - Starting Memory Write, at          16769235000
 test target 1 - Starting Memory Read, at          16769685000
 test target 1 - Starting Memory Write, at          16770555000
 test master 1 - Starting Memory Read, at          16770915000
 test master 1 - Starting Memory Write, at          16771305000
 test master 1 - Starting Memory Write, at          16771665000
 test master 1 - Starting Memory Read, at          16771965000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          16774485000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          16775565000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          16800585000
 test target 1 - Starting Config Write, at          16801605000
 test target 1 - Starting Config Write, at          16802595000
 test target 2 - Starting Config Write, at          16803585000
 test target 2 - Starting Config Write, at          16804605000
 test target 2 - Starting Config Write, at          16805595000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          16807575000
 test target 1 - Starting Memory Read, at          16807815000
 test target 1 - Starting Memory Write, at          16808475000
 test target 1 - Starting Memory Read, at          16808715000
 test target 1 - Starting Memory Write, at          16809795000
 test target 1 - Starting Memory Read, at          16810875000
 test target 1 - Starting Memory Read, at          16811445000
 test target 1 - Starting Memory Read, at          16812105000
 test target 1 - Starting Memory Read, at          16812645000
 test target 1 - Starting Memory Read, at          16813455000
 test target 1 - Starting Memory Read, at          16814535000
 test target 1 - Starting Memory Read, at          16815495000
 test target 1 - Starting Memory Read, at          16816575000
 test target 1 - Starting Memory Read, at          16817535000
 test target 1 - Starting Memory Read, at          16819635000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          16826115000
 test target 1 - Starting Memory Read, at          16826355000
 test target 1 - Starting Memory Write, at          16827015000
 test target 1 - Starting Memory Read, at          16827255000
 test target 1 - Starting Memory Write, at          16828335000
 test target 1 - Starting Memory Read, at          16829415000
 test target 1 - Starting Memory Read, at          16829985000
 test target 1 - Starting Memory Read, at          16830645000
 test target 1 - Starting Memory Read, at          16831185000
 test target 1 - Starting Memory Read, at          16831995000
 test target 1 - Starting Memory Read, at          16833075000
 test target 1 - Starting Memory Read, at          16834035000
 test target 1 - Starting Memory Read, at          16835115000
 test target 1 - Starting Memory Read, at          16836075000
 test target 1 - Starting Memory Read, at          16838175000
 test target 1 - Starting Memory Write, at          16844655000
 test target 1 - Starting Memory Read, at          16844895000
 test target 1 - Starting Memory Write, at          16845555000
 test target 1 - Starting Memory Read, at          16845795000
 test target 1 - Starting Memory Write, at          16846875000
 test target 1 - Starting Memory Read, at          16847955000
 test target 1 - Starting Memory Read, at          16848525000
 test target 1 - Starting Memory Read, at          16849185000
 test target 1 - Starting Memory Read, at          16849725000
 test target 1 - Starting Memory Read, at          16850535000
 test target 1 - Starting Memory Read, at          16851615000
 test target 1 - Starting Memory Read, at          16852575000
 test target 1 - Starting Memory Read, at          16853655000
 test target 1 - Starting Memory Read, at          16854615000
 test target 1 - Starting Memory Read, at          16856715000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          16869015000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          16875585000
 test target 1 - Starting Memory Write, at          16876545000
 test target 1 - Starting Memory Read, at          16876965000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          16878165000
 test target 1 - Starting Config Write, at          16880265000
 test target 1 - Starting Memory Read, at          16881015000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          16882575000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          16884735000
 test target 1 - Starting Memory Write, at          16885995000
 test target 1 - Starting Memory Write, at          16886265000
 test target 1 - Starting Memory Read, at          16886505000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          16888935000
 test target 1 - Starting Memory Write, at          16892055000
 test target 1 - Starting Memory Write, at          16892415000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          16896495000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          16898595000
 test target 1 - Starting Memory Read, at          16899975000
 test target 1 - Starting Memory Read, at          16901025000
 test target 1 - Starting Memory Read, at          16902795000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          16908855000
 test target 2 - Starting Config Write, at          16909845000
 test target 1 - Starting Memory Write, at          16910625000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          16910775000
 test target 1 - Starting Memory Write, at          16911795000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          16911945000
 test target 1 - Starting Memory Write, at          16912995000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          16914435000
 test target 1 - Starting Memory Read, at          16916745000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          16916895000
 test target 1 - Starting Memory Read, at          16919115000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          16920915000
 test master 2 - Starting Memory Write, at          16920915000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          16920975000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16921815000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16921845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16922145000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16922175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16923075000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16923105000
 test target 1 - Starting Memory Write, at          16924935000
 test master 2 - Starting Memory Write, at          16924935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16926675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16926705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16928415000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16928445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16930155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16930185000
 test target 1 - Starting Memory Write, at          16932255000
 test master 2 - Starting Memory Write, at          16932255000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          16932315000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16933965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16933995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16934295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16934325000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16935225000
*** monitor - CBE Bus Changed when TRDY Desserted, at          16935255000
 test target 1 - Starting Memory Write, at          16936455000
 test master 2 - Starting Memory Write, at          16936455000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          16939395000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          16941045000
 test master 1 - Starting Memory Read, at          16941405000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          16941555000
 test target 1 - Starting Config Write, at          16944135000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          16946535000
 test target 1 - Starting Memory Write, at          16946715000
 test target 1 - Starting Memory Write, at          16946895000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          16947405000
 test target 1 - Starting Memory Write, at          16947615000
 test target 1 - Starting Memory Write, at          16947825000
 test target 1 - Starting Memory Write, at          16948335000
 test target 1 - Starting Memory Write, at          16948605000
 test target 1 - Starting Memory Write, at          16949115000
 test target 1 - Starting Memory Write, at          16949775000
 test target 1 - Starting Memory Write, at          16949985000
 test target 1 - Starting Memory Write, at          16950675000
 test target 1 - Starting Memory Write, at          16950975000
 test target 1 - Starting Memory Write, at          16951575000
 test target 1 - Starting Memory Write, at          16957095000
 test target 1 - Starting Memory Write, at          16957305000
 test target 1 - Starting Memory Write, at          16957515000
 test target 1 - Starting Memory Write, at          16957815000
 test target 1 - Starting Memory Write, at          16958115000
 test target 1 - Starting Memory Read, at          16963485000
 test target 1 - Starting Memory Read, at          16964625000
 test target 1 - Starting Memory Read, at          16965705000
 test target 1 - Starting Memory Read, at          16966755000
 test target 1 - Starting Memory Read, at          16967805000
 test target 1 - Starting Memory Read, at          16968885000
 test target 1 - Starting Memory Read, at          16969935000
 test target 1 - Starting Memory Read, at          16970985000
 test target 1 - Starting Memory Read, at          16972065000
 test target 1 - Starting Memory Read, at          16973115000
 test target 1 - Starting Memory Read, at          16974165000
 test target 1 - Starting Memory Read, at          16975245000
 test target 1 - Starting Memory Read, at          16976295000
 test target 1 - Starting Memory Read, at          16977345000
 test target 1 - Starting Memory Read, at          16978425000
 test target 1 - Starting Memory Read, at          16979475000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          16980405000
 test target 1 - Starting Memory Read, at          16980585000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          16982505000
 test target 1 - Starting Memory Read, at          16984095000
 test target 1 - Starting Memory Read, at          16984755000
 test target 1 - Starting Memory Read, at          16985415000
 test target 1 - Starting Memory Read, at          16986255000
 test target 1 - Starting Memory Read, at          16987035000
 test target 1 - Starting Memory Read, at          16988205000
 test target 1 - Starting Memory Read, at          16989285000
 test target 1 - Starting Memory Read, at          16990275000
 test target 1 - Starting Memory Read, at          16993215000
 test target 1 - Starting Memory Read, at          16995495000
 test target 1 - Starting Memory Read, at          16996305000
 test target 1 - Starting Memory Read, at          16997115000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          16998375000
 test master 1 - Starting Memory Write, at          16998705000
 test target 1 - Starting Memory Write, at          16998705000
 test target 1 - Starting Memory Write, at          16998885000
 test target 1 - Starting Memory Read, at          16999305000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          17001645000
 test master 1 - Starting Memory Write, at          17001975000
 test target 1 - Starting Memory Write, at          17001975000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          17006985000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          17008065000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          17033085000
 test target 1 - Starting Config Write, at          17034105000
 test target 1 - Starting Config Write, at          17035095000
 test target 2 - Starting Config Write, at          17036085000
 test target 2 - Starting Config Write, at          17037105000
 test target 2 - Starting Config Write, at          17038095000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          17040075000
 test target 1 - Starting Memory Read, at          17040345000
 test target 1 - Starting Memory Write, at          17040975000
 test target 1 - Starting Memory Read, at          17041245000
 test target 1 - Starting Memory Write, at          17042295000
 test target 1 - Starting Memory Read, at          17043435000
 test target 1 - Starting Memory Read, at          17044125000
 test target 1 - Starting Memory Read, at          17044815000
 test target 1 - Starting Memory Read, at          17045505000
 test target 1 - Starting Memory Read, at          17046435000
 test target 1 - Starting Memory Read, at          17047515000
 test target 1 - Starting Memory Read, at          17048475000
 test target 1 - Starting Memory Read, at          17049555000
 test target 1 - Starting Memory Read, at          17050515000
 test target 1 - Starting Memory Read, at          17052765000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          17059215000
 test target 1 - Starting Memory Read, at          17059485000
 test target 1 - Starting Memory Write, at          17060115000
 test target 1 - Starting Memory Read, at          17060385000
 test target 1 - Starting Memory Write, at          17061435000
 test target 1 - Starting Memory Read, at          17062575000
 test target 1 - Starting Memory Read, at          17063265000
 test target 1 - Starting Memory Read, at          17063955000
 test target 1 - Starting Memory Read, at          17064645000
 test target 1 - Starting Memory Read, at          17065575000
 test target 1 - Starting Memory Read, at          17066655000
 test target 1 - Starting Memory Read, at          17067615000
 test target 1 - Starting Memory Read, at          17068695000
 test target 1 - Starting Memory Read, at          17069655000
 test target 1 - Starting Memory Read, at          17071905000
 test target 1 - Starting Memory Write, at          17078355000
 test target 1 - Starting Memory Read, at          17078625000
 test target 1 - Starting Memory Write, at          17079255000
 test target 1 - Starting Memory Read, at          17079525000
 test target 1 - Starting Memory Write, at          17080575000
 test target 1 - Starting Memory Read, at          17081715000
 test target 1 - Starting Memory Read, at          17082405000
 test target 1 - Starting Memory Read, at          17083095000
 test target 1 - Starting Memory Read, at          17083785000
 test target 1 - Starting Memory Read, at          17084715000
 test target 1 - Starting Memory Read, at          17085795000
 test target 1 - Starting Memory Read, at          17086755000
 test target 1 - Starting Memory Read, at          17087835000
 test target 1 - Starting Memory Read, at          17088795000
 test target 1 - Starting Memory Read, at          17091045000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          17103315000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          17109885000
 test target 1 - Starting Memory Write, at          17110845000
 test target 1 - Starting Memory Read, at          17111295000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          17112615000
 test target 1 - Starting Config Write, at          17114685000
 test target 1 - Starting Memory Read, at          17115435000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          17116995000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          17119155000
 test target 1 - Starting Memory Write, at          17120415000
 test target 1 - Starting Memory Write, at          17120715000
 test target 1 - Starting Memory Read, at          17120985000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          17123535000
 test target 1 - Starting Memory Write, at          17126655000
 test target 1 - Starting Memory Write, at          17127045000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          17131155000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          17133255000
 test target 1 - Starting Memory Read, at          17134635000
 test target 1 - Starting Memory Read, at          17135685000
 test target 1 - Starting Memory Read, at          17137455000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          17143515000
 test target 2 - Starting Config Write, at          17144505000
 test target 1 - Starting Memory Write, at          17145285000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          17145465000
 test target 1 - Starting Memory Write, at          17146515000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          17146695000
 test target 1 - Starting Memory Write, at          17147715000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          17149155000
 test target 1 - Starting Memory Read, at          17151465000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          17151645000
 test target 1 - Starting Memory Read, at          17153835000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          17155635000
 test master 2 - Starting Memory Write, at          17155635000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          17155695000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17156565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17156595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17156895000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17156925000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17157825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17157855000
 test target 1 - Starting Memory Write, at          17159685000
 test master 2 - Starting Memory Write, at          17159685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17161455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17161485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17163195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17163225000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17164935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17164965000
 test target 1 - Starting Memory Write, at          17167035000
 test master 2 - Starting Memory Write, at          17167035000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          17167095000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17168775000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17168805000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17169105000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17169135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17170035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17170065000
 test target 1 - Starting Memory Write, at          17171265000
 test master 2 - Starting Memory Write, at          17171265000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          17174235000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          17175885000
 test master 1 - Starting Memory Read, at          17176245000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          17176395000
 test target 1 - Starting Config Write, at          17178975000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          17181375000
 test target 1 - Starting Memory Write, at          17181585000
 test target 1 - Starting Memory Write, at          17181795000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          17182335000
 test target 1 - Starting Memory Write, at          17182575000
 test target 1 - Starting Memory Write, at          17182815000
 test target 1 - Starting Memory Write, at          17183355000
 test target 1 - Starting Memory Write, at          17183655000
 test target 1 - Starting Memory Write, at          17184195000
 test target 1 - Starting Memory Write, at          17184915000
 test target 1 - Starting Memory Write, at          17185155000
 test target 1 - Starting Memory Write, at          17185875000
 test target 1 - Starting Memory Write, at          17186205000
 test target 1 - Starting Memory Write, at          17186835000
 test target 1 - Starting Memory Write, at          17192385000
 test target 1 - Starting Memory Write, at          17192625000
 test target 1 - Starting Memory Write, at          17192865000
 test target 1 - Starting Memory Write, at          17193195000
 test target 1 - Starting Memory Write, at          17193525000
 test target 1 - Starting Memory Read, at          17198925000
 test target 1 - Starting Memory Read, at          17200065000
 test target 1 - Starting Memory Read, at          17201265000
 test target 1 - Starting Memory Read, at          17202465000
 test target 1 - Starting Memory Read, at          17203665000
 test target 1 - Starting Memory Read, at          17204865000
 test target 1 - Starting Memory Read, at          17206065000
 test target 1 - Starting Memory Read, at          17207265000
 test target 1 - Starting Memory Read, at          17208465000
 test target 1 - Starting Memory Read, at          17209665000
 test target 1 - Starting Memory Read, at          17210865000
 test target 1 - Starting Memory Read, at          17212065000
 test target 1 - Starting Memory Read, at          17213265000
 test target 1 - Starting Memory Read, at          17214465000
 test target 1 - Starting Memory Read, at          17215665000
 test target 1 - Starting Memory Read, at          17216865000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          17217945000
 test target 1 - Starting Memory Read, at          17218155000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          17220015000
 test target 1 - Starting Memory Read, at          17221635000
 test target 1 - Starting Memory Read, at          17222295000
 test target 1 - Starting Memory Read, at          17223075000
 test target 1 - Starting Memory Read, at          17223915000
 test target 1 - Starting Memory Read, at          17224695000
 test target 1 - Starting Memory Read, at          17225865000
 test target 1 - Starting Memory Read, at          17226945000
 test target 1 - Starting Memory Read, at          17227935000
 test target 1 - Starting Memory Read, at          17231025000
 test target 1 - Starting Memory Read, at          17233455000
 test target 1 - Starting Memory Read, at          17234415000
 test target 1 - Starting Memory Read, at          17235375000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          17236755000
 test master 1 - Starting Memory Write, at          17237025000
 test target 1 - Starting Memory Write, at          17237025000
 test target 1 - Starting Memory Write, at          17237235000
 test target 1 - Starting Memory Read, at          17237775000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          17240085000
 test master 1 - Starting Memory Write, at          17240355000
 test target 1 - Starting Memory Write, at          17240355000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          17245305000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          17246385000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          17271405000
 test target 1 - Starting Config Write, at          17272425000
 test target 1 - Starting Config Write, at          17273415000
 test target 2 - Starting Config Write, at          17274405000
 test target 2 - Starting Config Write, at          17275425000
 test target 2 - Starting Config Write, at          17276415000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          17278395000
 test target 1 - Starting Memory Read, at          17278695000
 test target 1 - Starting Memory Write, at          17279475000
 test target 1 - Starting Memory Read, at          17279775000
 test target 1 - Starting Memory Write, at          17280975000
 test target 1 - Starting Memory Read, at          17282115000
 test target 1 - Starting Memory Read, at          17282805000
 test target 1 - Starting Memory Read, at          17283495000
 test target 1 - Starting Memory Read, at          17284185000
 test target 1 - Starting Memory Read, at          17285115000
 test target 1 - Starting Memory Read, at          17286345000
 test target 1 - Starting Memory Read, at          17287305000
 test target 1 - Starting Memory Read, at          17288535000
 test target 1 - Starting Memory Read, at          17289495000
 test target 1 - Starting Memory Read, at          17291745000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          17298195000
 test target 1 - Starting Memory Read, at          17298495000
 test target 1 - Starting Memory Write, at          17299275000
 test target 1 - Starting Memory Read, at          17299575000
 test target 1 - Starting Memory Write, at          17300775000
 test target 1 - Starting Memory Read, at          17301915000
 test target 1 - Starting Memory Read, at          17302605000
 test target 1 - Starting Memory Read, at          17303295000
 test target 1 - Starting Memory Read, at          17303985000
 test target 1 - Starting Memory Read, at          17304915000
 test target 1 - Starting Memory Read, at          17306145000
 test target 1 - Starting Memory Read, at          17307105000
 test target 1 - Starting Memory Read, at          17308335000
 test target 1 - Starting Memory Read, at          17309295000
 test target 1 - Starting Memory Read, at          17311545000
 test target 1 - Starting Memory Write, at          17317995000
 test target 1 - Starting Memory Read, at          17318295000
 test target 1 - Starting Memory Write, at          17319075000
 test target 1 - Starting Memory Read, at          17319375000
 test target 1 - Starting Memory Write, at          17320575000
 test target 1 - Starting Memory Read, at          17321715000
 test target 1 - Starting Memory Read, at          17322405000
 test target 1 - Starting Memory Read, at          17323095000
 test target 1 - Starting Memory Read, at          17323785000
 test target 1 - Starting Memory Read, at          17324715000
 test target 1 - Starting Memory Read, at          17325945000
 test target 1 - Starting Memory Read, at          17326905000
 test target 1 - Starting Memory Read, at          17328135000
 test target 1 - Starting Memory Read, at          17329095000
 test target 1 - Starting Memory Read, at          17331345000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          17343615000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          17350185000
 test target 1 - Starting Memory Write, at          17351145000
 test target 1 - Starting Memory Read, at          17351625000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          17352915000
 test target 1 - Starting Config Write, at          17354985000
 test target 1 - Starting Memory Read, at          17355735000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          17357295000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          17359455000
 test target 1 - Starting Memory Write, at          17360715000
 test target 1 - Starting Memory Write, at          17361045000
 test target 1 - Starting Memory Read, at          17361345000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          17363835000
 test target 1 - Starting Memory Write, at          17367015000
 test target 1 - Starting Memory Write, at          17367435000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          17371575000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          17373675000
 test target 1 - Starting Memory Read, at          17375055000
 test target 1 - Starting Memory Read, at          17376225000
 test target 1 - Starting Memory Read, at          17378025000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          17384235000
 test target 2 - Starting Config Write, at          17385225000
 test target 1 - Starting Memory Write, at          17386005000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          17386215000
 test target 1 - Starting Memory Write, at          17387235000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          17387445000
 test target 1 - Starting Memory Write, at          17388495000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          17389995000
 test target 1 - Starting Memory Read, at          17392305000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          17392515000
 test target 1 - Starting Memory Read, at          17394675000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          17396475000
 test master 2 - Starting Memory Write, at          17396475000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          17396535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17397435000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17397465000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17397765000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17397795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17398695000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17398725000
 test target 1 - Starting Memory Write, at          17400555000
 test master 2 - Starting Memory Write, at          17400555000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17402355000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17402385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17404095000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17404125000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17405835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17405865000
 test target 1 - Starting Memory Write, at          17407935000
 test master 2 - Starting Memory Write, at          17407935000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          17407995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17409705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17409735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17410035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17410065000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17410965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17410995000
 test target 1 - Starting Memory Write, at          17412195000
 test master 2 - Starting Memory Write, at          17412195000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          17415195000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          17416845000
 test master 1 - Starting Memory Read, at          17417205000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          17417355000
 test target 1 - Starting Config Write, at          17419935000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          17422335000
 test target 1 - Starting Memory Write, at          17422575000
 test target 1 - Starting Memory Write, at          17422815000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          17423385000
 test target 1 - Starting Memory Write, at          17423655000
 test target 1 - Starting Memory Write, at          17423925000
 test target 1 - Starting Memory Write, at          17424495000
 test target 1 - Starting Memory Write, at          17424825000
 test target 1 - Starting Memory Write, at          17425395000
 test target 1 - Starting Memory Write, at          17426115000
 test target 1 - Starting Memory Write, at          17426385000
 test target 1 - Starting Memory Write, at          17427135000
 test target 1 - Starting Memory Write, at          17427495000
 test target 1 - Starting Memory Write, at          17428155000
 test target 1 - Starting Memory Write, at          17433735000
 test target 1 - Starting Memory Write, at          17434005000
 test target 1 - Starting Memory Write, at          17434275000
 test target 1 - Starting Memory Write, at          17434635000
 test target 1 - Starting Memory Write, at          17434995000
 test target 1 - Starting Memory Read, at          17440425000
 test target 1 - Starting Memory Read, at          17441565000
 test target 1 - Starting Memory Read, at          17442765000
 test target 1 - Starting Memory Read, at          17443965000
 test target 1 - Starting Memory Read, at          17445165000
 test target 1 - Starting Memory Read, at          17446365000
 test target 1 - Starting Memory Read, at          17447565000
 test target 1 - Starting Memory Read, at          17448765000
 test target 1 - Starting Memory Read, at          17449965000
 test target 1 - Starting Memory Read, at          17451165000
 test target 1 - Starting Memory Read, at          17452365000
 test target 1 - Starting Memory Read, at          17453565000
 test target 1 - Starting Memory Read, at          17454765000
 test target 1 - Starting Memory Read, at          17455965000
 test target 1 - Starting Memory Read, at          17457165000
 test target 1 - Starting Memory Read, at          17458365000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          17459445000
 test target 1 - Starting Memory Read, at          17459685000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          17461695000
 test target 1 - Starting Memory Read, at          17463345000
 test target 1 - Starting Memory Read, at          17464155000
 test target 1 - Starting Memory Read, at          17464935000
 test target 1 - Starting Memory Read, at          17465775000
 test target 1 - Starting Memory Read, at          17466555000
 test target 1 - Starting Memory Read, at          17467875000
 test target 1 - Starting Memory Read, at          17469105000
 test target 1 - Starting Memory Read, at          17470065000
 test target 1 - Starting Memory Read, at          17473155000
 test target 1 - Starting Memory Read, at          17475615000
 test target 1 - Starting Memory Read, at          17476575000
 test target 1 - Starting Memory Read, at          17477535000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          17478915000
 test master 1 - Starting Memory Write, at          17479215000
 test target 1 - Starting Memory Write, at          17479215000
 test target 1 - Starting Memory Write, at          17479455000
 test target 1 - Starting Memory Read, at          17480025000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          17482425000
 test master 1 - Starting Memory Write, at          17482725000
 test target 1 - Starting Memory Write, at          17482725000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          17487765000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          17488965000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          17514105000
 test target 1 - Starting Config Write, at          17515125000
 test target 1 - Starting Config Write, at          17516115000
 test target 2 - Starting Config Write, at          17517105000
 test target 2 - Starting Config Write, at          17518125000
 test target 2 - Starting Config Write, at          17519115000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          17521095000
 test target 1 - Starting Memory Read, at          17521425000
 test target 1 - Starting Memory Write, at          17522175000
 test target 1 - Starting Memory Read, at          17522505000
 test target 1 - Starting Memory Write, at          17523675000
 test target 1 - Starting Memory Read, at          17524875000
 test target 1 - Starting Memory Read, at          17525565000
 test target 1 - Starting Memory Read, at          17526255000
 test target 1 - Starting Memory Read, at          17526945000
 test target 1 - Starting Memory Read, at          17527875000
 test target 1 - Starting Memory Read, at          17529105000
 test target 1 - Starting Memory Read, at          17530065000
 test target 1 - Starting Memory Read, at          17531295000
 test target 1 - Starting Memory Read, at          17532255000
 test target 1 - Starting Memory Read, at          17534505000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          17540955000
 test target 1 - Starting Memory Read, at          17541285000
 test target 1 - Starting Memory Write, at          17542035000
 test target 1 - Starting Memory Read, at          17542365000
 test target 1 - Starting Memory Write, at          17543535000
 test target 1 - Starting Memory Read, at          17544735000
 test target 1 - Starting Memory Read, at          17545425000
 test target 1 - Starting Memory Read, at          17546115000
 test target 1 - Starting Memory Read, at          17546805000
 test target 1 - Starting Memory Read, at          17547735000
 test target 1 - Starting Memory Read, at          17548965000
 test target 1 - Starting Memory Read, at          17549925000
 test target 1 - Starting Memory Read, at          17551155000
 test target 1 - Starting Memory Read, at          17552115000
 test target 1 - Starting Memory Read, at          17554365000
 test target 1 - Starting Memory Write, at          17560815000
 test target 1 - Starting Memory Read, at          17561145000
 test target 1 - Starting Memory Write, at          17561895000
 test target 1 - Starting Memory Read, at          17562225000
 test target 1 - Starting Memory Write, at          17563395000
 test target 1 - Starting Memory Read, at          17564595000
 test target 1 - Starting Memory Read, at          17565285000
 test target 1 - Starting Memory Read, at          17565975000
 test target 1 - Starting Memory Read, at          17566665000
 test target 1 - Starting Memory Read, at          17567595000
 test target 1 - Starting Memory Read, at          17568825000
 test target 1 - Starting Memory Read, at          17569785000
 test target 1 - Starting Memory Read, at          17571015000
 test target 1 - Starting Memory Read, at          17571975000
 test target 1 - Starting Memory Read, at          17574225000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          17586495000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          17593065000
 test target 1 - Starting Memory Write, at          17594025000
 test target 1 - Starting Memory Read, at          17594535000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          17595945000
 test target 1 - Starting Config Write, at          17598015000
 test target 1 - Starting Memory Read, at          17598765000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          17600325000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          17602485000
 test target 1 - Starting Memory Write, at          17603775000
 test target 1 - Starting Memory Write, at          17604135000
 test target 1 - Starting Memory Read, at          17604465000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          17607075000
 test target 1 - Starting Memory Write, at          17610255000
 test target 1 - Starting Memory Write, at          17610705000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          17614875000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          17616975000
 test target 1 - Starting Memory Read, at          17618505000
 test target 1 - Starting Memory Read, at          17619705000
 test target 1 - Starting Memory Read, at          17621475000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          17627655000
 test target 2 - Starting Config Write, at          17628645000
 test target 1 - Starting Memory Write, at          17629425000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          17629665000
 test target 1 - Starting Memory Write, at          17630715000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          17630955000
 test target 1 - Starting Memory Write, at          17631975000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          17633475000
 test target 1 - Starting Memory Read, at          17635785000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          17636025000
 test target 1 - Starting Memory Read, at          17638155000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          17639955000
 test master 2 - Starting Memory Write, at          17639955000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          17640015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17640945000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17640975000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17641275000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17641305000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17642205000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17642235000
 test target 1 - Starting Memory Write, at          17644065000
 test master 2 - Starting Memory Write, at          17644065000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17645895000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17645925000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17647635000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17647665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17649375000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17649405000
 test target 1 - Starting Memory Write, at          17651475000
 test master 2 - Starting Memory Write, at          17651475000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          17651535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17653275000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17653305000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17653605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17653635000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17654535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17654565000
 test target 1 - Starting Memory Write, at          17655765000
 test master 2 - Starting Memory Write, at          17655765000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          17658795000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          17660445000
 test master 1 - Starting Memory Read, at          17660805000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          17660955000
 test target 1 - Starting Config Write, at          17663535000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          17665935000
 test target 1 - Starting Memory Write, at          17666205000
 test target 1 - Starting Memory Write, at          17666475000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          17667075000
 test target 1 - Starting Memory Write, at          17667375000
 test target 1 - Starting Memory Write, at          17667675000
 test target 1 - Starting Memory Write, at          17668275000
 test target 1 - Starting Memory Write, at          17668635000
 test target 1 - Starting Memory Write, at          17669235000
 test target 1 - Starting Memory Write, at          17670015000
 test target 1 - Starting Memory Write, at          17670315000
 test target 1 - Starting Memory Write, at          17671095000
 test target 1 - Starting Memory Write, at          17671485000
 test target 1 - Starting Memory Write, at          17672175000
 test target 1 - Starting Memory Write, at          17677785000
 test target 1 - Starting Memory Write, at          17678085000
 test target 1 - Starting Memory Write, at          17678385000
 test target 1 - Starting Memory Write, at          17678775000
 test target 1 - Starting Memory Write, at          17679165000
 test target 1 - Starting Memory Read, at          17684625000
 test target 1 - Starting Memory Read, at          17685885000
 test target 1 - Starting Memory Read, at          17687085000
 test target 1 - Starting Memory Read, at          17688285000
 test target 1 - Starting Memory Read, at          17689485000
 test target 1 - Starting Memory Read, at          17690685000
 test target 1 - Starting Memory Read, at          17691885000
 test target 1 - Starting Memory Read, at          17693085000
 test target 1 - Starting Memory Read, at          17694285000
 test target 1 - Starting Memory Read, at          17695485000
 test target 1 - Starting Memory Read, at          17696685000
 test target 1 - Starting Memory Read, at          17697885000
 test target 1 - Starting Memory Read, at          17699085000
 test target 1 - Starting Memory Read, at          17700285000
 test target 1 - Starting Memory Read, at          17701485000
 test target 1 - Starting Memory Read, at          17702685000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          17703765000
 test target 1 - Starting Memory Read, at          17704035000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          17706015000
 test target 1 - Starting Memory Read, at          17707695000
 test target 1 - Starting Memory Read, at          17708475000
 test target 1 - Starting Memory Read, at          17709255000
 test target 1 - Starting Memory Read, at          17710095000
 test target 1 - Starting Memory Read, at          17710875000
 test target 1 - Starting Memory Read, at          17712195000
 test target 1 - Starting Memory Read, at          17713425000
 test target 1 - Starting Memory Read, at          17714385000
 test target 1 - Starting Memory Read, at          17717475000
 test target 1 - Starting Memory Read, at          17719935000
 test target 1 - Starting Memory Read, at          17720895000
 test target 1 - Starting Memory Read, at          17721855000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          17723235000
 test master 1 - Starting Memory Write, at          17723565000
 test target 1 - Starting Memory Write, at          17723565000
 test target 1 - Starting Memory Write, at          17723835000
 test target 1 - Starting Memory Read, at          17724435000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          17726775000
 test master 1 - Starting Memory Write, at          17727105000
 test target 1 - Starting Memory Write, at          17727105000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17732415000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          17732655000
 test master 2 - Starting Memory Read, at          17732835000
 test master 2 - Starting Memory Read, at          17733045000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17734635000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          17734995000
 test master 2 - Starting Memory Read, at          17735175000
 test master 2 - Starting Memory Read, at          17735385000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17736795000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17737245000
 test master 2 - Starting Memory Read Line Multiple, at          17737425000
 test master 2 - Starting Memory Read Line Multiple, at          17737695000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17739555000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17746515000
 test master 2 - Starting Memory Read Line Multiple, at          17746695000
 test master 2 - Starting Memory Read Line Multiple, at          17746965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17747685000
 test master 2 - Starting Memory Read Line Multiple, at          17747865000
 test master 2 - Starting Memory Read Line Multiple, at          17748165000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17748885000
 test master 2 - Starting Memory Read Line Multiple, at          17749065000
 test master 2 - Starting Memory Read Line Multiple, at          17749365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17750085000
 test master 2 - Starting Memory Read Line Multiple, at          17750265000
 test master 2 - Starting Memory Read Line Multiple, at          17750565000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17751285000
 test master 2 - Starting Memory Read Line Multiple, at          17751465000
 test master 2 - Starting Memory Read Line Multiple, at          17751765000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17752485000
 test master 2 - Starting Memory Read Line Multiple, at          17752665000
 test master 2 - Starting Memory Read Line Multiple, at          17752965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17753685000
 test master 2 - Starting Memory Read Line Multiple, at          17753865000
 test master 2 - Starting Memory Read Line Multiple, at          17754165000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17754885000
 test master 2 - Starting Memory Read Line Multiple, at          17755065000
 test master 2 - Starting Memory Read Line Multiple, at          17755365000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          17756085000
 test master 2 - Starting Memory Read Line, at          17756265000
 test master 2 - Starting Memory Read Line, at          17756505000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          17756955000
 test master 2 - Starting Memory Read Line, at          17757135000
 test master 2 - Starting Memory Read Line, at          17757345000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17758515000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17760075000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17762955000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17764695000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          17769345000
 test master 2 - Starting Memory Write, at          17769585000
 test master 2 - Starting Memory Write, at          17769825000
 test master 2 - Starting Memory Write, at          17770065000
 test master 2 - Starting Memory Write, at          17770305000
 test master 1 - Starting Memory Read, at          17770665000
 test master 1 - Starting Memory Read, at          17770965000
 test master 1 - Starting Memory Read, at          17771505000
 test master 1 - Starting Memory Read, at          17771805000
 test master 1 - Starting Memory Read, at          17772345000
 test master 1 - Starting Memory Read, at          17772645000
 test master 2 - Starting Memory Write, at          17773935000
 test master 2 - Starting Memory Write, at          17774175000
 test master 2 - Starting Memory Write, at          17774415000
 test master 2 - Starting Memory Write, at          17774655000
 test master 2 - Starting Memory Write, at          17774895000
 test master 1 - Starting Memory Read, at          17775255000
 test master 1 - Starting Memory Read, at          17775555000
 test master 1 - Starting Memory Read, at          17776095000
 test master 1 - Starting Memory Read, at          17776395000
 test master 1 - Starting Memory Read, at          17776935000
 test master 1 - Starting Memory Read, at          17777235000
 test master 2 - Starting Memory Write, at          17779035000
 test master 2 - Starting Memory Write, at          17780115000
 test master 2 - Starting Memory Write, at          17781195000
 test master 2 - Starting Memory Write, at          17782275000
 test master 2 - Starting Memory Write, at          17784495000
 test master 2 - Starting Memory Write, at          17785575000
 test master 2 - Starting Memory Write, at          17786655000
 test master 2 - Starting Memory Write, at          17787735000
 test master 2 - Starting Memory Write, at          17789955000
 test master 2 - Starting Memory Write, at          17792055000
 test master 2 - Starting Memory Write, at          17794155000
 test master 2 - Starting Memory Write, at          17796255000
 test master 2 - Starting Memory Write, at          17799495000
 test master 2 - Starting Memory Write, at          17801835000
 test master 2 - Starting Memory Write, at          17804175000
 test master 2 - Starting Memory Write, at          17806515000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          17810985000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17811015000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17813115000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          17813355000
 test master 2 - Starting Memory Read, at          17813535000
 test master 2 - Starting Memory Read, at          17813745000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17815335000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          17815695000
 test master 2 - Starting Memory Read, at          17815875000
 test master 2 - Starting Memory Read, at          17816085000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17817495000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17817945000
 test master 2 - Starting Memory Read Line Multiple, at          17818125000
 test master 2 - Starting Memory Read Line Multiple, at          17818395000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17820255000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17827215000
 test master 2 - Starting Memory Read Line Multiple, at          17827395000
 test master 2 - Starting Memory Read Line Multiple, at          17827665000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17828385000
 test master 2 - Starting Memory Read Line Multiple, at          17828565000
 test master 2 - Starting Memory Read Line Multiple, at          17828865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17829585000
 test master 2 - Starting Memory Read Line Multiple, at          17829765000
 test master 2 - Starting Memory Read Line Multiple, at          17830065000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17830785000
 test master 2 - Starting Memory Read Line Multiple, at          17830965000
 test master 2 - Starting Memory Read Line Multiple, at          17831265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17831985000
 test master 2 - Starting Memory Read Line Multiple, at          17832165000
 test master 2 - Starting Memory Read Line Multiple, at          17832465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17833185000
 test master 2 - Starting Memory Read Line Multiple, at          17833365000
 test master 2 - Starting Memory Read Line Multiple, at          17833665000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17834385000
 test master 2 - Starting Memory Read Line Multiple, at          17834565000
 test master 2 - Starting Memory Read Line Multiple, at          17834865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17835585000
 test master 2 - Starting Memory Read Line Multiple, at          17835765000
 test master 2 - Starting Memory Read Line Multiple, at          17836065000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          17836785000
 test master 2 - Starting Memory Read Line, at          17836965000
 test master 2 - Starting Memory Read Line, at          17837205000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          17837655000
 test master 2 - Starting Memory Read Line, at          17837835000
 test master 2 - Starting Memory Read Line, at          17838045000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17839215000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17840775000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17843655000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17845395000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          17850045000
 test master 2 - Starting Memory Write, at          17850285000
 test master 2 - Starting Memory Write, at          17850525000
 test master 2 - Starting Memory Write, at          17850765000
 test master 2 - Starting Memory Write, at          17851005000
 test master 1 - Starting Memory Read, at          17851365000
 test master 1 - Starting Memory Read, at          17851665000
 test master 1 - Starting Memory Read, at          17852205000
 test master 1 - Starting Memory Read, at          17852505000
 test master 1 - Starting Memory Read, at          17853045000
 test master 1 - Starting Memory Read, at          17853345000
 test master 2 - Starting Memory Write, at          17854635000
 test master 2 - Starting Memory Write, at          17854875000
 test master 2 - Starting Memory Write, at          17855115000
 test master 2 - Starting Memory Write, at          17855355000
 test master 2 - Starting Memory Write, at          17855595000
 test master 1 - Starting Memory Read, at          17855955000
 test master 1 - Starting Memory Read, at          17856255000
 test master 1 - Starting Memory Read, at          17856795000
 test master 1 - Starting Memory Read, at          17857095000
 test master 1 - Starting Memory Read, at          17857635000
 test master 1 - Starting Memory Read, at          17857935000
 test master 2 - Starting Memory Write, at          17859735000
 test master 2 - Starting Memory Write, at          17860815000
 test master 2 - Starting Memory Write, at          17861895000
 test master 2 - Starting Memory Write, at          17862975000
 test master 2 - Starting Memory Write, at          17865195000
 test master 2 - Starting Memory Write, at          17866275000
 test master 2 - Starting Memory Write, at          17867355000
 test master 2 - Starting Memory Write, at          17868435000
 test master 2 - Starting Memory Write, at          17870655000
 test master 2 - Starting Memory Write, at          17872755000
 test master 2 - Starting Memory Write, at          17874855000
 test master 2 - Starting Memory Write, at          17876955000
 test master 2 - Starting Memory Write, at          17880195000
 test master 2 - Starting Memory Write, at          17882535000
 test master 2 - Starting Memory Write, at          17884875000
 test master 2 - Starting Memory Write, at          17887215000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          17891685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17891715000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17893815000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          17894055000
 test master 2 - Starting Memory Read, at          17894235000
 test master 2 - Starting Memory Read, at          17894445000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17896035000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          17896395000
 test master 2 - Starting Memory Read, at          17896575000
 test master 2 - Starting Memory Read, at          17896785000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17898195000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17898645000
 test master 2 - Starting Memory Read Line Multiple, at          17898825000
 test master 2 - Starting Memory Read Line Multiple, at          17899095000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17900955000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17907915000
 test master 2 - Starting Memory Read Line Multiple, at          17908095000
 test master 2 - Starting Memory Read Line Multiple, at          17908365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17909085000
 test master 2 - Starting Memory Read Line Multiple, at          17909265000
 test master 2 - Starting Memory Read Line Multiple, at          17909565000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17910285000
 test master 2 - Starting Memory Read Line Multiple, at          17910465000
 test master 2 - Starting Memory Read Line Multiple, at          17910765000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17911485000
 test master 2 - Starting Memory Read Line Multiple, at          17911665000
 test master 2 - Starting Memory Read Line Multiple, at          17911965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17912685000
 test master 2 - Starting Memory Read Line Multiple, at          17912865000
 test master 2 - Starting Memory Read Line Multiple, at          17913165000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17913885000
 test master 2 - Starting Memory Read Line Multiple, at          17914065000
 test master 2 - Starting Memory Read Line Multiple, at          17914365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17915085000
 test master 2 - Starting Memory Read Line Multiple, at          17915265000
 test master 2 - Starting Memory Read Line Multiple, at          17915565000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17916285000
 test master 2 - Starting Memory Read Line Multiple, at          17916465000
 test master 2 - Starting Memory Read Line Multiple, at          17916765000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          17917485000
 test master 2 - Starting Memory Read Line, at          17917665000
 test master 2 - Starting Memory Read Line, at          17917905000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          17918355000
 test master 2 - Starting Memory Read Line, at          17918535000
 test master 2 - Starting Memory Read Line, at          17918745000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17919915000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17921475000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17924355000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17926095000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          17930745000
 test master 2 - Starting Memory Write, at          17930985000
 test master 2 - Starting Memory Write, at          17931225000
 test master 2 - Starting Memory Write, at          17931465000
 test master 2 - Starting Memory Write, at          17931705000
 test master 1 - Starting Memory Read, at          17932065000
 test master 1 - Starting Memory Read, at          17932365000
 test master 1 - Starting Memory Read, at          17932905000
 test master 1 - Starting Memory Read, at          17933205000
 test master 1 - Starting Memory Read, at          17933745000
 test master 1 - Starting Memory Read, at          17934045000
 test master 2 - Starting Memory Write, at          17935335000
 test master 2 - Starting Memory Write, at          17935575000
 test master 2 - Starting Memory Write, at          17935815000
 test master 2 - Starting Memory Write, at          17936055000
 test master 2 - Starting Memory Write, at          17936295000
 test master 1 - Starting Memory Read, at          17936655000
 test master 1 - Starting Memory Read, at          17936955000
 test master 1 - Starting Memory Read, at          17937495000
 test master 1 - Starting Memory Read, at          17937795000
 test master 1 - Starting Memory Read, at          17938335000
 test master 1 - Starting Memory Read, at          17938635000
 test master 2 - Starting Memory Write, at          17940435000
 test master 2 - Starting Memory Write, at          17941515000
 test master 2 - Starting Memory Write, at          17942595000
 test master 2 - Starting Memory Write, at          17943675000
 test master 2 - Starting Memory Write, at          17945895000
 test master 2 - Starting Memory Write, at          17946975000
 test master 2 - Starting Memory Write, at          17948055000
 test master 2 - Starting Memory Write, at          17949135000
 test master 2 - Starting Memory Write, at          17951355000
 test master 2 - Starting Memory Write, at          17953455000
 test master 2 - Starting Memory Write, at          17955555000
 test master 2 - Starting Memory Write, at          17957655000
 test master 2 - Starting Memory Write, at          17960895000
 test master 2 - Starting Memory Write, at          17963235000
 test master 2 - Starting Memory Write, at          17965575000
 test master 2 - Starting Memory Write, at          17967915000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          17972385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          17972415000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17974515000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          17974755000
 test master 2 - Starting Memory Read, at          17974935000
 test master 2 - Starting Memory Read, at          17975145000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17976735000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          17977095000
 test master 2 - Starting Memory Read, at          17977275000
 test master 2 - Starting Memory Read, at          17977485000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17978895000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17979345000
 test master 2 - Starting Memory Read Line Multiple, at          17979525000
 test master 2 - Starting Memory Read Line Multiple, at          17979795000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          17981655000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17988615000
 test master 2 - Starting Memory Read Line Multiple, at          17988795000
 test master 2 - Starting Memory Read Line Multiple, at          17989065000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17989785000
 test master 2 - Starting Memory Read Line Multiple, at          17989965000
 test master 2 - Starting Memory Read Line Multiple, at          17990265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17990985000
 test master 2 - Starting Memory Read Line Multiple, at          17991165000
 test master 2 - Starting Memory Read Line Multiple, at          17991465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17992185000
 test master 2 - Starting Memory Read Line Multiple, at          17992365000
 test master 2 - Starting Memory Read Line Multiple, at          17992665000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17993385000
 test master 2 - Starting Memory Read Line Multiple, at          17993565000
 test master 2 - Starting Memory Read Line Multiple, at          17993865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17994585000
 test master 2 - Starting Memory Read Line Multiple, at          17994765000
 test master 2 - Starting Memory Read Line Multiple, at          17995065000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17995785000
 test master 2 - Starting Memory Read Line Multiple, at          17995965000
 test master 2 - Starting Memory Read Line Multiple, at          17996265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          17996985000
 test master 2 - Starting Memory Read Line Multiple, at          17997165000
 test master 2 - Starting Memory Read Line Multiple, at          17997465000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          17998185000
 test master 2 - Starting Memory Read Line, at          17998365000
 test master 2 - Starting Memory Read Line, at          17998605000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          17999055000
 test master 2 - Starting Memory Read Line, at          17999235000
 test master 2 - Starting Memory Read Line, at          17999445000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          18000615000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          18002175000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          18005055000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          18006795000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          18011445000
 test master 2 - Starting Memory Write, at          18011685000
 test master 2 - Starting Memory Write, at          18011925000
 test master 2 - Starting Memory Write, at          18012165000
 test master 2 - Starting Memory Write, at          18012405000
 test master 1 - Starting Memory Read, at          18012765000
 test master 1 - Starting Memory Read, at          18013065000
 test master 1 - Starting Memory Read, at          18013605000
 test master 1 - Starting Memory Read, at          18013905000
 test master 1 - Starting Memory Read, at          18014445000
 test master 1 - Starting Memory Read, at          18014745000
 test master 2 - Starting Memory Write, at          18016035000
 test master 2 - Starting Memory Write, at          18016275000
 test master 2 - Starting Memory Write, at          18016515000
 test master 2 - Starting Memory Write, at          18016755000
 test master 2 - Starting Memory Write, at          18016995000
 test master 1 - Starting Memory Read, at          18017355000
 test master 1 - Starting Memory Read, at          18017655000
 test master 1 - Starting Memory Read, at          18018195000
 test master 1 - Starting Memory Read, at          18018495000
 test master 1 - Starting Memory Read, at          18019035000
 test master 1 - Starting Memory Read, at          18019335000
 test master 2 - Starting Memory Write, at          18021135000
 test master 2 - Starting Memory Write, at          18022215000
 test master 2 - Starting Memory Write, at          18023295000
 test master 2 - Starting Memory Write, at          18024375000
 test master 2 - Starting Memory Write, at          18026595000
 test master 2 - Starting Memory Write, at          18027675000
 test master 2 - Starting Memory Write, at          18028755000
 test master 2 - Starting Memory Write, at          18029835000
 test master 2 - Starting Memory Write, at          18032055000
 test master 2 - Starting Memory Write, at          18034155000
 test master 2 - Starting Memory Write, at          18036255000
 test master 2 - Starting Memory Write, at          18038355000
 test master 2 - Starting Memory Write, at          18041595000
 test master 2 - Starting Memory Write, at          18043935000
 test master 2 - Starting Memory Write, at          18046275000
 test master 2 - Starting Memory Write, at          18048615000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          18053085000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18053115000
 test master 1 - Starting Memory Read, at          18055215000
 test master 1 - Starting Memory Read, at          18055545000
 test master 1 - Starting Memory Read, at          18056805000
 test master 1 - Starting Memory Read, at          18057135000
 test master 1 - Starting Memory Read Line, at          18058425000
 test master 1 - Starting Memory Read Line, at          18058755000
 test master 1 - Starting Memory Read Line, at          18060045000
 test master 1 - Starting Memory Read Line, at          18060405000
 test master 1 - Starting Memory Read Line, at          18061725000
 test master 1 - Starting Memory Read Line, at          18062115000
 test master 1 - Starting Memory Read Line, at          18063585000
 test master 1 - Starting Memory Read Line, at          18063975000
 test master 1 - Starting Memory Read Line Multiple, at          18065445000
 test master 1 - Starting Memory Read Line Multiple, at          18065895000
 test master 1 - Starting Memory Read Line Multiple, at          18067665000
 test master 1 - Starting Memory Read Line Multiple, at          18068115000
 test master 1 - Starting Memory Read Line, at          18069885000
 test master 1 - Starting Memory Read Line, at          18070275000
 test master 1 - Starting Memory Read, at          18072735000
 test master 1 - Starting Memory Read, at          18073065000
 test target 1 - Starting Config Write, at          18076335000
 test master 1 - Starting Memory Write, at          18076875000
 test master 1 - Starting Memory Write, at          18082485000
 test master 1 - Starting Memory Write, at          18083835000
 test master 1 - Starting Memory Write, at          18089085000
 test master 1 - Starting Memory Write, at          18090435000
 test master 1 - Starting Memory Read Line, at          18096045000
 test master 1 - Starting Memory Write, at          18097545000
 test master 1 - Starting Memory Read Line, at          18103155000
 test target 1 - Starting Config Write, at          18106515000
 test master 1 - Starting Memory Write, at          18107055000
 test master 1 - Starting Memory Write, at          18107175000
 test master 1 - Starting Memory Write, at          18107415000
 test master 1 - Starting Memory Read, at          18107535000
 test master 1 - Starting Memory Write, at          18107865000
 test master 1 - Starting Memory Read, at          18107985000
 test master 1 - Starting Memory Write, at          18109575000
 test master 1 - Starting Memory Write, at          18116535000
 test master 2 - Starting Memory Read Line, at          18123615000
 test master 2 - Starting Memory Read Line, at          18123975000
 test master 2 - Starting Memory Read Line, at          18124455000
 test master 2 - Starting Memory Read Line, at          18124815000
 test master 1 - Starting Memory Write, at          18125385000
 test master 1 - Starting Memory Write, at          18125655000
 test master 1 - Starting Memory Write, at          18125955000
 test master 2 - Starting Memory Read Line, at          18126375000
 test master 2 - Starting Memory Read Line, at          18126705000
 test master 2 - Starting Memory Read Line, at          18126975000
 test master 2 - Starting Memory Read Line, at          18127305000
 test master 2 - Starting Memory Read Line Multiple, at          18127605000
 test master 2 - Starting Memory Read Line Multiple, at          18127935000
 test master 1 - Starting Memory Write, at          18129795000
 test master 1 - Starting Memory Write, at          18130065000
 test master 2 - Starting Memory Read, at          18130485000
 test master 2 - Starting Memory Read, at          18130815000
 test master 2 - Starting Memory Read, at          18131085000
 test master 2 - Starting Memory Read, at          18131415000
 test master 1 - Starting Memory Write, at          18133035000
 test master 1 - Starting Memory Read, at          18133215000
 test master 1 - Starting Memory Write, at          18133395000
 test master 1 - Starting Memory Read, at          18133605000
 test master 1 - Starting Memory Write, at          18133815000
 test master 1 - Starting Memory Read, at          18133995000
 test master 1 - Starting Memory Read, at          18134205000
 test master 1 - Starting Memory Write, at          18134415000
 test master 1 - Starting Memory Write, at          18134595000
 test master 1 - Starting Memory Read, at          18134775000
 test master 1 - Starting Memory Write, at          18134955000
 test master 1 - Starting Memory Write, at          18135165000
 test master 1 - Starting Memory Write, at          18135375000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          18139785000
 test target 1 - Starting Memory Write, at          18140055000
 test master 1 - Starting Memory Write, at          18140295000
 test target 1 - Starting Memory Write, at          18140475000
 test target 1 - Starting Memory Write, at          18140745000
 test target 1 - Starting Memory Write, at          18141015000
 test master 1 - Starting Memory Write, at          18141375000
 test target 1 - Starting Memory Write, at          18141885000
 test target 1 - Starting Memory Write, at          18142485000
 test target 1 - Starting Memory Write, at          18142785000
 test master 1 - Starting Memory Write, at          18143055000
 test target 1 - Starting Memory Write, at          18143415000
 test target 1 - Starting Memory Write, at          18143715000
 test target 1 - Starting Memory Write, at          18144015000
 test master 1 - Starting Memory Write, at          18144555000
 test target 1 - Starting Memory Write, at          18145395000
 test target 1 - Starting Memory Write, at          18146235000
 test target 1 - Starting Memory Write, at          18146505000
 test master 1 - Starting Memory Read, at          18146745000
 test target 1 - Starting Memory Write, at          18146925000
 test master 1 - Starting Memory Read, at          18147165000
 test target 1 - Starting Memory Write, at          18147345000
 test master 1 - Starting Memory Read, at          18147585000
 test target 1 - Starting Memory Write, at          18147765000
 test master 1 - Starting Memory Read, at          18148005000
 test target 1 - Starting Memory Write, at          18148185000
 test master 1 - Starting Memory Read, at          18148425000
 test target 1 - Starting Memory Write, at          18148605000
 test master 1 - Starting Memory Write, at          18148845000
 test target 1 - Starting Memory Write, at          18149025000
 test target 1 - Starting Memory Write, at          18149295000
 test target 1 - Starting Memory Write, at          18149565000
 test target 1 - Starting Memory Read, at          18149895000
 test master 1 - Starting Memory Write, at          18150255000
 test master 1 - Starting Memory Read, at          18150495000
 test target 1 - Starting Memory Write, at          18151005000
 test master 1 - Starting Memory Write, at          18151455000
 test target 1 - Starting Memory Read, at          18151905000
 test target 1 - Starting Memory Write, at          18152775000
 test master 1 - Starting Memory Read, at          18153135000
 test master 1 - Starting Memory Write, at          18153465000
 test master 1 - Starting Memory Write, at          18153825000
 test master 1 - Starting Memory Read, at          18154065000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          18156705000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          18157815000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          18183915000
 test target 1 - Starting Config Write, at          18184785000
 test target 1 - Starting Config Write, at          18185685000
 test target 2 - Starting Config Write, at          18186795000
 test target 2 - Starting Config Write, at          18187665000
 test target 2 - Starting Config Write, at          18188565000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          18190755000
 test target 1 - Starting Memory Read, at          18190995000
 test target 1 - Starting Memory Write, at          18191775000
 test target 1 - Starting Memory Read, at          18192015000
 test target 1 - Starting Memory Write, at          18193275000
 test target 1 - Starting Memory Read, at          18194235000
 test target 1 - Starting Memory Read, at          18194865000
 test target 1 - Starting Memory Read, at          18195465000
 test target 1 - Starting Memory Read, at          18196095000
 test target 1 - Starting Memory Read, at          18196995000
 test target 1 - Starting Memory Read, at          18198075000
 test target 1 - Starting Memory Read, at          18198945000
 test target 1 - Starting Memory Read, at          18200025000
 test target 1 - Starting Memory Read, at          18200895000
 test target 1 - Starting Memory Read, at          18202665000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          18209775000
 test target 1 - Starting Memory Read, at          18210015000
 test target 1 - Starting Memory Write, at          18210795000
 test target 1 - Starting Memory Read, at          18211035000
 test target 1 - Starting Memory Write, at          18212295000
 test target 1 - Starting Memory Read, at          18213255000
 test target 1 - Starting Memory Read, at          18213885000
 test target 1 - Starting Memory Read, at          18214485000
 test target 1 - Starting Memory Read, at          18215115000
 test target 1 - Starting Memory Read, at          18216015000
 test target 1 - Starting Memory Read, at          18217095000
 test target 1 - Starting Memory Read, at          18217965000
 test target 1 - Starting Memory Read, at          18219045000
 test target 1 - Starting Memory Read, at          18219915000
 test target 1 - Starting Memory Read, at          18221685000
 test target 1 - Starting Memory Write, at          18228795000
 test target 1 - Starting Memory Read, at          18229035000
 test target 1 - Starting Memory Write, at          18229815000
 test target 1 - Starting Memory Read, at          18230055000
 test target 1 - Starting Memory Write, at          18231315000
 test target 1 - Starting Memory Read, at          18232275000
 test target 1 - Starting Memory Read, at          18232905000
 test target 1 - Starting Memory Read, at          18233505000
 test target 1 - Starting Memory Read, at          18234135000
 test target 1 - Starting Memory Read, at          18235035000
 test target 1 - Starting Memory Read, at          18236115000
 test target 1 - Starting Memory Read, at          18236985000
 test target 1 - Starting Memory Read, at          18238065000
 test target 1 - Starting Memory Read, at          18238935000
 test target 1 - Starting Memory Read, at          18240705000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          18254145000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          18261045000
 test target 1 - Starting Memory Write, at          18262095000
 test target 1 - Starting Memory Read, at          18262455000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          18263775000
 test target 1 - Starting Config Write, at          18265815000
 test target 1 - Starting Memory Read, at          18266415000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          18267945000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          18270285000
 test target 1 - Starting Memory Write, at          18271695000
 test target 1 - Starting Memory Write, at          18271965000
 test target 1 - Starting Memory Read, at          18272205000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          18274845000
 test target 1 - Starting Memory Write, at          18278115000
 test target 1 - Starting Memory Write, at          18278445000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          18282585000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          18284565000
 test target 1 - Starting Memory Read, at          18285915000
 test target 1 - Starting Memory Read, at          18286935000
 test target 1 - Starting Memory Read, at          18288615000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          18294945000
 test target 2 - Starting Config Write, at          18296025000
 test target 1 - Starting Memory Write, at          18296655000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          18296805000
 test target 1 - Starting Memory Write, at          18297855000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          18298005000
 test target 1 - Starting Memory Write, at          18299055000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          18300525000
 test target 1 - Starting Memory Read, at          18302775000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          18302925000
 test target 1 - Starting Memory Read, at          18305145000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          18306885000
 test master 2 - Starting Memory Write, at          18306885000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          18306945000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18307815000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18307845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18308145000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18308175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18309135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18309165000
 test target 1 - Starting Memory Write, at          18311055000
 test master 2 - Starting Memory Write, at          18311055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18312855000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18312885000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18314655000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18314685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18316455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18316485000
 test target 1 - Starting Memory Write, at          18318645000
 test master 2 - Starting Memory Write, at          18318645000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          18318705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18320415000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18320445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18320745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18320775000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18321735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18321765000
 test target 1 - Starting Memory Write, at          18322995000
 test master 2 - Starting Memory Write, at          18322995000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          18326145000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          18327855000
 test master 1 - Starting Memory Read, at          18328245000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          18328395000
 test target 1 - Starting Config Write, at          18331125000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          18333795000
 test target 1 - Starting Memory Write, at          18333975000
 test target 1 - Starting Memory Write, at          18334155000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          18334695000
 test target 1 - Starting Memory Write, at          18334905000
 test target 1 - Starting Memory Write, at          18335115000
 test target 1 - Starting Memory Write, at          18335655000
 test target 1 - Starting Memory Write, at          18335895000
 test target 1 - Starting Memory Write, at          18336435000
 test target 1 - Starting Memory Write, at          18337125000
 test target 1 - Starting Memory Write, at          18337335000
 test target 1 - Starting Memory Write, at          18338025000
 test target 1 - Starting Memory Write, at          18338295000
 test target 1 - Starting Memory Write, at          18338925000
 test target 1 - Starting Memory Write, at          18345615000
 test target 1 - Starting Memory Write, at          18345825000
 test target 1 - Starting Memory Write, at          18346035000
 test target 1 - Starting Memory Write, at          18346305000
 test target 1 - Starting Memory Write, at          18346575000
 test target 1 - Starting Memory Read, at          18350235000
 test target 1 - Starting Memory Read, at          18351345000
 test target 1 - Starting Memory Read, at          18352425000
 test target 1 - Starting Memory Read, at          18353505000
 test target 1 - Starting Memory Read, at          18354585000
 test target 1 - Starting Memory Read, at          18355665000
 test target 1 - Starting Memory Read, at          18356745000
 test target 1 - Starting Memory Read, at          18357825000
 test target 1 - Starting Memory Read, at          18358905000
 test target 1 - Starting Memory Read, at          18359985000
 test target 1 - Starting Memory Read, at          18361065000
 test target 1 - Starting Memory Read, at          18362145000
 test target 1 - Starting Memory Read, at          18363225000
 test target 1 - Starting Memory Read, at          18364305000
 test target 1 - Starting Memory Read, at          18365385000
 test target 1 - Starting Memory Read, at          18366465000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          18367365000
 test target 1 - Starting Memory Read, at          18367545000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          18369855000
 test target 1 - Starting Memory Read, at          18370995000
 test target 1 - Starting Memory Read, at          18371775000
 test target 1 - Starting Memory Read, at          18372435000
 test target 1 - Starting Memory Read, at          18373155000
 test target 1 - Starting Memory Read, at          18373815000
 test target 1 - Starting Memory Read, at          18374955000
 test target 1 - Starting Memory Read, at          18376035000
 test target 1 - Starting Memory Read, at          18376905000
 test target 1 - Starting Memory Read, at          18379725000
 test target 1 - Starting Memory Read, at          18381645000
 test target 1 - Starting Memory Read, at          18382545000
 test target 1 - Starting Memory Read, at          18383445000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          18384885000
 test master 1 - Starting Memory Write, at          18385155000
 test target 1 - Starting Memory Write, at          18385155000
 test target 1 - Starting Memory Write, at          18385335000
 test target 1 - Starting Memory Read, at          18385695000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          18387675000
 test master 1 - Starting Memory Write, at          18387945000
 test target 1 - Starting Memory Write, at          18387945000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          18393165000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          18394275000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          18420375000
 test target 1 - Starting Config Write, at          18421485000
 test target 1 - Starting Config Write, at          18422565000
 test target 2 - Starting Config Write, at          18423675000
 test target 2 - Starting Config Write, at          18424785000
 test target 2 - Starting Config Write, at          18425865000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          18428055000
 test target 1 - Starting Memory Read, at          18428325000
 test target 1 - Starting Memory Write, at          18429075000
 test target 1 - Starting Memory Read, at          18429345000
 test target 1 - Starting Memory Write, at          18430575000
 test target 1 - Starting Memory Read, at          18431565000
 test target 1 - Starting Memory Read, at          18432195000
 test target 1 - Starting Memory Read, at          18432825000
 test target 1 - Starting Memory Read, at          18433425000
 test target 1 - Starting Memory Read, at          18434325000
 test target 1 - Starting Memory Read, at          18435405000
 test target 1 - Starting Memory Read, at          18436485000
 test target 1 - Starting Memory Read, at          18437565000
 test target 1 - Starting Memory Read, at          18438645000
 test target 1 - Starting Memory Read, at          18440415000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          18447495000
 test target 1 - Starting Memory Read, at          18447765000
 test target 1 - Starting Memory Write, at          18448515000
 test target 1 - Starting Memory Read, at          18448785000
 test target 1 - Starting Memory Write, at          18450015000
 test target 1 - Starting Memory Read, at          18451005000
 test target 1 - Starting Memory Read, at          18451635000
 test target 1 - Starting Memory Read, at          18452265000
 test target 1 - Starting Memory Read, at          18452865000
 test target 1 - Starting Memory Read, at          18453765000
 test target 1 - Starting Memory Read, at          18454845000
 test target 1 - Starting Memory Read, at          18455925000
 test target 1 - Starting Memory Read, at          18457005000
 test target 1 - Starting Memory Read, at          18458085000
 test target 1 - Starting Memory Read, at          18459855000
 test target 1 - Starting Memory Write, at          18466935000
 test target 1 - Starting Memory Read, at          18467205000
 test target 1 - Starting Memory Write, at          18467955000
 test target 1 - Starting Memory Read, at          18468225000
 test target 1 - Starting Memory Write, at          18469455000
 test target 1 - Starting Memory Read, at          18470445000
 test target 1 - Starting Memory Read, at          18471075000
 test target 1 - Starting Memory Read, at          18471705000
 test target 1 - Starting Memory Read, at          18472305000
 test target 1 - Starting Memory Read, at          18473205000
 test target 1 - Starting Memory Read, at          18474285000
 test target 1 - Starting Memory Read, at          18475365000
 test target 1 - Starting Memory Read, at          18476445000
 test target 1 - Starting Memory Read, at          18477525000
 test target 1 - Starting Memory Read, at          18479295000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          18492705000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          18499605000
 test target 1 - Starting Memory Write, at          18500655000
 test target 1 - Starting Memory Read, at          18501045000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          18502335000
 test target 1 - Starting Config Write, at          18504615000
 test target 1 - Starting Memory Read, at          18505455000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          18507165000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          18509505000
 test target 1 - Starting Memory Write, at          18510915000
 test target 1 - Starting Memory Write, at          18511215000
 test target 1 - Starting Memory Read, at          18511485000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          18514065000
 test target 1 - Starting Memory Write, at          18517335000
 test target 1 - Starting Memory Write, at          18517695000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          18521865000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          18524085000
 test target 1 - Starting Memory Read, at          18525435000
 test target 1 - Starting Memory Read, at          18526455000
 test target 1 - Starting Memory Read, at          18528315000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          18534645000
 test target 2 - Starting Config Write, at          18535725000
 test target 1 - Starting Memory Write, at          18536595000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          18536775000
 test target 1 - Starting Memory Write, at          18537855000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          18538035000
 test target 1 - Starting Memory Write, at          18539115000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          18540645000
 test target 1 - Starting Memory Read, at          18543135000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          18543315000
 test target 1 - Starting Memory Read, at          18545685000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          18547665000
 test master 2 - Starting Memory Write, at          18547665000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          18547725000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18548655000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18548685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18548985000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18549015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18549975000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18550005000
 test target 1 - Starting Memory Write, at          18551895000
 test master 2 - Starting Memory Write, at          18551895000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18553755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18553785000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18555555000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18555585000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18557355000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18557385000
 test target 1 - Starting Memory Write, at          18559545000
 test master 2 - Starting Memory Write, at          18559545000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          18559605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18561375000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18561405000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18561705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18561735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18562695000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18562725000
 test target 1 - Starting Memory Write, at          18563955000
 test master 2 - Starting Memory Write, at          18563955000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          18567105000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          18568815000
 test master 1 - Starting Memory Read, at          18569205000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          18569355000
 test target 1 - Starting Config Write, at          18572085000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          18574755000
 test target 1 - Starting Memory Write, at          18574965000
 test target 1 - Starting Memory Write, at          18575175000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          18575715000
 test target 1 - Starting Memory Write, at          18575955000
 test target 1 - Starting Memory Write, at          18576195000
 test target 1 - Starting Memory Write, at          18576735000
 test target 1 - Starting Memory Write, at          18577005000
 test target 1 - Starting Memory Write, at          18577575000
 test target 1 - Starting Memory Write, at          18578295000
 test target 1 - Starting Memory Write, at          18578535000
 test target 1 - Starting Memory Write, at          18579255000
 test target 1 - Starting Memory Write, at          18579555000
 test target 1 - Starting Memory Write, at          18580215000
 test target 1 - Starting Memory Write, at          18586935000
 test target 1 - Starting Memory Write, at          18587175000
 test target 1 - Starting Memory Write, at          18587415000
 test target 1 - Starting Memory Write, at          18587715000
 test target 1 - Starting Memory Write, at          18588015000
 test target 1 - Starting Memory Read, at          18591705000
 test target 1 - Starting Memory Read, at          18592815000
 test target 1 - Starting Memory Read, at          18593895000
 test target 1 - Starting Memory Read, at          18594975000
 test target 1 - Starting Memory Read, at          18596055000
 test target 1 - Starting Memory Read, at          18597135000
 test target 1 - Starting Memory Read, at          18598215000
 test target 1 - Starting Memory Read, at          18599295000
 test target 1 - Starting Memory Read, at          18600375000
 test target 1 - Starting Memory Read, at          18601455000
 test target 1 - Starting Memory Read, at          18602535000
 test target 1 - Starting Memory Read, at          18603615000
 test target 1 - Starting Memory Read, at          18604695000
 test target 1 - Starting Memory Read, at          18605775000
 test target 1 - Starting Memory Read, at          18606855000
 test target 1 - Starting Memory Read, at          18607935000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          18608865000
 test target 1 - Starting Memory Read, at          18609075000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          18611355000
 test target 1 - Starting Memory Read, at          18612525000
 test target 1 - Starting Memory Read, at          18613245000
 test target 1 - Starting Memory Read, at          18613905000
 test target 1 - Starting Memory Read, at          18614625000
 test target 1 - Starting Memory Read, at          18615495000
 test target 1 - Starting Memory Read, at          18616635000
 test target 1 - Starting Memory Read, at          18617715000
 test target 1 - Starting Memory Read, at          18618795000
 test target 1 - Starting Memory Read, at          18621735000
 test target 1 - Starting Memory Read, at          18623835000
 test target 1 - Starting Memory Read, at          18624735000
 test target 1 - Starting Memory Read, at          18625635000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          18627075000
 test master 1 - Starting Memory Write, at          18627315000
 test target 1 - Starting Memory Write, at          18627315000
 test target 1 - Starting Memory Write, at          18627525000
 test target 1 - Starting Memory Read, at          18627975000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          18629985000
 test master 1 - Starting Memory Write, at          18630225000
 test target 1 - Starting Memory Write, at          18630225000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          18635445000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          18636555000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          18662655000
 test target 1 - Starting Config Write, at          18663765000
 test target 1 - Starting Config Write, at          18664845000
 test target 2 - Starting Config Write, at          18665955000
 test target 2 - Starting Config Write, at          18667065000
 test target 2 - Starting Config Write, at          18668145000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          18670335000
 test target 1 - Starting Memory Read, at          18670635000
 test target 1 - Starting Memory Write, at          18671355000
 test target 1 - Starting Memory Read, at          18671655000
 test target 1 - Starting Memory Write, at          18672855000
 test target 1 - Starting Memory Read, at          18673875000
 test target 1 - Starting Memory Read, at          18674505000
 test target 1 - Starting Memory Read, at          18675105000
 test target 1 - Starting Memory Read, at          18675735000
 test target 1 - Starting Memory Read, at          18676635000
 test target 1 - Starting Memory Read, at          18677715000
 test target 1 - Starting Memory Read, at          18678795000
 test target 1 - Starting Memory Read, at          18679875000
 test target 1 - Starting Memory Read, at          18680955000
 test target 1 - Starting Memory Read, at          18682875000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          18689955000
 test target 1 - Starting Memory Read, at          18690255000
 test target 1 - Starting Memory Write, at          18690975000
 test target 1 - Starting Memory Read, at          18691275000
 test target 1 - Starting Memory Write, at          18692475000
 test target 1 - Starting Memory Read, at          18693495000
 test target 1 - Starting Memory Read, at          18694125000
 test target 1 - Starting Memory Read, at          18694725000
 test target 1 - Starting Memory Read, at          18695355000
 test target 1 - Starting Memory Read, at          18696255000
 test target 1 - Starting Memory Read, at          18697335000
 test target 1 - Starting Memory Read, at          18698415000
 test target 1 - Starting Memory Read, at          18699495000
 test target 1 - Starting Memory Read, at          18700575000
 test target 1 - Starting Memory Read, at          18702495000
 test target 1 - Starting Memory Write, at          18709575000
 test target 1 - Starting Memory Read, at          18709875000
 test target 1 - Starting Memory Write, at          18710595000
 test target 1 - Starting Memory Read, at          18710895000
 test target 1 - Starting Memory Write, at          18712095000
 test target 1 - Starting Memory Read, at          18713115000
 test target 1 - Starting Memory Read, at          18713745000
 test target 1 - Starting Memory Read, at          18714345000
 test target 1 - Starting Memory Read, at          18714975000
 test target 1 - Starting Memory Read, at          18715875000
 test target 1 - Starting Memory Read, at          18716955000
 test target 1 - Starting Memory Read, at          18718035000
 test target 1 - Starting Memory Read, at          18719115000
 test target 1 - Starting Memory Read, at          18720195000
 test target 1 - Starting Memory Read, at          18722115000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          18735525000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          18742425000
 test target 1 - Starting Memory Write, at          18743475000
 test target 1 - Starting Memory Read, at          18743895000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          18745155000
 test target 1 - Starting Config Write, at          18747435000
 test target 1 - Starting Memory Read, at          18748275000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          18749985000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          18752325000
 test target 1 - Starting Memory Write, at          18753735000
 test target 1 - Starting Memory Write, at          18754065000
 test target 1 - Starting Memory Read, at          18754365000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          18757065000
 test target 1 - Starting Memory Write, at          18760395000
 test target 1 - Starting Memory Write, at          18760785000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          18764985000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          18767205000
 test target 1 - Starting Memory Read, at          18768735000
 test target 1 - Starting Memory Read, at          18769755000
 test target 1 - Starting Memory Read, at          18771615000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          18777945000
 test target 2 - Starting Config Write, at          18779025000
 test target 1 - Starting Memory Write, at          18779895000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          18780105000
 test target 1 - Starting Memory Write, at          18781155000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          18781365000
 test target 1 - Starting Memory Write, at          18782415000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          18783945000
 test target 1 - Starting Memory Read, at          18786435000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          18786645000
 test target 1 - Starting Memory Read, at          18788985000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          18790965000
 test master 2 - Starting Memory Write, at          18790965000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          18791025000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18791955000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18791985000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18792285000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18792315000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18793275000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18793305000
 test target 1 - Starting Memory Write, at          18795195000
 test master 2 - Starting Memory Write, at          18795195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18797055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18797085000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18798855000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18798885000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18800655000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18800685000
 test target 1 - Starting Memory Write, at          18802845000
 test master 2 - Starting Memory Write, at          18802845000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          18802905000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18804675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18804705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18805005000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18805035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18805995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          18806025000
 test target 1 - Starting Memory Write, at          18807255000
 test master 2 - Starting Memory Write, at          18807255000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          18810465000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          18812175000
 test master 1 - Starting Memory Read, at          18812565000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          18812715000
 test target 1 - Starting Config Write, at          18815445000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          18818115000
 test target 1 - Starting Memory Write, at          18818355000
 test target 1 - Starting Memory Write, at          18818595000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          18819195000
 test target 1 - Starting Memory Write, at          18819465000
 test target 1 - Starting Memory Write, at          18819735000
 test target 1 - Starting Memory Write, at          18820335000
 test target 1 - Starting Memory Write, at          18820635000
 test target 1 - Starting Memory Write, at          18821235000
 test target 1 - Starting Memory Write, at          18821985000
 test target 1 - Starting Memory Write, at          18822255000
 test target 1 - Starting Memory Write, at          18823005000
 test target 1 - Starting Memory Write, at          18823335000
 test target 1 - Starting Memory Write, at          18824025000
 test target 1 - Starting Memory Write, at          18830775000
 test target 1 - Starting Memory Write, at          18831045000
 test target 1 - Starting Memory Write, at          18831315000
 test target 1 - Starting Memory Write, at          18831645000
 test target 1 - Starting Memory Write, at          18831975000
 test target 1 - Starting Memory Read, at          18835695000
 test target 1 - Starting Memory Read, at          18836805000
 test target 1 - Starting Memory Read, at          18837885000
 test target 1 - Starting Memory Read, at          18838965000
 test target 1 - Starting Memory Read, at          18840045000
 test target 1 - Starting Memory Read, at          18841125000
 test target 1 - Starting Memory Read, at          18842205000
 test target 1 - Starting Memory Read, at          18843285000
 test target 1 - Starting Memory Read, at          18844365000
 test target 1 - Starting Memory Read, at          18845445000
 test target 1 - Starting Memory Read, at          18846525000
 test target 1 - Starting Memory Read, at          18847605000
 test target 1 - Starting Memory Read, at          18848685000
 test target 1 - Starting Memory Read, at          18849765000
 test target 1 - Starting Memory Read, at          18850845000
 test target 1 - Starting Memory Read, at          18851925000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          18852855000
 test target 1 - Starting Memory Read, at          18853095000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          18855345000
 test target 1 - Starting Memory Read, at          18856545000
 test target 1 - Starting Memory Read, at          18857235000
 test target 1 - Starting Memory Read, at          18858045000
 test target 1 - Starting Memory Read, at          18858915000
 test target 1 - Starting Memory Read, at          18859755000
 test target 1 - Starting Memory Read, at          18860925000
 test target 1 - Starting Memory Read, at          18862005000
 test target 1 - Starting Memory Read, at          18863085000
 test target 1 - Starting Memory Read, at          18866025000
 test target 1 - Starting Memory Read, at          18868125000
 test target 1 - Starting Memory Read, at          18869025000
 test target 1 - Starting Memory Read, at          18869925000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          18871365000
 test master 1 - Starting Memory Write, at          18871635000
 test target 1 - Starting Memory Write, at          18871635000
 test target 1 - Starting Memory Write, at          18871875000
 test target 1 - Starting Memory Read, at          18872355000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          18874485000
 test master 1 - Starting Memory Write, at          18874755000
 test target 1 - Starting Memory Write, at          18874755000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          18879945000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          18881175000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          18907395000
 test target 1 - Starting Config Write, at          18908505000
 test target 1 - Starting Config Write, at          18909585000
 test target 2 - Starting Config Write, at          18910695000
 test target 2 - Starting Config Write, at          18911805000
 test target 2 - Starting Config Write, at          18912885000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          18915075000
 test target 1 - Starting Memory Read, at          18915405000
 test target 1 - Starting Memory Write, at          18916275000
 test target 1 - Starting Memory Read, at          18916605000
 test target 1 - Starting Memory Write, at          18918015000
 test target 1 - Starting Memory Read, at          18919065000
 test target 1 - Starting Memory Read, at          18919695000
 test target 1 - Starting Memory Read, at          18920475000
 test target 1 - Starting Memory Read, at          18921255000
 test target 1 - Starting Memory Read, at          18922305000
 test target 1 - Starting Memory Read, at          18923565000
 test target 1 - Starting Memory Read, at          18924615000
 test target 1 - Starting Memory Read, at          18925845000
 test target 1 - Starting Memory Read, at          18926925000
 test target 1 - Starting Memory Read, at          18928845000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          18935955000
 test target 1 - Starting Memory Read, at          18936285000
 test target 1 - Starting Memory Write, at          18937155000
 test target 1 - Starting Memory Read, at          18937485000
 test target 1 - Starting Memory Write, at          18938895000
 test target 1 - Starting Memory Read, at          18939945000
 test target 1 - Starting Memory Read, at          18940575000
 test target 1 - Starting Memory Read, at          18941355000
 test target 1 - Starting Memory Read, at          18942135000
 test target 1 - Starting Memory Read, at          18943185000
 test target 1 - Starting Memory Read, at          18944445000
 test target 1 - Starting Memory Read, at          18945495000
 test target 1 - Starting Memory Read, at          18946725000
 test target 1 - Starting Memory Read, at          18947805000
 test target 1 - Starting Memory Read, at          18949725000
 test target 1 - Starting Memory Write, at          18956835000
 test target 1 - Starting Memory Read, at          18957165000
 test target 1 - Starting Memory Write, at          18958035000
 test target 1 - Starting Memory Read, at          18958365000
 test target 1 - Starting Memory Write, at          18959775000
 test target 1 - Starting Memory Read, at          18960825000
 test target 1 - Starting Memory Read, at          18961455000
 test target 1 - Starting Memory Read, at          18962235000
 test target 1 - Starting Memory Read, at          18963015000
 test target 1 - Starting Memory Read, at          18964065000
 test target 1 - Starting Memory Read, at          18965325000
 test target 1 - Starting Memory Read, at          18966375000
 test target 1 - Starting Memory Read, at          18967605000
 test target 1 - Starting Memory Read, at          18968685000
 test target 1 - Starting Memory Read, at          18970605000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          18984045000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          18990945000
 test target 1 - Starting Memory Write, at          18991995000
 test target 1 - Starting Memory Read, at          18992445000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          18993825000
 test target 1 - Starting Config Write, at          18996105000
 test target 1 - Starting Memory Read, at          18996945000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          18998685000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          19001025000
 test target 1 - Starting Memory Write, at          19002435000
 test target 1 - Starting Memory Write, at          19002795000
 test target 1 - Starting Memory Read, at          19003125000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          19005765000
 test target 1 - Starting Memory Write, at          19009095000
 test target 1 - Starting Memory Write, at          19009515000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          19013745000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          19015965000
 test target 1 - Starting Memory Read, at          19017495000
 test target 1 - Starting Memory Read, at          19018665000
 test target 1 - Starting Memory Read, at          19020495000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          19027005000
 test target 2 - Starting Config Write, at          19028085000
 test target 1 - Starting Memory Write, at          19028955000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          19029195000
 test target 1 - Starting Memory Write, at          19030275000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          19030515000
 test target 1 - Starting Memory Write, at          19031595000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          19033185000
 test target 1 - Starting Memory Read, at          19035675000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          19035915000
 test target 1 - Starting Memory Read, at          19038225000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          19040205000
 test master 2 - Starting Memory Write, at          19040205000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          19040265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19041255000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19041285000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19041585000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19041615000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19042575000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19042605000
 test target 1 - Starting Memory Write, at          19044495000
 test master 2 - Starting Memory Write, at          19044495000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19046415000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19046445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19048215000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19048245000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19050015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19050045000
 test target 1 - Starting Memory Write, at          19052205000
 test master 2 - Starting Memory Write, at          19052205000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          19052265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19054095000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19054125000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19054425000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19054455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19055415000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19055445000
 test target 1 - Starting Memory Write, at          19056675000
 test master 2 - Starting Memory Write, at          19056675000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          19059885000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          19061595000
 test master 1 - Starting Memory Read, at          19061985000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          19062135000
 test target 1 - Starting Config Write, at          19064865000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          19067535000
 test target 1 - Starting Memory Write, at          19067805000
 test target 1 - Starting Memory Write, at          19068075000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          19068675000
 test target 1 - Starting Memory Write, at          19068975000
 test target 1 - Starting Memory Write, at          19069275000
 test target 1 - Starting Memory Write, at          19069875000
 test target 1 - Starting Memory Write, at          19070205000
 test target 1 - Starting Memory Write, at          19070835000
 test target 1 - Starting Memory Write, at          19071615000
 test target 1 - Starting Memory Write, at          19071915000
 test target 1 - Starting Memory Write, at          19072695000
 test target 1 - Starting Memory Write, at          19073055000
 test target 1 - Starting Memory Write, at          19073775000
 test target 1 - Starting Memory Write, at          19080555000
 test target 1 - Starting Memory Write, at          19080855000
 test target 1 - Starting Memory Write, at          19081155000
 test target 1 - Starting Memory Write, at          19081515000
 test target 1 - Starting Memory Write, at          19081875000
 test target 1 - Starting Memory Read, at          19085625000
 test target 1 - Starting Memory Read, at          19086765000
 test target 1 - Starting Memory Read, at          19087995000
 test target 1 - Starting Memory Read, at          19089225000
 test target 1 - Starting Memory Read, at          19090485000
 test target 1 - Starting Memory Read, at          19091715000
 test target 1 - Starting Memory Read, at          19092945000
 test target 1 - Starting Memory Read, at          19094205000
 test target 1 - Starting Memory Read, at          19095435000
 test target 1 - Starting Memory Read, at          19096665000
 test target 1 - Starting Memory Read, at          19097925000
 test target 1 - Starting Memory Read, at          19099155000
 test target 1 - Starting Memory Read, at          19100385000
 test target 1 - Starting Memory Read, at          19101645000
 test target 1 - Starting Memory Read, at          19102875000
 test target 1 - Starting Memory Read, at          19104105000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          19105185000
 test target 1 - Starting Memory Read, at          19105455000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          19107675000
 test target 1 - Starting Memory Read, at          19108905000
 test target 1 - Starting Memory Read, at          19109595000
 test target 1 - Starting Memory Read, at          19110405000
 test target 1 - Starting Memory Read, at          19111245000
 test target 1 - Starting Memory Read, at          19112115000
 test target 1 - Starting Memory Read, at          19113435000
 test target 1 - Starting Memory Read, at          19114665000
 test target 1 - Starting Memory Read, at          19115745000
 test target 1 - Starting Memory Read, at          19118685000
 test target 1 - Starting Memory Read, at          19120785000
 test target 1 - Starting Memory Read, at          19121685000
 test target 1 - Starting Memory Read, at          19122585000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          19124025000
 test master 1 - Starting Memory Write, at          19124325000
 test target 1 - Starting Memory Write, at          19124325000
 test target 1 - Starting Memory Write, at          19124595000
 test target 1 - Starting Memory Read, at          19125105000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          19127175000
 test master 1 - Starting Memory Write, at          19127475000
 test target 1 - Starting Memory Write, at          19127475000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19133085000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          19133385000
 test master 2 - Starting Memory Read, at          19133565000
 test master 2 - Starting Memory Read, at          19133745000
 test master 2 - Starting Memory Read, at          19134015000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19135575000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          19135995000
 test master 2 - Starting Memory Read, at          19136175000
 test master 2 - Starting Memory Read, at          19136625000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19138095000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19138665000
 test master 2 - Starting Memory Read Line Multiple, at          19138845000
 test master 2 - Starting Memory Read Line Multiple, at          19139025000
 test master 2 - Starting Memory Read Line Multiple, at          19139205000
 test master 2 - Starting Memory Read Line Multiple, at          19139535000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19141275000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19150095000
 test master 2 - Starting Memory Read Line Multiple, at          19150275000
 test master 2 - Starting Memory Read Line Multiple, at          19150455000
 test master 2 - Starting Memory Read Line Multiple, at          19150635000
 test master 2 - Starting Memory Read Line Multiple, at          19150965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19151505000
 test master 2 - Starting Memory Read Line Multiple, at          19151685000
 test master 2 - Starting Memory Read Line Multiple, at          19151865000
 test master 2 - Starting Memory Read Line Multiple, at          19152045000
 test master 2 - Starting Memory Read Line Multiple, at          19152405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19152945000
 test master 2 - Starting Memory Read Line Multiple, at          19153125000
 test master 2 - Starting Memory Read Line Multiple, at          19153305000
 test master 2 - Starting Memory Read Line Multiple, at          19153485000
 test master 2 - Starting Memory Read Line Multiple, at          19153845000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19154385000
 test master 2 - Starting Memory Read Line Multiple, at          19154565000
 test master 2 - Starting Memory Read Line Multiple, at          19154745000
 test master 2 - Starting Memory Read Line Multiple, at          19154925000
 test master 2 - Starting Memory Read Line Multiple, at          19155285000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19155825000
 test master 2 - Starting Memory Read Line Multiple, at          19156005000
 test master 2 - Starting Memory Read Line Multiple, at          19156185000
 test master 2 - Starting Memory Read Line Multiple, at          19156365000
 test master 2 - Starting Memory Read Line Multiple, at          19156725000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19157265000
 test master 2 - Starting Memory Read Line Multiple, at          19157445000
 test master 2 - Starting Memory Read Line Multiple, at          19157625000
 test master 2 - Starting Memory Read Line Multiple, at          19157805000
 test master 2 - Starting Memory Read Line Multiple, at          19158165000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19158705000
 test master 2 - Starting Memory Read Line Multiple, at          19158885000
 test master 2 - Starting Memory Read Line Multiple, at          19159065000
 test master 2 - Starting Memory Read Line Multiple, at          19159245000
 test master 2 - Starting Memory Read Line Multiple, at          19159605000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19160145000
 test master 2 - Starting Memory Read Line Multiple, at          19160325000
 test master 2 - Starting Memory Read Line Multiple, at          19160505000
 test master 2 - Starting Memory Read Line Multiple, at          19160685000
 test master 2 - Starting Memory Read Line Multiple, at          19161045000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          19161585000
 test master 2 - Starting Memory Read Line, at          19161765000
 test master 2 - Starting Memory Read Line, at          19161945000
 test master 2 - Starting Memory Read Line, at          19162245000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          19162605000
 test master 2 - Starting Memory Read Line, at          19162785000
 test master 2 - Starting Memory Read Line, at          19163235000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19164405000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19166085000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19169145000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19171065000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          19176195000
 test master 2 - Starting Memory Write, at          19176495000
 test master 2 - Starting Memory Write, at          19176795000
 test master 2 - Starting Memory Write, at          19177095000
 test master 2 - Starting Memory Write, at          19177395000
 test master 1 - Starting Memory Read, at          19177815000
 test master 1 - Starting Memory Read, at          19178175000
 test master 1 - Starting Memory Read, at          19178715000
 test master 1 - Starting Memory Read, at          19179075000
 test master 1 - Starting Memory Read, at          19179615000
 test master 1 - Starting Memory Read, at          19179975000
 test master 2 - Starting Memory Write, at          19181295000
 test master 2 - Starting Memory Write, at          19181595000
 test master 2 - Starting Memory Write, at          19181895000
 test master 2 - Starting Memory Write, at          19182195000
 test master 2 - Starting Memory Write, at          19182495000
 test master 1 - Starting Memory Read, at          19182915000
 test master 1 - Starting Memory Read, at          19183275000
 test master 1 - Starting Memory Read, at          19183815000
 test master 1 - Starting Memory Read, at          19184175000
 test master 1 - Starting Memory Read, at          19184715000
 test master 1 - Starting Memory Read, at          19185075000
 test master 2 - Starting Memory Write, at          19186935000
 test master 2 - Starting Memory Write, at          19188105000
 test master 2 - Starting Memory Write, at          19189305000
 test master 2 - Starting Memory Write, at          19190505000
 test master 2 - Starting Memory Write, at          19192935000
 test master 2 - Starting Memory Write, at          19194105000
 test master 2 - Starting Memory Write, at          19195305000
 test master 2 - Starting Memory Write, at          19196505000
 test master 2 - Starting Memory Write, at          19198935000
 test master 2 - Starting Memory Write, at          19201125000
 test master 2 - Starting Memory Write, at          19203345000
 test master 2 - Starting Memory Write, at          19205565000
 test master 2 - Starting Memory Write, at          19209015000
 test master 2 - Starting Memory Write, at          19211475000
 test master 2 - Starting Memory Write, at          19213935000
 test master 2 - Starting Memory Write, at          19216395000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          19220985000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19221015000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19223295000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          19223595000
 test master 2 - Starting Memory Read, at          19223775000
 test master 2 - Starting Memory Read, at          19223955000
 test master 2 - Starting Memory Read, at          19224225000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19225815000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          19226235000
 test master 2 - Starting Memory Read, at          19226415000
 test master 2 - Starting Memory Read, at          19226865000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19228335000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19228905000
 test master 2 - Starting Memory Read Line Multiple, at          19229085000
 test master 2 - Starting Memory Read Line Multiple, at          19229265000
 test master 2 - Starting Memory Read Line Multiple, at          19229445000
 test master 2 - Starting Memory Read Line Multiple, at          19229775000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19231515000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19240335000
 test master 2 - Starting Memory Read Line Multiple, at          19240515000
 test master 2 - Starting Memory Read Line Multiple, at          19240695000
 test master 2 - Starting Memory Read Line Multiple, at          19240875000
 test master 2 - Starting Memory Read Line Multiple, at          19241205000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19241745000
 test master 2 - Starting Memory Read Line Multiple, at          19241925000
 test master 2 - Starting Memory Read Line Multiple, at          19242105000
 test master 2 - Starting Memory Read Line Multiple, at          19242285000
 test master 2 - Starting Memory Read Line Multiple, at          19242645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19243185000
 test master 2 - Starting Memory Read Line Multiple, at          19243365000
 test master 2 - Starting Memory Read Line Multiple, at          19243545000
 test master 2 - Starting Memory Read Line Multiple, at          19243725000
 test master 2 - Starting Memory Read Line Multiple, at          19244085000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19244625000
 test master 2 - Starting Memory Read Line Multiple, at          19244805000
 test master 2 - Starting Memory Read Line Multiple, at          19244985000
 test master 2 - Starting Memory Read Line Multiple, at          19245165000
 test master 2 - Starting Memory Read Line Multiple, at          19245525000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19246065000
 test master 2 - Starting Memory Read Line Multiple, at          19246245000
 test master 2 - Starting Memory Read Line Multiple, at          19246425000
 test master 2 - Starting Memory Read Line Multiple, at          19246605000
 test master 2 - Starting Memory Read Line Multiple, at          19246965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19247505000
 test master 2 - Starting Memory Read Line Multiple, at          19247685000
 test master 2 - Starting Memory Read Line Multiple, at          19247865000
 test master 2 - Starting Memory Read Line Multiple, at          19248045000
 test master 2 - Starting Memory Read Line Multiple, at          19248405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19248945000
 test master 2 - Starting Memory Read Line Multiple, at          19249125000
 test master 2 - Starting Memory Read Line Multiple, at          19249305000
 test master 2 - Starting Memory Read Line Multiple, at          19249485000
 test master 2 - Starting Memory Read Line Multiple, at          19249845000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19250385000
 test master 2 - Starting Memory Read Line Multiple, at          19250565000
 test master 2 - Starting Memory Read Line Multiple, at          19250745000
 test master 2 - Starting Memory Read Line Multiple, at          19250925000
 test master 2 - Starting Memory Read Line Multiple, at          19251285000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          19251825000
 test master 2 - Starting Memory Read Line, at          19252005000
 test master 2 - Starting Memory Read Line, at          19252185000
 test master 2 - Starting Memory Read Line, at          19252485000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          19252845000
 test master 2 - Starting Memory Read Line, at          19253025000
 test master 2 - Starting Memory Read Line, at          19253475000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19254645000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19256325000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19259385000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19261305000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          19266435000
 test master 2 - Starting Memory Write, at          19266735000
 test master 2 - Starting Memory Write, at          19267035000
 test master 2 - Starting Memory Write, at          19267335000
 test master 2 - Starting Memory Write, at          19267635000
 test master 1 - Starting Memory Read, at          19268055000
 test master 1 - Starting Memory Read, at          19268415000
 test master 1 - Starting Memory Read, at          19268955000
 test master 1 - Starting Memory Read, at          19269315000
 test master 1 - Starting Memory Read, at          19269855000
 test master 1 - Starting Memory Read, at          19270215000
 test master 2 - Starting Memory Write, at          19271535000
 test master 2 - Starting Memory Write, at          19271835000
 test master 2 - Starting Memory Write, at          19272135000
 test master 2 - Starting Memory Write, at          19272435000
 test master 2 - Starting Memory Write, at          19272735000
 test master 1 - Starting Memory Read, at          19273155000
 test master 1 - Starting Memory Read, at          19273515000
 test master 1 - Starting Memory Read, at          19274055000
 test master 1 - Starting Memory Read, at          19274415000
 test master 1 - Starting Memory Read, at          19274955000
 test master 1 - Starting Memory Read, at          19275315000
 test master 2 - Starting Memory Write, at          19277175000
 test master 2 - Starting Memory Write, at          19278345000
 test master 2 - Starting Memory Write, at          19279545000
 test master 2 - Starting Memory Write, at          19280745000
 test master 2 - Starting Memory Write, at          19283175000
 test master 2 - Starting Memory Write, at          19284345000
 test master 2 - Starting Memory Write, at          19285545000
 test master 2 - Starting Memory Write, at          19286745000
 test master 2 - Starting Memory Write, at          19289175000
 test master 2 - Starting Memory Write, at          19291365000
 test master 2 - Starting Memory Write, at          19293585000
 test master 2 - Starting Memory Write, at          19295805000
 test master 2 - Starting Memory Write, at          19299255000
 test master 2 - Starting Memory Write, at          19301715000
 test master 2 - Starting Memory Write, at          19304175000
 test master 2 - Starting Memory Write, at          19306635000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          19311225000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19311255000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19313535000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          19313835000
 test master 2 - Starting Memory Read, at          19314015000
 test master 2 - Starting Memory Read, at          19314195000
 test master 2 - Starting Memory Read, at          19314465000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19316055000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          19316475000
 test master 2 - Starting Memory Read, at          19316655000
 test master 2 - Starting Memory Read, at          19317105000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19318575000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19319145000
 test master 2 - Starting Memory Read Line Multiple, at          19319325000
 test master 2 - Starting Memory Read Line Multiple, at          19319505000
 test master 2 - Starting Memory Read Line Multiple, at          19319685000
 test master 2 - Starting Memory Read Line Multiple, at          19320015000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19321755000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19330575000
 test master 2 - Starting Memory Read Line Multiple, at          19330755000
 test master 2 - Starting Memory Read Line Multiple, at          19330935000
 test master 2 - Starting Memory Read Line Multiple, at          19331115000
 test master 2 - Starting Memory Read Line Multiple, at          19331445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19331985000
 test master 2 - Starting Memory Read Line Multiple, at          19332165000
 test master 2 - Starting Memory Read Line Multiple, at          19332345000
 test master 2 - Starting Memory Read Line Multiple, at          19332525000
 test master 2 - Starting Memory Read Line Multiple, at          19332885000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19333425000
 test master 2 - Starting Memory Read Line Multiple, at          19333605000
 test master 2 - Starting Memory Read Line Multiple, at          19333785000
 test master 2 - Starting Memory Read Line Multiple, at          19333965000
 test master 2 - Starting Memory Read Line Multiple, at          19334325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19334865000
 test master 2 - Starting Memory Read Line Multiple, at          19335045000
 test master 2 - Starting Memory Read Line Multiple, at          19335225000
 test master 2 - Starting Memory Read Line Multiple, at          19335405000
 test master 2 - Starting Memory Read Line Multiple, at          19335765000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19336305000
 test master 2 - Starting Memory Read Line Multiple, at          19336485000
 test master 2 - Starting Memory Read Line Multiple, at          19336665000
 test master 2 - Starting Memory Read Line Multiple, at          19336845000
 test master 2 - Starting Memory Read Line Multiple, at          19337205000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19337745000
 test master 2 - Starting Memory Read Line Multiple, at          19337925000
 test master 2 - Starting Memory Read Line Multiple, at          19338105000
 test master 2 - Starting Memory Read Line Multiple, at          19338285000
 test master 2 - Starting Memory Read Line Multiple, at          19338645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19339185000
 test master 2 - Starting Memory Read Line Multiple, at          19339365000
 test master 2 - Starting Memory Read Line Multiple, at          19339545000
 test master 2 - Starting Memory Read Line Multiple, at          19339725000
 test master 2 - Starting Memory Read Line Multiple, at          19340085000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19340625000
 test master 2 - Starting Memory Read Line Multiple, at          19340805000
 test master 2 - Starting Memory Read Line Multiple, at          19340985000
 test master 2 - Starting Memory Read Line Multiple, at          19341165000
 test master 2 - Starting Memory Read Line Multiple, at          19341525000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          19342065000
 test master 2 - Starting Memory Read Line, at          19342245000
 test master 2 - Starting Memory Read Line, at          19342425000
 test master 2 - Starting Memory Read Line, at          19342725000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          19343085000
 test master 2 - Starting Memory Read Line, at          19343265000
 test master 2 - Starting Memory Read Line, at          19343715000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19344885000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19346565000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19349625000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19351545000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          19356675000
 test master 2 - Starting Memory Write, at          19356975000
 test master 2 - Starting Memory Write, at          19357275000
 test master 2 - Starting Memory Write, at          19357575000
 test master 2 - Starting Memory Write, at          19357875000
 test master 1 - Starting Memory Read, at          19358295000
 test master 1 - Starting Memory Read, at          19358655000
 test master 1 - Starting Memory Read, at          19359195000
 test master 1 - Starting Memory Read, at          19359555000
 test master 1 - Starting Memory Read, at          19360095000
 test master 1 - Starting Memory Read, at          19360455000
 test master 2 - Starting Memory Write, at          19361775000
 test master 2 - Starting Memory Write, at          19362075000
 test master 2 - Starting Memory Write, at          19362375000
 test master 2 - Starting Memory Write, at          19362675000
 test master 2 - Starting Memory Write, at          19362975000
 test master 1 - Starting Memory Read, at          19363395000
 test master 1 - Starting Memory Read, at          19363755000
 test master 1 - Starting Memory Read, at          19364295000
 test master 1 - Starting Memory Read, at          19364655000
 test master 1 - Starting Memory Read, at          19365195000
 test master 1 - Starting Memory Read, at          19365555000
 test master 2 - Starting Memory Write, at          19367415000
 test master 2 - Starting Memory Write, at          19368585000
 test master 2 - Starting Memory Write, at          19369785000
 test master 2 - Starting Memory Write, at          19370985000
 test master 2 - Starting Memory Write, at          19373415000
 test master 2 - Starting Memory Write, at          19374585000
 test master 2 - Starting Memory Write, at          19375785000
 test master 2 - Starting Memory Write, at          19376985000
 test master 2 - Starting Memory Write, at          19379415000
 test master 2 - Starting Memory Write, at          19381605000
 test master 2 - Starting Memory Write, at          19383825000
 test master 2 - Starting Memory Write, at          19386045000
 test master 2 - Starting Memory Write, at          19389495000
 test master 2 - Starting Memory Write, at          19391955000
 test master 2 - Starting Memory Write, at          19394415000
 test master 2 - Starting Memory Write, at          19396875000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          19401465000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19401495000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19403775000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          19404075000
 test master 2 - Starting Memory Read, at          19404255000
 test master 2 - Starting Memory Read, at          19404435000
 test master 2 - Starting Memory Read, at          19404705000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19406295000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          19406715000
 test master 2 - Starting Memory Read, at          19406895000
 test master 2 - Starting Memory Read, at          19407345000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19408815000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19409385000
 test master 2 - Starting Memory Read Line Multiple, at          19409565000
 test master 2 - Starting Memory Read Line Multiple, at          19409745000
 test master 2 - Starting Memory Read Line Multiple, at          19409925000
 test master 2 - Starting Memory Read Line Multiple, at          19410255000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19411995000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19420815000
 test master 2 - Starting Memory Read Line Multiple, at          19420995000
 test master 2 - Starting Memory Read Line Multiple, at          19421175000
 test master 2 - Starting Memory Read Line Multiple, at          19421355000
 test master 2 - Starting Memory Read Line Multiple, at          19421685000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19422225000
 test master 2 - Starting Memory Read Line Multiple, at          19422405000
 test master 2 - Starting Memory Read Line Multiple, at          19422585000
 test master 2 - Starting Memory Read Line Multiple, at          19422765000
 test master 2 - Starting Memory Read Line Multiple, at          19423125000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19423665000
 test master 2 - Starting Memory Read Line Multiple, at          19423845000
 test master 2 - Starting Memory Read Line Multiple, at          19424025000
 test master 2 - Starting Memory Read Line Multiple, at          19424205000
 test master 2 - Starting Memory Read Line Multiple, at          19424565000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19425105000
 test master 2 - Starting Memory Read Line Multiple, at          19425285000
 test master 2 - Starting Memory Read Line Multiple, at          19425465000
 test master 2 - Starting Memory Read Line Multiple, at          19425645000
 test master 2 - Starting Memory Read Line Multiple, at          19426005000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19426545000
 test master 2 - Starting Memory Read Line Multiple, at          19426725000
 test master 2 - Starting Memory Read Line Multiple, at          19426905000
 test master 2 - Starting Memory Read Line Multiple, at          19427085000
 test master 2 - Starting Memory Read Line Multiple, at          19427445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19427985000
 test master 2 - Starting Memory Read Line Multiple, at          19428165000
 test master 2 - Starting Memory Read Line Multiple, at          19428345000
 test master 2 - Starting Memory Read Line Multiple, at          19428525000
 test master 2 - Starting Memory Read Line Multiple, at          19428885000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19429425000
 test master 2 - Starting Memory Read Line Multiple, at          19429605000
 test master 2 - Starting Memory Read Line Multiple, at          19429785000
 test master 2 - Starting Memory Read Line Multiple, at          19429965000
 test master 2 - Starting Memory Read Line Multiple, at          19430325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          19430865000
 test master 2 - Starting Memory Read Line Multiple, at          19431045000
 test master 2 - Starting Memory Read Line Multiple, at          19431225000
 test master 2 - Starting Memory Read Line Multiple, at          19431405000
 test master 2 - Starting Memory Read Line Multiple, at          19431765000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          19432305000
 test master 2 - Starting Memory Read Line, at          19432485000
 test master 2 - Starting Memory Read Line, at          19432665000
 test master 2 - Starting Memory Read Line, at          19432965000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          19433325000
 test master 2 - Starting Memory Read Line, at          19433505000
 test master 2 - Starting Memory Read Line, at          19433955000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19435125000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19436805000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19439865000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          19441785000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          19446915000
 test master 2 - Starting Memory Write, at          19447215000
 test master 2 - Starting Memory Write, at          19447515000
 test master 2 - Starting Memory Write, at          19447815000
 test master 2 - Starting Memory Write, at          19448115000
 test master 1 - Starting Memory Read, at          19448535000
 test master 1 - Starting Memory Read, at          19448895000
 test master 1 - Starting Memory Read, at          19449435000
 test master 1 - Starting Memory Read, at          19449795000
 test master 1 - Starting Memory Read, at          19450335000
 test master 1 - Starting Memory Read, at          19450695000
 test master 2 - Starting Memory Write, at          19452015000
 test master 2 - Starting Memory Write, at          19452315000
 test master 2 - Starting Memory Write, at          19452615000
 test master 2 - Starting Memory Write, at          19452915000
 test master 2 - Starting Memory Write, at          19453215000
 test master 1 - Starting Memory Read, at          19453635000
 test master 1 - Starting Memory Read, at          19453995000
 test master 1 - Starting Memory Read, at          19454535000
 test master 1 - Starting Memory Read, at          19454895000
 test master 1 - Starting Memory Read, at          19455435000
 test master 1 - Starting Memory Read, at          19455795000
 test master 2 - Starting Memory Write, at          19457655000
 test master 2 - Starting Memory Write, at          19458825000
 test master 2 - Starting Memory Write, at          19460025000
 test master 2 - Starting Memory Write, at          19461225000
 test master 2 - Starting Memory Write, at          19463655000
 test master 2 - Starting Memory Write, at          19464825000
 test master 2 - Starting Memory Write, at          19466025000
 test master 2 - Starting Memory Write, at          19467225000
 test master 2 - Starting Memory Write, at          19469655000
 test master 2 - Starting Memory Write, at          19471845000
 test master 2 - Starting Memory Write, at          19474065000
 test master 2 - Starting Memory Write, at          19476285000
 test master 2 - Starting Memory Write, at          19479735000
 test master 2 - Starting Memory Write, at          19482195000
 test master 2 - Starting Memory Write, at          19484655000
 test master 2 - Starting Memory Write, at          19487115000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          19491705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19491735000
 test master 1 - Starting Memory Read, at          19494015000
 test master 1 - Starting Memory Read, at          19494405000
 test master 1 - Starting Memory Read, at          19495695000
 test master 1 - Starting Memory Read, at          19496085000
 test master 1 - Starting Memory Read Line, at          19497375000
 test master 1 - Starting Memory Read Line, at          19497765000
 test master 1 - Starting Memory Read Line, at          19499055000
 test master 1 - Starting Memory Read Line, at          19499505000
 test master 1 - Starting Memory Read Line, at          19500855000
 test master 1 - Starting Memory Read Line, at          19501485000
 test master 1 - Starting Memory Read Line, at          19502955000
 test master 1 - Starting Memory Read Line, at          19503585000
 test master 1 - Starting Memory Read Line Multiple, at          19505055000
 test master 1 - Starting Memory Read Line Multiple, at          19505925000
 test master 1 - Starting Memory Read Line Multiple, at          19507575000
 test master 1 - Starting Memory Read Line Multiple, at          19508445000
 test master 1 - Starting Memory Read Line, at          19510095000
 test master 1 - Starting Memory Read Line, at          19510725000
 test master 1 - Starting Memory Read, at          19513335000
 test master 1 - Starting Memory Read, at          19513725000
 test target 1 - Starting Config Write, at          19517235000
 test master 1 - Starting Memory Write, at          19517865000
 test master 1 - Starting Memory Write, at          19521645000
 test master 1 - Starting Memory Write, at          19526715000
 test master 1 - Starting Memory Write, at          19530255000
 test master 1 - Starting Memory Write, at          19535175000
 test master 1 - Starting Memory Read Line, at          19538955000
 test master 1 - Starting Memory Write, at          19544415000
 test master 1 - Starting Memory Read Line, at          19548195000
 test target 1 - Starting Config Write, at          19555455000
 test master 1 - Starting Memory Write, at          19556085000
 test master 1 - Starting Memory Write, at          19556205000
 test master 1 - Starting Memory Write, at          19556505000
 test master 1 - Starting Memory Read, at          19556625000
 test master 1 - Starting Memory Write, at          19557015000
 test master 1 - Starting Memory Read, at          19557135000
 test master 1 - Starting Memory Write, at          19558905000
 test master 1 - Starting Memory Write, at          19567755000
 test master 2 - Starting Memory Read Line, at          19576695000
 test master 2 - Starting Memory Read Line, at          19577295000
 test master 2 - Starting Memory Read Line, at          19577685000
 test master 2 - Starting Memory Read Line, at          19578285000
 test master 1 - Starting Memory Write, at          19578765000
 test master 1 - Starting Memory Write, at          19579065000
 test master 1 - Starting Memory Write, at          19579365000
 test master 2 - Starting Memory Read Line, at          19579785000
 test master 2 - Starting Memory Read Line, at          19580175000
 test master 2 - Starting Memory Read Line, at          19580415000
 test master 2 - Starting Memory Read Line, at          19580805000
 test master 2 - Starting Memory Read Line Multiple, at          19581075000
 test master 2 - Starting Memory Read Line Multiple, at          19581465000
 test master 1 - Starting Memory Write, at          19583475000
 test master 1 - Starting Memory Write, at          19583775000
 test master 2 - Starting Memory Read, at          19584195000
 test master 2 - Starting Memory Read, at          19584585000
 test master 2 - Starting Memory Read, at          19584825000
 test master 2 - Starting Memory Read, at          19585215000
 test master 1 - Starting Memory Write, at          19586955000
 test master 1 - Starting Memory Read, at          19587135000
 test master 1 - Starting Memory Write, at          19587315000
 test master 1 - Starting Memory Read, at          19587525000
 test master 1 - Starting Memory Write, at          19587735000
 test master 1 - Starting Memory Read, at          19587915000
 test master 1 - Starting Memory Read, at          19588125000
 test master 1 - Starting Memory Write, at          19588335000
 test master 1 - Starting Memory Write, at          19588515000
 test master 1 - Starting Memory Read, at          19588695000
 test master 1 - Starting Memory Write, at          19588875000
 test master 1 - Starting Memory Write, at          19589085000
 test master 1 - Starting Memory Write, at          19589295000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          19594095000
 test target 1 - Starting Memory Write, at          19594365000
 test master 1 - Starting Memory Write, at          19594605000
 test target 1 - Starting Memory Write, at          19594785000
 test target 1 - Starting Memory Write, at          19595055000
 test target 1 - Starting Memory Write, at          19595325000
 test master 1 - Starting Memory Write, at          19595685000
 test target 1 - Starting Memory Write, at          19596255000
 test target 1 - Starting Memory Write, at          19596915000
 test target 1 - Starting Memory Write, at          19597215000
 test master 1 - Starting Memory Write, at          19597485000
 test target 1 - Starting Memory Write, at          19597785000
 test target 1 - Starting Memory Write, at          19598085000
 test target 1 - Starting Memory Write, at          19598385000
 test master 1 - Starting Memory Write, at          19598865000
 test target 1 - Starting Memory Write, at          19599705000
 test target 1 - Starting Memory Write, at          19600665000
 test target 1 - Starting Memory Write, at          19600935000
 test master 1 - Starting Memory Read, at          19601175000
 test target 1 - Starting Memory Write, at          19601355000
 test master 1 - Starting Memory Read, at          19601595000
 test target 1 - Starting Memory Write, at          19601775000
 test master 1 - Starting Memory Read, at          19602015000
 test target 1 - Starting Memory Write, at          19602195000
 test master 1 - Starting Memory Read, at          19602435000
 test target 1 - Starting Memory Write, at          19602615000
 test master 1 - Starting Memory Read, at          19602855000
 test target 1 - Starting Memory Write, at          19603035000
 test master 1 - Starting Memory Write, at          19603275000
 test target 1 - Starting Memory Write, at          19603455000
 test target 1 - Starting Memory Write, at          19603725000
 test target 1 - Starting Memory Write, at          19603995000
 test target 1 - Starting Memory Read, at          19604325000
 test master 1 - Starting Memory Write, at          19604685000
 test master 1 - Starting Memory Read, at          19604895000
 test target 1 - Starting Memory Write, at          19605405000
 test master 1 - Starting Memory Write, at          19605855000
 test target 1 - Starting Memory Read, at          19606305000
 test target 1 - Starting Memory Write, at          19607175000
 test master 1 - Starting Memory Read, at          19607535000
 test master 1 - Starting Memory Write, at          19607925000
 test master 1 - Starting Memory Write, at          19608285000
 test master 1 - Starting Memory Read, at          19608585000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          19611315000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          19612425000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          19639125000
 test target 1 - Starting Config Write, at          19640085000
 test target 1 - Starting Config Write, at          19641045000
 test target 2 - Starting Config Write, at          19642005000
 test target 2 - Starting Config Write, at          19642965000
 test target 2 - Starting Config Write, at          19643925000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          19646115000
 test target 1 - Starting Memory Read, at          19646355000
 test target 1 - Starting Memory Write, at          19647015000
 test target 1 - Starting Memory Read, at          19647255000
 test target 1 - Starting Memory Write, at          19648515000
 test target 1 - Starting Memory Read, at          19649355000
 test target 1 - Starting Memory Read, at          19650045000
 test target 1 - Starting Memory Read, at          19650735000
 test target 1 - Starting Memory Read, at          19651455000
 test target 1 - Starting Memory Read, at          19652415000
 test target 1 - Starting Memory Read, at          19653465000
 test target 1 - Starting Memory Read, at          19654395000
 test target 1 - Starting Memory Read, at          19655445000
 test target 1 - Starting Memory Read, at          19656375000
 test target 1 - Starting Memory Read, at          19657815000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          19664655000
 test target 1 - Starting Memory Read, at          19664895000
 test target 1 - Starting Memory Write, at          19665555000
 test target 1 - Starting Memory Read, at          19665795000
 test target 1 - Starting Memory Write, at          19667055000
 test target 1 - Starting Memory Read, at          19667895000
 test target 1 - Starting Memory Read, at          19668585000
 test target 1 - Starting Memory Read, at          19669275000
 test target 1 - Starting Memory Read, at          19669995000
 test target 1 - Starting Memory Read, at          19670955000
 test target 1 - Starting Memory Read, at          19672005000
 test target 1 - Starting Memory Read, at          19672935000
 test target 1 - Starting Memory Read, at          19673985000
 test target 1 - Starting Memory Read, at          19674915000
 test target 1 - Starting Memory Read, at          19676355000
 test target 1 - Starting Memory Write, at          19683195000
 test target 1 - Starting Memory Read, at          19683435000
 test target 1 - Starting Memory Write, at          19684095000
 test target 1 - Starting Memory Read, at          19684335000
 test target 1 - Starting Memory Write, at          19685595000
 test target 1 - Starting Memory Read, at          19686435000
 test target 1 - Starting Memory Read, at          19687125000
 test target 1 - Starting Memory Read, at          19687815000
 test target 1 - Starting Memory Read, at          19688535000
 test target 1 - Starting Memory Read, at          19689495000
 test target 1 - Starting Memory Read, at          19690545000
 test target 1 - Starting Memory Read, at          19691475000
 test target 1 - Starting Memory Read, at          19692525000
 test target 1 - Starting Memory Read, at          19693455000
 test target 1 - Starting Memory Read, at          19694895000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          19708545000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          19715745000
 test target 1 - Starting Memory Write, at          19716675000
 test target 1 - Starting Memory Read, at          19716975000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          19718175000
 test target 1 - Starting Config Write, at          19720185000
 test target 1 - Starting Memory Read, at          19720875000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          19722525000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          19724865000
 test target 1 - Starting Memory Write, at          19726155000
 test target 1 - Starting Memory Write, at          19726425000
 test target 1 - Starting Memory Read, at          19726665000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          19729365000
 test target 1 - Starting Memory Write, at          19732845000
 test target 1 - Starting Memory Write, at          19733235000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          19737585000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          19739745000
 test target 1 - Starting Memory Read, at          19741245000
 test target 1 - Starting Memory Read, at          19742205000
 test target 1 - Starting Memory Read, at          19743915000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          19750605000
 test target 2 - Starting Config Write, at          19751565000
 test target 1 - Starting Memory Write, at          19752255000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          19752405000
 test target 1 - Starting Memory Write, at          19753515000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          19753665000
 test target 1 - Starting Memory Write, at          19754775000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          19756335000
 test target 1 - Starting Memory Read, at          19758765000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          19758915000
 test target 1 - Starting Memory Read, at          19761315000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          19763235000
 test master 2 - Starting Memory Write, at          19763235000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          19763295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19764225000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19764255000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19764555000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19764585000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19765575000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19765605000
 test target 1 - Starting Memory Write, at          19767615000
 test master 2 - Starting Memory Write, at          19767615000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19769535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19769565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19771455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19771485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19773375000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19773405000
 test target 1 - Starting Memory Write, at          19775715000
 test master 2 - Starting Memory Write, at          19775715000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          19775775000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19777605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19777635000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19777935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19777965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19778955000
*** monitor - CBE Bus Changed when TRDY Desserted, at          19778985000
 test target 1 - Starting Memory Write, at          19780275000
 test master 2 - Starting Memory Write, at          19780275000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          19783665000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          19785495000
 test master 1 - Starting Memory Read, at          19785825000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          19785975000
 test target 1 - Starting Config Write, at          19788885000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          19791855000
 test target 1 - Starting Memory Write, at          19792035000
 test target 1 - Starting Memory Write, at          19792215000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          19792755000
 test target 1 - Starting Memory Write, at          19792965000
 test target 1 - Starting Memory Write, at          19793175000
 test target 1 - Starting Memory Write, at          19793715000
 test target 1 - Starting Memory Write, at          19793925000
 test target 1 - Starting Memory Write, at          19794465000
 test target 1 - Starting Memory Write, at          19795155000
 test target 1 - Starting Memory Write, at          19795365000
 test target 1 - Starting Memory Write, at          19796055000
 test target 1 - Starting Memory Write, at          19796295000
 test target 1 - Starting Memory Write, at          19796955000
 test target 1 - Starting Memory Write, at          19804845000
 test target 1 - Starting Memory Write, at          19805055000
 test target 1 - Starting Memory Write, at          19805265000
 test target 1 - Starting Memory Write, at          19805505000
 test target 1 - Starting Memory Write, at          19805745000
 test target 1 - Starting Memory Read, at          19807695000
 test target 1 - Starting Memory Read, at          19808745000
 test target 1 - Starting Memory Read, at          19809795000
 test target 1 - Starting Memory Read, at          19810875000
 test target 1 - Starting Memory Read, at          19811925000
 test target 1 - Starting Memory Read, at          19812975000
 test target 1 - Starting Memory Read, at          19814055000
 test target 1 - Starting Memory Read, at          19815105000
 test target 1 - Starting Memory Read, at          19816155000
 test target 1 - Starting Memory Read, at          19817235000
 test target 1 - Starting Memory Read, at          19818285000
 test target 1 - Starting Memory Read, at          19819335000
 test target 1 - Starting Memory Read, at          19820415000
 test target 1 - Starting Memory Read, at          19821465000
 test target 1 - Starting Memory Read, at          19822515000
 test target 1 - Starting Memory Read, at          19823595000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          19824435000
 test target 1 - Starting Memory Read, at          19824615000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          19827105000
 test target 1 - Starting Memory Read, at          19827795000
 test target 1 - Starting Memory Read, at          19828515000
 test target 1 - Starting Memory Read, at          19829205000
 test target 1 - Starting Memory Read, at          19829955000
 test target 1 - Starting Memory Read, at          19830675000
 test target 1 - Starting Memory Read, at          19831755000
 test target 1 - Starting Memory Read, at          19832805000
 test target 1 - Starting Memory Read, at          19833735000
 test target 1 - Starting Memory Read, at          19836405000
 test target 1 - Starting Memory Read, at          19837995000
 test target 1 - Starting Memory Read, at          19838955000
 test target 1 - Starting Memory Read, at          19839915000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          19841505000
 test master 1 - Starting Memory Write, at          19841715000
 test target 1 - Starting Memory Write, at          19841715000
 test target 1 - Starting Memory Write, at          19841895000
 test target 1 - Starting Memory Read, at          19842195000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          19843815000
 test master 1 - Starting Memory Write, at          19844025000
 test target 1 - Starting Memory Write, at          19844025000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          19849365000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          19850475000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          19877205000
 test target 1 - Starting Config Write, at          19878165000
 test target 1 - Starting Config Write, at          19879125000
 test target 2 - Starting Config Write, at          19880085000
 test target 2 - Starting Config Write, at          19881045000
 test target 2 - Starting Config Write, at          19882005000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          19884195000
 test target 1 - Starting Memory Read, at          19884465000
 test target 1 - Starting Memory Write, at          19885275000
 test target 1 - Starting Memory Read, at          19885545000
 test target 1 - Starting Memory Write, at          19887015000
 test target 1 - Starting Memory Read, at          19887885000
 test target 1 - Starting Memory Read, at          19888575000
 test target 1 - Starting Memory Read, at          19889295000
 test target 1 - Starting Memory Read, at          19889985000
 test target 1 - Starting Memory Read, at          19890975000
 test target 1 - Starting Memory Read, at          19892025000
 test target 1 - Starting Memory Read, at          19892955000
 test target 1 - Starting Memory Read, at          19894005000
 test target 1 - Starting Memory Read, at          19894935000
 test target 1 - Starting Memory Read, at          19896375000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          19903455000
 test target 1 - Starting Memory Read, at          19903725000
 test target 1 - Starting Memory Write, at          19904565000
 test target 1 - Starting Memory Read, at          19904835000
 test target 1 - Starting Memory Write, at          19906275000
 test target 1 - Starting Memory Read, at          19907145000
 test target 1 - Starting Memory Read, at          19907835000
 test target 1 - Starting Memory Read, at          19908555000
 test target 1 - Starting Memory Read, at          19909245000
 test target 1 - Starting Memory Read, at          19910235000
 test target 1 - Starting Memory Read, at          19911285000
 test target 1 - Starting Memory Read, at          19912215000
 test target 1 - Starting Memory Read, at          19913265000
 test target 1 - Starting Memory Read, at          19914195000
 test target 1 - Starting Memory Read, at          19915635000
 test target 1 - Starting Memory Write, at          19922715000
 test target 1 - Starting Memory Read, at          19922985000
 test target 1 - Starting Memory Write, at          19923825000
 test target 1 - Starting Memory Read, at          19924095000
 test target 1 - Starting Memory Write, at          19925535000
 test target 1 - Starting Memory Read, at          19926405000
 test target 1 - Starting Memory Read, at          19927095000
 test target 1 - Starting Memory Read, at          19927815000
 test target 1 - Starting Memory Read, at          19928505000
 test target 1 - Starting Memory Read, at          19929495000
 test target 1 - Starting Memory Read, at          19930545000
 test target 1 - Starting Memory Read, at          19931475000
 test target 1 - Starting Memory Read, at          19932525000
 test target 1 - Starting Memory Read, at          19933455000
 test target 1 - Starting Memory Read, at          19934895000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          19948785000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          19955985000
 test target 1 - Starting Memory Write, at          19956915000
 test target 1 - Starting Memory Read, at          19957245000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          19958595000
 test target 1 - Starting Config Write, at          19960605000
 test target 1 - Starting Memory Read, at          19961295000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          19962945000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          19965285000
 test target 1 - Starting Memory Write, at          19966575000
 test target 1 - Starting Memory Write, at          19966875000
 test target 1 - Starting Memory Read, at          19967145000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          19969995000
 test target 1 - Starting Memory Write, at          19973505000
 test target 1 - Starting Memory Write, at          19973895000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          19978305000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          19980465000
 test target 1 - Starting Memory Read, at          19981965000
 test target 1 - Starting Memory Read, at          19982925000
 test target 1 - Starting Memory Read, at          19984815000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          19991505000
 test target 2 - Starting Config Write, at          19992465000
 test target 1 - Starting Memory Write, at          19993155000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          19993335000
 test target 1 - Starting Memory Write, at          19994475000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          19994655000
 test target 1 - Starting Memory Write, at          19995795000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          19997385000
 test target 1 - Starting Memory Read, at          19999815000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          19999995000
 test target 1 - Starting Memory Read, at          20002365000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          20004285000
 test master 2 - Starting Memory Write, at          20004285000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          20004345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20005305000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20005335000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20005635000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20005665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20006655000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20006685000
 test target 1 - Starting Memory Write, at          20008695000
 test master 2 - Starting Memory Write, at          20008695000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20010645000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20010675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20012565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20012595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20014485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20014515000
 test target 1 - Starting Memory Write, at          20016825000
 test master 2 - Starting Memory Write, at          20016825000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          20016885000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20018745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20018775000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20019075000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20019105000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20020095000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20020125000
 test target 1 - Starting Memory Write, at          20021415000
 test master 2 - Starting Memory Write, at          20021415000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          20024835000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          20026665000
 test master 1 - Starting Memory Read, at          20027025000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          20027175000
 test target 1 - Starting Config Write, at          20030085000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          20033055000
 test target 1 - Starting Memory Write, at          20033265000
 test target 1 - Starting Memory Write, at          20033475000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          20034045000
 test target 1 - Starting Memory Write, at          20034285000
 test target 1 - Starting Memory Write, at          20034525000
 test target 1 - Starting Memory Write, at          20035095000
 test target 1 - Starting Memory Write, at          20035335000
 test target 1 - Starting Memory Write, at          20035905000
 test target 1 - Starting Memory Write, at          20036625000
 test target 1 - Starting Memory Write, at          20036865000
 test target 1 - Starting Memory Write, at          20037585000
 test target 1 - Starting Memory Write, at          20037855000
 test target 1 - Starting Memory Write, at          20038545000
 test target 1 - Starting Memory Write, at          20046465000
 test target 1 - Starting Memory Write, at          20046705000
 test target 1 - Starting Memory Write, at          20046945000
 test target 1 - Starting Memory Write, at          20047215000
 test target 1 - Starting Memory Write, at          20047485000
 test target 1 - Starting Memory Read, at          20049465000
 test target 1 - Starting Memory Read, at          20050545000
 test target 1 - Starting Memory Read, at          20051595000
 test target 1 - Starting Memory Read, at          20052675000
 test target 1 - Starting Memory Read, at          20053725000
 test target 1 - Starting Memory Read, at          20054775000
 test target 1 - Starting Memory Read, at          20055855000
 test target 1 - Starting Memory Read, at          20056905000
 test target 1 - Starting Memory Read, at          20057955000
 test target 1 - Starting Memory Read, at          20059035000
 test target 1 - Starting Memory Read, at          20060085000
 test target 1 - Starting Memory Read, at          20061135000
 test target 1 - Starting Memory Read, at          20062215000
 test target 1 - Starting Memory Read, at          20063265000
 test target 1 - Starting Memory Read, at          20064315000
 test target 1 - Starting Memory Read, at          20065395000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          20066235000
 test target 1 - Starting Memory Read, at          20066445000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          20069115000
 test target 1 - Starting Memory Read, at          20069835000
 test target 1 - Starting Memory Read, at          20070555000
 test target 1 - Starting Memory Read, at          20071365000
 test target 1 - Starting Memory Read, at          20072115000
 test target 1 - Starting Memory Read, at          20072835000
 test target 1 - Starting Memory Read, at          20073915000
 test target 1 - Starting Memory Read, at          20074965000
 test target 1 - Starting Memory Read, at          20075895000
 test target 1 - Starting Memory Read, at          20078715000
 test target 1 - Starting Memory Read, at          20080305000
 test target 1 - Starting Memory Read, at          20081295000
 test target 1 - Starting Memory Read, at          20082255000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          20083845000
 test master 1 - Starting Memory Write, at          20084055000
 test target 1 - Starting Memory Write, at          20084055000
 test target 1 - Starting Memory Write, at          20084265000
 test target 1 - Starting Memory Read, at          20084625000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          20086335000
 test master 1 - Starting Memory Write, at          20086545000
 test target 1 - Starting Memory Write, at          20086545000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          20091885000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          20092995000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          20119725000
 test target 1 - Starting Config Write, at          20120925000
 test target 1 - Starting Config Write, at          20122125000
 test target 2 - Starting Config Write, at          20123325000
 test target 2 - Starting Config Write, at          20124525000
 test target 2 - Starting Config Write, at          20125725000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          20128155000
 test target 1 - Starting Memory Read, at          20128455000
 test target 1 - Starting Memory Write, at          20129235000
 test target 1 - Starting Memory Read, at          20129535000
 test target 1 - Starting Memory Write, at          20130975000
 test target 1 - Starting Memory Read, at          20131875000
 test target 1 - Starting Memory Read, at          20132565000
 test target 1 - Starting Memory Read, at          20133255000
 test target 1 - Starting Memory Read, at          20133975000
 test target 1 - Starting Memory Read, at          20134935000
 test target 1 - Starting Memory Read, at          20136165000
 test target 1 - Starting Memory Read, at          20137335000
 test target 1 - Starting Memory Read, at          20138565000
 test target 1 - Starting Memory Read, at          20139735000
 test target 1 - Starting Memory Read, at          20141175000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          20148255000
 test target 1 - Starting Memory Read, at          20148555000
 test target 1 - Starting Memory Write, at          20149365000
 test target 1 - Starting Memory Read, at          20149665000
 test target 1 - Starting Memory Write, at          20151075000
 test target 1 - Starting Memory Read, at          20151975000
 test target 1 - Starting Memory Read, at          20152665000
 test target 1 - Starting Memory Read, at          20153355000
 test target 1 - Starting Memory Read, at          20154075000
 test target 1 - Starting Memory Read, at          20155035000
 test target 1 - Starting Memory Read, at          20156265000
 test target 1 - Starting Memory Read, at          20157435000
 test target 1 - Starting Memory Read, at          20158665000
 test target 1 - Starting Memory Read, at          20159835000
 test target 1 - Starting Memory Read, at          20161275000
 test target 1 - Starting Memory Write, at          20168355000
 test target 1 - Starting Memory Read, at          20168655000
 test target 1 - Starting Memory Write, at          20169465000
 test target 1 - Starting Memory Read, at          20169765000
 test target 1 - Starting Memory Write, at          20171175000
 test target 1 - Starting Memory Read, at          20172075000
 test target 1 - Starting Memory Read, at          20172765000
 test target 1 - Starting Memory Read, at          20173455000
 test target 1 - Starting Memory Read, at          20174175000
 test target 1 - Starting Memory Read, at          20175135000
 test target 1 - Starting Memory Read, at          20176365000
 test target 1 - Starting Memory Read, at          20177535000
 test target 1 - Starting Memory Read, at          20178765000
 test target 1 - Starting Memory Read, at          20179935000
 test target 1 - Starting Memory Read, at          20181375000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          20195265000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          20202705000
 test target 1 - Starting Memory Write, at          20203875000
 test target 1 - Starting Memory Read, at          20204235000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          20205555000
 test target 1 - Starting Config Write, at          20207805000
 test target 1 - Starting Memory Read, at          20208735000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          20210565000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          20213145000
 test target 1 - Starting Memory Write, at          20214675000
 test target 1 - Starting Memory Write, at          20215005000
 test target 1 - Starting Memory Read, at          20215305000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          20218125000
 test target 1 - Starting Memory Write, at          20221665000
 test target 1 - Starting Memory Write, at          20222055000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          20226465000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          20228865000
 test target 1 - Starting Memory Read, at          20230365000
 test target 1 - Starting Memory Read, at          20231325000
 test target 1 - Starting Memory Read, at          20233215000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          20240085000
 test target 2 - Starting Config Write, at          20241285000
 test target 1 - Starting Memory Write, at          20242215000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          20242425000
 test target 1 - Starting Memory Write, at          20243535000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          20243745000
 test target 1 - Starting Memory Write, at          20244855000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          20246475000
 test target 1 - Starting Memory Read, at          20249115000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          20249325000
 test target 1 - Starting Memory Read, at          20251875000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          20254005000
 test master 2 - Starting Memory Write, at          20254005000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          20254065000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20255055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20255085000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20255385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20255415000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20256405000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20256435000
 test target 1 - Starting Memory Write, at          20258445000
 test master 2 - Starting Memory Write, at          20258445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20260425000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20260455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20262345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20262375000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20264265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20264295000
 test target 1 - Starting Memory Write, at          20266605000
 test master 2 - Starting Memory Write, at          20266605000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          20266665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20268555000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20268585000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20268885000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20268915000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20269905000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20269935000
 test target 1 - Starting Memory Write, at          20271225000
 test master 2 - Starting Memory Write, at          20271225000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          20274675000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          20276505000
 test master 1 - Starting Memory Read, at          20276865000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          20277015000
 test target 1 - Starting Config Write, at          20279925000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          20282895000
 test target 1 - Starting Memory Write, at          20283135000
 test target 1 - Starting Memory Write, at          20283375000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          20283975000
 test target 1 - Starting Memory Write, at          20284245000
 test target 1 - Starting Memory Write, at          20284515000
 test target 1 - Starting Memory Write, at          20285115000
 test target 1 - Starting Memory Write, at          20285385000
 test target 1 - Starting Memory Write, at          20285985000
 test target 1 - Starting Memory Write, at          20286735000
 test target 1 - Starting Memory Write, at          20287005000
 test target 1 - Starting Memory Write, at          20287755000
 test target 1 - Starting Memory Write, at          20288055000
 test target 1 - Starting Memory Write, at          20288775000
 test target 1 - Starting Memory Write, at          20296725000
 test target 1 - Starting Memory Write, at          20296995000
 test target 1 - Starting Memory Write, at          20297265000
 test target 1 - Starting Memory Write, at          20297565000
 test target 1 - Starting Memory Write, at          20297865000
 test target 1 - Starting Memory Read, at          20299875000
 test target 1 - Starting Memory Read, at          20300985000
 test target 1 - Starting Memory Read, at          20302035000
 test target 1 - Starting Memory Read, at          20303115000
 test target 1 - Starting Memory Read, at          20304345000
 test target 1 - Starting Memory Read, at          20305395000
 test target 1 - Starting Memory Read, at          20306475000
 test target 1 - Starting Memory Read, at          20307705000
 test target 1 - Starting Memory Read, at          20308755000
 test target 1 - Starting Memory Read, at          20309835000
 test target 1 - Starting Memory Read, at          20311065000
 test target 1 - Starting Memory Read, at          20312115000
 test target 1 - Starting Memory Read, at          20313195000
 test target 1 - Starting Memory Read, at          20314425000
 test target 1 - Starting Memory Read, at          20315475000
 test target 1 - Starting Memory Read, at          20316555000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          20317575000
 test target 1 - Starting Memory Read, at          20317815000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          20320455000
 test target 1 - Starting Memory Read, at          20321205000
 test target 1 - Starting Memory Read, at          20321895000
 test target 1 - Starting Memory Read, at          20322705000
 test target 1 - Starting Memory Read, at          20323455000
 test target 1 - Starting Memory Read, at          20324175000
 test target 1 - Starting Memory Read, at          20325435000
 test target 1 - Starting Memory Read, at          20326665000
 test target 1 - Starting Memory Read, at          20327835000
 test target 1 - Starting Memory Read, at          20330655000
 test target 1 - Starting Memory Read, at          20332425000
 test target 1 - Starting Memory Read, at          20333415000
 test target 1 - Starting Memory Read, at          20334375000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          20335965000
 test master 1 - Starting Memory Write, at          20336205000
 test target 1 - Starting Memory Write, at          20336205000
 test target 1 - Starting Memory Write, at          20336445000
 test target 1 - Starting Memory Read, at          20336835000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          20338485000
 test master 1 - Starting Memory Write, at          20338725000
 test target 1 - Starting Memory Write, at          20338725000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          20344035000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          20345265000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          20372085000
 test target 1 - Starting Config Write, at          20373285000
 test target 1 - Starting Config Write, at          20374485000
 test target 2 - Starting Config Write, at          20375685000
 test target 2 - Starting Config Write, at          20376885000
 test target 2 - Starting Config Write, at          20378085000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          20380515000
 test target 1 - Starting Memory Read, at          20380845000
 test target 1 - Starting Memory Write, at          20381625000
 test target 1 - Starting Memory Read, at          20381955000
 test target 1 - Starting Memory Write, at          20383335000
 test target 1 - Starting Memory Read, at          20384265000
 test target 1 - Starting Memory Read, at          20384955000
 test target 1 - Starting Memory Read, at          20385675000
 test target 1 - Starting Memory Read, at          20386365000
 test target 1 - Starting Memory Read, at          20387355000
 test target 1 - Starting Memory Read, at          20388585000
 test target 1 - Starting Memory Read, at          20389755000
 test target 1 - Starting Memory Read, at          20390985000
 test target 1 - Starting Memory Read, at          20392155000
 test target 1 - Starting Memory Read, at          20393775000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          20400855000
 test target 1 - Starting Memory Read, at          20401185000
 test target 1 - Starting Memory Write, at          20401965000
 test target 1 - Starting Memory Read, at          20402295000
 test target 1 - Starting Memory Write, at          20403675000
 test target 1 - Starting Memory Read, at          20404605000
 test target 1 - Starting Memory Read, at          20405295000
 test target 1 - Starting Memory Read, at          20406015000
 test target 1 - Starting Memory Read, at          20406705000
 test target 1 - Starting Memory Read, at          20407695000
 test target 1 - Starting Memory Read, at          20408925000
 test target 1 - Starting Memory Read, at          20410095000
 test target 1 - Starting Memory Read, at          20411325000
 test target 1 - Starting Memory Read, at          20412495000
 test target 1 - Starting Memory Read, at          20414115000
 test target 1 - Starting Memory Write, at          20421195000
 test target 1 - Starting Memory Read, at          20421525000
 test target 1 - Starting Memory Write, at          20422305000
 test target 1 - Starting Memory Read, at          20422635000
 test target 1 - Starting Memory Write, at          20424015000
 test target 1 - Starting Memory Read, at          20424945000
 test target 1 - Starting Memory Read, at          20425635000
 test target 1 - Starting Memory Read, at          20426355000
 test target 1 - Starting Memory Read, at          20427045000
 test target 1 - Starting Memory Read, at          20428035000
 test target 1 - Starting Memory Read, at          20429265000
 test target 1 - Starting Memory Read, at          20430435000
 test target 1 - Starting Memory Read, at          20431665000
 test target 1 - Starting Memory Read, at          20432835000
 test target 1 - Starting Memory Read, at          20434455000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          20448345000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          20455785000
 test target 1 - Starting Memory Write, at          20456955000
 test target 1 - Starting Memory Read, at          20457345000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          20458635000
 test target 1 - Starting Config Write, at          20460885000
 test target 1 - Starting Memory Read, at          20461815000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          20463645000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          20466225000
 test target 1 - Starting Memory Write, at          20467755000
 test target 1 - Starting Memory Write, at          20468115000
 test target 1 - Starting Memory Read, at          20468445000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          20471205000
 test target 1 - Starting Memory Write, at          20474775000
 test target 1 - Starting Memory Write, at          20475165000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          20479605000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          20482005000
 test target 1 - Starting Memory Read, at          20483505000
 test target 1 - Starting Memory Read, at          20484645000
 test target 1 - Starting Memory Read, at          20486535000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          20493405000
 test target 2 - Starting Config Write, at          20494605000
 test target 1 - Starting Memory Write, at          20495535000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          20495775000
 test target 1 - Starting Memory Write, at          20496915000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          20497155000
 test target 1 - Starting Memory Write, at          20498295000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          20499945000
 test target 1 - Starting Memory Read, at          20502615000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          20502855000
 test target 1 - Starting Memory Read, at          20505375000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          20507505000
 test master 2 - Starting Memory Write, at          20507505000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          20507565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20508585000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20508615000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20508915000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20508945000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20509935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20509965000
 test target 1 - Starting Memory Write, at          20511975000
 test master 2 - Starting Memory Write, at          20511975000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20513985000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20514015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20515905000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20515935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20517825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20517855000
 test target 1 - Starting Memory Write, at          20520165000
 test master 2 - Starting Memory Write, at          20520165000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          20520225000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20522145000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20522175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20522475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20522505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20523495000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20523525000
 test target 1 - Starting Memory Write, at          20524815000
 test master 2 - Starting Memory Write, at          20524815000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          20528295000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          20530125000
 test master 1 - Starting Memory Read, at          20530485000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          20530635000
 test target 1 - Starting Config Write, at          20533545000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          20536515000
 test target 1 - Starting Memory Write, at          20536785000
 test target 1 - Starting Memory Write, at          20537055000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          20537685000
 test target 1 - Starting Memory Write, at          20537985000
 test target 1 - Starting Memory Write, at          20538285000
 test target 1 - Starting Memory Write, at          20538915000
 test target 1 - Starting Memory Write, at          20539215000
 test target 1 - Starting Memory Write, at          20539845000
 test target 1 - Starting Memory Write, at          20540625000
 test target 1 - Starting Memory Write, at          20540925000
 test target 1 - Starting Memory Write, at          20541705000
 test target 1 - Starting Memory Write, at          20542035000
 test target 1 - Starting Memory Write, at          20542785000
 test target 1 - Starting Memory Write, at          20550765000
 test target 1 - Starting Memory Write, at          20551065000
 test target 1 - Starting Memory Write, at          20551365000
 test target 1 - Starting Memory Write, at          20551695000
 test target 1 - Starting Memory Write, at          20552025000
 test target 1 - Starting Memory Read, at          20554065000
 test target 1 - Starting Memory Read, at          20555205000
 test target 1 - Starting Memory Read, at          20556435000
 test target 1 - Starting Memory Read, at          20557695000
 test target 1 - Starting Memory Read, at          20558925000
 test target 1 - Starting Memory Read, at          20560155000
 test target 1 - Starting Memory Read, at          20561415000
 test target 1 - Starting Memory Read, at          20562645000
 test target 1 - Starting Memory Read, at          20563875000
 test target 1 - Starting Memory Read, at          20565135000
 test target 1 - Starting Memory Read, at          20566365000
 test target 1 - Starting Memory Read, at          20567595000
 test target 1 - Starting Memory Read, at          20568855000
 test target 1 - Starting Memory Read, at          20570085000
 test target 1 - Starting Memory Read, at          20571315000
 test target 1 - Starting Memory Read, at          20572575000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          20573595000
 test target 1 - Starting Memory Read, at          20573865000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          20576475000
 test target 1 - Starting Memory Read, at          20577255000
 test target 1 - Starting Memory Read, at          20578125000
 test target 1 - Starting Memory Read, at          20578965000
 test target 1 - Starting Memory Read, at          20579835000
 test target 1 - Starting Memory Read, at          20580765000
 test target 1 - Starting Memory Read, at          20582055000
 test target 1 - Starting Memory Read, at          20583285000
 test target 1 - Starting Memory Read, at          20584455000
 test target 1 - Starting Memory Read, at          20587275000
 test target 1 - Starting Memory Read, at          20589045000
 test target 1 - Starting Memory Read, at          20590035000
 test target 1 - Starting Memory Read, at          20590995000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          20592585000
 test master 1 - Starting Memory Write, at          20592855000
 test target 1 - Starting Memory Write, at          20592855000
 test target 1 - Starting Memory Write, at          20593125000
 test target 1 - Starting Memory Read, at          20593545000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          20595315000
 test master 1 - Starting Memory Write, at          20595585000
 test target 1 - Starting Memory Write, at          20595585000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20601645000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          20601885000
 test master 2 - Starting Memory Read, at          20602065000
 test master 2 - Starting Memory Read, at          20602275000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20603865000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          20604135000
 test master 2 - Starting Memory Read, at          20604315000
 test master 2 - Starting Memory Read, at          20604525000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20606055000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20606385000
 test master 2 - Starting Memory Read Line Multiple, at          20606565000
 test master 2 - Starting Memory Read Line Multiple, at          20606835000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20608515000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20611815000
 test master 2 - Starting Memory Read Line Multiple, at          20611995000
 test master 2 - Starting Memory Read Line Multiple, at          20612265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20612625000
 test master 2 - Starting Memory Read Line Multiple, at          20612805000
 test master 2 - Starting Memory Read Line Multiple, at          20613105000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20613465000
 test master 2 - Starting Memory Read Line Multiple, at          20613645000
 test master 2 - Starting Memory Read Line Multiple, at          20613945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20614305000
 test master 2 - Starting Memory Read Line Multiple, at          20614485000
 test master 2 - Starting Memory Read Line Multiple, at          20614785000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20615145000
 test master 2 - Starting Memory Read Line Multiple, at          20615325000
 test master 2 - Starting Memory Read Line Multiple, at          20615625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20615985000
 test master 2 - Starting Memory Read Line Multiple, at          20616165000
 test master 2 - Starting Memory Read Line Multiple, at          20616465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20616825000
 test master 2 - Starting Memory Read Line Multiple, at          20617005000
 test master 2 - Starting Memory Read Line Multiple, at          20617305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20617665000
 test master 2 - Starting Memory Read Line Multiple, at          20617845000
 test master 2 - Starting Memory Read Line Multiple, at          20618145000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          20618505000
 test master 2 - Starting Memory Read Line, at          20618685000
 test master 2 - Starting Memory Read Line, at          20618925000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          20619195000
 test master 2 - Starting Memory Read Line, at          20619375000
 test master 2 - Starting Memory Read Line, at          20619585000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20620815000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20622525000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20625705000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20627505000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          20632305000
 test master 2 - Starting Memory Write, at          20632545000
 test master 2 - Starting Memory Write, at          20632785000
 test master 2 - Starting Memory Write, at          20633025000
 test master 2 - Starting Memory Write, at          20633265000
 test master 1 - Starting Memory Read, at          20633625000
 test master 1 - Starting Memory Read, at          20633925000
 test master 1 - Starting Memory Read, at          20634465000
 test master 1 - Starting Memory Read, at          20634765000
 test master 1 - Starting Memory Read, at          20635305000
 test master 1 - Starting Memory Read, at          20635605000
 test master 2 - Starting Memory Write, at          20636985000
 test master 2 - Starting Memory Write, at          20637225000
 test master 2 - Starting Memory Write, at          20637465000
 test master 2 - Starting Memory Write, at          20637705000
 test master 2 - Starting Memory Write, at          20637945000
 test master 1 - Starting Memory Read, at          20638305000
 test master 1 - Starting Memory Read, at          20638605000
 test master 1 - Starting Memory Read, at          20639145000
 test master 1 - Starting Memory Read, at          20639445000
 test master 1 - Starting Memory Read, at          20639985000
 test master 1 - Starting Memory Read, at          20640285000
 test master 2 - Starting Memory Write, at          20642265000
 test master 2 - Starting Memory Write, at          20643465000
 test master 2 - Starting Memory Write, at          20644665000
 test master 2 - Starting Memory Write, at          20645865000
 test master 2 - Starting Memory Write, at          20648385000
 test master 2 - Starting Memory Write, at          20649585000
 test master 2 - Starting Memory Write, at          20650785000
 test master 2 - Starting Memory Write, at          20651985000
 test master 2 - Starting Memory Write, at          20654505000
 test master 2 - Starting Memory Write, at          20656815000
 test master 2 - Starting Memory Write, at          20659095000
 test master 2 - Starting Memory Write, at          20661375000
 test master 2 - Starting Memory Write, at          20664975000
 test master 2 - Starting Memory Write, at          20667555000
 test master 2 - Starting Memory Write, at          20670135000
 test master 2 - Starting Memory Write, at          20672715000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          20677425000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20677455000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20679945000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          20680185000
 test master 2 - Starting Memory Read, at          20680365000
 test master 2 - Starting Memory Read, at          20680575000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20682165000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          20682435000
 test master 2 - Starting Memory Read, at          20682615000
 test master 2 - Starting Memory Read, at          20682825000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20684355000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20684685000
 test master 2 - Starting Memory Read Line Multiple, at          20684865000
 test master 2 - Starting Memory Read Line Multiple, at          20685135000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20686815000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20690115000
 test master 2 - Starting Memory Read Line Multiple, at          20690295000
 test master 2 - Starting Memory Read Line Multiple, at          20690565000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20690925000
 test master 2 - Starting Memory Read Line Multiple, at          20691105000
 test master 2 - Starting Memory Read Line Multiple, at          20691405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20691765000
 test master 2 - Starting Memory Read Line Multiple, at          20691945000
 test master 2 - Starting Memory Read Line Multiple, at          20692245000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20692605000
 test master 2 - Starting Memory Read Line Multiple, at          20692785000
 test master 2 - Starting Memory Read Line Multiple, at          20693085000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20693445000
 test master 2 - Starting Memory Read Line Multiple, at          20693625000
 test master 2 - Starting Memory Read Line Multiple, at          20693925000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20694285000
 test master 2 - Starting Memory Read Line Multiple, at          20694465000
 test master 2 - Starting Memory Read Line Multiple, at          20694765000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20695125000
 test master 2 - Starting Memory Read Line Multiple, at          20695305000
 test master 2 - Starting Memory Read Line Multiple, at          20695605000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20695965000
 test master 2 - Starting Memory Read Line Multiple, at          20696145000
 test master 2 - Starting Memory Read Line Multiple, at          20696445000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          20696805000
 test master 2 - Starting Memory Read Line, at          20696985000
 test master 2 - Starting Memory Read Line, at          20697225000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          20697495000
 test master 2 - Starting Memory Read Line, at          20697675000
 test master 2 - Starting Memory Read Line, at          20697885000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20699115000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20700825000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20704005000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20705805000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          20710605000
 test master 2 - Starting Memory Write, at          20710845000
 test master 2 - Starting Memory Write, at          20711085000
 test master 2 - Starting Memory Write, at          20711325000
 test master 2 - Starting Memory Write, at          20711565000
 test master 1 - Starting Memory Read, at          20711925000
 test master 1 - Starting Memory Read, at          20712225000
 test master 1 - Starting Memory Read, at          20712765000
 test master 1 - Starting Memory Read, at          20713065000
 test master 1 - Starting Memory Read, at          20713605000
 test master 1 - Starting Memory Read, at          20713905000
 test master 2 - Starting Memory Write, at          20715285000
 test master 2 - Starting Memory Write, at          20715525000
 test master 2 - Starting Memory Write, at          20715765000
 test master 2 - Starting Memory Write, at          20716005000
 test master 2 - Starting Memory Write, at          20716245000
 test master 1 - Starting Memory Read, at          20716605000
 test master 1 - Starting Memory Read, at          20716905000
 test master 1 - Starting Memory Read, at          20717445000
 test master 1 - Starting Memory Read, at          20717745000
 test master 1 - Starting Memory Read, at          20718285000
 test master 1 - Starting Memory Read, at          20718585000
 test master 2 - Starting Memory Write, at          20720565000
 test master 2 - Starting Memory Write, at          20721765000
 test master 2 - Starting Memory Write, at          20722965000
 test master 2 - Starting Memory Write, at          20724165000
 test master 2 - Starting Memory Write, at          20726685000
 test master 2 - Starting Memory Write, at          20727885000
 test master 2 - Starting Memory Write, at          20729085000
 test master 2 - Starting Memory Write, at          20730285000
 test master 2 - Starting Memory Write, at          20732805000
 test master 2 - Starting Memory Write, at          20735115000
 test master 2 - Starting Memory Write, at          20737395000
 test master 2 - Starting Memory Write, at          20739675000
 test master 2 - Starting Memory Write, at          20743275000
 test master 2 - Starting Memory Write, at          20745855000
 test master 2 - Starting Memory Write, at          20748435000
 test master 2 - Starting Memory Write, at          20751015000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          20755725000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20755755000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20758245000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          20758485000
 test master 2 - Starting Memory Read, at          20758665000
 test master 2 - Starting Memory Read, at          20758875000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20760465000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          20760735000
 test master 2 - Starting Memory Read, at          20760915000
 test master 2 - Starting Memory Read, at          20761125000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20762655000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20762985000
 test master 2 - Starting Memory Read Line Multiple, at          20763165000
 test master 2 - Starting Memory Read Line Multiple, at          20763435000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20765115000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20768415000
 test master 2 - Starting Memory Read Line Multiple, at          20768595000
 test master 2 - Starting Memory Read Line Multiple, at          20768865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20769225000
 test master 2 - Starting Memory Read Line Multiple, at          20769405000
 test master 2 - Starting Memory Read Line Multiple, at          20769705000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20770065000
 test master 2 - Starting Memory Read Line Multiple, at          20770245000
 test master 2 - Starting Memory Read Line Multiple, at          20770545000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20770905000
 test master 2 - Starting Memory Read Line Multiple, at          20771085000
 test master 2 - Starting Memory Read Line Multiple, at          20771385000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20771745000
 test master 2 - Starting Memory Read Line Multiple, at          20771925000
 test master 2 - Starting Memory Read Line Multiple, at          20772225000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20772585000
 test master 2 - Starting Memory Read Line Multiple, at          20772765000
 test master 2 - Starting Memory Read Line Multiple, at          20773065000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20773425000
 test master 2 - Starting Memory Read Line Multiple, at          20773605000
 test master 2 - Starting Memory Read Line Multiple, at          20773905000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20774265000
 test master 2 - Starting Memory Read Line Multiple, at          20774445000
 test master 2 - Starting Memory Read Line Multiple, at          20774745000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          20775105000
 test master 2 - Starting Memory Read Line, at          20775285000
 test master 2 - Starting Memory Read Line, at          20775525000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          20775795000
 test master 2 - Starting Memory Read Line, at          20775975000
 test master 2 - Starting Memory Read Line, at          20776185000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20777415000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20779125000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20782305000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20784105000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          20788905000
 test master 2 - Starting Memory Write, at          20789145000
 test master 2 - Starting Memory Write, at          20789385000
 test master 2 - Starting Memory Write, at          20789625000
 test master 2 - Starting Memory Write, at          20789865000
 test master 1 - Starting Memory Read, at          20790225000
 test master 1 - Starting Memory Read, at          20790525000
 test master 1 - Starting Memory Read, at          20791065000
 test master 1 - Starting Memory Read, at          20791365000
 test master 1 - Starting Memory Read, at          20791905000
 test master 1 - Starting Memory Read, at          20792205000
 test master 2 - Starting Memory Write, at          20793585000
 test master 2 - Starting Memory Write, at          20793825000
 test master 2 - Starting Memory Write, at          20794065000
 test master 2 - Starting Memory Write, at          20794305000
 test master 2 - Starting Memory Write, at          20794545000
 test master 1 - Starting Memory Read, at          20794905000
 test master 1 - Starting Memory Read, at          20795205000
 test master 1 - Starting Memory Read, at          20795745000
 test master 1 - Starting Memory Read, at          20796045000
 test master 1 - Starting Memory Read, at          20796585000
 test master 1 - Starting Memory Read, at          20796885000
 test master 2 - Starting Memory Write, at          20798865000
 test master 2 - Starting Memory Write, at          20800065000
 test master 2 - Starting Memory Write, at          20801265000
 test master 2 - Starting Memory Write, at          20802465000
 test master 2 - Starting Memory Write, at          20804985000
 test master 2 - Starting Memory Write, at          20806185000
 test master 2 - Starting Memory Write, at          20807385000
 test master 2 - Starting Memory Write, at          20808585000
 test master 2 - Starting Memory Write, at          20811105000
 test master 2 - Starting Memory Write, at          20813415000
 test master 2 - Starting Memory Write, at          20815695000
 test master 2 - Starting Memory Write, at          20817975000
 test master 2 - Starting Memory Write, at          20821575000
 test master 2 - Starting Memory Write, at          20824155000
 test master 2 - Starting Memory Write, at          20826735000
 test master 2 - Starting Memory Write, at          20829315000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          20834025000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20834055000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20836545000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          20836785000
 test master 2 - Starting Memory Read, at          20836965000
 test master 2 - Starting Memory Read, at          20837175000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20838765000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          20839035000
 test master 2 - Starting Memory Read, at          20839215000
 test master 2 - Starting Memory Read, at          20839425000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20840955000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20841285000
 test master 2 - Starting Memory Read Line Multiple, at          20841465000
 test master 2 - Starting Memory Read Line Multiple, at          20841735000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20843415000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20846715000
 test master 2 - Starting Memory Read Line Multiple, at          20846895000
 test master 2 - Starting Memory Read Line Multiple, at          20847165000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20847525000
 test master 2 - Starting Memory Read Line Multiple, at          20847705000
 test master 2 - Starting Memory Read Line Multiple, at          20848005000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20848365000
 test master 2 - Starting Memory Read Line Multiple, at          20848545000
 test master 2 - Starting Memory Read Line Multiple, at          20848845000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20849205000
 test master 2 - Starting Memory Read Line Multiple, at          20849385000
 test master 2 - Starting Memory Read Line Multiple, at          20849685000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20850045000
 test master 2 - Starting Memory Read Line Multiple, at          20850225000
 test master 2 - Starting Memory Read Line Multiple, at          20850525000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20850885000
 test master 2 - Starting Memory Read Line Multiple, at          20851065000
 test master 2 - Starting Memory Read Line Multiple, at          20851365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20851725000
 test master 2 - Starting Memory Read Line Multiple, at          20851905000
 test master 2 - Starting Memory Read Line Multiple, at          20852205000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          20852565000
 test master 2 - Starting Memory Read Line Multiple, at          20852745000
 test master 2 - Starting Memory Read Line Multiple, at          20853045000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          20853405000
 test master 2 - Starting Memory Read Line, at          20853585000
 test master 2 - Starting Memory Read Line, at          20853825000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          20854095000
 test master 2 - Starting Memory Read Line, at          20854275000
 test master 2 - Starting Memory Read Line, at          20854485000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20855715000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20857425000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20860605000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          20862405000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          20867205000
 test master 2 - Starting Memory Write, at          20867445000
 test master 2 - Starting Memory Write, at          20867685000
 test master 2 - Starting Memory Write, at          20867925000
 test master 2 - Starting Memory Write, at          20868165000
 test master 1 - Starting Memory Read, at          20868525000
 test master 1 - Starting Memory Read, at          20868825000
 test master 1 - Starting Memory Read, at          20869365000
 test master 1 - Starting Memory Read, at          20869665000
 test master 1 - Starting Memory Read, at          20870205000
 test master 1 - Starting Memory Read, at          20870505000
 test master 2 - Starting Memory Write, at          20871885000
 test master 2 - Starting Memory Write, at          20872125000
 test master 2 - Starting Memory Write, at          20872365000
 test master 2 - Starting Memory Write, at          20872605000
 test master 2 - Starting Memory Write, at          20872845000
 test master 1 - Starting Memory Read, at          20873205000
 test master 1 - Starting Memory Read, at          20873505000
 test master 1 - Starting Memory Read, at          20874045000
 test master 1 - Starting Memory Read, at          20874345000
 test master 1 - Starting Memory Read, at          20874885000
 test master 1 - Starting Memory Read, at          20875185000
 test master 2 - Starting Memory Write, at          20877165000
 test master 2 - Starting Memory Write, at          20878365000
 test master 2 - Starting Memory Write, at          20879565000
 test master 2 - Starting Memory Write, at          20880765000
 test master 2 - Starting Memory Write, at          20883285000
 test master 2 - Starting Memory Write, at          20884485000
 test master 2 - Starting Memory Write, at          20885685000
 test master 2 - Starting Memory Write, at          20886885000
 test master 2 - Starting Memory Write, at          20889405000
 test master 2 - Starting Memory Write, at          20891715000
 test master 2 - Starting Memory Write, at          20893995000
 test master 2 - Starting Memory Write, at          20896275000
 test master 2 - Starting Memory Write, at          20899875000
 test master 2 - Starting Memory Write, at          20902455000
 test master 2 - Starting Memory Write, at          20905035000
 test master 2 - Starting Memory Write, at          20907615000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          20912325000
*** monitor - CBE Bus Changed when TRDY Desserted, at          20912355000
 test master 1 - Starting Memory Read, at          20914845000
 test master 1 - Starting Memory Read, at          20915175000
 test master 1 - Starting Memory Read, at          20916525000
 test master 1 - Starting Memory Read, at          20916855000
 test master 1 - Starting Memory Read Line, at          20918265000
 test master 1 - Starting Memory Read Line, at          20918595000
 test master 1 - Starting Memory Read Line, at          20920005000
 test master 1 - Starting Memory Read Line, at          20920365000
 test master 1 - Starting Memory Read Line, at          20921805000
 test master 1 - Starting Memory Read Line, at          20922195000
 test master 1 - Starting Memory Read Line, at          20923665000
 test master 1 - Starting Memory Read Line, at          20924055000
 test master 1 - Starting Memory Read Line Multiple, at          20925525000
 test master 1 - Starting Memory Read Line Multiple, at          20925975000
 test master 1 - Starting Memory Read Line Multiple, at          20927505000
 test master 1 - Starting Memory Read Line Multiple, at          20927955000
 test master 1 - Starting Memory Read Line, at          20929545000
 test master 1 - Starting Memory Read Line, at          20929935000
 test master 1 - Starting Memory Read, at          20932695000
 test master 1 - Starting Memory Read, at          20933025000
 test target 1 - Starting Config Write, at          20936805000
 test master 1 - Starting Memory Write, at          20937525000
 test master 1 - Starting Memory Write, at          20939475000
 test master 1 - Starting Memory Write, at          20940795000
 test master 1 - Starting Memory Write, at          20942625000
 test master 1 - Starting Memory Write, at          20943975000
 test master 1 - Starting Memory Read Line, at          20945925000
 test master 1 - Starting Memory Write, at          20947425000
 test master 1 - Starting Memory Read Line, at          20949375000
 test target 1 - Starting Config Write, at          20953065000
 test master 1 - Starting Memory Write, at          20953785000
 test master 1 - Starting Memory Write, at          20953905000
 test master 1 - Starting Memory Write, at          20954145000
 test master 1 - Starting Memory Read, at          20954265000
 test master 1 - Starting Memory Write, at          20954595000
 test master 1 - Starting Memory Read, at          20954715000
 test master 1 - Starting Memory Write, at          20956665000
 test master 1 - Starting Memory Write, at          20959935000
 test master 2 - Starting Memory Read Line, at          20963355000
 test master 2 - Starting Memory Read Line, at          20963715000
 test master 2 - Starting Memory Read Line, at          20964015000
 test master 2 - Starting Memory Read Line, at          20964375000
 test master 1 - Starting Memory Write, at          20964765000
 test master 1 - Starting Memory Write, at          20965005000
 test master 1 - Starting Memory Write, at          20965245000
 test master 2 - Starting Memory Read Line, at          20965605000
 test master 2 - Starting Memory Read Line, at          20965935000
 test master 2 - Starting Memory Read Line, at          20966145000
 test master 2 - Starting Memory Read Line, at          20966475000
 test master 2 - Starting Memory Read Line Multiple, at          20966715000
 test master 2 - Starting Memory Read Line Multiple, at          20967045000
 test master 1 - Starting Memory Write, at          20969205000
 test master 1 - Starting Memory Write, at          20969445000
 test master 2 - Starting Memory Read, at          20969805000
 test master 2 - Starting Memory Read, at          20970135000
 test master 2 - Starting Memory Read, at          20970345000
 test master 2 - Starting Memory Read, at          20970675000
 test master 1 - Starting Memory Write, at          20972535000
 test master 1 - Starting Memory Read, at          20972715000
 test master 1 - Starting Memory Write, at          20972895000
 test master 1 - Starting Memory Read, at          20973105000
 test master 1 - Starting Memory Write, at          20973315000
 test master 1 - Starting Memory Read, at          20973495000
 test master 1 - Starting Memory Read, at          20973705000
 test master 1 - Starting Memory Write, at          20973915000
 test master 1 - Starting Memory Write, at          20974095000
 test master 1 - Starting Memory Read, at          20974275000
 test master 1 - Starting Memory Write, at          20974455000
 test master 1 - Starting Memory Write, at          20974665000
 test master 1 - Starting Memory Write, at          20974875000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          20980095000
 test target 1 - Starting Memory Write, at          20980365000
 test master 1 - Starting Memory Write, at          20980605000
 test target 1 - Starting Memory Write, at          20980785000
 test target 1 - Starting Memory Write, at          20981055000
 test target 1 - Starting Memory Write, at          20981325000
 test master 1 - Starting Memory Write, at          20981685000
 test target 1 - Starting Memory Write, at          20982195000
 test target 1 - Starting Memory Write, at          20982795000
 test target 1 - Starting Memory Write, at          20983095000
 test master 1 - Starting Memory Write, at          20983365000
 test target 1 - Starting Memory Write, at          20983605000
 test target 1 - Starting Memory Write, at          20983905000
 test target 1 - Starting Memory Write, at          20984205000
 test master 1 - Starting Memory Write, at          20984625000
 test target 1 - Starting Memory Write, at          20985345000
 test target 1 - Starting Memory Write, at          20985975000
 test target 1 - Starting Memory Write, at          20986245000
 test master 1 - Starting Memory Read, at          20986485000
 test target 1 - Starting Memory Write, at          20986665000
 test master 1 - Starting Memory Read, at          20986905000
 test target 1 - Starting Memory Write, at          20987085000
 test master 1 - Starting Memory Read, at          20987325000
 test target 1 - Starting Memory Write, at          20987505000
 test master 1 - Starting Memory Read, at          20987745000
 test target 1 - Starting Memory Write, at          20987925000
 test master 1 - Starting Memory Read, at          20988165000
 test target 1 - Starting Memory Write, at          20988345000
 test master 1 - Starting Memory Write, at          20988585000
 test target 1 - Starting Memory Write, at          20988765000
 test target 1 - Starting Memory Write, at          20989035000
 test target 1 - Starting Memory Write, at          20989305000
 test target 1 - Starting Memory Read, at          20989635000
 test master 1 - Starting Memory Write, at          20989995000
 test master 1 - Starting Memory Read, at          20990235000
 test target 1 - Starting Memory Write, at          20990745000
 test master 1 - Starting Memory Write, at          20991195000
 test target 1 - Starting Memory Read, at          20991645000
 test target 1 - Starting Memory Write, at          20992515000
 test master 1 - Starting Memory Read, at          20992875000
 test master 1 - Starting Memory Write, at          20993205000
 test master 1 - Starting Memory Write, at          20993565000
 test master 1 - Starting Memory Read, at          20993805000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          20996235000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          20997285000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          21021735000
 test target 1 - Starting Config Write, at          21022635000
 test target 1 - Starting Config Write, at          21023535000
 test target 2 - Starting Config Write, at          21024435000
 test target 2 - Starting Config Write, at          21025335000
 test target 2 - Starting Config Write, at          21026235000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          21028125000
 test target 1 - Starting Memory Read, at          21028335000
 test target 1 - Starting Memory Write, at          21028935000
 test target 1 - Starting Memory Read, at          21029145000
 test target 1 - Starting Memory Write, at          21029955000
 test target 1 - Starting Memory Read, at          21031335000
 test target 1 - Starting Memory Read, at          21031875000
 test target 1 - Starting Memory Read, at          21032445000
 test target 1 - Starting Memory Read, at          21033045000
 test target 1 - Starting Memory Read, at          21033855000
 test target 1 - Starting Memory Read, at          21034935000
 test target 1 - Starting Memory Read, at          21035835000
 test target 1 - Starting Memory Read, at          21037005000
 test target 1 - Starting Memory Read, at          21037875000
 test target 1 - Starting Memory Read, at          21040695000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          21046905000
 test target 1 - Starting Memory Read, at          21047115000
 test target 1 - Starting Memory Write, at          21047715000
 test target 1 - Starting Memory Read, at          21047925000
 test target 1 - Starting Memory Write, at          21048735000
 test target 1 - Starting Memory Read, at          21050115000
 test target 1 - Starting Memory Read, at          21050655000
 test target 1 - Starting Memory Read, at          21051225000
 test target 1 - Starting Memory Read, at          21051825000
 test target 1 - Starting Memory Read, at          21052635000
 test target 1 - Starting Memory Read, at          21053715000
 test target 1 - Starting Memory Read, at          21054615000
 test target 1 - Starting Memory Read, at          21055785000
 test target 1 - Starting Memory Read, at          21056655000
 test target 1 - Starting Memory Read, at          21059475000
 test target 1 - Starting Memory Write, at          21065685000
 test target 1 - Starting Memory Read, at          21065895000
 test target 1 - Starting Memory Write, at          21066495000
 test target 1 - Starting Memory Read, at          21066705000
 test target 1 - Starting Memory Write, at          21067515000
 test target 1 - Starting Memory Read, at          21068895000
 test target 1 - Starting Memory Read, at          21069435000
 test target 1 - Starting Memory Read, at          21070005000
 test target 1 - Starting Memory Read, at          21070605000
 test target 1 - Starting Memory Read, at          21071415000
 test target 1 - Starting Memory Read, at          21072495000
 test target 1 - Starting Memory Read, at          21073395000
 test target 1 - Starting Memory Read, at          21074565000
 test target 1 - Starting Memory Read, at          21075435000
 test target 1 - Starting Memory Read, at          21078255000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          21089985000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          21096165000
 test target 1 - Starting Memory Write, at          21096975000
 test target 1 - Starting Memory Read, at          21097485000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          21098865000
 test target 1 - Starting Config Write, at          21100725000
 test target 1 - Starting Memory Read, at          21101415000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          21102855000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          21104985000
 test target 1 - Starting Memory Write, at          21106155000
 test target 1 - Starting Memory Write, at          21106395000
 test target 1 - Starting Memory Read, at          21106605000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          21108795000
 test target 1 - Starting Memory Write, at          21111705000
 test target 1 - Starting Memory Write, at          21112095000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          21116115000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          21118035000
 test target 1 - Starting Memory Read, at          21119415000
 test target 1 - Starting Memory Read, at          21120585000
 test target 1 - Starting Memory Read, at          21122295000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          21128175000
 test target 2 - Starting Config Write, at          21129075000
 test target 1 - Starting Memory Write, at          21129765000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          21129885000
 test target 1 - Starting Memory Write, at          21130905000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          21131025000
 test target 1 - Starting Memory Write, at          21132045000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          21133395000
 test target 1 - Starting Memory Read, at          21135555000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          21135675000
 test target 1 - Starting Memory Read, at          21137775000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          21139425000
 test master 2 - Starting Memory Write, at          21139425000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          21139485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21140265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21140295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21140595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21140625000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21141495000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21141525000
 test target 1 - Starting Memory Write, at          21143295000
 test master 2 - Starting Memory Write, at          21143295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21144945000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21144975000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21146625000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21146655000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21148305000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21148335000
 test target 1 - Starting Memory Write, at          21150345000
 test master 2 - Starting Memory Write, at          21150345000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          21150405000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21151965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21151995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21152295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21152325000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21153195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21153225000
 test target 1 - Starting Memory Write, at          21154395000
 test master 2 - Starting Memory Write, at          21154395000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          21157215000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          21158805000
 test master 1 - Starting Memory Read, at          21159105000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          21159255000
 test target 1 - Starting Config Write, at          21161745000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          21164055000
 test target 1 - Starting Memory Write, at          21164205000
 test target 1 - Starting Memory Write, at          21164355000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          21164805000
 test target 1 - Starting Memory Write, at          21164985000
 test target 1 - Starting Memory Write, at          21165165000
 test target 1 - Starting Memory Write, at          21165615000
 test target 1 - Starting Memory Write, at          21165915000
 test target 1 - Starting Memory Write, at          21166365000
 test target 1 - Starting Memory Write, at          21166995000
 test target 1 - Starting Memory Write, at          21167175000
 test target 1 - Starting Memory Write, at          21167835000
 test target 1 - Starting Memory Write, at          21168165000
 test target 1 - Starting Memory Write, at          21168675000
 test target 1 - Starting Memory Write, at          21171825000
 test target 1 - Starting Memory Write, at          21172005000
 test target 1 - Starting Memory Write, at          21172185000
 test target 1 - Starting Memory Write, at          21172515000
 test target 1 - Starting Memory Write, at          21172845000
 test target 1 - Starting Memory Read, at          21181605000
 test target 1 - Starting Memory Read, at          21182745000
 test target 1 - Starting Memory Read, at          21183855000
 test target 1 - Starting Memory Read, at          21184965000
 test target 1 - Starting Memory Read, at          21186045000
 test target 1 - Starting Memory Read, at          21187155000
 test target 1 - Starting Memory Read, at          21188265000
 test target 1 - Starting Memory Read, at          21189345000
 test target 1 - Starting Memory Read, at          21190455000
 test target 1 - Starting Memory Read, at          21191565000
 test target 1 - Starting Memory Read, at          21192645000
 test target 1 - Starting Memory Read, at          21193755000
 test target 1 - Starting Memory Read, at          21194865000
 test target 1 - Starting Memory Read, at          21195945000
 test target 1 - Starting Memory Read, at          21197055000
 test target 1 - Starting Memory Read, at          21198165000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          21199215000
 test target 1 - Starting Memory Read, at          21199365000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          21200625000
 test target 1 - Starting Memory Read, at          21203085000
 test target 1 - Starting Memory Read, at          21203625000
 test target 1 - Starting Memory Read, at          21204285000
 test target 1 - Starting Memory Read, at          21205035000
 test target 1 - Starting Memory Read, at          21205755000
 test target 1 - Starting Memory Read, at          21207075000
 test target 1 - Starting Memory Read, at          21208155000
 test target 1 - Starting Memory Read, at          21209055000
 test target 1 - Starting Memory Read, at          21212325000
 test target 1 - Starting Memory Read, at          21215415000
 test target 1 - Starting Memory Read, at          21216195000
 test target 1 - Starting Memory Read, at          21216975000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          21217995000
 test master 1 - Starting Memory Write, at          21218415000
 test target 1 - Starting Memory Write, at          21218415000
 test target 1 - Starting Memory Write, at          21218565000
 test target 1 - Starting Memory Read, at          21219075000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          21221955000
 test master 1 - Starting Memory Write, at          21222375000
 test target 1 - Starting Memory Write, at          21222375000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          21227175000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          21228225000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          21252675000
 test target 1 - Starting Config Write, at          21253575000
 test target 1 - Starting Config Write, at          21254475000
 test target 2 - Starting Config Write, at          21255375000
 test target 2 - Starting Config Write, at          21256275000
 test target 2 - Starting Config Write, at          21257175000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          21259065000
 test target 1 - Starting Memory Read, at          21259305000
 test target 1 - Starting Memory Write, at          21260025000
 test target 1 - Starting Memory Read, at          21260265000
 test target 1 - Starting Memory Write, at          21261195000
 test target 1 - Starting Memory Read, at          21262575000
 test target 1 - Starting Memory Read, at          21263145000
 test target 1 - Starting Memory Read, at          21263715000
 test target 1 - Starting Memory Read, at          21264285000
 test target 1 - Starting Memory Read, at          21265095000
 test target 1 - Starting Memory Read, at          21266295000
 test target 1 - Starting Memory Read, at          21267135000
 test target 1 - Starting Memory Read, at          21268335000
 test target 1 - Starting Memory Read, at          21269175000
 test target 1 - Starting Memory Read, at          21271995000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          21278205000
 test target 1 - Starting Memory Read, at          21278445000
 test target 1 - Starting Memory Write, at          21279165000
 test target 1 - Starting Memory Read, at          21279405000
 test target 1 - Starting Memory Write, at          21280335000
 test target 1 - Starting Memory Read, at          21281715000
 test target 1 - Starting Memory Read, at          21282285000
 test target 1 - Starting Memory Read, at          21282855000
 test target 1 - Starting Memory Read, at          21283425000
 test target 1 - Starting Memory Read, at          21284235000
 test target 1 - Starting Memory Read, at          21285435000
 test target 1 - Starting Memory Read, at          21286275000
 test target 1 - Starting Memory Read, at          21287475000
 test target 1 - Starting Memory Read, at          21288315000
 test target 1 - Starting Memory Read, at          21291135000
 test target 1 - Starting Memory Write, at          21297345000
 test target 1 - Starting Memory Read, at          21297585000
 test target 1 - Starting Memory Write, at          21298305000
 test target 1 - Starting Memory Read, at          21298545000
 test target 1 - Starting Memory Write, at          21299475000
 test target 1 - Starting Memory Read, at          21300855000
 test target 1 - Starting Memory Read, at          21301425000
 test target 1 - Starting Memory Read, at          21301995000
 test target 1 - Starting Memory Read, at          21302565000
 test target 1 - Starting Memory Read, at          21303375000
 test target 1 - Starting Memory Read, at          21304575000
 test target 1 - Starting Memory Read, at          21305415000
 test target 1 - Starting Memory Read, at          21306615000
 test target 1 - Starting Memory Read, at          21307455000
 test target 1 - Starting Memory Read, at          21310275000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          21322005000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          21328185000
 test target 1 - Starting Memory Write, at          21328995000
 test target 1 - Starting Memory Read, at          21329535000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          21330885000
 test target 1 - Starting Config Write, at          21332745000
 test target 1 - Starting Memory Read, at          21333435000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          21334875000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          21337005000
 test target 1 - Starting Memory Write, at          21338175000
 test target 1 - Starting Memory Write, at          21338445000
 test target 1 - Starting Memory Read, at          21338685000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          21340935000
 test target 1 - Starting Memory Write, at          21343875000
 test target 1 - Starting Memory Write, at          21344295000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          21348315000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          21350235000
 test target 1 - Starting Memory Read, at          21351615000
 test target 1 - Starting Memory Read, at          21352785000
 test target 1 - Starting Memory Read, at          21354495000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          21360495000
 test target 2 - Starting Config Write, at          21361395000
 test target 1 - Starting Memory Write, at          21362085000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          21362235000
 test target 1 - Starting Memory Write, at          21363255000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          21363405000
 test target 1 - Starting Memory Write, at          21364425000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          21365835000
 test target 1 - Starting Memory Read, at          21367995000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          21368145000
 test target 1 - Starting Memory Read, at          21370215000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          21371865000
 test master 2 - Starting Memory Write, at          21371865000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          21371925000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21372735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21372765000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21373065000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21373095000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21373965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21373995000
 test target 1 - Starting Memory Write, at          21375765000
 test master 2 - Starting Memory Write, at          21375765000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21377445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21377475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21379125000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21379155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21380805000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21380835000
 test target 1 - Starting Memory Write, at          21382845000
 test master 2 - Starting Memory Write, at          21382845000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          21382905000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21384495000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21384525000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21384825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21384855000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21385725000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21385755000
 test target 1 - Starting Memory Write, at          21386925000
 test master 2 - Starting Memory Write, at          21386925000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          21389775000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          21391365000
 test master 1 - Starting Memory Read, at          21391665000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          21391815000
 test target 1 - Starting Config Write, at          21394305000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          21396615000
 test target 1 - Starting Memory Write, at          21396795000
 test target 1 - Starting Memory Write, at          21396975000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          21397455000
 test target 1 - Starting Memory Write, at          21397665000
 test target 1 - Starting Memory Write, at          21397875000
 test target 1 - Starting Memory Write, at          21398355000
 test target 1 - Starting Memory Write, at          21398685000
 test target 1 - Starting Memory Write, at          21399165000
 test target 1 - Starting Memory Write, at          21399855000
 test target 1 - Starting Memory Write, at          21400065000
 test target 1 - Starting Memory Write, at          21400755000
 test target 1 - Starting Memory Write, at          21401115000
 test target 1 - Starting Memory Write, at          21401655000
 test target 1 - Starting Memory Write, at          21404835000
 test target 1 - Starting Memory Write, at          21405045000
 test target 1 - Starting Memory Write, at          21405255000
 test target 1 - Starting Memory Write, at          21405615000
 test target 1 - Starting Memory Write, at          21405975000
 test target 1 - Starting Memory Read, at          21414765000
 test target 1 - Starting Memory Read, at          21415875000
 test target 1 - Starting Memory Read, at          21417075000
 test target 1 - Starting Memory Read, at          21418275000
 test target 1 - Starting Memory Read, at          21419475000
 test target 1 - Starting Memory Read, at          21420675000
 test target 1 - Starting Memory Read, at          21421875000
 test target 1 - Starting Memory Read, at          21423075000
 test target 1 - Starting Memory Read, at          21424275000
 test target 1 - Starting Memory Read, at          21425475000
 test target 1 - Starting Memory Read, at          21426675000
 test target 1 - Starting Memory Read, at          21427875000
 test target 1 - Starting Memory Read, at          21429075000
 test target 1 - Starting Memory Read, at          21430275000
 test target 1 - Starting Memory Read, at          21431475000
 test target 1 - Starting Memory Read, at          21432675000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          21433845000
 test target 1 - Starting Memory Read, at          21434025000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          21435255000
 test target 1 - Starting Memory Read, at          21437745000
 test target 1 - Starting Memory Read, at          21438405000
 test target 1 - Starting Memory Read, at          21439065000
 test target 1 - Starting Memory Read, at          21439815000
 test target 1 - Starting Memory Read, at          21440535000
 test target 1 - Starting Memory Read, at          21441855000
 test target 1 - Starting Memory Read, at          21443055000
 test target 1 - Starting Memory Read, at          21443895000
 test target 1 - Starting Memory Read, at          21447165000
 test target 1 - Starting Memory Read, at          21450315000
 test target 1 - Starting Memory Read, at          21451095000
 test target 1 - Starting Memory Read, at          21451875000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          21452895000
 test master 1 - Starting Memory Write, at          21453345000
 test target 1 - Starting Memory Write, at          21453345000
 test target 1 - Starting Memory Write, at          21453525000
 test target 1 - Starting Memory Read, at          21454065000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          21457005000
 test master 1 - Starting Memory Write, at          21457455000
 test target 1 - Starting Memory Write, at          21457455000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          21462315000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          21463365000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          21487815000
 test target 1 - Starting Config Write, at          21488715000
 test target 1 - Starting Config Write, at          21489615000
 test target 2 - Starting Config Write, at          21490515000
 test target 2 - Starting Config Write, at          21491415000
 test target 2 - Starting Config Write, at          21492315000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          21494205000
 test target 1 - Starting Memory Read, at          21494475000
 test target 1 - Starting Memory Write, at          21495165000
 test target 1 - Starting Memory Read, at          21495435000
 test target 1 - Starting Memory Write, at          21496335000
 test target 1 - Starting Memory Read, at          21497775000
 test target 1 - Starting Memory Read, at          21498405000
 test target 1 - Starting Memory Read, at          21499005000
 test target 1 - Starting Memory Read, at          21499575000
 test target 1 - Starting Memory Read, at          21500415000
 test target 1 - Starting Memory Read, at          21501585000
 test target 1 - Starting Memory Read, at          21502455000
 test target 1 - Starting Memory Read, at          21503655000
 test target 1 - Starting Memory Read, at          21504495000
 test target 1 - Starting Memory Read, at          21507405000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          21513585000
 test target 1 - Starting Memory Read, at          21513855000
 test target 1 - Starting Memory Write, at          21514545000
 test target 1 - Starting Memory Read, at          21514815000
 test target 1 - Starting Memory Write, at          21515715000
 test target 1 - Starting Memory Read, at          21517155000
 test target 1 - Starting Memory Read, at          21517785000
 test target 1 - Starting Memory Read, at          21518385000
 test target 1 - Starting Memory Read, at          21518955000
 test target 1 - Starting Memory Read, at          21519795000
 test target 1 - Starting Memory Read, at          21520965000
 test target 1 - Starting Memory Read, at          21521835000
 test target 1 - Starting Memory Read, at          21523035000
 test target 1 - Starting Memory Read, at          21523875000
 test target 1 - Starting Memory Read, at          21526785000
 test target 1 - Starting Memory Write, at          21532965000
 test target 1 - Starting Memory Read, at          21533235000
 test target 1 - Starting Memory Write, at          21533925000
 test target 1 - Starting Memory Read, at          21534195000
 test target 1 - Starting Memory Write, at          21535095000
 test target 1 - Starting Memory Read, at          21536535000
 test target 1 - Starting Memory Read, at          21537165000
 test target 1 - Starting Memory Read, at          21537765000
 test target 1 - Starting Memory Read, at          21538335000
 test target 1 - Starting Memory Read, at          21539175000
 test target 1 - Starting Memory Read, at          21540345000
 test target 1 - Starting Memory Read, at          21541215000
 test target 1 - Starting Memory Read, at          21542415000
 test target 1 - Starting Memory Read, at          21543255000
 test target 1 - Starting Memory Read, at          21546165000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          21557865000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          21564045000
 test target 1 - Starting Memory Write, at          21564855000
 test target 1 - Starting Memory Read, at          21565425000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          21566835000
 test target 1 - Starting Config Write, at          21568695000
 test target 1 - Starting Memory Read, at          21569355000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          21570795000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          21572925000
 test target 1 - Starting Memory Write, at          21574095000
 test target 1 - Starting Memory Write, at          21574395000
 test target 1 - Starting Memory Read, at          21574665000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          21576855000
 test target 1 - Starting Memory Write, at          21579825000
 test target 1 - Starting Memory Write, at          21580275000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          21584355000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          21586275000
 test target 1 - Starting Memory Read, at          21587655000
 test target 1 - Starting Memory Read, at          21588825000
 test target 1 - Starting Memory Read, at          21590655000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          21596625000
 test target 2 - Starting Config Write, at          21597525000
 test target 1 - Starting Memory Write, at          21598215000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          21598395000
 test target 1 - Starting Memory Write, at          21599415000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          21599595000
 test target 1 - Starting Memory Write, at          21600615000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          21602055000
 test target 1 - Starting Memory Read, at          21604215000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          21604395000
 test target 1 - Starting Memory Read, at          21606435000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          21608085000
 test master 2 - Starting Memory Write, at          21608085000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          21608145000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21608985000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21609015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21609315000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21609345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21610215000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21610245000
 test target 1 - Starting Memory Write, at          21612015000
 test master 2 - Starting Memory Write, at          21612015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21613725000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21613755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21615405000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21615435000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21617085000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21617115000
 test target 1 - Starting Memory Write, at          21619125000
 test master 2 - Starting Memory Write, at          21619125000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          21619185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21620805000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21620835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21621135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21621165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21622035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21622065000
 test target 1 - Starting Memory Write, at          21623235000
 test master 2 - Starting Memory Write, at          21623235000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          21626115000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          21627705000
 test master 1 - Starting Memory Read, at          21628005000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          21628155000
 test target 1 - Starting Config Write, at          21630645000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          21632955000
 test target 1 - Starting Memory Write, at          21633165000
 test target 1 - Starting Memory Write, at          21633375000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          21633885000
 test target 1 - Starting Memory Write, at          21634125000
 test target 1 - Starting Memory Write, at          21634365000
 test target 1 - Starting Memory Write, at          21634875000
 test target 1 - Starting Memory Write, at          21635235000
 test target 1 - Starting Memory Write, at          21635745000
 test target 1 - Starting Memory Write, at          21636435000
 test target 1 - Starting Memory Write, at          21636675000
 test target 1 - Starting Memory Write, at          21637395000
 test target 1 - Starting Memory Write, at          21637785000
 test target 1 - Starting Memory Write, at          21638355000
 test target 1 - Starting Memory Write, at          21641565000
 test target 1 - Starting Memory Write, at          21641805000
 test target 1 - Starting Memory Write, at          21642045000
 test target 1 - Starting Memory Write, at          21642435000
 test target 1 - Starting Memory Write, at          21642825000
 test target 1 - Starting Memory Read, at          21651645000
 test target 1 - Starting Memory Read, at          21652785000
 test target 1 - Starting Memory Read, at          21653985000
 test target 1 - Starting Memory Read, at          21655185000
 test target 1 - Starting Memory Read, at          21656385000
 test target 1 - Starting Memory Read, at          21657585000
 test target 1 - Starting Memory Read, at          21658785000
 test target 1 - Starting Memory Read, at          21659985000
 test target 1 - Starting Memory Read, at          21661185000
 test target 1 - Starting Memory Read, at          21662385000
 test target 1 - Starting Memory Read, at          21663585000
 test target 1 - Starting Memory Read, at          21664785000
 test target 1 - Starting Memory Read, at          21665985000
 test target 1 - Starting Memory Read, at          21667185000
 test target 1 - Starting Memory Read, at          21668385000
 test target 1 - Starting Memory Read, at          21669585000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          21670755000
 test target 1 - Starting Memory Read, at          21670965000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          21672315000
 test target 1 - Starting Memory Read, at          21674835000
 test target 1 - Starting Memory Read, at          21675495000
 test target 1 - Starting Memory Read, at          21676155000
 test target 1 - Starting Memory Read, at          21677055000
 test target 1 - Starting Memory Read, at          21677925000
 test target 1 - Starting Memory Read, at          21679275000
 test target 1 - Starting Memory Read, at          21680445000
 test target 1 - Starting Memory Read, at          21681315000
 test target 1 - Starting Memory Read, at          21684585000
 test target 1 - Starting Memory Read, at          21687795000
 test target 1 - Starting Memory Read, at          21688695000
 test target 1 - Starting Memory Read, at          21689595000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          21690735000
 test master 1 - Starting Memory Write, at          21691065000
 test target 1 - Starting Memory Write, at          21691065000
 test target 1 - Starting Memory Write, at          21691275000
 test target 1 - Starting Memory Read, at          21691995000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          21694905000
 test master 1 - Starting Memory Write, at          21695235000
 test target 1 - Starting Memory Write, at          21695235000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          21700035000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          21701085000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          21725535000
 test target 1 - Starting Config Write, at          21726435000
 test target 1 - Starting Config Write, at          21727335000
 test target 2 - Starting Config Write, at          21728235000
 test target 2 - Starting Config Write, at          21729135000
 test target 2 - Starting Config Write, at          21730035000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          21731925000
 test target 1 - Starting Memory Read, at          21732225000
 test target 1 - Starting Memory Write, at          21732885000
 test target 1 - Starting Memory Read, at          21733185000
 test target 1 - Starting Memory Write, at          21734055000
 test target 1 - Starting Memory Read, at          21735495000
 test target 1 - Starting Memory Read, at          21736155000
 test target 1 - Starting Memory Read, at          21736845000
 test target 1 - Starting Memory Read, at          21737505000
 test target 1 - Starting Memory Read, at          21738435000
 test target 1 - Starting Memory Read, at          21739635000
 test target 1 - Starting Memory Read, at          21740475000
 test target 1 - Starting Memory Read, at          21741675000
 test target 1 - Starting Memory Read, at          21742515000
 test target 1 - Starting Memory Read, at          21745425000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          21751605000
 test target 1 - Starting Memory Read, at          21751905000
 test target 1 - Starting Memory Write, at          21752565000
 test target 1 - Starting Memory Read, at          21752865000
 test target 1 - Starting Memory Write, at          21753735000
 test target 1 - Starting Memory Read, at          21755175000
 test target 1 - Starting Memory Read, at          21755835000
 test target 1 - Starting Memory Read, at          21756525000
 test target 1 - Starting Memory Read, at          21757185000
 test target 1 - Starting Memory Read, at          21758115000
 test target 1 - Starting Memory Read, at          21759315000
 test target 1 - Starting Memory Read, at          21760155000
 test target 1 - Starting Memory Read, at          21761355000
 test target 1 - Starting Memory Read, at          21762195000
 test target 1 - Starting Memory Read, at          21765105000
 test target 1 - Starting Memory Write, at          21771285000
 test target 1 - Starting Memory Read, at          21771585000
 test target 1 - Starting Memory Write, at          21772245000
 test target 1 - Starting Memory Read, at          21772545000
 test target 1 - Starting Memory Write, at          21773415000
 test target 1 - Starting Memory Read, at          21774855000
 test target 1 - Starting Memory Read, at          21775515000
 test target 1 - Starting Memory Read, at          21776205000
 test target 1 - Starting Memory Read, at          21776865000
 test target 1 - Starting Memory Read, at          21777795000
 test target 1 - Starting Memory Read, at          21778995000
 test target 1 - Starting Memory Read, at          21779835000
 test target 1 - Starting Memory Read, at          21781035000
 test target 1 - Starting Memory Read, at          21781875000
 test target 1 - Starting Memory Read, at          21784785000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          21796485000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          21802665000
 test target 1 - Starting Memory Write, at          21803475000
 test target 1 - Starting Memory Read, at          21804075000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          21805455000
 test target 1 - Starting Config Write, at          21807315000
 test target 1 - Starting Memory Read, at          21807975000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          21809415000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          21811545000
 test target 1 - Starting Memory Write, at          21812715000
 test target 1 - Starting Memory Write, at          21813045000
 test target 1 - Starting Memory Read, at          21813345000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          21815655000
 test target 1 - Starting Memory Write, at          21818655000
 test target 1 - Starting Memory Write, at          21819135000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          21823215000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          21825135000
 test target 1 - Starting Memory Read, at          21826575000
 test target 1 - Starting Memory Read, at          21827745000
 test target 1 - Starting Memory Read, at          21829575000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          21835575000
 test target 2 - Starting Config Write, at          21836475000
 test target 1 - Starting Memory Write, at          21837165000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          21837375000
 test target 1 - Starting Memory Write, at          21838395000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          21838605000
 test target 1 - Starting Memory Write, at          21839625000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          21841095000
 test target 1 - Starting Memory Read, at          21843255000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          21843465000
 test target 1 - Starting Memory Read, at          21845475000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          21847125000
 test master 2 - Starting Memory Write, at          21847125000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          21847185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21848055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21848085000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21848385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21848415000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21849285000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21849315000
 test target 1 - Starting Memory Write, at          21851085000
 test master 2 - Starting Memory Write, at          21851085000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21852825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21852855000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21854505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21854535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21856185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21856215000
 test target 1 - Starting Memory Write, at          21858225000
 test master 2 - Starting Memory Write, at          21858225000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          21858285000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21859935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21859965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21860265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21860295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21861165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          21861195000
 test target 1 - Starting Memory Write, at          21862365000
 test master 2 - Starting Memory Write, at          21862365000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          21865275000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          21866865000
 test master 1 - Starting Memory Read, at          21867165000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          21867315000
 test target 1 - Starting Config Write, at          21869805000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          21872295000
 test target 1 - Starting Memory Write, at          21872535000
 test target 1 - Starting Memory Write, at          21872775000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          21873315000
 test target 1 - Starting Memory Write, at          21873585000
 test target 1 - Starting Memory Write, at          21873855000
 test target 1 - Starting Memory Write, at          21874395000
 test target 1 - Starting Memory Write, at          21874785000
 test target 1 - Starting Memory Write, at          21875325000
 test target 1 - Starting Memory Write, at          21876075000
 test target 1 - Starting Memory Write, at          21876345000
 test target 1 - Starting Memory Write, at          21877095000
 test target 1 - Starting Memory Write, at          21877515000
 test target 1 - Starting Memory Write, at          21878115000
 test target 1 - Starting Memory Write, at          21881355000
 test target 1 - Starting Memory Write, at          21881625000
 test target 1 - Starting Memory Write, at          21881895000
 test target 1 - Starting Memory Write, at          21882315000
 test target 1 - Starting Memory Write, at          21882735000
 test target 1 - Starting Memory Read, at          21891585000
 test target 1 - Starting Memory Read, at          21892785000
 test target 1 - Starting Memory Read, at          21893985000
 test target 1 - Starting Memory Read, at          21895185000
 test target 1 - Starting Memory Read, at          21896385000
 test target 1 - Starting Memory Read, at          21897585000
 test target 1 - Starting Memory Read, at          21898785000
 test target 1 - Starting Memory Read, at          21899985000
 test target 1 - Starting Memory Read, at          21901185000
 test target 1 - Starting Memory Read, at          21902385000
 test target 1 - Starting Memory Read, at          21903585000
 test target 1 - Starting Memory Read, at          21904785000
 test target 1 - Starting Memory Read, at          21905985000
 test target 1 - Starting Memory Read, at          21907185000
 test target 1 - Starting Memory Read, at          21908385000
 test target 1 - Starting Memory Read, at          21909585000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          21910755000
 test target 1 - Starting Memory Read, at          21910995000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          21912315000
 test target 1 - Starting Memory Read, at          21914865000
 test target 1 - Starting Memory Read, at          21915495000
 test target 1 - Starting Memory Read, at          21916155000
 test target 1 - Starting Memory Read, at          21917055000
 test target 1 - Starting Memory Read, at          21917925000
 test target 1 - Starting Memory Read, at          21919275000
 test target 1 - Starting Memory Read, at          21920535000
 test target 1 - Starting Memory Read, at          21921435000
 test target 1 - Starting Memory Read, at          21924705000
 test target 1 - Starting Memory Read, at          21927915000
 test target 1 - Starting Memory Read, at          21928815000
 test target 1 - Starting Memory Read, at          21929715000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          21930855000
 test master 1 - Starting Memory Write, at          21931215000
 test target 1 - Starting Memory Write, at          21931215000
 test target 1 - Starting Memory Write, at          21931455000
 test target 1 - Starting Memory Read, at          21932205000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          21935145000
 test master 1 - Starting Memory Write, at          21935505000
 test target 1 - Starting Memory Write, at          21935505000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          21940635000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          21940875000
 test master 2 - Starting Memory Read, at          21941055000
 test master 2 - Starting Memory Read, at          21941235000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          21942945000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          21943335000
 test master 2 - Starting Memory Read, at          21943515000
 test master 2 - Starting Memory Read, at          21943695000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          21945105000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          21945675000
 test master 2 - Starting Memory Read Line Multiple, at          21945855000
 test master 2 - Starting Memory Read Line Multiple, at          21946095000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          21948255000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          21958875000
 test master 2 - Starting Memory Read Line Multiple, at          21959055000
 test master 2 - Starting Memory Read Line Multiple, at          21959325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          21960405000
 test master 2 - Starting Memory Read Line Multiple, at          21960585000
 test master 2 - Starting Memory Read Line Multiple, at          21960825000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          21961905000
 test master 2 - Starting Memory Read Line Multiple, at          21962085000
 test master 2 - Starting Memory Read Line Multiple, at          21962325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          21963405000
 test master 2 - Starting Memory Read Line Multiple, at          21963585000
 test master 2 - Starting Memory Read Line Multiple, at          21963825000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          21964905000
 test master 2 - Starting Memory Read Line Multiple, at          21965085000
 test master 2 - Starting Memory Read Line Multiple, at          21965325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          21966405000
 test master 2 - Starting Memory Read Line Multiple, at          21966585000
 test master 2 - Starting Memory Read Line Multiple, at          21966825000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          21967905000
 test master 2 - Starting Memory Read Line Multiple, at          21968085000
 test master 2 - Starting Memory Read Line Multiple, at          21968325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          21969405000
 test master 2 - Starting Memory Read Line Multiple, at          21969585000
 test master 2 - Starting Memory Read Line Multiple, at          21969825000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          21970905000
 test master 2 - Starting Memory Read Line, at          21971085000
 test master 2 - Starting Memory Read Line, at          21971265000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          21971895000
 test master 2 - Starting Memory Read Line, at          21972075000
 test master 2 - Starting Memory Read Line, at          21972255000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          21973425000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          21974895000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          21977715000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          21979515000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          21984435000
 test master 2 - Starting Memory Write, at          21984675000
 test master 2 - Starting Memory Write, at          21984915000
 test master 2 - Starting Memory Write, at          21985155000
 test master 2 - Starting Memory Write, at          21985395000
 test master 1 - Starting Memory Read, at          21985755000
 test master 1 - Starting Memory Read, at          21986025000
 test master 1 - Starting Memory Read, at          21986565000
 test master 1 - Starting Memory Read, at          21986835000
 test master 1 - Starting Memory Read, at          21987375000
 test master 1 - Starting Memory Read, at          21987645000
 test master 2 - Starting Memory Write, at          21988905000
 test master 2 - Starting Memory Write, at          21989145000
 test master 2 - Starting Memory Write, at          21989385000
 test master 2 - Starting Memory Write, at          21989625000
 test master 2 - Starting Memory Write, at          21989865000
 test master 1 - Starting Memory Read, at          21990225000
 test master 1 - Starting Memory Read, at          21990495000
 test master 1 - Starting Memory Read, at          21991035000
 test master 1 - Starting Memory Read, at          21991305000
 test master 1 - Starting Memory Read, at          21991845000
 test master 1 - Starting Memory Read, at          21992115000
 test master 2 - Starting Memory Write, at          21993855000
 test master 2 - Starting Memory Write, at          21994905000
 test master 2 - Starting Memory Write, at          21995985000
 test master 2 - Starting Memory Write, at          21997065000
 test master 2 - Starting Memory Write, at          21999225000
 test master 2 - Starting Memory Write, at          22000305000
 test master 2 - Starting Memory Write, at          22001385000
 test master 2 - Starting Memory Write, at          22002465000
 test master 2 - Starting Memory Write, at          22004625000
 test master 2 - Starting Memory Write, at          22006635000
 test master 2 - Starting Memory Write, at          22008615000
 test master 2 - Starting Memory Write, at          22010595000
 test master 2 - Starting Memory Write, at          22013655000
 test master 2 - Starting Memory Write, at          22015875000
 test master 2 - Starting Memory Write, at          22018095000
 test master 2 - Starting Memory Write, at          22020315000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          22024665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22024695000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22026765000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          22027005000
 test master 2 - Starting Memory Read, at          22027185000
 test master 2 - Starting Memory Read, at          22027365000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22029075000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          22029495000
 test master 2 - Starting Memory Read, at          22029675000
 test master 2 - Starting Memory Read, at          22029855000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22031265000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22031835000
 test master 2 - Starting Memory Read Line Multiple, at          22032015000
 test master 2 - Starting Memory Read Line Multiple, at          22032255000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22034415000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22045035000
 test master 2 - Starting Memory Read Line Multiple, at          22045215000
 test master 2 - Starting Memory Read Line Multiple, at          22045485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22046565000
 test master 2 - Starting Memory Read Line Multiple, at          22046745000
 test master 2 - Starting Memory Read Line Multiple, at          22046985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22048065000
 test master 2 - Starting Memory Read Line Multiple, at          22048245000
 test master 2 - Starting Memory Read Line Multiple, at          22048485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22049565000
 test master 2 - Starting Memory Read Line Multiple, at          22049745000
 test master 2 - Starting Memory Read Line Multiple, at          22049985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22051065000
 test master 2 - Starting Memory Read Line Multiple, at          22051245000
 test master 2 - Starting Memory Read Line Multiple, at          22051485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22052565000
 test master 2 - Starting Memory Read Line Multiple, at          22052745000
 test master 2 - Starting Memory Read Line Multiple, at          22052985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22054065000
 test master 2 - Starting Memory Read Line Multiple, at          22054245000
 test master 2 - Starting Memory Read Line Multiple, at          22054485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22055565000
 test master 2 - Starting Memory Read Line Multiple, at          22055745000
 test master 2 - Starting Memory Read Line Multiple, at          22055985000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          22057065000
 test master 2 - Starting Memory Read Line, at          22057245000
 test master 2 - Starting Memory Read Line, at          22057425000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          22058055000
 test master 2 - Starting Memory Read Line, at          22058235000
 test master 2 - Starting Memory Read Line, at          22058415000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22059585000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22061055000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22063875000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22065675000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          22070595000
 test master 2 - Starting Memory Write, at          22070835000
 test master 2 - Starting Memory Write, at          22071075000
 test master 2 - Starting Memory Write, at          22071315000
 test master 2 - Starting Memory Write, at          22071555000
 test master 1 - Starting Memory Read, at          22071915000
 test master 1 - Starting Memory Read, at          22072185000
 test master 1 - Starting Memory Read, at          22072725000
 test master 1 - Starting Memory Read, at          22072995000
 test master 1 - Starting Memory Read, at          22073535000
 test master 1 - Starting Memory Read, at          22073805000
 test master 2 - Starting Memory Write, at          22075065000
 test master 2 - Starting Memory Write, at          22075305000
 test master 2 - Starting Memory Write, at          22075545000
 test master 2 - Starting Memory Write, at          22075785000
 test master 2 - Starting Memory Write, at          22076025000
 test master 1 - Starting Memory Read, at          22076385000
 test master 1 - Starting Memory Read, at          22076655000
 test master 1 - Starting Memory Read, at          22077195000
 test master 1 - Starting Memory Read, at          22077465000
 test master 1 - Starting Memory Read, at          22078005000
 test master 1 - Starting Memory Read, at          22078275000
 test master 2 - Starting Memory Write, at          22080015000
 test master 2 - Starting Memory Write, at          22081065000
 test master 2 - Starting Memory Write, at          22082145000
 test master 2 - Starting Memory Write, at          22083225000
 test master 2 - Starting Memory Write, at          22085385000
 test master 2 - Starting Memory Write, at          22086465000
 test master 2 - Starting Memory Write, at          22087545000
 test master 2 - Starting Memory Write, at          22088625000
 test master 2 - Starting Memory Write, at          22090785000
 test master 2 - Starting Memory Write, at          22092795000
 test master 2 - Starting Memory Write, at          22094775000
 test master 2 - Starting Memory Write, at          22096755000
 test master 2 - Starting Memory Write, at          22099815000
 test master 2 - Starting Memory Write, at          22102035000
 test master 2 - Starting Memory Write, at          22104255000
 test master 2 - Starting Memory Write, at          22106475000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          22110825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22110855000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22112925000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          22113165000
 test master 2 - Starting Memory Read, at          22113345000
 test master 2 - Starting Memory Read, at          22113525000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22115235000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          22115655000
 test master 2 - Starting Memory Read, at          22115835000
 test master 2 - Starting Memory Read, at          22116015000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22117425000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22117995000
 test master 2 - Starting Memory Read Line Multiple, at          22118175000
 test master 2 - Starting Memory Read Line Multiple, at          22118415000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22120575000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22131195000
 test master 2 - Starting Memory Read Line Multiple, at          22131375000
 test master 2 - Starting Memory Read Line Multiple, at          22131645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22132725000
 test master 2 - Starting Memory Read Line Multiple, at          22132905000
 test master 2 - Starting Memory Read Line Multiple, at          22133145000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22134225000
 test master 2 - Starting Memory Read Line Multiple, at          22134405000
 test master 2 - Starting Memory Read Line Multiple, at          22134645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22135725000
 test master 2 - Starting Memory Read Line Multiple, at          22135905000
 test master 2 - Starting Memory Read Line Multiple, at          22136145000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22137225000
 test master 2 - Starting Memory Read Line Multiple, at          22137405000
 test master 2 - Starting Memory Read Line Multiple, at          22137645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22138725000
 test master 2 - Starting Memory Read Line Multiple, at          22138905000
 test master 2 - Starting Memory Read Line Multiple, at          22139145000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22140225000
 test master 2 - Starting Memory Read Line Multiple, at          22140405000
 test master 2 - Starting Memory Read Line Multiple, at          22140645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22141725000
 test master 2 - Starting Memory Read Line Multiple, at          22141905000
 test master 2 - Starting Memory Read Line Multiple, at          22142145000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          22143225000
 test master 2 - Starting Memory Read Line, at          22143405000
 test master 2 - Starting Memory Read Line, at          22143585000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          22144215000
 test master 2 - Starting Memory Read Line, at          22144395000
 test master 2 - Starting Memory Read Line, at          22144575000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22145745000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22147215000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22150035000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22151835000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          22156755000
 test master 2 - Starting Memory Write, at          22156995000
 test master 2 - Starting Memory Write, at          22157235000
 test master 2 - Starting Memory Write, at          22157475000
 test master 2 - Starting Memory Write, at          22157715000
 test master 1 - Starting Memory Read, at          22158075000
 test master 1 - Starting Memory Read, at          22158345000
 test master 1 - Starting Memory Read, at          22158885000
 test master 1 - Starting Memory Read, at          22159155000
 test master 1 - Starting Memory Read, at          22159695000
 test master 1 - Starting Memory Read, at          22159965000
 test master 2 - Starting Memory Write, at          22161225000
 test master 2 - Starting Memory Write, at          22161465000
 test master 2 - Starting Memory Write, at          22161705000
 test master 2 - Starting Memory Write, at          22161945000
 test master 2 - Starting Memory Write, at          22162185000
 test master 1 - Starting Memory Read, at          22162545000
 test master 1 - Starting Memory Read, at          22162815000
 test master 1 - Starting Memory Read, at          22163355000
 test master 1 - Starting Memory Read, at          22163625000
 test master 1 - Starting Memory Read, at          22164165000
 test master 1 - Starting Memory Read, at          22164435000
 test master 2 - Starting Memory Write, at          22166175000
 test master 2 - Starting Memory Write, at          22167225000
 test master 2 - Starting Memory Write, at          22168305000
 test master 2 - Starting Memory Write, at          22169385000
 test master 2 - Starting Memory Write, at          22171545000
 test master 2 - Starting Memory Write, at          22172625000
 test master 2 - Starting Memory Write, at          22173705000
 test master 2 - Starting Memory Write, at          22174785000
 test master 2 - Starting Memory Write, at          22176945000
 test master 2 - Starting Memory Write, at          22178955000
 test master 2 - Starting Memory Write, at          22180935000
 test master 2 - Starting Memory Write, at          22182915000
 test master 2 - Starting Memory Write, at          22185975000
 test master 2 - Starting Memory Write, at          22188195000
 test master 2 - Starting Memory Write, at          22190415000
 test master 2 - Starting Memory Write, at          22192635000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          22196985000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22197015000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22199085000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          22199325000
 test master 2 - Starting Memory Read, at          22199505000
 test master 2 - Starting Memory Read, at          22199685000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22201395000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          22201815000
 test master 2 - Starting Memory Read, at          22201995000
 test master 2 - Starting Memory Read, at          22202175000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22203585000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22204155000
 test master 2 - Starting Memory Read Line Multiple, at          22204335000
 test master 2 - Starting Memory Read Line Multiple, at          22204575000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22206735000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22217355000
 test master 2 - Starting Memory Read Line Multiple, at          22217535000
 test master 2 - Starting Memory Read Line Multiple, at          22217805000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22218885000
 test master 2 - Starting Memory Read Line Multiple, at          22219065000
 test master 2 - Starting Memory Read Line Multiple, at          22219305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22220385000
 test master 2 - Starting Memory Read Line Multiple, at          22220565000
 test master 2 - Starting Memory Read Line Multiple, at          22220805000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22221885000
 test master 2 - Starting Memory Read Line Multiple, at          22222065000
 test master 2 - Starting Memory Read Line Multiple, at          22222305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22223385000
 test master 2 - Starting Memory Read Line Multiple, at          22223565000
 test master 2 - Starting Memory Read Line Multiple, at          22223805000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22224885000
 test master 2 - Starting Memory Read Line Multiple, at          22225065000
 test master 2 - Starting Memory Read Line Multiple, at          22225305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22226385000
 test master 2 - Starting Memory Read Line Multiple, at          22226565000
 test master 2 - Starting Memory Read Line Multiple, at          22226805000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          22227885000
 test master 2 - Starting Memory Read Line Multiple, at          22228065000
 test master 2 - Starting Memory Read Line Multiple, at          22228305000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          22229385000
 test master 2 - Starting Memory Read Line, at          22229565000
 test master 2 - Starting Memory Read Line, at          22229745000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          22230375000
 test master 2 - Starting Memory Read Line, at          22230555000
 test master 2 - Starting Memory Read Line, at          22230735000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22231905000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22233375000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22236195000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          22237995000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          22242915000
 test master 2 - Starting Memory Write, at          22243155000
 test master 2 - Starting Memory Write, at          22243395000
 test master 2 - Starting Memory Write, at          22243635000
 test master 2 - Starting Memory Write, at          22243875000
 test master 1 - Starting Memory Read, at          22244235000
 test master 1 - Starting Memory Read, at          22244505000
 test master 1 - Starting Memory Read, at          22245045000
 test master 1 - Starting Memory Read, at          22245315000
 test master 1 - Starting Memory Read, at          22245855000
 test master 1 - Starting Memory Read, at          22246125000
 test master 2 - Starting Memory Write, at          22247385000
 test master 2 - Starting Memory Write, at          22247625000
 test master 2 - Starting Memory Write, at          22247865000
 test master 2 - Starting Memory Write, at          22248105000
 test master 2 - Starting Memory Write, at          22248345000
 test master 1 - Starting Memory Read, at          22248705000
 test master 1 - Starting Memory Read, at          22248975000
 test master 1 - Starting Memory Read, at          22249515000
 test master 1 - Starting Memory Read, at          22249785000
 test master 1 - Starting Memory Read, at          22250325000
 test master 1 - Starting Memory Read, at          22250595000
 test master 2 - Starting Memory Write, at          22252335000
 test master 2 - Starting Memory Write, at          22253385000
 test master 2 - Starting Memory Write, at          22254465000
 test master 2 - Starting Memory Write, at          22255545000
 test master 2 - Starting Memory Write, at          22257705000
 test master 2 - Starting Memory Write, at          22258785000
 test master 2 - Starting Memory Write, at          22259865000
 test master 2 - Starting Memory Write, at          22260945000
 test master 2 - Starting Memory Write, at          22263105000
 test master 2 - Starting Memory Write, at          22265115000
 test master 2 - Starting Memory Write, at          22267095000
 test master 2 - Starting Memory Write, at          22269075000
 test master 2 - Starting Memory Write, at          22272135000
 test master 2 - Starting Memory Write, at          22274355000
 test master 2 - Starting Memory Write, at          22276575000
 test master 2 - Starting Memory Write, at          22278795000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          22283145000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22283175000
 test master 1 - Starting Memory Read, at          22285245000
 test master 1 - Starting Memory Read, at          22285545000
 test master 1 - Starting Memory Read, at          22286745000
 test master 1 - Starting Memory Read, at          22287045000
 test master 1 - Starting Memory Read Line, at          22288245000
 test master 1 - Starting Memory Read Line, at          22288545000
 test master 1 - Starting Memory Read Line, at          22289745000
 test master 1 - Starting Memory Read Line, at          22290045000
 test master 1 - Starting Memory Read Line, at          22291305000
 test master 1 - Starting Memory Read Line, at          22291665000
 test master 1 - Starting Memory Read Line, at          22293225000
 test master 1 - Starting Memory Read Line, at          22293585000
 test master 1 - Starting Memory Read Line Multiple, at          22295145000
 test master 1 - Starting Memory Read Line Multiple, at          22295565000
 test master 1 - Starting Memory Read Line Multiple, at          22297545000
 test master 1 - Starting Memory Read Line Multiple, at          22297965000
 test master 1 - Starting Memory Read Line, at          22299945000
 test master 1 - Starting Memory Read Line, at          22300305000
 test master 1 - Starting Memory Read, at          22302825000
 test master 1 - Starting Memory Read, at          22303125000
 test target 1 - Starting Config Write, at          22306335000
 test master 1 - Starting Memory Write, at          22306965000
 test master 1 - Starting Memory Write, at          22316235000
 test master 1 - Starting Memory Write, at          22317555000
 test master 1 - Starting Memory Write, at          22326225000
 test master 1 - Starting Memory Write, at          22327575000
 test master 1 - Starting Memory Read Line, at          22336845000
 test master 1 - Starting Memory Write, at          22338345000
 test master 1 - Starting Memory Read Line, at          22347615000
 test target 1 - Starting Config Write, at          22350915000
 test master 1 - Starting Memory Write, at          22351545000
 test master 1 - Starting Memory Write, at          22351665000
 test master 1 - Starting Memory Write, at          22351905000
 test master 1 - Starting Memory Read, at          22352025000
 test master 1 - Starting Memory Write, at          22352325000
 test master 1 - Starting Memory Read, at          22352445000
 test master 1 - Starting Memory Write, at          22354035000
 test master 1 - Starting Memory Write, at          22364655000
 test master 2 - Starting Memory Read Line, at          22375395000
 test master 2 - Starting Memory Read Line, at          22375725000
 test master 2 - Starting Memory Read Line, at          22376385000
 test master 2 - Starting Memory Read Line, at          22376715000
 test master 1 - Starting Memory Write, at          22377465000
 test master 1 - Starting Memory Write, at          22377795000
 test master 1 - Starting Memory Write, at          22378155000
 test master 2 - Starting Memory Read Line, at          22378635000
 test master 2 - Starting Memory Read Line, at          22378935000
 test master 2 - Starting Memory Read Line, at          22379265000
 test master 2 - Starting Memory Read Line, at          22379565000
 test master 2 - Starting Memory Read Line Multiple, at          22379925000
 test master 2 - Starting Memory Read Line Multiple, at          22380225000
 test master 1 - Starting Memory Write, at          22382145000
 test master 1 - Starting Memory Write, at          22382475000
 test master 2 - Starting Memory Read, at          22382955000
 test master 2 - Starting Memory Read, at          22383255000
 test master 2 - Starting Memory Read, at          22383585000
 test master 2 - Starting Memory Read, at          22383885000
 test master 1 - Starting Memory Write, at          22385565000
 test master 1 - Starting Memory Read, at          22385745000
 test master 1 - Starting Memory Write, at          22385925000
 test master 1 - Starting Memory Read, at          22386135000
 test master 1 - Starting Memory Write, at          22386345000
 test master 1 - Starting Memory Read, at          22386525000
 test master 1 - Starting Memory Read, at          22386735000
 test master 1 - Starting Memory Write, at          22386945000
 test master 1 - Starting Memory Write, at          22387125000
 test master 1 - Starting Memory Read, at          22387305000
 test master 1 - Starting Memory Write, at          22387485000
 test master 1 - Starting Memory Write, at          22387695000
 test master 1 - Starting Memory Write, at          22387905000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          22392225000
 test target 1 - Starting Memory Write, at          22392465000
 test master 1 - Starting Memory Write, at          22392675000
 test target 1 - Starting Memory Write, at          22392855000
 test target 1 - Starting Memory Write, at          22393095000
 test target 1 - Starting Memory Write, at          22393335000
 test master 1 - Starting Memory Write, at          22393665000
 test target 1 - Starting Memory Write, at          22394175000
 test target 1 - Starting Memory Write, at          22394745000
 test target 1 - Starting Memory Write, at          22395015000
 test master 1 - Starting Memory Write, at          22395255000
 test target 1 - Starting Memory Write, at          22395735000
 test target 1 - Starting Memory Write, at          22396005000
 test target 1 - Starting Memory Write, at          22396275000
 test master 1 - Starting Memory Write, at          22396905000
 test target 1 - Starting Memory Write, at          22397865000
 test target 1 - Starting Memory Write, at          22398825000
 test target 1 - Starting Memory Write, at          22399065000
 test master 1 - Starting Memory Read, at          22399275000
 test target 1 - Starting Memory Write, at          22399455000
 test master 1 - Starting Memory Read, at          22399665000
 test target 1 - Starting Memory Write, at          22399845000
 test master 1 - Starting Memory Read, at          22400055000
 test target 1 - Starting Memory Write, at          22400235000
 test master 1 - Starting Memory Read, at          22400445000
 test target 1 - Starting Memory Write, at          22400625000
 test master 1 - Starting Memory Read, at          22400835000
 test target 1 - Starting Memory Write, at          22401015000
 test master 1 - Starting Memory Write, at          22401225000
 test target 1 - Starting Memory Write, at          22401405000
 test target 1 - Starting Memory Write, at          22401645000
 test target 1 - Starting Memory Write, at          22401885000
 test target 1 - Starting Memory Read, at          22402185000
 test master 1 - Starting Memory Write, at          22402515000
 test master 1 - Starting Memory Read, at          22402755000
 test target 1 - Starting Memory Write, at          22403265000
 test master 1 - Starting Memory Write, at          22403655000
 test target 1 - Starting Memory Read, at          22404105000
 test target 1 - Starting Memory Write, at          22404915000
 test master 1 - Starting Memory Read, at          22405245000
 test master 1 - Starting Memory Write, at          22405545000
 test master 1 - Starting Memory Write, at          22405905000
 test master 1 - Starting Memory Read, at          22406145000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          22408665000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          22409745000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          22434795000
 test target 1 - Starting Config Write, at          22435785000
 test target 1 - Starting Config Write, at          22436595000
 test target 2 - Starting Config Write, at          22437615000
 test target 2 - Starting Config Write, at          22438605000
 test target 2 - Starting Config Write, at          22439415000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          22441425000
 test target 1 - Starting Memory Read, at          22441635000
 test target 1 - Starting Memory Write, at          22442325000
 test target 1 - Starting Memory Read, at          22442535000
 test target 1 - Starting Memory Write, at          22443555000
 test target 1 - Starting Memory Read, at          22444755000
 test target 1 - Starting Memory Read, at          22445265000
 test target 1 - Starting Memory Read, at          22445865000
 test target 1 - Starting Memory Read, at          22446435000
 test target 1 - Starting Memory Read, at          22447275000
 test target 1 - Starting Memory Read, at          22448355000
 test target 1 - Starting Memory Read, at          22449315000
 test target 1 - Starting Memory Read, at          22450395000
 test target 1 - Starting Memory Read, at          22451355000
 test target 1 - Starting Memory Read, at          22453785000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          22460385000
 test target 1 - Starting Memory Read, at          22460595000
 test target 1 - Starting Memory Write, at          22461285000
 test target 1 - Starting Memory Read, at          22461495000
 test target 1 - Starting Memory Write, at          22462515000
 test target 1 - Starting Memory Read, at          22463715000
 test target 1 - Starting Memory Read, at          22464225000
 test target 1 - Starting Memory Read, at          22464825000
 test target 1 - Starting Memory Read, at          22465395000
 test target 1 - Starting Memory Read, at          22466235000
 test target 1 - Starting Memory Read, at          22467315000
 test target 1 - Starting Memory Read, at          22468275000
 test target 1 - Starting Memory Read, at          22469355000
 test target 1 - Starting Memory Read, at          22470315000
 test target 1 - Starting Memory Read, at          22472745000
 test target 1 - Starting Memory Write, at          22479345000
 test target 1 - Starting Memory Read, at          22479555000
 test target 1 - Starting Memory Write, at          22480245000
 test target 1 - Starting Memory Read, at          22480455000
 test target 1 - Starting Memory Write, at          22481475000
 test target 1 - Starting Memory Read, at          22482675000
 test target 1 - Starting Memory Read, at          22483185000
 test target 1 - Starting Memory Read, at          22483785000
 test target 1 - Starting Memory Read, at          22484355000
 test target 1 - Starting Memory Read, at          22485195000
 test target 1 - Starting Memory Read, at          22486275000
 test target 1 - Starting Memory Read, at          22487235000
 test target 1 - Starting Memory Read, at          22488315000
 test target 1 - Starting Memory Read, at          22489275000
 test target 1 - Starting Memory Read, at          22491705000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          22504245000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          22510815000
 test target 1 - Starting Memory Write, at          22511715000
 test target 1 - Starting Memory Read, at          22512165000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          22513455000
 test target 1 - Starting Config Write, at          22515525000
 test target 1 - Starting Memory Read, at          22516095000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          22517655000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          22519905000
 test target 1 - Starting Memory Write, at          22521165000
 test target 1 - Starting Memory Write, at          22521405000
 test target 1 - Starting Memory Read, at          22521615000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          22524075000
 test target 1 - Starting Memory Write, at          22527135000
 test target 1 - Starting Memory Write, at          22527495000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          22531605000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          22533495000
 test target 1 - Starting Memory Read, at          22534815000
 test target 1 - Starting Memory Read, at          22535955000
 test target 1 - Starting Memory Read, at          22537695000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          22543785000
 test target 2 - Starting Config Write, at          22544775000
 test target 1 - Starting Memory Write, at          22545555000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          22545675000
 test target 1 - Starting Memory Write, at          22546725000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          22546845000
 test target 1 - Starting Memory Write, at          22547895000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          22549275000
 test target 1 - Starting Memory Read, at          22551435000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          22551555000
 test target 1 - Starting Memory Read, at          22553775000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          22555395000
 test master 2 - Starting Memory Write, at          22555395000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          22555455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22556265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22556295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22556595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22556625000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22557525000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22557555000
 test target 1 - Starting Memory Write, at          22559385000
 test master 2 - Starting Memory Write, at          22559385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22561095000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22561125000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22562835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22562865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22564575000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22564605000
 test target 1 - Starting Memory Write, at          22566675000
 test master 2 - Starting Memory Write, at          22566675000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          22566735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22568355000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22568385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22568685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22568715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22569615000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22569645000
 test target 1 - Starting Memory Write, at          22570845000
 test master 2 - Starting Memory Write, at          22570845000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          22573755000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          22575405000
 test master 1 - Starting Memory Read, at          22575765000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          22575915000
 test target 1 - Starting Config Write, at          22578525000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          22580925000
 test target 1 - Starting Memory Write, at          22581075000
 test target 1 - Starting Memory Write, at          22581225000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          22581705000
 test target 1 - Starting Memory Write, at          22581885000
 test target 1 - Starting Memory Write, at          22582065000
 test target 1 - Starting Memory Write, at          22582545000
 test target 1 - Starting Memory Write, at          22582815000
 test target 1 - Starting Memory Write, at          22583295000
 test target 1 - Starting Memory Write, at          22583955000
 test target 1 - Starting Memory Write, at          22584135000
 test target 1 - Starting Memory Write, at          22584795000
 test target 1 - Starting Memory Write, at          22585095000
 test target 1 - Starting Memory Write, at          22585635000
 test target 1 - Starting Memory Write, at          22589955000
 test target 1 - Starting Memory Write, at          22590135000
 test target 1 - Starting Memory Write, at          22590315000
 test target 1 - Starting Memory Write, at          22590615000
 test target 1 - Starting Memory Write, at          22590915000
 test target 1 - Starting Memory Read, at          22597965000
 test target 1 - Starting Memory Read, at          22599105000
 test target 1 - Starting Memory Read, at          22600215000
 test target 1 - Starting Memory Read, at          22601325000
 test target 1 - Starting Memory Read, at          22602465000
 test target 1 - Starting Memory Read, at          22603575000
 test target 1 - Starting Memory Read, at          22604685000
 test target 1 - Starting Memory Read, at          22605825000
 test target 1 - Starting Memory Read, at          22606935000
 test target 1 - Starting Memory Read, at          22608045000
 test target 1 - Starting Memory Read, at          22609185000
 test target 1 - Starting Memory Read, at          22610295000
 test target 1 - Starting Memory Read, at          22611405000
 test target 1 - Starting Memory Read, at          22612545000
 test target 1 - Starting Memory Read, at          22613655000
 test target 1 - Starting Memory Read, at          22614765000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          22615815000
 test target 1 - Starting Memory Read, at          22615965000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          22617435000
 test target 1 - Starting Memory Read, at          22619445000
 test target 1 - Starting Memory Read, at          22620075000
 test target 1 - Starting Memory Read, at          22620765000
 test target 1 - Starting Memory Read, at          22621545000
 test target 1 - Starting Memory Read, at          22622325000
 test target 1 - Starting Memory Read, at          22623495000
 test target 1 - Starting Memory Read, at          22624575000
 test target 1 - Starting Memory Read, at          22625535000
 test target 1 - Starting Memory Read, at          22628625000
 test target 1 - Starting Memory Read, at          22631415000
 test target 1 - Starting Memory Read, at          22632195000
 test target 1 - Starting Memory Read, at          22632975000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          22634115000
 test master 1 - Starting Memory Write, at          22634475000
 test target 1 - Starting Memory Write, at          22634475000
 test target 1 - Starting Memory Write, at          22634625000
 test target 1 - Starting Memory Read, at          22635075000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          22637625000
 test master 1 - Starting Memory Write, at          22637985000
 test target 1 - Starting Memory Write, at          22637985000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          22643025000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          22644105000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          22669155000
 test target 1 - Starting Config Write, at          22670145000
 test target 1 - Starting Config Write, at          22671165000
 test target 2 - Starting Config Write, at          22672155000
 test target 2 - Starting Config Write, at          22673145000
 test target 2 - Starting Config Write, at          22674165000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          22676145000
 test target 1 - Starting Memory Read, at          22676385000
 test target 1 - Starting Memory Write, at          22677045000
 test target 1 - Starting Memory Read, at          22677285000
 test target 1 - Starting Memory Write, at          22678275000
 test target 1 - Starting Memory Read, at          22679535000
 test target 1 - Starting Memory Read, at          22680165000
 test target 1 - Starting Memory Read, at          22680765000
 test target 1 - Starting Memory Read, at          22681335000
 test target 1 - Starting Memory Read, at          22682175000
 test target 1 - Starting Memory Read, at          22683375000
 test target 1 - Starting Memory Read, at          22684335000
 test target 1 - Starting Memory Read, at          22685535000
 test target 1 - Starting Memory Read, at          22686495000
 test target 1 - Starting Memory Read, at          22689045000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          22695645000
 test target 1 - Starting Memory Read, at          22695885000
 test target 1 - Starting Memory Write, at          22696545000
 test target 1 - Starting Memory Read, at          22696785000
 test target 1 - Starting Memory Write, at          22697775000
 test target 1 - Starting Memory Read, at          22699035000
 test target 1 - Starting Memory Read, at          22699665000
 test target 1 - Starting Memory Read, at          22700265000
 test target 1 - Starting Memory Read, at          22700835000
 test target 1 - Starting Memory Read, at          22701675000
 test target 1 - Starting Memory Read, at          22702875000
 test target 1 - Starting Memory Read, at          22703835000
 test target 1 - Starting Memory Read, at          22705035000
 test target 1 - Starting Memory Read, at          22705995000
 test target 1 - Starting Memory Read, at          22708545000
 test target 1 - Starting Memory Write, at          22715145000
 test target 1 - Starting Memory Read, at          22715385000
 test target 1 - Starting Memory Write, at          22716045000
 test target 1 - Starting Memory Read, at          22716285000
 test target 1 - Starting Memory Write, at          22717275000
 test target 1 - Starting Memory Read, at          22718535000
 test target 1 - Starting Memory Read, at          22719165000
 test target 1 - Starting Memory Read, at          22719765000
 test target 1 - Starting Memory Read, at          22720335000
 test target 1 - Starting Memory Read, at          22721175000
 test target 1 - Starting Memory Read, at          22722375000
 test target 1 - Starting Memory Read, at          22723335000
 test target 1 - Starting Memory Read, at          22724535000
 test target 1 - Starting Memory Read, at          22725495000
 test target 1 - Starting Memory Read, at          22728045000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          22740585000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          22747155000
 test target 1 - Starting Memory Write, at          22748055000
 test target 1 - Starting Memory Read, at          22748535000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          22749915000
 test target 1 - Starting Config Write, at          22751985000
 test target 1 - Starting Memory Read, at          22752735000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          22754325000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          22756575000
 test target 1 - Starting Memory Write, at          22757865000
 test target 1 - Starting Memory Write, at          22758135000
 test target 1 - Starting Memory Read, at          22758375000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          22760775000
 test target 1 - Starting Memory Write, at          22763895000
 test target 1 - Starting Memory Write, at          22764285000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          22768425000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          22770495000
 test target 1 - Starting Memory Read, at          22771935000
 test target 1 - Starting Memory Read, at          22773075000
 test target 1 - Starting Memory Read, at          22774815000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          22781025000
 test target 2 - Starting Config Write, at          22782015000
 test target 1 - Starting Memory Write, at          22782795000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          22782945000
 test target 1 - Starting Memory Write, at          22783995000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          22784145000
 test target 1 - Starting Memory Write, at          22785195000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          22786635000
 test target 1 - Starting Memory Read, at          22788975000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          22789125000
 test target 1 - Starting Memory Read, at          22791315000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          22793115000
 test master 2 - Starting Memory Write, at          22793115000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          22793175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22794015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22794045000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22794345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22794375000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22795275000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22795305000
 test target 1 - Starting Memory Write, at          22797135000
 test master 2 - Starting Memory Write, at          22797135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22798875000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22798905000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22800615000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22800645000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22802355000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22802385000
 test target 1 - Starting Memory Write, at          22804455000
 test master 2 - Starting Memory Write, at          22804455000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          22804515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22806165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22806195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22806495000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22806525000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22807425000
*** monitor - CBE Bus Changed when TRDY Desserted, at          22807455000
 test target 1 - Starting Memory Write, at          22808655000
 test master 2 - Starting Memory Write, at          22808655000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          22811595000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          22813245000
 test master 1 - Starting Memory Read, at          22813605000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          22813755000
 test target 1 - Starting Config Write, at          22816365000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          22818765000
 test target 1 - Starting Memory Write, at          22818945000
 test target 1 - Starting Memory Write, at          22819125000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          22819635000
 test target 1 - Starting Memory Write, at          22819845000
 test target 1 - Starting Memory Write, at          22820055000
 test target 1 - Starting Memory Write, at          22820565000
 test target 1 - Starting Memory Write, at          22820865000
 test target 1 - Starting Memory Write, at          22821375000
 test target 1 - Starting Memory Write, at          22822065000
 test target 1 - Starting Memory Write, at          22822275000
 test target 1 - Starting Memory Write, at          22822965000
 test target 1 - Starting Memory Write, at          22823295000
 test target 1 - Starting Memory Write, at          22823865000
 test target 1 - Starting Memory Write, at          22828215000
 test target 1 - Starting Memory Write, at          22828425000
 test target 1 - Starting Memory Write, at          22828635000
 test target 1 - Starting Memory Write, at          22828965000
 test target 1 - Starting Memory Write, at          22829295000
 test target 1 - Starting Memory Read, at          22836375000
 test target 1 - Starting Memory Read, at          22837485000
 test target 1 - Starting Memory Read, at          22838595000
 test target 1 - Starting Memory Read, at          22839705000
 test target 1 - Starting Memory Read, at          22840845000
 test target 1 - Starting Memory Read, at          22841955000
 test target 1 - Starting Memory Read, at          22843065000
 test target 1 - Starting Memory Read, at          22844205000
 test target 1 - Starting Memory Read, at          22845315000
 test target 1 - Starting Memory Read, at          22846425000
 test target 1 - Starting Memory Read, at          22847565000
 test target 1 - Starting Memory Read, at          22848675000
 test target 1 - Starting Memory Read, at          22849785000
 test target 1 - Starting Memory Read, at          22850925000
 test target 1 - Starting Memory Read, at          22852035000
 test target 1 - Starting Memory Read, at          22853145000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          22854195000
 test target 1 - Starting Memory Read, at          22854375000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          22855995000
 test target 1 - Starting Memory Read, at          22858035000
 test target 1 - Starting Memory Read, at          22858635000
 test target 1 - Starting Memory Read, at          22859325000
 test target 1 - Starting Memory Read, at          22860105000
 test target 1 - Starting Memory Read, at          22860885000
 test target 1 - Starting Memory Read, at          22862175000
 test target 1 - Starting Memory Read, at          22863375000
 test target 1 - Starting Memory Read, at          22864335000
 test target 1 - Starting Memory Read, at          22867425000
 test target 1 - Starting Memory Read, at          22870215000
 test target 1 - Starting Memory Read, at          22871115000
 test target 1 - Starting Memory Read, at          22872015000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          22873275000
 test master 1 - Starting Memory Write, at          22873665000
 test target 1 - Starting Memory Write, at          22873665000
 test target 1 - Starting Memory Write, at          22873845000
 test target 1 - Starting Memory Read, at          22874325000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          22876935000
 test master 1 - Starting Memory Write, at          22877325000
 test target 1 - Starting Memory Write, at          22877325000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          22882305000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          22883385000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          22908435000
 test target 1 - Starting Config Write, at          22909425000
 test target 1 - Starting Config Write, at          22910445000
 test target 2 - Starting Config Write, at          22911435000
 test target 2 - Starting Config Write, at          22912425000
 test target 2 - Starting Config Write, at          22913445000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          22915425000
 test target 1 - Starting Memory Read, at          22915695000
 test target 1 - Starting Memory Write, at          22916325000
 test target 1 - Starting Memory Read, at          22916595000
 test target 1 - Starting Memory Write, at          22917555000
 test target 1 - Starting Memory Read, at          22918815000
 test target 1 - Starting Memory Read, at          22919445000
 test target 1 - Starting Memory Read, at          22920045000
 test target 1 - Starting Memory Read, at          22920615000
 test target 1 - Starting Memory Read, at          22921455000
 test target 1 - Starting Memory Read, at          22922655000
 test target 1 - Starting Memory Read, at          22923615000
 test target 1 - Starting Memory Read, at          22924815000
 test target 1 - Starting Memory Read, at          22925775000
 test target 1 - Starting Memory Read, at          22928325000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          22934925000
 test target 1 - Starting Memory Read, at          22935195000
 test target 1 - Starting Memory Write, at          22935825000
 test target 1 - Starting Memory Read, at          22936095000
 test target 1 - Starting Memory Write, at          22937055000
 test target 1 - Starting Memory Read, at          22938315000
 test target 1 - Starting Memory Read, at          22938945000
 test target 1 - Starting Memory Read, at          22939545000
 test target 1 - Starting Memory Read, at          22940115000
 test target 1 - Starting Memory Read, at          22940955000
 test target 1 - Starting Memory Read, at          22942155000
 test target 1 - Starting Memory Read, at          22943115000
 test target 1 - Starting Memory Read, at          22944315000
 test target 1 - Starting Memory Read, at          22945275000
 test target 1 - Starting Memory Read, at          22947825000
 test target 1 - Starting Memory Write, at          22954425000
 test target 1 - Starting Memory Read, at          22954695000
 test target 1 - Starting Memory Write, at          22955325000
 test target 1 - Starting Memory Read, at          22955595000
 test target 1 - Starting Memory Write, at          22956555000
 test target 1 - Starting Memory Read, at          22957815000
 test target 1 - Starting Memory Read, at          22958445000
 test target 1 - Starting Memory Read, at          22959045000
 test target 1 - Starting Memory Read, at          22959615000
 test target 1 - Starting Memory Read, at          22960455000
 test target 1 - Starting Memory Read, at          22961655000
 test target 1 - Starting Memory Read, at          22962615000
 test target 1 - Starting Memory Read, at          22963815000
 test target 1 - Starting Memory Read, at          22964775000
 test target 1 - Starting Memory Read, at          22967325000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          22979865000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          22986435000
 test target 1 - Starting Memory Write, at          22987335000
 test target 1 - Starting Memory Read, at          22987845000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          22989195000
 test target 1 - Starting Config Write, at          22991265000
 test target 1 - Starting Memory Read, at          22992015000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          22993605000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          22995855000
 test target 1 - Starting Memory Write, at          22997145000
 test target 1 - Starting Memory Write, at          22997445000
 test target 1 - Starting Memory Read, at          22997715000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          23000235000
 test target 1 - Starting Memory Write, at          23003355000
 test target 1 - Starting Memory Write, at          23003775000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          23007945000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          23010015000
 test target 1 - Starting Memory Read, at          23011455000
 test target 1 - Starting Memory Read, at          23012595000
 test target 1 - Starting Memory Read, at          23014335000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          23020545000
 test target 2 - Starting Config Write, at          23021535000
 test target 1 - Starting Memory Write, at          23022315000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          23022495000
 test target 1 - Starting Memory Write, at          23023545000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          23023725000
 test target 1 - Starting Memory Write, at          23024775000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          23026215000
 test target 1 - Starting Memory Read, at          23028555000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          23028735000
 test target 1 - Starting Memory Read, at          23030895000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          23032695000
 test master 2 - Starting Memory Write, at          23032695000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          23032755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23033625000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23033655000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23033955000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23033985000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23034885000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23034915000
 test target 1 - Starting Memory Write, at          23036745000
 test master 2 - Starting Memory Write, at          23036745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23038515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23038545000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23040255000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23040285000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23041995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23042025000
 test target 1 - Starting Memory Write, at          23044095000
 test master 2 - Starting Memory Write, at          23044095000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          23044155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23045835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23045865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23046165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23046195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23047095000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23047125000
 test target 1 - Starting Memory Write, at          23048325000
 test master 2 - Starting Memory Write, at          23048325000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          23051295000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          23052945000
 test master 1 - Starting Memory Read, at          23053305000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          23053455000
 test target 1 - Starting Config Write, at          23056065000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          23058465000
 test target 1 - Starting Memory Write, at          23058675000
 test target 1 - Starting Memory Write, at          23058885000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          23059425000
 test target 1 - Starting Memory Write, at          23059665000
 test target 1 - Starting Memory Write, at          23059905000
 test target 1 - Starting Memory Write, at          23060445000
 test target 1 - Starting Memory Write, at          23060775000
 test target 1 - Starting Memory Write, at          23061315000
 test target 1 - Starting Memory Write, at          23062035000
 test target 1 - Starting Memory Write, at          23062275000
 test target 1 - Starting Memory Write, at          23062995000
 test target 1 - Starting Memory Write, at          23063355000
 test target 1 - Starting Memory Write, at          23063955000
 test target 1 - Starting Memory Write, at          23068335000
 test target 1 - Starting Memory Write, at          23068575000
 test target 1 - Starting Memory Write, at          23068815000
 test target 1 - Starting Memory Write, at          23069175000
 test target 1 - Starting Memory Write, at          23069535000
 test target 1 - Starting Memory Read, at          23076645000
 test target 1 - Starting Memory Read, at          23077845000
 test target 1 - Starting Memory Read, at          23078955000
 test target 1 - Starting Memory Read, at          23080065000
 test target 1 - Starting Memory Read, at          23081205000
 test target 1 - Starting Memory Read, at          23082315000
 test target 1 - Starting Memory Read, at          23083425000
 test target 1 - Starting Memory Read, at          23084565000
 test target 1 - Starting Memory Read, at          23085675000
 test target 1 - Starting Memory Read, at          23086785000
 test target 1 - Starting Memory Read, at          23087925000
 test target 1 - Starting Memory Read, at          23089035000
 test target 1 - Starting Memory Read, at          23090145000
 test target 1 - Starting Memory Read, at          23091285000
 test target 1 - Starting Memory Read, at          23092395000
 test target 1 - Starting Memory Read, at          23093505000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          23094555000
 test target 1 - Starting Memory Read, at          23094765000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          23096355000
 test target 1 - Starting Memory Read, at          23098425000
 test target 1 - Starting Memory Read, at          23099175000
 test target 1 - Starting Memory Read, at          23099865000
 test target 1 - Starting Memory Read, at          23100645000
 test target 1 - Starting Memory Read, at          23101425000
 test target 1 - Starting Memory Read, at          23102715000
 test target 1 - Starting Memory Read, at          23103915000
 test target 1 - Starting Memory Read, at          23104875000
 test target 1 - Starting Memory Read, at          23108115000
 test target 1 - Starting Memory Read, at          23110935000
 test target 1 - Starting Memory Read, at          23111835000
 test target 1 - Starting Memory Read, at          23112735000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          23113995000
 test master 1 - Starting Memory Write, at          23114295000
 test target 1 - Starting Memory Write, at          23114295000
 test target 1 - Starting Memory Write, at          23114505000
 test target 1 - Starting Memory Read, at          23115135000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          23117805000
 test master 1 - Starting Memory Write, at          23118105000
 test target 1 - Starting Memory Write, at          23118105000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          23123085000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          23124165000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          23149215000
 test target 1 - Starting Config Write, at          23150205000
 test target 1 - Starting Config Write, at          23151225000
 test target 2 - Starting Config Write, at          23152215000
 test target 2 - Starting Config Write, at          23153205000
 test target 2 - Starting Config Write, at          23154225000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          23156205000
 test target 1 - Starting Memory Read, at          23156505000
 test target 1 - Starting Memory Write, at          23157285000
 test target 1 - Starting Memory Read, at          23157585000
 test target 1 - Starting Memory Write, at          23158695000
 test target 1 - Starting Memory Read, at          23160015000
 test target 1 - Starting Memory Read, at          23160645000
 test target 1 - Starting Memory Read, at          23161365000
 test target 1 - Starting Memory Read, at          23162055000
 test target 1 - Starting Memory Read, at          23163015000
 test target 1 - Starting Memory Read, at          23164215000
 test target 1 - Starting Memory Read, at          23165175000
 test target 1 - Starting Memory Read, at          23166375000
 test target 1 - Starting Memory Read, at          23167335000
 test target 1 - Starting Memory Read, at          23169885000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          23176485000
 test target 1 - Starting Memory Read, at          23176785000
 test target 1 - Starting Memory Write, at          23177565000
 test target 1 - Starting Memory Read, at          23177865000
 test target 1 - Starting Memory Write, at          23178975000
 test target 1 - Starting Memory Read, at          23180295000
 test target 1 - Starting Memory Read, at          23180925000
 test target 1 - Starting Memory Read, at          23181645000
 test target 1 - Starting Memory Read, at          23182335000
 test target 1 - Starting Memory Read, at          23183295000
 test target 1 - Starting Memory Read, at          23184495000
 test target 1 - Starting Memory Read, at          23185455000
 test target 1 - Starting Memory Read, at          23186655000
 test target 1 - Starting Memory Read, at          23187615000
 test target 1 - Starting Memory Read, at          23190165000
 test target 1 - Starting Memory Write, at          23196765000
 test target 1 - Starting Memory Read, at          23197065000
 test target 1 - Starting Memory Write, at          23197845000
 test target 1 - Starting Memory Read, at          23198145000
 test target 1 - Starting Memory Write, at          23199255000
 test target 1 - Starting Memory Read, at          23200575000
 test target 1 - Starting Memory Read, at          23201205000
 test target 1 - Starting Memory Read, at          23201925000
 test target 1 - Starting Memory Read, at          23202615000
 test target 1 - Starting Memory Read, at          23203575000
 test target 1 - Starting Memory Read, at          23204775000
 test target 1 - Starting Memory Read, at          23205735000
 test target 1 - Starting Memory Read, at          23206935000
 test target 1 - Starting Memory Read, at          23207895000
 test target 1 - Starting Memory Read, at          23210445000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          23222985000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          23229555000
 test target 1 - Starting Memory Write, at          23230455000
 test target 1 - Starting Memory Read, at          23230995000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          23232435000
 test target 1 - Starting Config Write, at          23234505000
 test target 1 - Starting Memory Read, at          23235255000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          23236845000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          23239095000
 test target 1 - Starting Memory Write, at          23240385000
 test target 1 - Starting Memory Write, at          23240715000
 test target 1 - Starting Memory Read, at          23241015000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          23243475000
 test target 1 - Starting Memory Write, at          23246655000
 test target 1 - Starting Memory Write, at          23247105000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          23251305000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          23253375000
 test target 1 - Starting Memory Read, at          23254815000
 test target 1 - Starting Memory Read, at          23255955000
 test target 1 - Starting Memory Read, at          23257695000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          23263905000
 test target 2 - Starting Config Write, at          23264895000
 test target 1 - Starting Memory Write, at          23265675000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          23265885000
 test target 1 - Starting Memory Write, at          23266935000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          23267145000
 test target 1 - Starting Memory Write, at          23268195000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          23269695000
 test target 1 - Starting Memory Read, at          23272035000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          23272245000
 test target 1 - Starting Memory Read, at          23274375000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          23276175000
 test master 2 - Starting Memory Write, at          23276175000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          23276235000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23277135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23277165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23277465000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23277495000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23278395000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23278425000
 test target 1 - Starting Memory Write, at          23280255000
 test master 2 - Starting Memory Write, at          23280255000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23282055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23282085000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23283795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23283825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23285535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23285565000
 test target 1 - Starting Memory Write, at          23287635000
 test master 2 - Starting Memory Write, at          23287635000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          23287695000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23289405000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23289435000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23289735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23289765000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23290665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23290695000
 test target 1 - Starting Memory Write, at          23291895000
 test master 2 - Starting Memory Write, at          23291895000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          23294895000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          23296545000
 test master 1 - Starting Memory Read, at          23296905000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          23297055000
 test target 1 - Starting Config Write, at          23299665000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          23302065000
 test target 1 - Starting Memory Write, at          23302305000
 test target 1 - Starting Memory Write, at          23302545000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          23303115000
 test target 1 - Starting Memory Write, at          23303385000
 test target 1 - Starting Memory Write, at          23303655000
 test target 1 - Starting Memory Write, at          23304225000
 test target 1 - Starting Memory Write, at          23304585000
 test target 1 - Starting Memory Write, at          23305155000
 test target 1 - Starting Memory Write, at          23305905000
 test target 1 - Starting Memory Write, at          23306175000
 test target 1 - Starting Memory Write, at          23306925000
 test target 1 - Starting Memory Write, at          23307315000
 test target 1 - Starting Memory Write, at          23307945000
 test target 1 - Starting Memory Write, at          23312355000
 test target 1 - Starting Memory Write, at          23312625000
 test target 1 - Starting Memory Write, at          23312895000
 test target 1 - Starting Memory Write, at          23313285000
 test target 1 - Starting Memory Write, at          23313675000
 test target 1 - Starting Memory Read, at          23320815000
 test target 1 - Starting Memory Read, at          23321985000
 test target 1 - Starting Memory Read, at          23323215000
 test target 1 - Starting Memory Read, at          23324445000
 test target 1 - Starting Memory Read, at          23325705000
 test target 1 - Starting Memory Read, at          23326935000
 test target 1 - Starting Memory Read, at          23328165000
 test target 1 - Starting Memory Read, at          23329425000
 test target 1 - Starting Memory Read, at          23330655000
 test target 1 - Starting Memory Read, at          23331885000
 test target 1 - Starting Memory Read, at          23333145000
 test target 1 - Starting Memory Read, at          23334375000
 test target 1 - Starting Memory Read, at          23335605000
 test target 1 - Starting Memory Read, at          23336865000
 test target 1 - Starting Memory Read, at          23338095000
 test target 1 - Starting Memory Read, at          23339325000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          23340495000
 test target 1 - Starting Memory Read, at          23340735000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          23342295000
 test target 1 - Starting Memory Read, at          23344395000
 test target 1 - Starting Memory Read, at          23345115000
 test target 1 - Starting Memory Read, at          23345805000
 test target 1 - Starting Memory Read, at          23346735000
 test target 1 - Starting Memory Read, at          23347515000
 test target 1 - Starting Memory Read, at          23348835000
 test target 1 - Starting Memory Read, at          23350035000
 test target 1 - Starting Memory Read, at          23350995000
 test target 1 - Starting Memory Read, at          23354235000
 test target 1 - Starting Memory Read, at          23357055000
 test target 1 - Starting Memory Read, at          23357955000
 test target 1 - Starting Memory Read, at          23358855000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          23360115000
 test master 1 - Starting Memory Write, at          23360445000
 test target 1 - Starting Memory Write, at          23360445000
 test target 1 - Starting Memory Write, at          23360685000
 test target 1 - Starting Memory Read, at          23361345000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          23364075000
 test master 1 - Starting Memory Write, at          23364405000
 test target 1 - Starting Memory Write, at          23364405000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23369595000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          23369895000
 test master 2 - Starting Memory Read, at          23370075000
 test master 2 - Starting Memory Read, at          23370255000
 test master 2 - Starting Memory Read, at          23370495000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23372175000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          23372655000
 test master 2 - Starting Memory Read, at          23372835000
 test master 2 - Starting Memory Read, at          23373255000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23374695000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23375385000
 test master 2 - Starting Memory Read Line Multiple, at          23375565000
 test master 2 - Starting Memory Read Line Multiple, at          23375745000
 test master 2 - Starting Memory Read Line Multiple, at          23375925000
 test master 2 - Starting Memory Read Line Multiple, at          23376225000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23378235000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23390715000
 test master 2 - Starting Memory Read Line Multiple, at          23390895000
 test master 2 - Starting Memory Read Line Multiple, at          23391075000
 test master 2 - Starting Memory Read Line Multiple, at          23391255000
 test master 2 - Starting Memory Read Line Multiple, at          23391585000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23392485000
 test master 2 - Starting Memory Read Line Multiple, at          23392665000
 test master 2 - Starting Memory Read Line Multiple, at          23392845000
 test master 2 - Starting Memory Read Line Multiple, at          23393025000
 test master 2 - Starting Memory Read Line Multiple, at          23393325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23394225000
 test master 2 - Starting Memory Read Line Multiple, at          23394405000
 test master 2 - Starting Memory Read Line Multiple, at          23394585000
 test master 2 - Starting Memory Read Line Multiple, at          23394765000
 test master 2 - Starting Memory Read Line Multiple, at          23395065000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23395965000
 test master 2 - Starting Memory Read Line Multiple, at          23396145000
 test master 2 - Starting Memory Read Line Multiple, at          23396325000
 test master 2 - Starting Memory Read Line Multiple, at          23396505000
 test master 2 - Starting Memory Read Line Multiple, at          23396805000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23397705000
 test master 2 - Starting Memory Read Line Multiple, at          23397885000
 test master 2 - Starting Memory Read Line Multiple, at          23398065000
 test master 2 - Starting Memory Read Line Multiple, at          23398245000
 test master 2 - Starting Memory Read Line Multiple, at          23398545000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23399445000
 test master 2 - Starting Memory Read Line Multiple, at          23399625000
 test master 2 - Starting Memory Read Line Multiple, at          23399805000
 test master 2 - Starting Memory Read Line Multiple, at          23399985000
 test master 2 - Starting Memory Read Line Multiple, at          23400285000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23401185000
 test master 2 - Starting Memory Read Line Multiple, at          23401365000
 test master 2 - Starting Memory Read Line Multiple, at          23401545000
 test master 2 - Starting Memory Read Line Multiple, at          23401725000
 test master 2 - Starting Memory Read Line Multiple, at          23402025000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23402925000
 test master 2 - Starting Memory Read Line Multiple, at          23403105000
 test master 2 - Starting Memory Read Line Multiple, at          23403285000
 test master 2 - Starting Memory Read Line Multiple, at          23403465000
 test master 2 - Starting Memory Read Line Multiple, at          23403765000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          23404665000
 test master 2 - Starting Memory Read Line, at          23404845000
 test master 2 - Starting Memory Read Line, at          23405025000
 test master 2 - Starting Memory Read Line, at          23405265000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          23405805000
 test master 2 - Starting Memory Read Line, at          23405985000
 test master 2 - Starting Memory Read Line, at          23406405000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23407575000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23409195000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23412195000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23414175000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          23419485000
 test master 2 - Starting Memory Write, at          23419785000
 test master 2 - Starting Memory Write, at          23420085000
 test master 2 - Starting Memory Write, at          23420385000
 test master 2 - Starting Memory Write, at          23420685000
 test master 1 - Starting Memory Read, at          23421105000
 test master 1 - Starting Memory Read, at          23421435000
 test master 1 - Starting Memory Read, at          23421975000
 test master 1 - Starting Memory Read, at          23422305000
 test master 1 - Starting Memory Read, at          23422845000
 test master 1 - Starting Memory Read, at          23423175000
 test master 2 - Starting Memory Write, at          23424465000
 test master 2 - Starting Memory Write, at          23424765000
 test master 2 - Starting Memory Write, at          23425065000
 test master 2 - Starting Memory Write, at          23425365000
 test master 2 - Starting Memory Write, at          23425665000
 test master 1 - Starting Memory Read, at          23426085000
 test master 1 - Starting Memory Read, at          23426415000
 test master 1 - Starting Memory Read, at          23426955000
 test master 1 - Starting Memory Read, at          23427285000
 test master 1 - Starting Memory Read, at          23427825000
 test master 1 - Starting Memory Read, at          23428155000
 test master 2 - Starting Memory Write, at          23429955000
 test master 2 - Starting Memory Write, at          23431095000
 test master 2 - Starting Memory Write, at          23432235000
 test master 2 - Starting Memory Write, at          23433375000
 test master 2 - Starting Memory Write, at          23435655000
 test master 2 - Starting Memory Write, at          23436795000
 test master 2 - Starting Memory Write, at          23437935000
 test master 2 - Starting Memory Write, at          23439075000
 test master 2 - Starting Memory Write, at          23441355000
 test master 2 - Starting Memory Write, at          23443515000
 test master 2 - Starting Memory Write, at          23445675000
 test master 2 - Starting Memory Write, at          23447835000
 test master 2 - Starting Memory Write, at          23451135000
 test master 2 - Starting Memory Write, at          23453535000
 test master 2 - Starting Memory Write, at          23455935000
 test master 2 - Starting Memory Write, at          23458335000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          23462865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23462895000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23464995000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          23465295000
 test master 2 - Starting Memory Read, at          23465475000
 test master 2 - Starting Memory Read, at          23465655000
 test master 2 - Starting Memory Read, at          23465895000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23467575000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          23468055000
 test master 2 - Starting Memory Read, at          23468235000
 test master 2 - Starting Memory Read, at          23468655000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23470095000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23470785000
 test master 2 - Starting Memory Read Line Multiple, at          23470965000
 test master 2 - Starting Memory Read Line Multiple, at          23471145000
 test master 2 - Starting Memory Read Line Multiple, at          23471325000
 test master 2 - Starting Memory Read Line Multiple, at          23471625000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23473635000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23486115000
 test master 2 - Starting Memory Read Line Multiple, at          23486295000
 test master 2 - Starting Memory Read Line Multiple, at          23486475000
 test master 2 - Starting Memory Read Line Multiple, at          23486655000
 test master 2 - Starting Memory Read Line Multiple, at          23486985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23487885000
 test master 2 - Starting Memory Read Line Multiple, at          23488065000
 test master 2 - Starting Memory Read Line Multiple, at          23488245000
 test master 2 - Starting Memory Read Line Multiple, at          23488425000
 test master 2 - Starting Memory Read Line Multiple, at          23488725000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23489625000
 test master 2 - Starting Memory Read Line Multiple, at          23489805000
 test master 2 - Starting Memory Read Line Multiple, at          23489985000
 test master 2 - Starting Memory Read Line Multiple, at          23490165000
 test master 2 - Starting Memory Read Line Multiple, at          23490465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23491365000
 test master 2 - Starting Memory Read Line Multiple, at          23491545000
 test master 2 - Starting Memory Read Line Multiple, at          23491725000
 test master 2 - Starting Memory Read Line Multiple, at          23491905000
 test master 2 - Starting Memory Read Line Multiple, at          23492205000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23493105000
 test master 2 - Starting Memory Read Line Multiple, at          23493285000
 test master 2 - Starting Memory Read Line Multiple, at          23493465000
 test master 2 - Starting Memory Read Line Multiple, at          23493645000
 test master 2 - Starting Memory Read Line Multiple, at          23493945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23494845000
 test master 2 - Starting Memory Read Line Multiple, at          23495025000
 test master 2 - Starting Memory Read Line Multiple, at          23495205000
 test master 2 - Starting Memory Read Line Multiple, at          23495385000
 test master 2 - Starting Memory Read Line Multiple, at          23495685000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23496585000
 test master 2 - Starting Memory Read Line Multiple, at          23496765000
 test master 2 - Starting Memory Read Line Multiple, at          23496945000
 test master 2 - Starting Memory Read Line Multiple, at          23497125000
 test master 2 - Starting Memory Read Line Multiple, at          23497425000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23498325000
 test master 2 - Starting Memory Read Line Multiple, at          23498505000
 test master 2 - Starting Memory Read Line Multiple, at          23498685000
 test master 2 - Starting Memory Read Line Multiple, at          23498865000
 test master 2 - Starting Memory Read Line Multiple, at          23499165000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          23500065000
 test master 2 - Starting Memory Read Line, at          23500245000
 test master 2 - Starting Memory Read Line, at          23500425000
 test master 2 - Starting Memory Read Line, at          23500665000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          23501205000
 test master 2 - Starting Memory Read Line, at          23501385000
 test master 2 - Starting Memory Read Line, at          23501805000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23502975000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23504595000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23507595000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23509575000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          23514885000
 test master 2 - Starting Memory Write, at          23515185000
 test master 2 - Starting Memory Write, at          23515485000
 test master 2 - Starting Memory Write, at          23515785000
 test master 2 - Starting Memory Write, at          23516085000
 test master 1 - Starting Memory Read, at          23516505000
 test master 1 - Starting Memory Read, at          23516835000
 test master 1 - Starting Memory Read, at          23517375000
 test master 1 - Starting Memory Read, at          23517705000
 test master 1 - Starting Memory Read, at          23518245000
 test master 1 - Starting Memory Read, at          23518575000
 test master 2 - Starting Memory Write, at          23519865000
 test master 2 - Starting Memory Write, at          23520165000
 test master 2 - Starting Memory Write, at          23520465000
 test master 2 - Starting Memory Write, at          23520765000
 test master 2 - Starting Memory Write, at          23521065000
 test master 1 - Starting Memory Read, at          23521485000
 test master 1 - Starting Memory Read, at          23521815000
 test master 1 - Starting Memory Read, at          23522355000
 test master 1 - Starting Memory Read, at          23522685000
 test master 1 - Starting Memory Read, at          23523225000
 test master 1 - Starting Memory Read, at          23523555000
 test master 2 - Starting Memory Write, at          23525355000
 test master 2 - Starting Memory Write, at          23526495000
 test master 2 - Starting Memory Write, at          23527635000
 test master 2 - Starting Memory Write, at          23528775000
 test master 2 - Starting Memory Write, at          23531055000
 test master 2 - Starting Memory Write, at          23532195000
 test master 2 - Starting Memory Write, at          23533335000
 test master 2 - Starting Memory Write, at          23534475000
 test master 2 - Starting Memory Write, at          23536755000
 test master 2 - Starting Memory Write, at          23538915000
 test master 2 - Starting Memory Write, at          23541075000
 test master 2 - Starting Memory Write, at          23543235000
 test master 2 - Starting Memory Write, at          23546535000
 test master 2 - Starting Memory Write, at          23548935000
 test master 2 - Starting Memory Write, at          23551335000
 test master 2 - Starting Memory Write, at          23553735000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          23558265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23558295000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23560395000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          23560695000
 test master 2 - Starting Memory Read, at          23560875000
 test master 2 - Starting Memory Read, at          23561055000
 test master 2 - Starting Memory Read, at          23561295000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23562975000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          23563455000
 test master 2 - Starting Memory Read, at          23563635000
 test master 2 - Starting Memory Read, at          23564055000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23565495000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23566185000
 test master 2 - Starting Memory Read Line Multiple, at          23566365000
 test master 2 - Starting Memory Read Line Multiple, at          23566545000
 test master 2 - Starting Memory Read Line Multiple, at          23566725000
 test master 2 - Starting Memory Read Line Multiple, at          23567025000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23569035000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23581515000
 test master 2 - Starting Memory Read Line Multiple, at          23581695000
 test master 2 - Starting Memory Read Line Multiple, at          23581875000
 test master 2 - Starting Memory Read Line Multiple, at          23582055000
 test master 2 - Starting Memory Read Line Multiple, at          23582385000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23583285000
 test master 2 - Starting Memory Read Line Multiple, at          23583465000
 test master 2 - Starting Memory Read Line Multiple, at          23583645000
 test master 2 - Starting Memory Read Line Multiple, at          23583825000
 test master 2 - Starting Memory Read Line Multiple, at          23584125000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23585025000
 test master 2 - Starting Memory Read Line Multiple, at          23585205000
 test master 2 - Starting Memory Read Line Multiple, at          23585385000
 test master 2 - Starting Memory Read Line Multiple, at          23585565000
 test master 2 - Starting Memory Read Line Multiple, at          23585865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23586765000
 test master 2 - Starting Memory Read Line Multiple, at          23586945000
 test master 2 - Starting Memory Read Line Multiple, at          23587125000
 test master 2 - Starting Memory Read Line Multiple, at          23587305000
 test master 2 - Starting Memory Read Line Multiple, at          23587605000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23588505000
 test master 2 - Starting Memory Read Line Multiple, at          23588685000
 test master 2 - Starting Memory Read Line Multiple, at          23588865000
 test master 2 - Starting Memory Read Line Multiple, at          23589045000
 test master 2 - Starting Memory Read Line Multiple, at          23589345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23590245000
 test master 2 - Starting Memory Read Line Multiple, at          23590425000
 test master 2 - Starting Memory Read Line Multiple, at          23590605000
 test master 2 - Starting Memory Read Line Multiple, at          23590785000
 test master 2 - Starting Memory Read Line Multiple, at          23591085000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23591985000
 test master 2 - Starting Memory Read Line Multiple, at          23592165000
 test master 2 - Starting Memory Read Line Multiple, at          23592345000
 test master 2 - Starting Memory Read Line Multiple, at          23592525000
 test master 2 - Starting Memory Read Line Multiple, at          23592825000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23593725000
 test master 2 - Starting Memory Read Line Multiple, at          23593905000
 test master 2 - Starting Memory Read Line Multiple, at          23594085000
 test master 2 - Starting Memory Read Line Multiple, at          23594265000
 test master 2 - Starting Memory Read Line Multiple, at          23594565000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          23595465000
 test master 2 - Starting Memory Read Line, at          23595645000
 test master 2 - Starting Memory Read Line, at          23595825000
 test master 2 - Starting Memory Read Line, at          23596065000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          23596605000
 test master 2 - Starting Memory Read Line, at          23596785000
 test master 2 - Starting Memory Read Line, at          23597205000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23598375000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23599995000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23602995000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23604975000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          23610285000
 test master 2 - Starting Memory Write, at          23610585000
 test master 2 - Starting Memory Write, at          23610885000
 test master 2 - Starting Memory Write, at          23611185000
 test master 2 - Starting Memory Write, at          23611485000
 test master 1 - Starting Memory Read, at          23611905000
 test master 1 - Starting Memory Read, at          23612235000
 test master 1 - Starting Memory Read, at          23612775000
 test master 1 - Starting Memory Read, at          23613105000
 test master 1 - Starting Memory Read, at          23613645000
 test master 1 - Starting Memory Read, at          23613975000
 test master 2 - Starting Memory Write, at          23615265000
 test master 2 - Starting Memory Write, at          23615565000
 test master 2 - Starting Memory Write, at          23615865000
 test master 2 - Starting Memory Write, at          23616165000
 test master 2 - Starting Memory Write, at          23616465000
 test master 1 - Starting Memory Read, at          23616885000
 test master 1 - Starting Memory Read, at          23617215000
 test master 1 - Starting Memory Read, at          23617755000
 test master 1 - Starting Memory Read, at          23618085000
 test master 1 - Starting Memory Read, at          23618625000
 test master 1 - Starting Memory Read, at          23618955000
 test master 2 - Starting Memory Write, at          23620755000
 test master 2 - Starting Memory Write, at          23621895000
 test master 2 - Starting Memory Write, at          23623035000
 test master 2 - Starting Memory Write, at          23624175000
 test master 2 - Starting Memory Write, at          23626455000
 test master 2 - Starting Memory Write, at          23627595000
 test master 2 - Starting Memory Write, at          23628735000
 test master 2 - Starting Memory Write, at          23629875000
 test master 2 - Starting Memory Write, at          23632155000
 test master 2 - Starting Memory Write, at          23634315000
 test master 2 - Starting Memory Write, at          23636475000
 test master 2 - Starting Memory Write, at          23638635000
 test master 2 - Starting Memory Write, at          23641935000
 test master 2 - Starting Memory Write, at          23644335000
 test master 2 - Starting Memory Write, at          23646735000
 test master 2 - Starting Memory Write, at          23649135000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          23653665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23653695000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23655795000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          23656095000
 test master 2 - Starting Memory Read, at          23656275000
 test master 2 - Starting Memory Read, at          23656455000
 test master 2 - Starting Memory Read, at          23656695000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23658375000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          23658855000
 test master 2 - Starting Memory Read, at          23659035000
 test master 2 - Starting Memory Read, at          23659455000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23660895000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23661585000
 test master 2 - Starting Memory Read Line Multiple, at          23661765000
 test master 2 - Starting Memory Read Line Multiple, at          23661945000
 test master 2 - Starting Memory Read Line Multiple, at          23662125000
 test master 2 - Starting Memory Read Line Multiple, at          23662425000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23664435000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23676915000
 test master 2 - Starting Memory Read Line Multiple, at          23677095000
 test master 2 - Starting Memory Read Line Multiple, at          23677275000
 test master 2 - Starting Memory Read Line Multiple, at          23677455000
 test master 2 - Starting Memory Read Line Multiple, at          23677785000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23678685000
 test master 2 - Starting Memory Read Line Multiple, at          23678865000
 test master 2 - Starting Memory Read Line Multiple, at          23679045000
 test master 2 - Starting Memory Read Line Multiple, at          23679225000
 test master 2 - Starting Memory Read Line Multiple, at          23679525000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23680425000
 test master 2 - Starting Memory Read Line Multiple, at          23680605000
 test master 2 - Starting Memory Read Line Multiple, at          23680785000
 test master 2 - Starting Memory Read Line Multiple, at          23680965000
 test master 2 - Starting Memory Read Line Multiple, at          23681265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23682165000
 test master 2 - Starting Memory Read Line Multiple, at          23682345000
 test master 2 - Starting Memory Read Line Multiple, at          23682525000
 test master 2 - Starting Memory Read Line Multiple, at          23682705000
 test master 2 - Starting Memory Read Line Multiple, at          23683005000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23683905000
 test master 2 - Starting Memory Read Line Multiple, at          23684085000
 test master 2 - Starting Memory Read Line Multiple, at          23684265000
 test master 2 - Starting Memory Read Line Multiple, at          23684445000
 test master 2 - Starting Memory Read Line Multiple, at          23684745000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23685645000
 test master 2 - Starting Memory Read Line Multiple, at          23685825000
 test master 2 - Starting Memory Read Line Multiple, at          23686005000
 test master 2 - Starting Memory Read Line Multiple, at          23686185000
 test master 2 - Starting Memory Read Line Multiple, at          23686485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23687385000
 test master 2 - Starting Memory Read Line Multiple, at          23687565000
 test master 2 - Starting Memory Read Line Multiple, at          23687745000
 test master 2 - Starting Memory Read Line Multiple, at          23687925000
 test master 2 - Starting Memory Read Line Multiple, at          23688225000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          23689125000
 test master 2 - Starting Memory Read Line Multiple, at          23689305000
 test master 2 - Starting Memory Read Line Multiple, at          23689485000
 test master 2 - Starting Memory Read Line Multiple, at          23689665000
 test master 2 - Starting Memory Read Line Multiple, at          23689965000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          23690865000
 test master 2 - Starting Memory Read Line, at          23691045000
 test master 2 - Starting Memory Read Line, at          23691225000
 test master 2 - Starting Memory Read Line, at          23691465000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          23692005000
 test master 2 - Starting Memory Read Line, at          23692185000
 test master 2 - Starting Memory Read Line, at          23692605000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23693775000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23695395000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23698395000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          23700375000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          23705685000
 test master 2 - Starting Memory Write, at          23705985000
 test master 2 - Starting Memory Write, at          23706285000
 test master 2 - Starting Memory Write, at          23706585000
 test master 2 - Starting Memory Write, at          23706885000
 test master 1 - Starting Memory Read, at          23707305000
 test master 1 - Starting Memory Read, at          23707635000
 test master 1 - Starting Memory Read, at          23708175000
 test master 1 - Starting Memory Read, at          23708505000
 test master 1 - Starting Memory Read, at          23709045000
 test master 1 - Starting Memory Read, at          23709375000
 test master 2 - Starting Memory Write, at          23710665000
 test master 2 - Starting Memory Write, at          23710965000
 test master 2 - Starting Memory Write, at          23711265000
 test master 2 - Starting Memory Write, at          23711565000
 test master 2 - Starting Memory Write, at          23711865000
 test master 1 - Starting Memory Read, at          23712285000
 test master 1 - Starting Memory Read, at          23712615000
 test master 1 - Starting Memory Read, at          23713155000
 test master 1 - Starting Memory Read, at          23713485000
 test master 1 - Starting Memory Read, at          23714025000
 test master 1 - Starting Memory Read, at          23714355000
 test master 2 - Starting Memory Write, at          23716155000
 test master 2 - Starting Memory Write, at          23717295000
 test master 2 - Starting Memory Write, at          23718435000
 test master 2 - Starting Memory Write, at          23719575000
 test master 2 - Starting Memory Write, at          23721855000
 test master 2 - Starting Memory Write, at          23722995000
 test master 2 - Starting Memory Write, at          23724135000
 test master 2 - Starting Memory Write, at          23725275000
 test master 2 - Starting Memory Write, at          23727555000
 test master 2 - Starting Memory Write, at          23729715000
 test master 2 - Starting Memory Write, at          23731875000
 test master 2 - Starting Memory Write, at          23734035000
 test master 2 - Starting Memory Write, at          23737335000
 test master 2 - Starting Memory Write, at          23739735000
 test master 2 - Starting Memory Write, at          23742135000
 test master 2 - Starting Memory Write, at          23744535000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          23749065000
*** monitor - CBE Bus Changed when TRDY Desserted, at          23749095000
 test master 1 - Starting Memory Read, at          23751195000
 test master 1 - Starting Memory Read, at          23751555000
 test master 1 - Starting Memory Read, at          23752785000
 test master 1 - Starting Memory Read, at          23753145000
 test master 1 - Starting Memory Read Line, at          23754405000
 test master 1 - Starting Memory Read Line, at          23754765000
 test master 1 - Starting Memory Read Line, at          23756025000
 test master 1 - Starting Memory Read Line, at          23756445000
 test master 1 - Starting Memory Read Line, at          23757765000
 test master 1 - Starting Memory Read Line, at          23758365000
 test master 1 - Starting Memory Read Line, at          23759925000
 test master 1 - Starting Memory Read Line, at          23760525000
 test master 1 - Starting Memory Read Line Multiple, at          23762085000
 test master 1 - Starting Memory Read Line Multiple, at          23762925000
 test master 1 - Starting Memory Read Line Multiple, at          23764845000
 test master 1 - Starting Memory Read Line Multiple, at          23765685000
 test master 1 - Starting Memory Read Line, at          23767605000
 test master 1 - Starting Memory Read Line, at          23768205000
 test master 1 - Starting Memory Read, at          23770695000
 test master 1 - Starting Memory Read, at          23771055000
 test target 1 - Starting Config Write, at          23774325000
 test master 1 - Starting Memory Write, at          23774835000
 test master 1 - Starting Memory Write, at          23782275000
 test master 1 - Starting Memory Write, at          23787315000
 test master 1 - Starting Memory Write, at          23794275000
 test master 1 - Starting Memory Write, at          23799195000
 test master 1 - Starting Memory Read Line, at          23806635000
 test master 1 - Starting Memory Write, at          23812095000
 test master 1 - Starting Memory Read Line, at          23819535000
 test target 1 - Starting Config Write, at          23826645000
 test master 1 - Starting Memory Write, at          23827155000
 test master 1 - Starting Memory Write, at          23827275000
 test master 1 - Starting Memory Write, at          23827575000
 test master 1 - Starting Memory Read, at          23827695000
 test master 1 - Starting Memory Write, at          23828055000
 test master 1 - Starting Memory Read, at          23828175000
 test master 1 - Starting Memory Write, at          23829795000
 test master 1 - Starting Memory Write, at          23842275000
 test master 2 - Starting Memory Read Line, at          23854875000
 test master 2 - Starting Memory Read Line, at          23855445000
 test master 2 - Starting Memory Read Line, at          23856015000
 test master 2 - Starting Memory Read Line, at          23856585000
 test master 1 - Starting Memory Write, at          23857245000
 test master 1 - Starting Memory Write, at          23857545000
 test master 1 - Starting Memory Write, at          23857875000
 test master 2 - Starting Memory Read Line, at          23858325000
 test master 2 - Starting Memory Read Line, at          23858685000
 test master 2 - Starting Memory Read Line, at          23858985000
 test master 2 - Starting Memory Read Line, at          23859345000
 test master 2 - Starting Memory Read Line Multiple, at          23859675000
 test master 2 - Starting Memory Read Line Multiple, at          23860035000
 test master 1 - Starting Memory Write, at          23861955000
 test master 1 - Starting Memory Write, at          23862255000
 test master 2 - Starting Memory Read, at          23862705000
 test master 2 - Starting Memory Read, at          23863065000
 test master 2 - Starting Memory Read, at          23863365000
 test master 2 - Starting Memory Read, at          23863725000
 test master 1 - Starting Memory Write, at          23865375000
 test master 1 - Starting Memory Read, at          23865555000
 test master 1 - Starting Memory Write, at          23865735000
 test master 1 - Starting Memory Read, at          23865945000
 test master 1 - Starting Memory Write, at          23866155000
 test master 1 - Starting Memory Read, at          23866335000
 test master 1 - Starting Memory Read, at          23866545000
 test master 1 - Starting Memory Write, at          23866755000
 test master 1 - Starting Memory Write, at          23866935000
 test master 1 - Starting Memory Read, at          23867115000
 test master 1 - Starting Memory Write, at          23867295000
 test master 1 - Starting Memory Write, at          23867505000
 test master 1 - Starting Memory Write, at          23867715000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          23872125000
 test target 1 - Starting Memory Write, at          23872365000
 test master 1 - Starting Memory Write, at          23872575000
 test target 1 - Starting Memory Write, at          23872755000
 test target 1 - Starting Memory Write, at          23872995000
 test target 1 - Starting Memory Write, at          23873235000
 test master 1 - Starting Memory Write, at          23873565000
 test target 1 - Starting Memory Write, at          23874135000
 test target 1 - Starting Memory Write, at          23874795000
 test target 1 - Starting Memory Write, at          23875065000
 test master 1 - Starting Memory Write, at          23875305000
 test target 1 - Starting Memory Write, at          23875725000
 test target 1 - Starting Memory Write, at          23875995000
 test target 1 - Starting Memory Write, at          23876265000
 test master 1 - Starting Memory Write, at          23876835000
 test target 1 - Starting Memory Write, at          23877795000
 test target 1 - Starting Memory Write, at          23878845000
 test target 1 - Starting Memory Write, at          23879085000
 test master 1 - Starting Memory Read, at          23879295000
 test target 1 - Starting Memory Write, at          23879475000
 test master 1 - Starting Memory Read, at          23879685000
 test target 1 - Starting Memory Write, at          23879865000
 test master 1 - Starting Memory Read, at          23880075000
 test target 1 - Starting Memory Write, at          23880255000
 test master 1 - Starting Memory Read, at          23880465000
 test target 1 - Starting Memory Write, at          23880645000
 test master 1 - Starting Memory Read, at          23880855000
 test target 1 - Starting Memory Write, at          23881035000
 test master 1 - Starting Memory Write, at          23881245000
 test target 1 - Starting Memory Write, at          23881425000
 test target 1 - Starting Memory Write, at          23881665000
 test target 1 - Starting Memory Write, at          23881905000
 test target 1 - Starting Memory Read, at          23882205000
 test master 1 - Starting Memory Write, at          23882535000
 test master 1 - Starting Memory Read, at          23882775000
 test target 1 - Starting Memory Write, at          23883285000
 test master 1 - Starting Memory Write, at          23883675000
 test target 1 - Starting Memory Read, at          23884125000
 test target 1 - Starting Memory Write, at          23884935000
 test master 1 - Starting Memory Read, at          23885265000
 test master 1 - Starting Memory Write, at          23885655000
 test master 1 - Starting Memory Write, at          23886015000
 test master 1 - Starting Memory Read, at          23886315000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          23888985000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          23890095000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          23916225000
 test target 1 - Starting Config Write, at          23917095000
 test target 1 - Starting Config Write, at          23917965000
 test target 2 - Starting Config Write, at          23918865000
 test target 2 - Starting Config Write, at          23919735000
 test target 2 - Starting Config Write, at          23920605000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          23922585000
 test target 1 - Starting Memory Read, at          23922795000
 test target 1 - Starting Memory Write, at          23923395000
 test target 1 - Starting Memory Read, at          23923605000
 test target 1 - Starting Memory Write, at          23924595000
 test target 1 - Starting Memory Read, at          23925675000
 test target 1 - Starting Memory Read, at          23926245000
 test target 1 - Starting Memory Read, at          23926785000
 test target 1 - Starting Memory Read, at          23927325000
 test target 1 - Starting Memory Read, at          23928135000
 test target 1 - Starting Memory Read, at          23929245000
 test target 1 - Starting Memory Read, at          23930115000
 test target 1 - Starting Memory Read, at          23931225000
 test target 1 - Starting Memory Read, at          23932095000
 test target 1 - Starting Memory Read, at          23934225000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          23941215000
 test target 1 - Starting Memory Read, at          23941425000
 test target 1 - Starting Memory Write, at          23942025000
 test target 1 - Starting Memory Read, at          23942235000
 test target 1 - Starting Memory Write, at          23943255000
 test target 1 - Starting Memory Read, at          23944335000
 test target 1 - Starting Memory Read, at          23944905000
 test target 1 - Starting Memory Read, at          23945445000
 test target 1 - Starting Memory Read, at          23945985000
 test target 1 - Starting Memory Read, at          23946795000
 test target 1 - Starting Memory Read, at          23947905000
 test target 1 - Starting Memory Read, at          23948775000
 test target 1 - Starting Memory Read, at          23949885000
 test target 1 - Starting Memory Read, at          23950755000
 test target 1 - Starting Memory Read, at          23952885000
 test target 1 - Starting Memory Write, at          23959875000
 test target 1 - Starting Memory Read, at          23960085000
 test target 1 - Starting Memory Write, at          23960685000
 test target 1 - Starting Memory Read, at          23960895000
 test target 1 - Starting Memory Write, at          23961915000
 test target 1 - Starting Memory Read, at          23962995000
 test target 1 - Starting Memory Read, at          23963565000
 test target 1 - Starting Memory Read, at          23964105000
 test target 1 - Starting Memory Read, at          23964645000
 test target 1 - Starting Memory Read, at          23965455000
 test target 1 - Starting Memory Read, at          23966565000
 test target 1 - Starting Memory Read, at          23967435000
 test target 1 - Starting Memory Read, at          23968545000
 test target 1 - Starting Memory Read, at          23969415000
 test target 1 - Starting Memory Read, at          23971545000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          23984925000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          23991645000
 test target 1 - Starting Memory Write, at          23992455000
 test target 1 - Starting Memory Read, at          23992845000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          23994165000
 test target 1 - Starting Config Write, at          23996205000
 test target 1 - Starting Memory Read, at          23996805000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          23998305000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          24000525000
 test target 1 - Starting Memory Write, at          24001695000
 test target 1 - Starting Memory Write, at          24001935000
 test target 1 - Starting Memory Read, at          24002145000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          24004575000
 test target 1 - Starting Memory Write, at          24007815000
 test target 1 - Starting Memory Write, at          24008145000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          24012375000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          24014355000
 test target 1 - Starting Memory Read, at          24015795000
 test target 1 - Starting Memory Read, at          24016845000
 test target 1 - Starting Memory Read, at          24018555000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          24024945000
 test target 2 - Starting Config Write, at          24025845000
 test target 1 - Starting Memory Write, at          24026475000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          24026595000
 test target 1 - Starting Memory Write, at          24027705000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          24027825000
 test target 1 - Starting Memory Write, at          24028905000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          24030375000
 test target 1 - Starting Memory Read, at          24032595000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          24032715000
 test target 1 - Starting Memory Read, at          24034995000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          24036705000
 test master 2 - Starting Memory Write, at          24036705000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          24036765000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24037635000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24037665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24037965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24037995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24038955000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24038985000
 test target 1 - Starting Memory Write, at          24040875000
 test master 2 - Starting Memory Write, at          24040875000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24042675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24042705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24044475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24044505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24046275000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24046305000
 test target 1 - Starting Memory Write, at          24048465000
 test master 2 - Starting Memory Write, at          24048465000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          24048525000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24050235000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24050265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24050565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24050595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24051555000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24051585000
 test target 1 - Starting Memory Write, at          24052815000
 test master 2 - Starting Memory Write, at          24052815000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          24055905000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          24057615000
 test master 1 - Starting Memory Read, at          24057945000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          24058095000
 test target 1 - Starting Config Write, at          24060825000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          24063525000
 test target 1 - Starting Memory Write, at          24063675000
 test target 1 - Starting Memory Write, at          24063825000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          24064335000
 test target 1 - Starting Memory Write, at          24064515000
 test target 1 - Starting Memory Write, at          24064695000
 test target 1 - Starting Memory Write, at          24065175000
 test target 1 - Starting Memory Write, at          24065415000
 test target 1 - Starting Memory Write, at          24065895000
 test target 1 - Starting Memory Write, at          24066555000
 test target 1 - Starting Memory Write, at          24066735000
 test target 1 - Starting Memory Write, at          24067395000
 test target 1 - Starting Memory Write, at          24067665000
 test target 1 - Starting Memory Write, at          24068235000
 test target 1 - Starting Memory Write, at          24073755000
 test target 1 - Starting Memory Write, at          24073935000
 test target 1 - Starting Memory Write, at          24074115000
 test target 1 - Starting Memory Write, at          24074385000
 test target 1 - Starting Memory Write, at          24074655000
 test target 1 - Starting Memory Read, at          24079995000
 test target 1 - Starting Memory Read, at          24081015000
 test target 1 - Starting Memory Read, at          24082065000
 test target 1 - Starting Memory Read, at          24083145000
 test target 1 - Starting Memory Read, at          24084195000
 test target 1 - Starting Memory Read, at          24085245000
 test target 1 - Starting Memory Read, at          24086325000
 test target 1 - Starting Memory Read, at          24087375000
 test target 1 - Starting Memory Read, at          24088425000
 test target 1 - Starting Memory Read, at          24089505000
 test target 1 - Starting Memory Read, at          24090555000
 test target 1 - Starting Memory Read, at          24091605000
 test target 1 - Starting Memory Read, at          24092685000
 test target 1 - Starting Memory Read, at          24093735000
 test target 1 - Starting Memory Read, at          24094785000
 test target 1 - Starting Memory Read, at          24095865000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          24096795000
 test target 1 - Starting Memory Read, at          24096945000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          24098805000
 test target 1 - Starting Memory Read, at          24100365000
 test target 1 - Starting Memory Read, at          24100935000
 test target 1 - Starting Memory Read, at          24101625000
 test target 1 - Starting Memory Read, at          24102405000
 test target 1 - Starting Memory Read, at          24103095000
 test target 1 - Starting Memory Read, at          24104295000
 test target 1 - Starting Memory Read, at          24105405000
 test target 1 - Starting Memory Read, at          24106275000
 test target 1 - Starting Memory Read, at          24109305000
 test target 1 - Starting Memory Read, at          24111675000
 test target 1 - Starting Memory Read, at          24112515000
 test target 1 - Starting Memory Read, at          24113355000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          24114645000
 test master 1 - Starting Memory Write, at          24114945000
 test target 1 - Starting Memory Write, at          24114945000
 test target 1 - Starting Memory Write, at          24115095000
 test target 1 - Starting Memory Read, at          24115485000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          24117765000
 test master 1 - Starting Memory Write, at          24118065000
 test target 1 - Starting Memory Write, at          24118065000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          24123285000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          24124395000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          24150525000
 test target 1 - Starting Config Write, at          24151605000
 test target 1 - Starting Config Write, at          24152505000
 test target 2 - Starting Config Write, at          24153585000
 test target 2 - Starting Config Write, at          24154485000
 test target 2 - Starting Config Write, at          24155565000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          24157545000
 test target 1 - Starting Memory Read, at          24157785000
 test target 1 - Starting Memory Write, at          24158535000
 test target 1 - Starting Memory Read, at          24158775000
 test target 1 - Starting Memory Write, at          24159975000
 test target 1 - Starting Memory Read, at          24161115000
 test target 1 - Starting Memory Read, at          24161685000
 test target 1 - Starting Memory Read, at          24162345000
 test target 1 - Starting Memory Read, at          24162885000
 test target 1 - Starting Memory Read, at          24163695000
 test target 1 - Starting Memory Read, at          24164805000
 test target 1 - Starting Memory Read, at          24165675000
 test target 1 - Starting Memory Read, at          24166785000
 test target 1 - Starting Memory Read, at          24167655000
 test target 1 - Starting Memory Read, at          24169785000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          24176955000
 test target 1 - Starting Memory Read, at          24177195000
 test target 1 - Starting Memory Write, at          24177975000
 test target 1 - Starting Memory Read, at          24178215000
 test target 1 - Starting Memory Write, at          24179385000
 test target 1 - Starting Memory Read, at          24180495000
 test target 1 - Starting Memory Read, at          24181065000
 test target 1 - Starting Memory Read, at          24181605000
 test target 1 - Starting Memory Read, at          24182145000
 test target 1 - Starting Memory Read, at          24182955000
 test target 1 - Starting Memory Read, at          24184065000
 test target 1 - Starting Memory Read, at          24184935000
 test target 1 - Starting Memory Read, at          24186045000
 test target 1 - Starting Memory Read, at          24186915000
 test target 1 - Starting Memory Read, at          24189045000
 test target 1 - Starting Memory Write, at          24196215000
 test target 1 - Starting Memory Read, at          24196455000
 test target 1 - Starting Memory Write, at          24197235000
 test target 1 - Starting Memory Read, at          24197475000
 test target 1 - Starting Memory Write, at          24198645000
 test target 1 - Starting Memory Read, at          24199755000
 test target 1 - Starting Memory Read, at          24200325000
 test target 1 - Starting Memory Read, at          24200865000
 test target 1 - Starting Memory Read, at          24201405000
 test target 1 - Starting Memory Read, at          24202215000
 test target 1 - Starting Memory Read, at          24203325000
 test target 1 - Starting Memory Read, at          24204195000
 test target 1 - Starting Memory Read, at          24205305000
 test target 1 - Starting Memory Read, at          24206175000
 test target 1 - Starting Memory Read, at          24208305000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          24221865000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          24228585000
 test target 1 - Starting Memory Write, at          24229395000
 test target 1 - Starting Memory Read, at          24229815000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          24231105000
 test target 1 - Starting Config Write, at          24233385000
 test target 1 - Starting Memory Read, at          24234195000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          24235725000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          24237945000
 test target 1 - Starting Memory Write, at          24239115000
 test target 1 - Starting Memory Write, at          24239385000
 test target 1 - Starting Memory Read, at          24239625000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          24242235000
 test target 1 - Starting Memory Write, at          24245475000
 test target 1 - Starting Memory Write, at          24245835000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          24250095000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          24252075000
 test target 1 - Starting Memory Read, at          24253515000
 test target 1 - Starting Memory Read, at          24254565000
 test target 1 - Starting Memory Read, at          24256275000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          24262665000
 test target 2 - Starting Config Write, at          24263565000
 test target 1 - Starting Memory Write, at          24264405000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          24264555000
 test target 1 - Starting Memory Write, at          24265665000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          24265815000
 test target 1 - Starting Memory Write, at          24266925000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          24268455000
 test target 1 - Starting Memory Read, at          24270675000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          24270825000
 test target 1 - Starting Memory Read, at          24273075000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          24274785000
 test master 2 - Starting Memory Write, at          24274785000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          24274845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24275715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24275745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24276045000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24276075000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24277035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24277065000
 test target 1 - Starting Memory Write, at          24278955000
 test master 2 - Starting Memory Write, at          24278955000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24280755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24280785000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24282555000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24282585000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24284355000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24284385000
 test target 1 - Starting Memory Write, at          24286545000
 test master 2 - Starting Memory Write, at          24286545000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          24286605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24288315000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24288345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24288645000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24288675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24289635000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24289665000
 test target 1 - Starting Memory Write, at          24290895000
 test master 2 - Starting Memory Write, at          24290895000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          24294045000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          24295755000
 test master 1 - Starting Memory Read, at          24296085000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          24296235000
 test target 1 - Starting Config Write, at          24298965000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          24301665000
 test target 1 - Starting Memory Write, at          24301845000
 test target 1 - Starting Memory Write, at          24302025000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          24302535000
 test target 1 - Starting Memory Write, at          24302745000
 test target 1 - Starting Memory Write, at          24302955000
 test target 1 - Starting Memory Write, at          24303495000
 test target 1 - Starting Memory Write, at          24303765000
 test target 1 - Starting Memory Write, at          24304275000
 test target 1 - Starting Memory Write, at          24304965000
 test target 1 - Starting Memory Write, at          24305175000
 test target 1 - Starting Memory Write, at          24305865000
 test target 1 - Starting Memory Write, at          24306165000
 test target 1 - Starting Memory Write, at          24306765000
 test target 1 - Starting Memory Write, at          24312315000
 test target 1 - Starting Memory Write, at          24312525000
 test target 1 - Starting Memory Write, at          24312735000
 test target 1 - Starting Memory Write, at          24313035000
 test target 1 - Starting Memory Write, at          24313335000
 test target 1 - Starting Memory Read, at          24318705000
 test target 1 - Starting Memory Read, at          24319845000
 test target 1 - Starting Memory Read, at          24320925000
 test target 1 - Starting Memory Read, at          24321975000
 test target 1 - Starting Memory Read, at          24323025000
 test target 1 - Starting Memory Read, at          24324105000
 test target 1 - Starting Memory Read, at          24325155000
 test target 1 - Starting Memory Read, at          24326205000
 test target 1 - Starting Memory Read, at          24327285000
 test target 1 - Starting Memory Read, at          24328335000
 test target 1 - Starting Memory Read, at          24329385000
 test target 1 - Starting Memory Read, at          24330465000
 test target 1 - Starting Memory Read, at          24331515000
 test target 1 - Starting Memory Read, at          24332565000
 test target 1 - Starting Memory Read, at          24333645000
 test target 1 - Starting Memory Read, at          24334695000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          24335625000
 test target 1 - Starting Memory Read, at          24335805000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          24337635000
 test target 1 - Starting Memory Read, at          24339225000
 test target 1 - Starting Memory Read, at          24339975000
 test target 1 - Starting Memory Read, at          24340665000
 test target 1 - Starting Memory Read, at          24341445000
 test target 1 - Starting Memory Read, at          24342135000
 test target 1 - Starting Memory Read, at          24343335000
 test target 1 - Starting Memory Read, at          24344445000
 test target 1 - Starting Memory Read, at          24345315000
 test target 1 - Starting Memory Read, at          24348345000
 test target 1 - Starting Memory Read, at          24350715000
 test target 1 - Starting Memory Read, at          24351555000
 test target 1 - Starting Memory Read, at          24352395000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          24353685000
 test master 1 - Starting Memory Write, at          24354015000
 test target 1 - Starting Memory Write, at          24354015000
 test target 1 - Starting Memory Write, at          24354195000
 test target 1 - Starting Memory Read, at          24354615000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          24356955000
 test master 1 - Starting Memory Write, at          24357285000
 test target 1 - Starting Memory Write, at          24357285000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          24362505000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          24363615000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          24389745000
 test target 1 - Starting Config Write, at          24390825000
 test target 1 - Starting Config Write, at          24391935000
 test target 2 - Starting Config Write, at          24393045000
 test target 2 - Starting Config Write, at          24394125000
 test target 2 - Starting Config Write, at          24395235000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          24397425000
 test target 1 - Starting Memory Read, at          24397695000
 test target 1 - Starting Memory Write, at          24398415000
 test target 1 - Starting Memory Read, at          24398685000
 test target 1 - Starting Memory Write, at          24399855000
 test target 1 - Starting Memory Read, at          24400995000
 test target 1 - Starting Memory Read, at          24401565000
 test target 1 - Starting Memory Read, at          24402255000
 test target 1 - Starting Memory Read, at          24402945000
 test target 1 - Starting Memory Read, at          24403875000
 test target 1 - Starting Memory Read, at          24404985000
 test target 1 - Starting Memory Read, at          24406035000
 test target 1 - Starting Memory Read, at          24407145000
 test target 1 - Starting Memory Read, at          24408195000
 test target 1 - Starting Memory Read, at          24410325000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          24417495000
 test target 1 - Starting Memory Read, at          24417765000
 test target 1 - Starting Memory Write, at          24418515000
 test target 1 - Starting Memory Read, at          24418785000
 test target 1 - Starting Memory Write, at          24419925000
 test target 1 - Starting Memory Read, at          24421095000
 test target 1 - Starting Memory Read, at          24421785000
 test target 1 - Starting Memory Read, at          24422475000
 test target 1 - Starting Memory Read, at          24423165000
 test target 1 - Starting Memory Read, at          24424095000
 test target 1 - Starting Memory Read, at          24425205000
 test target 1 - Starting Memory Read, at          24426255000
 test target 1 - Starting Memory Read, at          24427365000
 test target 1 - Starting Memory Read, at          24428415000
 test target 1 - Starting Memory Read, at          24430545000
 test target 1 - Starting Memory Write, at          24437715000
 test target 1 - Starting Memory Read, at          24437985000
 test target 1 - Starting Memory Write, at          24438735000
 test target 1 - Starting Memory Read, at          24439005000
 test target 1 - Starting Memory Write, at          24440145000
 test target 1 - Starting Memory Read, at          24441315000
 test target 1 - Starting Memory Read, at          24442005000
 test target 1 - Starting Memory Read, at          24442695000
 test target 1 - Starting Memory Read, at          24443385000
 test target 1 - Starting Memory Read, at          24444315000
 test target 1 - Starting Memory Read, at          24445425000
 test target 1 - Starting Memory Read, at          24446475000
 test target 1 - Starting Memory Read, at          24447585000
 test target 1 - Starting Memory Read, at          24448635000
 test target 1 - Starting Memory Read, at          24450765000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          24464325000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          24471285000
 test target 1 - Starting Memory Write, at          24472335000
 test target 1 - Starting Memory Read, at          24472785000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          24474165000
 test target 1 - Starting Config Write, at          24476445000
 test target 1 - Starting Memory Read, at          24477255000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          24478965000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          24481305000
 test target 1 - Starting Memory Write, at          24482715000
 test target 1 - Starting Memory Write, at          24483015000
 test target 1 - Starting Memory Read, at          24483285000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          24485835000
 test target 1 - Starting Memory Write, at          24489135000
 test target 1 - Starting Memory Write, at          24489525000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          24493815000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          24496035000
 test target 1 - Starting Memory Read, at          24497475000
 test target 1 - Starting Memory Read, at          24498525000
 test target 1 - Starting Memory Read, at          24500355000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          24506745000
 test target 2 - Starting Config Write, at          24507855000
 test target 1 - Starting Memory Write, at          24508695000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          24508875000
 test target 1 - Starting Memory Write, at          24509985000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          24510165000
 test target 1 - Starting Memory Write, at          24511245000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          24512775000
 test target 1 - Starting Memory Read, at          24515235000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          24515415000
 test target 1 - Starting Memory Read, at          24517815000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          24519765000
 test master 2 - Starting Memory Write, at          24519765000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          24519825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24520755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24520785000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24521085000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24521115000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24522075000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24522105000
 test target 1 - Starting Memory Write, at          24523995000
 test master 2 - Starting Memory Write, at          24523995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24525855000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24525885000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24527655000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24527685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24529455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24529485000
 test target 1 - Starting Memory Write, at          24531645000
 test master 2 - Starting Memory Write, at          24531645000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          24531705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24533475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24533505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24533805000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24533835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24534795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24534825000
 test target 1 - Starting Memory Write, at          24536055000
 test master 2 - Starting Memory Write, at          24536055000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          24539205000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          24540915000
 test master 1 - Starting Memory Read, at          24541245000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          24541395000
 test target 1 - Starting Config Write, at          24544125000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          24546825000
 test target 1 - Starting Memory Write, at          24547035000
 test target 1 - Starting Memory Write, at          24547245000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          24547815000
 test target 1 - Starting Memory Write, at          24548055000
 test target 1 - Starting Memory Write, at          24548295000
 test target 1 - Starting Memory Write, at          24548835000
 test target 1 - Starting Memory Write, at          24549135000
 test target 1 - Starting Memory Write, at          24549675000
 test target 1 - Starting Memory Write, at          24550395000
 test target 1 - Starting Memory Write, at          24550635000
 test target 1 - Starting Memory Write, at          24551355000
 test target 1 - Starting Memory Write, at          24551685000
 test target 1 - Starting Memory Write, at          24552315000
 test target 1 - Starting Memory Write, at          24557895000
 test target 1 - Starting Memory Write, at          24558135000
 test target 1 - Starting Memory Write, at          24558375000
 test target 1 - Starting Memory Write, at          24558705000
 test target 1 - Starting Memory Write, at          24559035000
 test target 1 - Starting Memory Read, at          24564435000
 test target 1 - Starting Memory Read, at          24565575000
 test target 1 - Starting Memory Read, at          24566775000
 test target 1 - Starting Memory Read, at          24567975000
 test target 1 - Starting Memory Read, at          24569175000
 test target 1 - Starting Memory Read, at          24570375000
 test target 1 - Starting Memory Read, at          24571575000
 test target 1 - Starting Memory Read, at          24572775000
 test target 1 - Starting Memory Read, at          24573975000
 test target 1 - Starting Memory Read, at          24575175000
 test target 1 - Starting Memory Read, at          24576375000
 test target 1 - Starting Memory Read, at          24577575000
 test target 1 - Starting Memory Read, at          24578775000
 test target 1 - Starting Memory Read, at          24579975000
 test target 1 - Starting Memory Read, at          24581175000
 test target 1 - Starting Memory Read, at          24582375000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          24583455000
 test target 1 - Starting Memory Read, at          24583665000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          24585675000
 test target 1 - Starting Memory Read, at          24587295000
 test target 1 - Starting Memory Read, at          24587985000
 test target 1 - Starting Memory Read, at          24588705000
 test target 1 - Starting Memory Read, at          24589485000
 test target 1 - Starting Memory Read, at          24590355000
 test target 1 - Starting Memory Read, at          24591555000
 test target 1 - Starting Memory Read, at          24592665000
 test target 1 - Starting Memory Read, at          24593715000
 test target 1 - Starting Memory Read, at          24596745000
 test target 1 - Starting Memory Read, at          24599115000
 test target 1 - Starting Memory Read, at          24599955000
 test target 1 - Starting Memory Read, at          24600795000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          24602085000
 test master 1 - Starting Memory Write, at          24602355000
 test target 1 - Starting Memory Write, at          24602355000
 test target 1 - Starting Memory Write, at          24602565000
 test target 1 - Starting Memory Read, at          24603105000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          24605445000
 test master 1 - Starting Memory Write, at          24605715000
 test target 1 - Starting Memory Write, at          24605715000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          24610845000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          24611955000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          24638085000
 test target 1 - Starting Config Write, at          24639165000
 test target 1 - Starting Config Write, at          24640275000
 test target 2 - Starting Config Write, at          24641385000
 test target 2 - Starting Config Write, at          24642465000
 test target 2 - Starting Config Write, at          24643575000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          24645765000
 test target 1 - Starting Memory Read, at          24646065000
 test target 1 - Starting Memory Write, at          24646755000
 test target 1 - Starting Memory Read, at          24647055000
 test target 1 - Starting Memory Write, at          24648195000
 test target 1 - Starting Memory Read, at          24649395000
 test target 1 - Starting Memory Read, at          24650085000
 test target 1 - Starting Memory Read, at          24650775000
 test target 1 - Starting Memory Read, at          24651465000
 test target 1 - Starting Memory Read, at          24652395000
 test target 1 - Starting Memory Read, at          24653655000
 test target 1 - Starting Memory Read, at          24654735000
 test target 1 - Starting Memory Read, at          24655965000
 test target 1 - Starting Memory Read, at          24657015000
 test target 1 - Starting Memory Read, at          24659265000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          24666495000
 test target 1 - Starting Memory Read, at          24666795000
 test target 1 - Starting Memory Write, at          24667515000
 test target 1 - Starting Memory Read, at          24667815000
 test target 1 - Starting Memory Write, at          24668925000
 test target 1 - Starting Memory Read, at          24670095000
 test target 1 - Starting Memory Read, at          24670815000
 test target 1 - Starting Memory Read, at          24671505000
 test target 1 - Starting Memory Read, at          24672165000
 test target 1 - Starting Memory Read, at          24673155000
 test target 1 - Starting Memory Read, at          24674385000
 test target 1 - Starting Memory Read, at          24675435000
 test target 1 - Starting Memory Read, at          24676695000
 test target 1 - Starting Memory Read, at          24677775000
 test target 1 - Starting Memory Read, at          24680025000
 test target 1 - Starting Memory Write, at          24687195000
 test target 1 - Starting Memory Read, at          24687495000
 test target 1 - Starting Memory Write, at          24688215000
 test target 1 - Starting Memory Read, at          24688515000
 test target 1 - Starting Memory Write, at          24689625000
 test target 1 - Starting Memory Read, at          24690795000
 test target 1 - Starting Memory Read, at          24691515000
 test target 1 - Starting Memory Read, at          24692205000
 test target 1 - Starting Memory Read, at          24692865000
 test target 1 - Starting Memory Read, at          24693855000
 test target 1 - Starting Memory Read, at          24695085000
 test target 1 - Starting Memory Read, at          24696135000
 test target 1 - Starting Memory Read, at          24697395000
 test target 1 - Starting Memory Read, at          24698475000
 test target 1 - Starting Memory Read, at          24700725000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          24714285000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          24721245000
 test target 1 - Starting Memory Write, at          24722295000
 test target 1 - Starting Memory Read, at          24722775000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          24724125000
 test target 1 - Starting Config Write, at          24726405000
 test target 1 - Starting Memory Read, at          24727215000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          24728925000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          24731265000
 test target 1 - Starting Memory Write, at          24732675000
 test target 1 - Starting Memory Write, at          24733005000
 test target 1 - Starting Memory Read, at          24733305000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          24735975000
 test target 1 - Starting Memory Write, at          24739275000
 test target 1 - Starting Memory Write, at          24739695000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          24744015000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          24746235000
 test target 1 - Starting Memory Read, at          24747675000
 test target 1 - Starting Memory Read, at          24748875000
 test target 1 - Starting Memory Read, at          24750735000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          24757305000
 test target 2 - Starting Config Write, at          24758415000
 test target 1 - Starting Memory Write, at          24759255000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          24759465000
 test target 1 - Starting Memory Write, at          24760545000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          24760755000
 test target 1 - Starting Memory Write, at          24761865000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          24763455000
 test target 1 - Starting Memory Read, at          24765915000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          24766125000
 test target 1 - Starting Memory Read, at          24768495000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          24770445000
 test master 2 - Starting Memory Write, at          24770445000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          24770505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24771435000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24771465000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24771765000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24771795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24772755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24772785000
 test target 1 - Starting Memory Write, at          24774675000
 test master 2 - Starting Memory Write, at          24774675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24776535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24776565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24778335000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24778365000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24780135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24780165000
 test target 1 - Starting Memory Write, at          24782325000
 test master 2 - Starting Memory Write, at          24782325000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          24782385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24784155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24784185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24784485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24784515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24785475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24785505000
 test target 1 - Starting Memory Write, at          24786735000
 test master 2 - Starting Memory Write, at          24786735000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          24789945000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          24791655000
 test master 1 - Starting Memory Read, at          24791985000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          24792135000
 test target 1 - Starting Config Write, at          24794865000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          24797565000
 test target 1 - Starting Memory Write, at          24797805000
 test target 1 - Starting Memory Write, at          24798045000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          24798615000
 test target 1 - Starting Memory Write, at          24798885000
 test target 1 - Starting Memory Write, at          24799155000
 test target 1 - Starting Memory Write, at          24799755000
 test target 1 - Starting Memory Write, at          24800085000
 test target 1 - Starting Memory Write, at          24800655000
 test target 1 - Starting Memory Write, at          24801405000
 test target 1 - Starting Memory Write, at          24801675000
 test target 1 - Starting Memory Write, at          24802425000
 test target 1 - Starting Memory Write, at          24802785000
 test target 1 - Starting Memory Write, at          24803445000
 test target 1 - Starting Memory Write, at          24809055000
 test target 1 - Starting Memory Write, at          24809325000
 test target 1 - Starting Memory Write, at          24809595000
 test target 1 - Starting Memory Write, at          24809955000
 test target 1 - Starting Memory Write, at          24810315000
 test target 1 - Starting Memory Read, at          24815745000
 test target 1 - Starting Memory Read, at          24816885000
 test target 1 - Starting Memory Read, at          24818085000
 test target 1 - Starting Memory Read, at          24819285000
 test target 1 - Starting Memory Read, at          24820485000
 test target 1 - Starting Memory Read, at          24821685000
 test target 1 - Starting Memory Read, at          24822885000
 test target 1 - Starting Memory Read, at          24824085000
 test target 1 - Starting Memory Read, at          24825285000
 test target 1 - Starting Memory Read, at          24826485000
 test target 1 - Starting Memory Read, at          24827685000
 test target 1 - Starting Memory Read, at          24828885000
 test target 1 - Starting Memory Read, at          24830085000
 test target 1 - Starting Memory Read, at          24831285000
 test target 1 - Starting Memory Read, at          24832485000
 test target 1 - Starting Memory Read, at          24833685000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          24834765000
 test target 1 - Starting Memory Read, at          24835005000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          24836955000
 test target 1 - Starting Memory Read, at          24838605000
 test target 1 - Starting Memory Read, at          24839295000
 test target 1 - Starting Memory Read, at          24839985000
 test target 1 - Starting Memory Read, at          24840765000
 test target 1 - Starting Memory Read, at          24841635000
 test target 1 - Starting Memory Read, at          24843015000
 test target 1 - Starting Memory Read, at          24844245000
 test target 1 - Starting Memory Read, at          24845295000
 test target 1 - Starting Memory Read, at          24848325000
 test target 1 - Starting Memory Read, at          24850875000
 test target 1 - Starting Memory Read, at          24851835000
 test target 1 - Starting Memory Read, at          24852855000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          24854265000
 test master 1 - Starting Memory Write, at          24854565000
 test target 1 - Starting Memory Write, at          24854565000
 test target 1 - Starting Memory Write, at          24854805000
 test target 1 - Starting Memory Read, at          24855375000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          24857805000
 test master 1 - Starting Memory Write, at          24858105000
 test target 1 - Starting Memory Write, at          24858105000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24863775000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          24864015000
 test master 2 - Starting Memory Read, at          24864195000
 test master 2 - Starting Memory Read, at          24864375000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24866055000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          24866415000
 test master 2 - Starting Memory Read, at          24866595000
 test master 2 - Starting Memory Read, at          24866775000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24868275000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24868725000
 test master 2 - Starting Memory Read Line Multiple, at          24868905000
 test master 2 - Starting Memory Read Line Multiple, at          24869145000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24871095000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24878055000
 test master 2 - Starting Memory Read Line Multiple, at          24878235000
 test master 2 - Starting Memory Read Line Multiple, at          24878505000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24879225000
 test master 2 - Starting Memory Read Line Multiple, at          24879405000
 test master 2 - Starting Memory Read Line Multiple, at          24879645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24880365000
 test master 2 - Starting Memory Read Line Multiple, at          24880545000
 test master 2 - Starting Memory Read Line Multiple, at          24880785000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24881505000
 test master 2 - Starting Memory Read Line Multiple, at          24881685000
 test master 2 - Starting Memory Read Line Multiple, at          24881925000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24882645000
 test master 2 - Starting Memory Read Line Multiple, at          24882825000
 test master 2 - Starting Memory Read Line Multiple, at          24883065000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24883785000
 test master 2 - Starting Memory Read Line Multiple, at          24883965000
 test master 2 - Starting Memory Read Line Multiple, at          24884205000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24884925000
 test master 2 - Starting Memory Read Line Multiple, at          24885105000
 test master 2 - Starting Memory Read Line Multiple, at          24885345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24886065000
 test master 2 - Starting Memory Read Line Multiple, at          24886245000
 test master 2 - Starting Memory Read Line Multiple, at          24886485000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          24887205000
 test master 2 - Starting Memory Read Line, at          24887385000
 test master 2 - Starting Memory Read Line, at          24887565000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          24888015000
 test master 2 - Starting Memory Read Line, at          24888195000
 test master 2 - Starting Memory Read Line, at          24888375000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24889605000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24891225000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24894225000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24896025000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          24900915000
 test master 2 - Starting Memory Write, at          24901155000
 test master 2 - Starting Memory Write, at          24901395000
 test master 2 - Starting Memory Write, at          24901635000
 test master 2 - Starting Memory Write, at          24901875000
 test master 1 - Starting Memory Read, at          24902235000
 test master 1 - Starting Memory Read, at          24902505000
 test master 1 - Starting Memory Read, at          24903045000
 test master 1 - Starting Memory Read, at          24903315000
 test master 1 - Starting Memory Read, at          24903855000
 test master 1 - Starting Memory Read, at          24904125000
 test master 2 - Starting Memory Write, at          24905475000
 test master 2 - Starting Memory Write, at          24905715000
 test master 2 - Starting Memory Write, at          24905955000
 test master 2 - Starting Memory Write, at          24906195000
 test master 2 - Starting Memory Write, at          24906435000
 test master 1 - Starting Memory Read, at          24906795000
 test master 1 - Starting Memory Read, at          24907065000
 test master 1 - Starting Memory Read, at          24907605000
 test master 1 - Starting Memory Read, at          24907875000
 test master 1 - Starting Memory Read, at          24908415000
 test master 1 - Starting Memory Read, at          24908685000
 test master 2 - Starting Memory Write, at          24910575000
 test master 2 - Starting Memory Write, at          24911685000
 test master 2 - Starting Memory Write, at          24912825000
 test master 2 - Starting Memory Write, at          24913965000
 test master 2 - Starting Memory Write, at          24916335000
 test master 2 - Starting Memory Write, at          24917445000
 test master 2 - Starting Memory Write, at          24918585000
 test master 2 - Starting Memory Write, at          24919725000
 test master 2 - Starting Memory Write, at          24922095000
 test master 2 - Starting Memory Write, at          24924225000
 test master 2 - Starting Memory Write, at          24926385000
 test master 2 - Starting Memory Write, at          24928545000
 test master 2 - Starting Memory Write, at          24931935000
 test master 2 - Starting Memory Write, at          24934335000
 test master 2 - Starting Memory Write, at          24936735000
 test master 2 - Starting Memory Write, at          24939135000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          24943665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          24943695000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24945975000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          24946215000
 test master 2 - Starting Memory Read, at          24946395000
 test master 2 - Starting Memory Read, at          24946575000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24948255000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          24948615000
 test master 2 - Starting Memory Read, at          24948795000
 test master 2 - Starting Memory Read, at          24948975000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24950475000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24950925000
 test master 2 - Starting Memory Read Line Multiple, at          24951105000
 test master 2 - Starting Memory Read Line Multiple, at          24951345000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24953295000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24960255000
 test master 2 - Starting Memory Read Line Multiple, at          24960435000
 test master 2 - Starting Memory Read Line Multiple, at          24960705000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24961425000
 test master 2 - Starting Memory Read Line Multiple, at          24961605000
 test master 2 - Starting Memory Read Line Multiple, at          24961845000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24962565000
 test master 2 - Starting Memory Read Line Multiple, at          24962745000
 test master 2 - Starting Memory Read Line Multiple, at          24962985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24963705000
 test master 2 - Starting Memory Read Line Multiple, at          24963885000
 test master 2 - Starting Memory Read Line Multiple, at          24964125000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24964845000
 test master 2 - Starting Memory Read Line Multiple, at          24965025000
 test master 2 - Starting Memory Read Line Multiple, at          24965265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24965985000
 test master 2 - Starting Memory Read Line Multiple, at          24966165000
 test master 2 - Starting Memory Read Line Multiple, at          24966405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24967125000
 test master 2 - Starting Memory Read Line Multiple, at          24967305000
 test master 2 - Starting Memory Read Line Multiple, at          24967545000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          24968265000
 test master 2 - Starting Memory Read Line Multiple, at          24968445000
 test master 2 - Starting Memory Read Line Multiple, at          24968685000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          24969405000
 test master 2 - Starting Memory Read Line, at          24969585000
 test master 2 - Starting Memory Read Line, at          24969765000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          24970215000
 test master 2 - Starting Memory Read Line, at          24970395000
 test master 2 - Starting Memory Read Line, at          24970575000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24971805000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24973425000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24976425000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          24978225000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          24983115000
 test master 2 - Starting Memory Write, at          24983355000
 test master 2 - Starting Memory Write, at          24983595000
 test master 2 - Starting Memory Write, at          24983835000
 test master 2 - Starting Memory Write, at          24984075000
 test master 1 - Starting Memory Read, at          24984435000
 test master 1 - Starting Memory Read, at          24984705000
 test master 1 - Starting Memory Read, at          24985245000
 test master 1 - Starting Memory Read, at          24985515000
 test master 1 - Starting Memory Read, at          24986055000
 test master 1 - Starting Memory Read, at          24986325000
 test master 2 - Starting Memory Write, at          24987675000
 test master 2 - Starting Memory Write, at          24987915000
 test master 2 - Starting Memory Write, at          24988155000
 test master 2 - Starting Memory Write, at          24988395000
 test master 2 - Starting Memory Write, at          24988635000
 test master 1 - Starting Memory Read, at          24988995000
 test master 1 - Starting Memory Read, at          24989265000
 test master 1 - Starting Memory Read, at          24989805000
 test master 1 - Starting Memory Read, at          24990075000
 test master 1 - Starting Memory Read, at          24990615000
 test master 1 - Starting Memory Read, at          24990885000
 test master 2 - Starting Memory Write, at          24992775000
 test master 2 - Starting Memory Write, at          24993885000
 test master 2 - Starting Memory Write, at          24995025000
 test master 2 - Starting Memory Write, at          24996165000
 test master 2 - Starting Memory Write, at          24998535000
 test master 2 - Starting Memory Write, at          24999645000
 test master 2 - Starting Memory Write, at          25000785000
 test master 2 - Starting Memory Write, at          25001925000
 test master 2 - Starting Memory Write, at          25004295000
 test master 2 - Starting Memory Write, at          25006425000
 test master 2 - Starting Memory Write, at          25008585000
 test master 2 - Starting Memory Write, at          25010745000
 test master 2 - Starting Memory Write, at          25014135000
 test master 2 - Starting Memory Write, at          25016535000
 test master 2 - Starting Memory Write, at          25018935000
 test master 2 - Starting Memory Write, at          25021335000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          25025865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25025895000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25028175000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          25028415000
 test master 2 - Starting Memory Read, at          25028595000
 test master 2 - Starting Memory Read, at          25028775000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25030455000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          25030815000
 test master 2 - Starting Memory Read, at          25030995000
 test master 2 - Starting Memory Read, at          25031175000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25032675000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25033125000
 test master 2 - Starting Memory Read Line Multiple, at          25033305000
 test master 2 - Starting Memory Read Line Multiple, at          25033545000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25035495000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25042455000
 test master 2 - Starting Memory Read Line Multiple, at          25042635000
 test master 2 - Starting Memory Read Line Multiple, at          25042905000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25043625000
 test master 2 - Starting Memory Read Line Multiple, at          25043805000
 test master 2 - Starting Memory Read Line Multiple, at          25044045000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25044765000
 test master 2 - Starting Memory Read Line Multiple, at          25044945000
 test master 2 - Starting Memory Read Line Multiple, at          25045185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25045905000
 test master 2 - Starting Memory Read Line Multiple, at          25046085000
 test master 2 - Starting Memory Read Line Multiple, at          25046325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25047045000
 test master 2 - Starting Memory Read Line Multiple, at          25047225000
 test master 2 - Starting Memory Read Line Multiple, at          25047465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25048185000
 test master 2 - Starting Memory Read Line Multiple, at          25048365000
 test master 2 - Starting Memory Read Line Multiple, at          25048605000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25049325000
 test master 2 - Starting Memory Read Line Multiple, at          25049505000
 test master 2 - Starting Memory Read Line Multiple, at          25049745000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25050465000
 test master 2 - Starting Memory Read Line Multiple, at          25050645000
 test master 2 - Starting Memory Read Line Multiple, at          25050885000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          25051605000
 test master 2 - Starting Memory Read Line, at          25051785000
 test master 2 - Starting Memory Read Line, at          25051965000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          25052415000
 test master 2 - Starting Memory Read Line, at          25052595000
 test master 2 - Starting Memory Read Line, at          25052775000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25054005000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25055625000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25058625000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25060425000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          25065315000
 test master 2 - Starting Memory Write, at          25065555000
 test master 2 - Starting Memory Write, at          25065795000
 test master 2 - Starting Memory Write, at          25066035000
 test master 2 - Starting Memory Write, at          25066275000
 test master 1 - Starting Memory Read, at          25066635000
 test master 1 - Starting Memory Read, at          25066905000
 test master 1 - Starting Memory Read, at          25067445000
 test master 1 - Starting Memory Read, at          25067715000
 test master 1 - Starting Memory Read, at          25068255000
 test master 1 - Starting Memory Read, at          25068525000
 test master 2 - Starting Memory Write, at          25069875000
 test master 2 - Starting Memory Write, at          25070115000
 test master 2 - Starting Memory Write, at          25070355000
 test master 2 - Starting Memory Write, at          25070595000
 test master 2 - Starting Memory Write, at          25070835000
 test master 1 - Starting Memory Read, at          25071195000
 test master 1 - Starting Memory Read, at          25071465000
 test master 1 - Starting Memory Read, at          25072005000
 test master 1 - Starting Memory Read, at          25072275000
 test master 1 - Starting Memory Read, at          25072815000
 test master 1 - Starting Memory Read, at          25073085000
 test master 2 - Starting Memory Write, at          25074975000
 test master 2 - Starting Memory Write, at          25076085000
 test master 2 - Starting Memory Write, at          25077225000
 test master 2 - Starting Memory Write, at          25078365000
 test master 2 - Starting Memory Write, at          25080735000
 test master 2 - Starting Memory Write, at          25081845000
 test master 2 - Starting Memory Write, at          25082985000
 test master 2 - Starting Memory Write, at          25084125000
 test master 2 - Starting Memory Write, at          25086495000
 test master 2 - Starting Memory Write, at          25088625000
 test master 2 - Starting Memory Write, at          25090785000
 test master 2 - Starting Memory Write, at          25092945000
 test master 2 - Starting Memory Write, at          25096335000
 test master 2 - Starting Memory Write, at          25098735000
 test master 2 - Starting Memory Write, at          25101135000
 test master 2 - Starting Memory Write, at          25103535000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          25108065000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25108095000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25110375000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          25110615000
 test master 2 - Starting Memory Read, at          25110795000
 test master 2 - Starting Memory Read, at          25110975000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25112655000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          25113015000
 test master 2 - Starting Memory Read, at          25113195000
 test master 2 - Starting Memory Read, at          25113375000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25114875000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25115325000
 test master 2 - Starting Memory Read Line Multiple, at          25115505000
 test master 2 - Starting Memory Read Line Multiple, at          25115745000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25117695000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25124655000
 test master 2 - Starting Memory Read Line Multiple, at          25124835000
 test master 2 - Starting Memory Read Line Multiple, at          25125105000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25125825000
 test master 2 - Starting Memory Read Line Multiple, at          25126005000
 test master 2 - Starting Memory Read Line Multiple, at          25126245000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25126965000
 test master 2 - Starting Memory Read Line Multiple, at          25127145000
 test master 2 - Starting Memory Read Line Multiple, at          25127385000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25128105000
 test master 2 - Starting Memory Read Line Multiple, at          25128285000
 test master 2 - Starting Memory Read Line Multiple, at          25128525000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25129245000
 test master 2 - Starting Memory Read Line Multiple, at          25129425000
 test master 2 - Starting Memory Read Line Multiple, at          25129665000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25130385000
 test master 2 - Starting Memory Read Line Multiple, at          25130565000
 test master 2 - Starting Memory Read Line Multiple, at          25130805000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25131525000
 test master 2 - Starting Memory Read Line Multiple, at          25131705000
 test master 2 - Starting Memory Read Line Multiple, at          25131945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          25132665000
 test master 2 - Starting Memory Read Line Multiple, at          25132845000
 test master 2 - Starting Memory Read Line Multiple, at          25133085000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          25133805000
 test master 2 - Starting Memory Read Line, at          25133985000
 test master 2 - Starting Memory Read Line, at          25134165000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          25134615000
 test master 2 - Starting Memory Read Line, at          25134795000
 test master 2 - Starting Memory Read Line, at          25134975000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25136205000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25137825000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25140825000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          25142625000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          25147515000
 test master 2 - Starting Memory Write, at          25147755000
 test master 2 - Starting Memory Write, at          25147995000
 test master 2 - Starting Memory Write, at          25148235000
 test master 2 - Starting Memory Write, at          25148475000
 test master 1 - Starting Memory Read, at          25148835000
 test master 1 - Starting Memory Read, at          25149105000
 test master 1 - Starting Memory Read, at          25149645000
 test master 1 - Starting Memory Read, at          25149915000
 test master 1 - Starting Memory Read, at          25150455000
 test master 1 - Starting Memory Read, at          25150725000
 test master 2 - Starting Memory Write, at          25152075000
 test master 2 - Starting Memory Write, at          25152315000
 test master 2 - Starting Memory Write, at          25152555000
 test master 2 - Starting Memory Write, at          25152795000
 test master 2 - Starting Memory Write, at          25153035000
 test master 1 - Starting Memory Read, at          25153395000
 test master 1 - Starting Memory Read, at          25153665000
 test master 1 - Starting Memory Read, at          25154205000
 test master 1 - Starting Memory Read, at          25154475000
 test master 1 - Starting Memory Read, at          25155015000
 test master 1 - Starting Memory Read, at          25155285000
 test master 2 - Starting Memory Write, at          25157175000
 test master 2 - Starting Memory Write, at          25158285000
 test master 2 - Starting Memory Write, at          25159425000
 test master 2 - Starting Memory Write, at          25160565000
 test master 2 - Starting Memory Write, at          25162935000
 test master 2 - Starting Memory Write, at          25164045000
 test master 2 - Starting Memory Write, at          25165185000
 test master 2 - Starting Memory Write, at          25166325000
 test master 2 - Starting Memory Write, at          25168695000
 test master 2 - Starting Memory Write, at          25170825000
 test master 2 - Starting Memory Write, at          25172985000
 test master 2 - Starting Memory Write, at          25175145000
 test master 2 - Starting Memory Write, at          25178535000
 test master 2 - Starting Memory Write, at          25180935000
 test master 2 - Starting Memory Write, at          25183335000
 test master 2 - Starting Memory Write, at          25185735000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          25190265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25190295000
 test master 1 - Starting Memory Read, at          25192575000
 test master 1 - Starting Memory Read, at          25192875000
 test master 1 - Starting Memory Read, at          25194135000
 test master 1 - Starting Memory Read, at          25194435000
 test master 1 - Starting Memory Read Line, at          25195755000
 test master 1 - Starting Memory Read Line, at          25196055000
 test master 1 - Starting Memory Read Line, at          25197375000
 test master 1 - Starting Memory Read Line, at          25197705000
 test master 1 - Starting Memory Read Line, at          25199055000
 test master 1 - Starting Memory Read Line, at          25199415000
 test master 1 - Starting Memory Read Line, at          25200915000
 test master 1 - Starting Memory Read Line, at          25201275000
 test master 1 - Starting Memory Read Line Multiple, at          25202775000
 test master 1 - Starting Memory Read Line Multiple, at          25203195000
 test master 1 - Starting Memory Read Line Multiple, at          25204995000
 test master 1 - Starting Memory Read Line Multiple, at          25205415000
 test master 1 - Starting Memory Read Line, at          25207215000
 test master 1 - Starting Memory Read Line, at          25207575000
 test master 1 - Starting Memory Read, at          25210215000
 test master 1 - Starting Memory Read, at          25210515000
 test target 1 - Starting Config Write, at          25214025000
 test master 1 - Starting Memory Write, at          25214625000
 test master 1 - Starting Memory Write, at          25220235000
 test master 1 - Starting Memory Write, at          25221555000
 test master 1 - Starting Memory Write, at          25226805000
 test master 1 - Starting Memory Write, at          25228155000
 test master 1 - Starting Memory Read Line, at          25233765000
 test master 1 - Starting Memory Write, at          25235265000
 test master 1 - Starting Memory Read Line, at          25240875000
 test target 1 - Starting Config Write, at          25244445000
 test master 1 - Starting Memory Write, at          25245045000
 test master 1 - Starting Memory Write, at          25245165000
 test master 1 - Starting Memory Write, at          25245405000
 test master 1 - Starting Memory Read, at          25245525000
 test master 1 - Starting Memory Write, at          25245825000
 test master 1 - Starting Memory Read, at          25245945000
 test master 1 - Starting Memory Write, at          25247715000
 test master 1 - Starting Memory Write, at          25254675000
 test master 2 - Starting Memory Read Line, at          25261755000
 test master 2 - Starting Memory Read Line, at          25262085000
 test master 2 - Starting Memory Read Line, at          25262565000
 test master 2 - Starting Memory Read Line, at          25262895000
 test master 1 - Starting Memory Write, at          25263465000
 test master 1 - Starting Memory Write, at          25263735000
 test master 1 - Starting Memory Write, at          25264035000
 test master 2 - Starting Memory Read Line, at          25264455000
 test master 2 - Starting Memory Read Line, at          25264755000
 test master 2 - Starting Memory Read Line, at          25265025000
 test master 2 - Starting Memory Read Line, at          25265325000
 test master 2 - Starting Memory Read Line Multiple, at          25265625000
 test master 2 - Starting Memory Read Line Multiple, at          25265925000
 test master 1 - Starting Memory Write, at          25267965000
 test master 1 - Starting Memory Write, at          25268235000
 test master 2 - Starting Memory Read, at          25268655000
 test master 2 - Starting Memory Read, at          25268955000
 test master 2 - Starting Memory Read, at          25269225000
 test master 2 - Starting Memory Read, at          25269525000
 test master 1 - Starting Memory Write, at          25271295000
 test master 1 - Starting Memory Read, at          25271475000
 test master 1 - Starting Memory Write, at          25271655000
 test master 1 - Starting Memory Read, at          25271865000
 test master 1 - Starting Memory Write, at          25272075000
 test master 1 - Starting Memory Read, at          25272255000
 test master 1 - Starting Memory Read, at          25272465000
 test master 1 - Starting Memory Write, at          25272675000
 test master 1 - Starting Memory Write, at          25272855000
 test master 1 - Starting Memory Read, at          25273035000
 test master 1 - Starting Memory Write, at          25273215000
 test master 1 - Starting Memory Write, at          25273425000
 test master 1 - Starting Memory Write, at          25273635000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          25278435000
 test target 1 - Starting Memory Write, at          25278675000
 test master 1 - Starting Memory Write, at          25278885000
 test target 1 - Starting Memory Write, at          25279065000
 test target 1 - Starting Memory Write, at          25279305000
 test target 1 - Starting Memory Write, at          25279545000
 test master 1 - Starting Memory Write, at          25279875000
 test target 1 - Starting Memory Write, at          25280385000
 test target 1 - Starting Memory Write, at          25280955000
 test target 1 - Starting Memory Write, at          25281225000
 test master 1 - Starting Memory Write, at          25281465000
 test target 1 - Starting Memory Write, at          25281825000
 test target 1 - Starting Memory Write, at          25282095000
 test target 1 - Starting Memory Write, at          25282365000
 test master 1 - Starting Memory Write, at          25282875000
 test target 1 - Starting Memory Write, at          25283715000
 test target 1 - Starting Memory Write, at          25284495000
 test target 1 - Starting Memory Write, at          25284735000
 test master 1 - Starting Memory Read, at          25284945000
 test target 1 - Starting Memory Write, at          25285125000
 test master 1 - Starting Memory Read, at          25285335000
 test target 1 - Starting Memory Write, at          25285515000
 test master 1 - Starting Memory Read, at          25285725000
 test target 1 - Starting Memory Write, at          25285905000
 test master 1 - Starting Memory Read, at          25286115000
 test target 1 - Starting Memory Write, at          25286295000
 test master 1 - Starting Memory Read, at          25286505000
 test target 1 - Starting Memory Write, at          25286685000
 test master 1 - Starting Memory Write, at          25286895000
 test target 1 - Starting Memory Write, at          25287075000
 test target 1 - Starting Memory Write, at          25287315000
 test target 1 - Starting Memory Write, at          25287555000
 test target 1 - Starting Memory Read, at          25287855000
 test master 1 - Starting Memory Write, at          25288185000
 test master 1 - Starting Memory Read, at          25288395000
 test target 1 - Starting Memory Write, at          25288905000
 test master 1 - Starting Memory Write, at          25289295000
 test target 1 - Starting Memory Read, at          25289745000
 test target 1 - Starting Memory Write, at          25290555000
 test master 1 - Starting Memory Read, at          25290885000
 test master 1 - Starting Memory Write, at          25291185000
 test master 1 - Starting Memory Write, at          25291545000
 test master 1 - Starting Memory Read, at          25291785000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          25294515000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          25295625000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          25322355000
 test target 1 - Starting Config Write, at          25323315000
 test target 1 - Starting Config Write, at          25324275000
 test target 2 - Starting Config Write, at          25325235000
 test target 2 - Starting Config Write, at          25326195000
 test target 2 - Starting Config Write, at          25327155000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          25329345000
 test target 1 - Starting Memory Read, at          25329555000
 test target 1 - Starting Memory Write, at          25330215000
 test target 1 - Starting Memory Read, at          25330425000
 test target 1 - Starting Memory Write, at          25331625000
 test target 1 - Starting Memory Read, at          25332615000
 test target 1 - Starting Memory Read, at          25333245000
 test target 1 - Starting Memory Read, at          25333845000
 test target 1 - Starting Memory Read, at          25334475000
 test target 1 - Starting Memory Read, at          25335375000
 test target 1 - Starting Memory Read, at          25336485000
 test target 1 - Starting Memory Read, at          25337415000
 test target 1 - Starting Memory Read, at          25338525000
 test target 1 - Starting Memory Read, at          25339455000
 test target 1 - Starting Memory Read, at          25341225000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          25348185000
 test target 1 - Starting Memory Read, at          25348395000
 test target 1 - Starting Memory Write, at          25349055000
 test target 1 - Starting Memory Read, at          25349265000
 test target 1 - Starting Memory Write, at          25350465000
 test target 1 - Starting Memory Read, at          25351455000
 test target 1 - Starting Memory Read, at          25352085000
 test target 1 - Starting Memory Read, at          25352685000
 test target 1 - Starting Memory Read, at          25353315000
 test target 1 - Starting Memory Read, at          25354215000
 test target 1 - Starting Memory Read, at          25355325000
 test target 1 - Starting Memory Read, at          25356255000
 test target 1 - Starting Memory Read, at          25357365000
 test target 1 - Starting Memory Read, at          25358295000
 test target 1 - Starting Memory Read, at          25360065000
 test target 1 - Starting Memory Write, at          25367025000
 test target 1 - Starting Memory Read, at          25367235000
 test target 1 - Starting Memory Write, at          25367895000
 test target 1 - Starting Memory Read, at          25368105000
 test target 1 - Starting Memory Write, at          25369305000
 test target 1 - Starting Memory Read, at          25370295000
 test target 1 - Starting Memory Read, at          25370925000
 test target 1 - Starting Memory Read, at          25371525000
 test target 1 - Starting Memory Read, at          25372155000
 test target 1 - Starting Memory Read, at          25373055000
 test target 1 - Starting Memory Read, at          25374165000
 test target 1 - Starting Memory Read, at          25375095000
 test target 1 - Starting Memory Read, at          25376205000
 test target 1 - Starting Memory Read, at          25377135000
 test target 1 - Starting Memory Read, at          25378905000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          25392825000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          25399965000
 test target 1 - Starting Memory Write, at          25400895000
 test target 1 - Starting Memory Read, at          25401225000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          25402455000
 test target 1 - Starting Config Write, at          25404465000
 test target 1 - Starting Memory Read, at          25405155000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          25406775000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          25409055000
 test target 1 - Starting Memory Write, at          25410345000
 test target 1 - Starting Memory Write, at          25410585000
 test target 1 - Starting Memory Read, at          25410795000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          25413495000
 test target 1 - Starting Memory Write, at          25416945000
 test target 1 - Starting Memory Write, at          25417305000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          25421715000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          25423875000
 test target 1 - Starting Memory Read, at          25425315000
 test target 1 - Starting Memory Read, at          25426335000
 test target 1 - Starting Memory Read, at          25428075000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          25434885000
 test target 2 - Starting Config Write, at          25435845000
 test target 1 - Starting Memory Write, at          25436535000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          25436655000
 test target 1 - Starting Memory Write, at          25437795000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          25437915000
 test target 1 - Starting Memory Write, at          25439055000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          25440615000
 test target 1 - Starting Memory Read, at          25443015000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          25443135000
 test target 1 - Starting Memory Read, at          25445595000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          25447485000
 test master 2 - Starting Memory Write, at          25447485000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          25447545000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25448445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25448475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25448775000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25448805000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25449795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25449825000
 test target 1 - Starting Memory Write, at          25451835000
 test master 2 - Starting Memory Write, at          25451835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25453725000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25453755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25455645000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25455675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25457565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25457595000
 test target 1 - Starting Memory Write, at          25459905000
 test master 2 - Starting Memory Write, at          25459905000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          25459965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25461765000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25461795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25462095000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25462125000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25463115000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25463145000
 test target 1 - Starting Memory Write, at          25464435000
 test master 2 - Starting Memory Write, at          25464435000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          25467795000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          25469625000
 test master 1 - Starting Memory Read, at          25469985000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          25470135000
 test target 1 - Starting Config Write, at          25473045000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          25475775000
 test target 1 - Starting Memory Write, at          25475925000
 test target 1 - Starting Memory Write, at          25476075000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          25476585000
 test target 1 - Starting Memory Write, at          25476765000
 test target 1 - Starting Memory Write, at          25476945000
 test target 1 - Starting Memory Write, at          25477455000
 test target 1 - Starting Memory Write, at          25477665000
 test target 1 - Starting Memory Write, at          25478175000
 test target 1 - Starting Memory Write, at          25478835000
 test target 1 - Starting Memory Write, at          25479015000
 test target 1 - Starting Memory Write, at          25479675000
 test target 1 - Starting Memory Write, at          25479915000
 test target 1 - Starting Memory Write, at          25480515000
 test target 1 - Starting Memory Write, at          25487205000
 test target 1 - Starting Memory Write, at          25487385000
 test target 1 - Starting Memory Write, at          25487565000
 test target 1 - Starting Memory Write, at          25487805000
 test target 1 - Starting Memory Write, at          25488045000
 test target 1 - Starting Memory Read, at          25491675000
 test target 1 - Starting Memory Read, at          25492785000
 test target 1 - Starting Memory Read, at          25493865000
 test target 1 - Starting Memory Read, at          25494945000
 test target 1 - Starting Memory Read, at          25496025000
 test target 1 - Starting Memory Read, at          25497105000
 test target 1 - Starting Memory Read, at          25498185000
 test target 1 - Starting Memory Read, at          25499265000
 test target 1 - Starting Memory Read, at          25500345000
 test target 1 - Starting Memory Read, at          25501425000
 test target 1 - Starting Memory Read, at          25502505000
 test target 1 - Starting Memory Read, at          25503585000
 test target 1 - Starting Memory Read, at          25504665000
 test target 1 - Starting Memory Read, at          25505745000
 test target 1 - Starting Memory Read, at          25506825000
 test target 1 - Starting Memory Read, at          25507905000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          25508805000
 test target 1 - Starting Memory Read, at          25508955000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          25511205000
 test target 1 - Starting Memory Read, at          25512315000
 test target 1 - Starting Memory Read, at          25513095000
 test target 1 - Starting Memory Read, at          25513815000
 test target 1 - Starting Memory Read, at          25514625000
 test target 1 - Starting Memory Read, at          25515345000
 test target 1 - Starting Memory Read, at          25516515000
 test target 1 - Starting Memory Read, at          25517625000
 test target 1 - Starting Memory Read, at          25518555000
 test target 1 - Starting Memory Read, at          25521405000
 test target 1 - Starting Memory Read, at          25523415000
 test target 1 - Starting Memory Read, at          25524375000
 test target 1 - Starting Memory Read, at          25525275000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          25526775000
 test master 1 - Starting Memory Write, at          25527015000
 test target 1 - Starting Memory Write, at          25527015000
 test target 1 - Starting Memory Write, at          25527165000
 test target 1 - Starting Memory Read, at          25527495000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          25529385000
 test master 1 - Starting Memory Write, at          25529625000
 test target 1 - Starting Memory Write, at          25529625000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          25535055000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          25536165000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          25562895000
 test target 1 - Starting Config Write, at          25563855000
 test target 1 - Starting Config Write, at          25564815000
 test target 2 - Starting Config Write, at          25565775000
 test target 2 - Starting Config Write, at          25566735000
 test target 2 - Starting Config Write, at          25567695000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          25569885000
 test target 1 - Starting Memory Read, at          25570125000
 test target 1 - Starting Memory Write, at          25570755000
 test target 1 - Starting Memory Read, at          25570995000
 test target 1 - Starting Memory Write, at          25572165000
 test target 1 - Starting Memory Read, at          25573155000
 test target 1 - Starting Memory Read, at          25573785000
 test target 1 - Starting Memory Read, at          25574415000
 test target 1 - Starting Memory Read, at          25575045000
 test target 1 - Starting Memory Read, at          25575975000
 test target 1 - Starting Memory Read, at          25577055000
 test target 1 - Starting Memory Read, at          25578015000
 test target 1 - Starting Memory Read, at          25579125000
 test target 1 - Starting Memory Read, at          25580055000
 test target 1 - Starting Memory Read, at          25581825000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          25588785000
 test target 1 - Starting Memory Read, at          25589025000
 test target 1 - Starting Memory Write, at          25589655000
 test target 1 - Starting Memory Read, at          25589895000
 test target 1 - Starting Memory Write, at          25591065000
 test target 1 - Starting Memory Read, at          25592055000
 test target 1 - Starting Memory Read, at          25592685000
 test target 1 - Starting Memory Read, at          25593315000
 test target 1 - Starting Memory Read, at          25593945000
 test target 1 - Starting Memory Read, at          25594875000
 test target 1 - Starting Memory Read, at          25595955000
 test target 1 - Starting Memory Read, at          25596915000
 test target 1 - Starting Memory Read, at          25598025000
 test target 1 - Starting Memory Read, at          25598955000
 test target 1 - Starting Memory Read, at          25600725000
 test target 1 - Starting Memory Write, at          25607685000
 test target 1 - Starting Memory Read, at          25607925000
 test target 1 - Starting Memory Write, at          25608555000
 test target 1 - Starting Memory Read, at          25608795000
 test target 1 - Starting Memory Write, at          25609965000
 test target 1 - Starting Memory Read, at          25610955000
 test target 1 - Starting Memory Read, at          25611585000
 test target 1 - Starting Memory Read, at          25612215000
 test target 1 - Starting Memory Read, at          25612845000
 test target 1 - Starting Memory Read, at          25613775000
 test target 1 - Starting Memory Read, at          25614855000
 test target 1 - Starting Memory Read, at          25615815000
 test target 1 - Starting Memory Read, at          25616925000
 test target 1 - Starting Memory Read, at          25617855000
 test target 1 - Starting Memory Read, at          25619625000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          25633545000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          25640685000
 test target 1 - Starting Memory Write, at          25641615000
 test target 1 - Starting Memory Read, at          25641975000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          25643325000
 test target 1 - Starting Config Write, at          25645335000
 test target 1 - Starting Memory Read, at          25645995000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          25647645000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          25649955000
 test target 1 - Starting Memory Write, at          25651245000
 test target 1 - Starting Memory Write, at          25651515000
 test target 1 - Starting Memory Read, at          25651755000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          25654395000
 test target 1 - Starting Memory Write, at          25657875000
 test target 1 - Starting Memory Write, at          25658235000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          25662675000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          25664835000
 test target 1 - Starting Memory Read, at          25666275000
 test target 1 - Starting Memory Read, at          25667295000
 test target 1 - Starting Memory Read, at          25669035000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          25675845000
 test target 2 - Starting Config Write, at          25676805000
 test target 1 - Starting Memory Write, at          25677495000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          25677645000
 test target 1 - Starting Memory Write, at          25678785000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          25678935000
 test target 1 - Starting Memory Write, at          25680075000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          25681635000
 test target 1 - Starting Memory Read, at          25684095000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          25684245000
 test target 1 - Starting Memory Read, at          25686615000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          25688535000
 test master 2 - Starting Memory Write, at          25688535000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          25688595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25689525000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25689555000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25689855000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25689885000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25690875000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25690905000
 test target 1 - Starting Memory Write, at          25692915000
 test master 2 - Starting Memory Write, at          25692915000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25694835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25694865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25696755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25696785000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25698675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25698705000
 test target 1 - Starting Memory Write, at          25701015000
 test master 2 - Starting Memory Write, at          25701015000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          25701075000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25702905000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25702935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25703235000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25703265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25704255000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25704285000
 test target 1 - Starting Memory Write, at          25705575000
 test master 2 - Starting Memory Write, at          25705575000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          25708965000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          25710795000
 test master 1 - Starting Memory Read, at          25711185000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          25711335000
 test target 1 - Starting Config Write, at          25714245000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          25717215000
 test target 1 - Starting Memory Write, at          25717395000
 test target 1 - Starting Memory Write, at          25717575000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          25718115000
 test target 1 - Starting Memory Write, at          25718325000
 test target 1 - Starting Memory Write, at          25718535000
 test target 1 - Starting Memory Write, at          25719075000
 test target 1 - Starting Memory Write, at          25719315000
 test target 1 - Starting Memory Write, at          25719855000
 test target 1 - Starting Memory Write, at          25720575000
 test target 1 - Starting Memory Write, at          25720785000
 test target 1 - Starting Memory Write, at          25721475000
 test target 1 - Starting Memory Write, at          25721745000
 test target 1 - Starting Memory Write, at          25722375000
 test target 1 - Starting Memory Write, at          25729095000
 test target 1 - Starting Memory Write, at          25729305000
 test target 1 - Starting Memory Write, at          25729515000
 test target 1 - Starting Memory Write, at          25729785000
 test target 1 - Starting Memory Write, at          25730055000
 test target 1 - Starting Memory Read, at          25733715000
 test target 1 - Starting Memory Read, at          25734825000
 test target 1 - Starting Memory Read, at          25735905000
 test target 1 - Starting Memory Read, at          25736985000
 test target 1 - Starting Memory Read, at          25738065000
 test target 1 - Starting Memory Read, at          25739145000
 test target 1 - Starting Memory Read, at          25740225000
 test target 1 - Starting Memory Read, at          25741305000
 test target 1 - Starting Memory Read, at          25742385000
 test target 1 - Starting Memory Read, at          25743465000
 test target 1 - Starting Memory Read, at          25744545000
 test target 1 - Starting Memory Read, at          25745625000
 test target 1 - Starting Memory Read, at          25746705000
 test target 1 - Starting Memory Read, at          25747785000
 test target 1 - Starting Memory Read, at          25748865000
 test target 1 - Starting Memory Read, at          25749945000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          25750875000
 test target 1 - Starting Memory Read, at          25751055000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          25753275000
 test target 1 - Starting Memory Read, at          25754415000
 test target 1 - Starting Memory Read, at          25755135000
 test target 1 - Starting Memory Read, at          25755885000
 test target 1 - Starting Memory Read, at          25756665000
 test target 1 - Starting Memory Read, at          25757415000
 test target 1 - Starting Memory Read, at          25758615000
 test target 1 - Starting Memory Read, at          25759695000
 test target 1 - Starting Memory Read, at          25760655000
 test target 1 - Starting Memory Read, at          25763505000
 test target 1 - Starting Memory Read, at          25765515000
 test target 1 - Starting Memory Read, at          25766475000
 test target 1 - Starting Memory Read, at          25767375000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          25768875000
 test master 1 - Starting Memory Write, at          25769145000
 test target 1 - Starting Memory Write, at          25769145000
 test target 1 - Starting Memory Write, at          25769325000
 test target 1 - Starting Memory Read, at          25769685000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          25771695000
 test master 1 - Starting Memory Write, at          25771965000
 test target 1 - Starting Memory Write, at          25771965000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          25777335000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          25778445000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          25805175000
 test target 1 - Starting Config Write, at          25806135000
 test target 1 - Starting Config Write, at          25807095000
 test target 2 - Starting Config Write, at          25808055000
 test target 2 - Starting Config Write, at          25809015000
 test target 2 - Starting Config Write, at          25809975000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          25812165000
 test target 1 - Starting Memory Read, at          25812435000
 test target 1 - Starting Memory Write, at          25813275000
 test target 1 - Starting Memory Read, at          25813545000
 test target 1 - Starting Memory Write, at          25814895000
 test target 1 - Starting Memory Read, at          25815915000
 test target 1 - Starting Memory Read, at          25816545000
 test target 1 - Starting Memory Read, at          25817175000
 test target 1 - Starting Memory Read, at          25817805000
 test target 1 - Starting Memory Read, at          25818735000
 test target 1 - Starting Memory Read, at          25819815000
 test target 1 - Starting Memory Read, at          25820775000
 test target 1 - Starting Memory Read, at          25821885000
 test target 1 - Starting Memory Read, at          25822815000
 test target 1 - Starting Memory Read, at          25824585000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          25831545000
 test target 1 - Starting Memory Read, at          25831815000
 test target 1 - Starting Memory Write, at          25832655000
 test target 1 - Starting Memory Read, at          25832925000
 test target 1 - Starting Memory Write, at          25834275000
 test target 1 - Starting Memory Read, at          25835295000
 test target 1 - Starting Memory Read, at          25835925000
 test target 1 - Starting Memory Read, at          25836555000
 test target 1 - Starting Memory Read, at          25837185000
 test target 1 - Starting Memory Read, at          25838115000
 test target 1 - Starting Memory Read, at          25839195000
 test target 1 - Starting Memory Read, at          25840155000
 test target 1 - Starting Memory Read, at          25841265000
 test target 1 - Starting Memory Read, at          25842195000
 test target 1 - Starting Memory Read, at          25843965000
 test target 1 - Starting Memory Write, at          25850925000
 test target 1 - Starting Memory Read, at          25851195000
 test target 1 - Starting Memory Write, at          25852035000
 test target 1 - Starting Memory Read, at          25852305000
 test target 1 - Starting Memory Write, at          25853655000
 test target 1 - Starting Memory Read, at          25854675000
 test target 1 - Starting Memory Read, at          25855305000
 test target 1 - Starting Memory Read, at          25855935000
 test target 1 - Starting Memory Read, at          25856565000
 test target 1 - Starting Memory Read, at          25857495000
 test target 1 - Starting Memory Read, at          25858575000
 test target 1 - Starting Memory Read, at          25859535000
 test target 1 - Starting Memory Read, at          25860645000
 test target 1 - Starting Memory Read, at          25861575000
 test target 1 - Starting Memory Read, at          25863345000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          25877265000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          25884405000
 test target 1 - Starting Memory Write, at          25885335000
 test target 1 - Starting Memory Read, at          25885725000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          25887045000
 test target 1 - Starting Config Write, at          25889055000
 test target 1 - Starting Memory Read, at          25889715000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          25891365000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          25893675000
 test target 1 - Starting Memory Write, at          25894965000
 test target 1 - Starting Memory Write, at          25895265000
 test target 1 - Starting Memory Read, at          25895535000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          25898355000
 test target 1 - Starting Memory Write, at          25901865000
 test target 1 - Starting Memory Write, at          25902225000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          25906695000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          25908855000
 test target 1 - Starting Memory Read, at          25910415000
 test target 1 - Starting Memory Read, at          25911465000
 test target 1 - Starting Memory Read, at          25913235000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          25920015000
 test target 2 - Starting Config Write, at          25920975000
 test target 1 - Starting Memory Write, at          25921665000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          25921845000
 test target 1 - Starting Memory Write, at          25922985000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          25923165000
 test target 1 - Starting Memory Write, at          25924305000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          25925895000
 test target 1 - Starting Memory Read, at          25928355000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          25928535000
 test target 1 - Starting Memory Read, at          25930875000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          25932795000
 test master 2 - Starting Memory Write, at          25932795000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          25932855000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25933815000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25933845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25934145000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25934175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25935165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25935195000
 test target 1 - Starting Memory Write, at          25937205000
 test master 2 - Starting Memory Write, at          25937205000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25939155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25939185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25941075000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25941105000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25942995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25943025000
 test target 1 - Starting Memory Write, at          25945335000
 test master 2 - Starting Memory Write, at          25945335000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          25945395000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25947255000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25947285000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25947585000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25947615000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25948605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          25948635000
 test target 1 - Starting Memory Write, at          25949925000
 test master 2 - Starting Memory Write, at          25949925000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          25953345000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          25955175000
 test master 1 - Starting Memory Read, at          25955565000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          25955715000
 test target 1 - Starting Config Write, at          25958625000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          25961595000
 test target 1 - Starting Memory Write, at          25961805000
 test target 1 - Starting Memory Write, at          25962015000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          25962585000
 test target 1 - Starting Memory Write, at          25962825000
 test target 1 - Starting Memory Write, at          25963065000
 test target 1 - Starting Memory Write, at          25963635000
 test target 1 - Starting Memory Write, at          25963905000
 test target 1 - Starting Memory Write, at          25964475000
 test target 1 - Starting Memory Write, at          25965195000
 test target 1 - Starting Memory Write, at          25965435000
 test target 1 - Starting Memory Write, at          25966155000
 test target 1 - Starting Memory Write, at          25966455000
 test target 1 - Starting Memory Write, at          25967115000
 test target 1 - Starting Memory Write, at          25973865000
 test target 1 - Starting Memory Write, at          25974105000
 test target 1 - Starting Memory Write, at          25974345000
 test target 1 - Starting Memory Write, at          25974645000
 test target 1 - Starting Memory Write, at          25974945000
 test target 1 - Starting Memory Read, at          25978635000
 test target 1 - Starting Memory Read, at          25979745000
 test target 1 - Starting Memory Read, at          25980825000
 test target 1 - Starting Memory Read, at          25981905000
 test target 1 - Starting Memory Read, at          25982985000
 test target 1 - Starting Memory Read, at          25984065000
 test target 1 - Starting Memory Read, at          25985145000
 test target 1 - Starting Memory Read, at          25986225000
 test target 1 - Starting Memory Read, at          25987305000
 test target 1 - Starting Memory Read, at          25988385000
 test target 1 - Starting Memory Read, at          25989465000
 test target 1 - Starting Memory Read, at          25990545000
 test target 1 - Starting Memory Read, at          25991625000
 test target 1 - Starting Memory Read, at          25992705000
 test target 1 - Starting Memory Read, at          25993785000
 test target 1 - Starting Memory Read, at          25994865000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          25995795000
 test target 1 - Starting Memory Read, at          25996005000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          25998195000
 test target 1 - Starting Memory Read, at          25999365000
 test target 1 - Starting Memory Read, at          26000055000
 test target 1 - Starting Memory Read, at          26000805000
 test target 1 - Starting Memory Read, at          26001585000
 test target 1 - Starting Memory Read, at          26002335000
 test target 1 - Starting Memory Read, at          26003535000
 test target 1 - Starting Memory Read, at          26004615000
 test target 1 - Starting Memory Read, at          26005575000
 test target 1 - Starting Memory Read, at          26008425000
 test target 1 - Starting Memory Read, at          26010435000
 test target 1 - Starting Memory Read, at          26011395000
 test target 1 - Starting Memory Read, at          26012295000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          26013795000
 test master 1 - Starting Memory Write, at          26014035000
 test target 1 - Starting Memory Write, at          26014035000
 test target 1 - Starting Memory Write, at          26014245000
 test target 1 - Starting Memory Read, at          26014695000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          26016735000
 test master 1 - Starting Memory Write, at          26016975000
 test target 1 - Starting Memory Write, at          26016975000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          26022375000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          26023485000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          26050215000
 test target 1 - Starting Config Write, at          26051415000
 test target 1 - Starting Config Write, at          26052615000
 test target 2 - Starting Config Write, at          26053815000
 test target 2 - Starting Config Write, at          26055015000
 test target 2 - Starting Config Write, at          26056215000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          26058645000
 test target 1 - Starting Memory Read, at          26058945000
 test target 1 - Starting Memory Write, at          26059755000
 test target 1 - Starting Memory Read, at          26060055000
 test target 1 - Starting Memory Write, at          26061375000
 test target 1 - Starting Memory Read, at          26062455000
 test target 1 - Starting Memory Read, at          26063085000
 test target 1 - Starting Memory Read, at          26063685000
 test target 1 - Starting Memory Read, at          26064315000
 test target 1 - Starting Memory Read, at          26065215000
 test target 1 - Starting Memory Read, at          26066325000
 test target 1 - Starting Memory Read, at          26067495000
 test target 1 - Starting Memory Read, at          26068605000
 test target 1 - Starting Memory Read, at          26069775000
 test target 1 - Starting Memory Read, at          26071545000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          26078715000
 test target 1 - Starting Memory Read, at          26079015000
 test target 1 - Starting Memory Write, at          26079825000
 test target 1 - Starting Memory Read, at          26080125000
 test target 1 - Starting Memory Write, at          26081445000
 test target 1 - Starting Memory Read, at          26082495000
 test target 1 - Starting Memory Read, at          26083125000
 test target 1 - Starting Memory Read, at          26083755000
 test target 1 - Starting Memory Read, at          26084385000
 test target 1 - Starting Memory Read, at          26085315000
 test target 1 - Starting Memory Read, at          26086395000
 test target 1 - Starting Memory Read, at          26087355000
 test target 1 - Starting Memory Read, at          26088465000
 test target 1 - Starting Memory Read, at          26089635000
 test target 1 - Starting Memory Read, at          26091405000
 test target 1 - Starting Memory Write, at          26098575000
 test target 1 - Starting Memory Read, at          26098875000
 test target 1 - Starting Memory Write, at          26099685000
 test target 1 - Starting Memory Read, at          26099985000
 test target 1 - Starting Memory Write, at          26101305000
 test target 1 - Starting Memory Read, at          26102355000
 test target 1 - Starting Memory Read, at          26102985000
 test target 1 - Starting Memory Read, at          26103615000
 test target 1 - Starting Memory Read, at          26104245000
 test target 1 - Starting Memory Read, at          26105175000
 test target 1 - Starting Memory Read, at          26106255000
 test target 1 - Starting Memory Read, at          26107215000
 test target 1 - Starting Memory Read, at          26108325000
 test target 1 - Starting Memory Read, at          26109495000
 test target 1 - Starting Memory Read, at          26111265000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          26125395000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          26132745000
 test target 1 - Starting Memory Write, at          26133915000
 test target 1 - Starting Memory Read, at          26134335000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          26135625000
 test target 1 - Starting Config Write, at          26137875000
 test target 1 - Starting Memory Read, at          26138775000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          26140425000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          26142975000
 test target 1 - Starting Memory Write, at          26144505000
 test target 1 - Starting Memory Write, at          26144835000
 test target 1 - Starting Memory Read, at          26145135000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          26147895000
 test target 1 - Starting Memory Write, at          26151435000
 test target 1 - Starting Memory Write, at          26151825000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          26156355000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          26158755000
 test target 1 - Starting Memory Read, at          26160315000
 test target 1 - Starting Memory Read, at          26161365000
 test target 1 - Starting Memory Read, at          26163255000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          26170065000
 test target 2 - Starting Config Write, at          26171265000
 test target 1 - Starting Memory Write, at          26172195000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          26172405000
 test target 1 - Starting Memory Write, at          26173545000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          26173755000
 test target 1 - Starting Memory Write, at          26174895000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          26176515000
 test target 1 - Starting Memory Read, at          26178975000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          26179185000
 test target 1 - Starting Memory Read, at          26181735000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          26183655000
 test master 2 - Starting Memory Write, at          26183655000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          26183715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26184705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26184735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26185035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26185065000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26186055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26186085000
 test target 1 - Starting Memory Write, at          26188095000
 test master 2 - Starting Memory Write, at          26188095000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26190075000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26190105000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26191995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26192025000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26193915000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26193945000
 test target 1 - Starting Memory Write, at          26196255000
 test master 2 - Starting Memory Write, at          26196255000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          26196315000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26198205000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26198235000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26198535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26198565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26199555000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26199585000
 test target 1 - Starting Memory Write, at          26200875000
 test master 2 - Starting Memory Write, at          26200875000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          26204325000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          26206155000
 test master 1 - Starting Memory Read, at          26206545000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          26206695000
 test target 1 - Starting Config Write, at          26209605000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          26212575000
 test target 1 - Starting Memory Write, at          26212815000
 test target 1 - Starting Memory Write, at          26213055000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          26213655000
 test target 1 - Starting Memory Write, at          26213925000
 test target 1 - Starting Memory Write, at          26214195000
 test target 1 - Starting Memory Write, at          26214795000
 test target 1 - Starting Memory Write, at          26215095000
 test target 1 - Starting Memory Write, at          26215695000
 test target 1 - Starting Memory Write, at          26216475000
 test target 1 - Starting Memory Write, at          26216745000
 test target 1 - Starting Memory Write, at          26217495000
 test target 1 - Starting Memory Write, at          26217825000
 test target 1 - Starting Memory Write, at          26218515000
 test target 1 - Starting Memory Write, at          26225295000
 test target 1 - Starting Memory Write, at          26225565000
 test target 1 - Starting Memory Write, at          26225835000
 test target 1 - Starting Memory Write, at          26226165000
 test target 1 - Starting Memory Write, at          26226495000
 test target 1 - Starting Memory Read, at          26230215000
 test target 1 - Starting Memory Read, at          26231355000
 test target 1 - Starting Memory Read, at          26232435000
 test target 1 - Starting Memory Read, at          26233515000
 test target 1 - Starting Memory Read, at          26234595000
 test target 1 - Starting Memory Read, at          26235675000
 test target 1 - Starting Memory Read, at          26236755000
 test target 1 - Starting Memory Read, at          26237835000
 test target 1 - Starting Memory Read, at          26238915000
 test target 1 - Starting Memory Read, at          26239995000
 test target 1 - Starting Memory Read, at          26241075000
 test target 1 - Starting Memory Read, at          26242155000
 test target 1 - Starting Memory Read, at          26243235000
 test target 1 - Starting Memory Read, at          26244315000
 test target 1 - Starting Memory Read, at          26245395000
 test target 1 - Starting Memory Read, at          26246475000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          26247405000
 test target 1 - Starting Memory Read, at          26247645000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          26250015000
 test target 1 - Starting Memory Read, at          26251215000
 test target 1 - Starting Memory Read, at          26251875000
 test target 1 - Starting Memory Read, at          26252625000
 test target 1 - Starting Memory Read, at          26253405000
 test target 1 - Starting Memory Read, at          26254155000
 test target 1 - Starting Memory Read, at          26255355000
 test target 1 - Starting Memory Read, at          26256435000
 test target 1 - Starting Memory Read, at          26257395000
 test target 1 - Starting Memory Read, at          26260245000
 test target 1 - Starting Memory Read, at          26262435000
 test target 1 - Starting Memory Read, at          26263335000
 test target 1 - Starting Memory Read, at          26264295000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          26265735000
 test master 1 - Starting Memory Write, at          26266005000
 test target 1 - Starting Memory Write, at          26266005000
 test target 1 - Starting Memory Write, at          26266245000
 test target 1 - Starting Memory Read, at          26266725000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          26268705000
 test master 1 - Starting Memory Write, at          26268975000
 test target 1 - Starting Memory Write, at          26268975000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26274975000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          26275275000
 test master 2 - Starting Memory Read, at          26275455000
 test master 2 - Starting Memory Read, at          26275635000
 test master 2 - Starting Memory Read, at          26275875000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26277555000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          26277975000
 test master 2 - Starting Memory Read, at          26278155000
 test master 2 - Starting Memory Read, at          26278575000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26280135000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26280705000
 test master 2 - Starting Memory Read Line Multiple, at          26280885000
 test master 2 - Starting Memory Read Line Multiple, at          26281065000
 test master 2 - Starting Memory Read Line Multiple, at          26281245000
 test master 2 - Starting Memory Read Line Multiple, at          26281545000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26283405000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26292255000
 test master 2 - Starting Memory Read Line Multiple, at          26292435000
 test master 2 - Starting Memory Read Line Multiple, at          26292615000
 test master 2 - Starting Memory Read Line Multiple, at          26292795000
 test master 2 - Starting Memory Read Line Multiple, at          26293125000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26293665000
 test master 2 - Starting Memory Read Line Multiple, at          26293845000
 test master 2 - Starting Memory Read Line Multiple, at          26294025000
 test master 2 - Starting Memory Read Line Multiple, at          26294205000
 test master 2 - Starting Memory Read Line Multiple, at          26294505000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26295045000
 test master 2 - Starting Memory Read Line Multiple, at          26295225000
 test master 2 - Starting Memory Read Line Multiple, at          26295405000
 test master 2 - Starting Memory Read Line Multiple, at          26295585000
 test master 2 - Starting Memory Read Line Multiple, at          26295885000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26296425000
 test master 2 - Starting Memory Read Line Multiple, at          26296605000
 test master 2 - Starting Memory Read Line Multiple, at          26296785000
 test master 2 - Starting Memory Read Line Multiple, at          26296965000
 test master 2 - Starting Memory Read Line Multiple, at          26297265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26297805000
 test master 2 - Starting Memory Read Line Multiple, at          26297985000
 test master 2 - Starting Memory Read Line Multiple, at          26298165000
 test master 2 - Starting Memory Read Line Multiple, at          26298345000
 test master 2 - Starting Memory Read Line Multiple, at          26298645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26299185000
 test master 2 - Starting Memory Read Line Multiple, at          26299365000
 test master 2 - Starting Memory Read Line Multiple, at          26299545000
 test master 2 - Starting Memory Read Line Multiple, at          26299725000
 test master 2 - Starting Memory Read Line Multiple, at          26300025000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26300565000
 test master 2 - Starting Memory Read Line Multiple, at          26300745000
 test master 2 - Starting Memory Read Line Multiple, at          26300925000
 test master 2 - Starting Memory Read Line Multiple, at          26301105000
 test master 2 - Starting Memory Read Line Multiple, at          26301405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26301945000
 test master 2 - Starting Memory Read Line Multiple, at          26302125000
 test master 2 - Starting Memory Read Line Multiple, at          26302305000
 test master 2 - Starting Memory Read Line Multiple, at          26302485000
 test master 2 - Starting Memory Read Line Multiple, at          26302785000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          26303325000
 test master 2 - Starting Memory Read Line, at          26303505000
 test master 2 - Starting Memory Read Line, at          26303685000
 test master 2 - Starting Memory Read Line, at          26303925000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          26304285000
 test master 2 - Starting Memory Read Line, at          26304465000
 test master 2 - Starting Memory Read Line, at          26304885000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26306145000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26307915000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26311185000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26313225000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          26318655000
 test master 2 - Starting Memory Write, at          26318955000
 test master 2 - Starting Memory Write, at          26319255000
 test master 2 - Starting Memory Write, at          26319555000
 test master 2 - Starting Memory Write, at          26319855000
 test master 1 - Starting Memory Read, at          26320275000
 test master 1 - Starting Memory Read, at          26320605000
 test master 1 - Starting Memory Read, at          26321145000
 test master 1 - Starting Memory Read, at          26321475000
 test master 1 - Starting Memory Read, at          26322015000
 test master 1 - Starting Memory Read, at          26322345000
 test master 2 - Starting Memory Write, at          26323725000
 test master 2 - Starting Memory Write, at          26324025000
 test master 2 - Starting Memory Write, at          26324325000
 test master 2 - Starting Memory Write, at          26324625000
 test master 2 - Starting Memory Write, at          26324925000
 test master 1 - Starting Memory Read, at          26325345000
 test master 1 - Starting Memory Read, at          26325675000
 test master 1 - Starting Memory Read, at          26326215000
 test master 1 - Starting Memory Read, at          26326545000
 test master 1 - Starting Memory Read, at          26327085000
 test master 1 - Starting Memory Read, at          26327415000
 test master 2 - Starting Memory Write, at          26329395000
 test master 2 - Starting Memory Write, at          26330625000
 test master 2 - Starting Memory Write, at          26331885000
 test master 2 - Starting Memory Write, at          26333145000
 test master 2 - Starting Memory Write, at          26335725000
 test master 2 - Starting Memory Write, at          26336985000
 test master 2 - Starting Memory Write, at          26338245000
 test master 2 - Starting Memory Write, at          26339505000
 test master 2 - Starting Memory Write, at          26342085000
 test master 2 - Starting Memory Write, at          26344455000
 test master 2 - Starting Memory Write, at          26346795000
 test master 2 - Starting Memory Write, at          26349135000
 test master 2 - Starting Memory Write, at          26352795000
 test master 2 - Starting Memory Write, at          26355435000
 test master 2 - Starting Memory Write, at          26358075000
 test master 2 - Starting Memory Write, at          26360715000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          26365485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26365515000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26368005000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          26368305000
 test master 2 - Starting Memory Read, at          26368485000
 test master 2 - Starting Memory Read, at          26368665000
 test master 2 - Starting Memory Read, at          26368905000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26370585000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          26371035000
 test master 2 - Starting Memory Read, at          26371215000
 test master 2 - Starting Memory Read, at          26371635000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26373195000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26373765000
 test master 2 - Starting Memory Read Line Multiple, at          26373945000
 test master 2 - Starting Memory Read Line Multiple, at          26374125000
 test master 2 - Starting Memory Read Line Multiple, at          26374305000
 test master 2 - Starting Memory Read Line Multiple, at          26374605000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26376465000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26385315000
 test master 2 - Starting Memory Read Line Multiple, at          26385495000
 test master 2 - Starting Memory Read Line Multiple, at          26385675000
 test master 2 - Starting Memory Read Line Multiple, at          26385855000
 test master 2 - Starting Memory Read Line Multiple, at          26386185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26386725000
 test master 2 - Starting Memory Read Line Multiple, at          26386905000
 test master 2 - Starting Memory Read Line Multiple, at          26387085000
 test master 2 - Starting Memory Read Line Multiple, at          26387265000
 test master 2 - Starting Memory Read Line Multiple, at          26387565000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26388105000
 test master 2 - Starting Memory Read Line Multiple, at          26388285000
 test master 2 - Starting Memory Read Line Multiple, at          26388465000
 test master 2 - Starting Memory Read Line Multiple, at          26388645000
 test master 2 - Starting Memory Read Line Multiple, at          26388945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26389485000
 test master 2 - Starting Memory Read Line Multiple, at          26389665000
 test master 2 - Starting Memory Read Line Multiple, at          26389845000
 test master 2 - Starting Memory Read Line Multiple, at          26390025000
 test master 2 - Starting Memory Read Line Multiple, at          26390325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26390865000
 test master 2 - Starting Memory Read Line Multiple, at          26391045000
 test master 2 - Starting Memory Read Line Multiple, at          26391225000
 test master 2 - Starting Memory Read Line Multiple, at          26391405000
 test master 2 - Starting Memory Read Line Multiple, at          26391705000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26392245000
 test master 2 - Starting Memory Read Line Multiple, at          26392425000
 test master 2 - Starting Memory Read Line Multiple, at          26392605000
 test master 2 - Starting Memory Read Line Multiple, at          26392785000
 test master 2 - Starting Memory Read Line Multiple, at          26393085000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26393625000
 test master 2 - Starting Memory Read Line Multiple, at          26393805000
 test master 2 - Starting Memory Read Line Multiple, at          26393985000
 test master 2 - Starting Memory Read Line Multiple, at          26394165000
 test master 2 - Starting Memory Read Line Multiple, at          26394465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26395005000
 test master 2 - Starting Memory Read Line Multiple, at          26395185000
 test master 2 - Starting Memory Read Line Multiple, at          26395365000
 test master 2 - Starting Memory Read Line Multiple, at          26395545000
 test master 2 - Starting Memory Read Line Multiple, at          26395845000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          26396385000
 test master 2 - Starting Memory Read Line, at          26396565000
 test master 2 - Starting Memory Read Line, at          26396745000
 test master 2 - Starting Memory Read Line, at          26396985000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          26397345000
 test master 2 - Starting Memory Read Line, at          26397525000
 test master 2 - Starting Memory Read Line, at          26397945000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26399205000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26400975000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26404245000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26406285000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          26411715000
 test master 2 - Starting Memory Write, at          26412015000
 test master 2 - Starting Memory Write, at          26412315000
 test master 2 - Starting Memory Write, at          26412615000
 test master 2 - Starting Memory Write, at          26412915000
 test master 1 - Starting Memory Read, at          26413335000
 test master 1 - Starting Memory Read, at          26413665000
 test master 1 - Starting Memory Read, at          26414205000
 test master 1 - Starting Memory Read, at          26414535000
 test master 1 - Starting Memory Read, at          26415075000
 test master 1 - Starting Memory Read, at          26415405000
 test master 2 - Starting Memory Write, at          26416785000
 test master 2 - Starting Memory Write, at          26417085000
 test master 2 - Starting Memory Write, at          26417385000
 test master 2 - Starting Memory Write, at          26417685000
 test master 2 - Starting Memory Write, at          26417985000
 test master 1 - Starting Memory Read, at          26418405000
 test master 1 - Starting Memory Read, at          26418735000
 test master 1 - Starting Memory Read, at          26419275000
 test master 1 - Starting Memory Read, at          26419605000
 test master 1 - Starting Memory Read, at          26420145000
 test master 1 - Starting Memory Read, at          26420475000
 test master 2 - Starting Memory Write, at          26422455000
 test master 2 - Starting Memory Write, at          26423685000
 test master 2 - Starting Memory Write, at          26424945000
 test master 2 - Starting Memory Write, at          26426205000
 test master 2 - Starting Memory Write, at          26428785000
 test master 2 - Starting Memory Write, at          26430045000
 test master 2 - Starting Memory Write, at          26431305000
 test master 2 - Starting Memory Write, at          26432565000
 test master 2 - Starting Memory Write, at          26435145000
 test master 2 - Starting Memory Write, at          26437515000
 test master 2 - Starting Memory Write, at          26439855000
 test master 2 - Starting Memory Write, at          26442195000
 test master 2 - Starting Memory Write, at          26445855000
 test master 2 - Starting Memory Write, at          26448495000
 test master 2 - Starting Memory Write, at          26451135000
 test master 2 - Starting Memory Write, at          26453775000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          26458545000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26458575000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26461065000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          26461365000
 test master 2 - Starting Memory Read, at          26461545000
 test master 2 - Starting Memory Read, at          26461725000
 test master 2 - Starting Memory Read, at          26461965000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26463645000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          26464095000
 test master 2 - Starting Memory Read, at          26464275000
 test master 2 - Starting Memory Read, at          26464695000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26466255000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26466825000
 test master 2 - Starting Memory Read Line Multiple, at          26467005000
 test master 2 - Starting Memory Read Line Multiple, at          26467185000
 test master 2 - Starting Memory Read Line Multiple, at          26467365000
 test master 2 - Starting Memory Read Line Multiple, at          26467665000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26469525000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26478375000
 test master 2 - Starting Memory Read Line Multiple, at          26478555000
 test master 2 - Starting Memory Read Line Multiple, at          26478735000
 test master 2 - Starting Memory Read Line Multiple, at          26478915000
 test master 2 - Starting Memory Read Line Multiple, at          26479245000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26479785000
 test master 2 - Starting Memory Read Line Multiple, at          26479965000
 test master 2 - Starting Memory Read Line Multiple, at          26480145000
 test master 2 - Starting Memory Read Line Multiple, at          26480325000
 test master 2 - Starting Memory Read Line Multiple, at          26480625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26481165000
 test master 2 - Starting Memory Read Line Multiple, at          26481345000
 test master 2 - Starting Memory Read Line Multiple, at          26481525000
 test master 2 - Starting Memory Read Line Multiple, at          26481705000
 test master 2 - Starting Memory Read Line Multiple, at          26482005000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26482545000
 test master 2 - Starting Memory Read Line Multiple, at          26482725000
 test master 2 - Starting Memory Read Line Multiple, at          26482905000
 test master 2 - Starting Memory Read Line Multiple, at          26483085000
 test master 2 - Starting Memory Read Line Multiple, at          26483385000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26483925000
 test master 2 - Starting Memory Read Line Multiple, at          26484105000
 test master 2 - Starting Memory Read Line Multiple, at          26484285000
 test master 2 - Starting Memory Read Line Multiple, at          26484465000
 test master 2 - Starting Memory Read Line Multiple, at          26484765000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26485305000
 test master 2 - Starting Memory Read Line Multiple, at          26485485000
 test master 2 - Starting Memory Read Line Multiple, at          26485665000
 test master 2 - Starting Memory Read Line Multiple, at          26485845000
 test master 2 - Starting Memory Read Line Multiple, at          26486145000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26486685000
 test master 2 - Starting Memory Read Line Multiple, at          26486865000
 test master 2 - Starting Memory Read Line Multiple, at          26487045000
 test master 2 - Starting Memory Read Line Multiple, at          26487225000
 test master 2 - Starting Memory Read Line Multiple, at          26487525000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26488065000
 test master 2 - Starting Memory Read Line Multiple, at          26488245000
 test master 2 - Starting Memory Read Line Multiple, at          26488425000
 test master 2 - Starting Memory Read Line Multiple, at          26488605000
 test master 2 - Starting Memory Read Line Multiple, at          26488905000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          26489445000
 test master 2 - Starting Memory Read Line, at          26489625000
 test master 2 - Starting Memory Read Line, at          26489805000
 test master 2 - Starting Memory Read Line, at          26490045000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          26490405000
 test master 2 - Starting Memory Read Line, at          26490585000
 test master 2 - Starting Memory Read Line, at          26491005000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26492265000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26494035000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26497305000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26499345000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          26504775000
 test master 2 - Starting Memory Write, at          26505075000
 test master 2 - Starting Memory Write, at          26505375000
 test master 2 - Starting Memory Write, at          26505675000
 test master 2 - Starting Memory Write, at          26505975000
 test master 1 - Starting Memory Read, at          26506395000
 test master 1 - Starting Memory Read, at          26506725000
 test master 1 - Starting Memory Read, at          26507265000
 test master 1 - Starting Memory Read, at          26507595000
 test master 1 - Starting Memory Read, at          26508135000
 test master 1 - Starting Memory Read, at          26508465000
 test master 2 - Starting Memory Write, at          26509845000
 test master 2 - Starting Memory Write, at          26510145000
 test master 2 - Starting Memory Write, at          26510445000
 test master 2 - Starting Memory Write, at          26510745000
 test master 2 - Starting Memory Write, at          26511045000
 test master 1 - Starting Memory Read, at          26511465000
 test master 1 - Starting Memory Read, at          26511795000
 test master 1 - Starting Memory Read, at          26512335000
 test master 1 - Starting Memory Read, at          26512665000
 test master 1 - Starting Memory Read, at          26513205000
 test master 1 - Starting Memory Read, at          26513535000
 test master 2 - Starting Memory Write, at          26515515000
 test master 2 - Starting Memory Write, at          26516745000
 test master 2 - Starting Memory Write, at          26518005000
 test master 2 - Starting Memory Write, at          26519265000
 test master 2 - Starting Memory Write, at          26521845000
 test master 2 - Starting Memory Write, at          26523105000
 test master 2 - Starting Memory Write, at          26524365000
 test master 2 - Starting Memory Write, at          26525625000
 test master 2 - Starting Memory Write, at          26528205000
 test master 2 - Starting Memory Write, at          26530575000
 test master 2 - Starting Memory Write, at          26532915000
 test master 2 - Starting Memory Write, at          26535255000
 test master 2 - Starting Memory Write, at          26538915000
 test master 2 - Starting Memory Write, at          26541555000
 test master 2 - Starting Memory Write, at          26544195000
 test master 2 - Starting Memory Write, at          26546835000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          26551605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26551635000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26554125000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          26554425000
 test master 2 - Starting Memory Read, at          26554605000
 test master 2 - Starting Memory Read, at          26554785000
 test master 2 - Starting Memory Read, at          26555025000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26556705000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          26557155000
 test master 2 - Starting Memory Read, at          26557335000
 test master 2 - Starting Memory Read, at          26557755000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26559315000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26559885000
 test master 2 - Starting Memory Read Line Multiple, at          26560065000
 test master 2 - Starting Memory Read Line Multiple, at          26560245000
 test master 2 - Starting Memory Read Line Multiple, at          26560425000
 test master 2 - Starting Memory Read Line Multiple, at          26560725000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26562585000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26571435000
 test master 2 - Starting Memory Read Line Multiple, at          26571615000
 test master 2 - Starting Memory Read Line Multiple, at          26571795000
 test master 2 - Starting Memory Read Line Multiple, at          26571975000
 test master 2 - Starting Memory Read Line Multiple, at          26572305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26572845000
 test master 2 - Starting Memory Read Line Multiple, at          26573025000
 test master 2 - Starting Memory Read Line Multiple, at          26573205000
 test master 2 - Starting Memory Read Line Multiple, at          26573385000
 test master 2 - Starting Memory Read Line Multiple, at          26573685000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26574225000
 test master 2 - Starting Memory Read Line Multiple, at          26574405000
 test master 2 - Starting Memory Read Line Multiple, at          26574585000
 test master 2 - Starting Memory Read Line Multiple, at          26574765000
 test master 2 - Starting Memory Read Line Multiple, at          26575065000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26575605000
 test master 2 - Starting Memory Read Line Multiple, at          26575785000
 test master 2 - Starting Memory Read Line Multiple, at          26575965000
 test master 2 - Starting Memory Read Line Multiple, at          26576145000
 test master 2 - Starting Memory Read Line Multiple, at          26576445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26576985000
 test master 2 - Starting Memory Read Line Multiple, at          26577165000
 test master 2 - Starting Memory Read Line Multiple, at          26577345000
 test master 2 - Starting Memory Read Line Multiple, at          26577525000
 test master 2 - Starting Memory Read Line Multiple, at          26577825000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26578365000
 test master 2 - Starting Memory Read Line Multiple, at          26578545000
 test master 2 - Starting Memory Read Line Multiple, at          26578725000
 test master 2 - Starting Memory Read Line Multiple, at          26578905000
 test master 2 - Starting Memory Read Line Multiple, at          26579205000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26579745000
 test master 2 - Starting Memory Read Line Multiple, at          26579925000
 test master 2 - Starting Memory Read Line Multiple, at          26580105000
 test master 2 - Starting Memory Read Line Multiple, at          26580285000
 test master 2 - Starting Memory Read Line Multiple, at          26580585000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          26581125000
 test master 2 - Starting Memory Read Line Multiple, at          26581305000
 test master 2 - Starting Memory Read Line Multiple, at          26581485000
 test master 2 - Starting Memory Read Line Multiple, at          26581665000
 test master 2 - Starting Memory Read Line Multiple, at          26581965000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          26582505000
 test master 2 - Starting Memory Read Line, at          26582685000
 test master 2 - Starting Memory Read Line, at          26582865000
 test master 2 - Starting Memory Read Line, at          26583105000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          26583465000
 test master 2 - Starting Memory Read Line, at          26583645000
 test master 2 - Starting Memory Read Line, at          26584065000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26585325000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26587095000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26590365000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          26592405000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          26597835000
 test master 2 - Starting Memory Write, at          26598135000
 test master 2 - Starting Memory Write, at          26598435000
 test master 2 - Starting Memory Write, at          26598735000
 test master 2 - Starting Memory Write, at          26599035000
 test master 1 - Starting Memory Read, at          26599455000
 test master 1 - Starting Memory Read, at          26599785000
 test master 1 - Starting Memory Read, at          26600325000
 test master 1 - Starting Memory Read, at          26600655000
 test master 1 - Starting Memory Read, at          26601195000
 test master 1 - Starting Memory Read, at          26601525000
 test master 2 - Starting Memory Write, at          26602905000
 test master 2 - Starting Memory Write, at          26603205000
 test master 2 - Starting Memory Write, at          26603505000
 test master 2 - Starting Memory Write, at          26603805000
 test master 2 - Starting Memory Write, at          26604105000
 test master 1 - Starting Memory Read, at          26604525000
 test master 1 - Starting Memory Read, at          26604855000
 test master 1 - Starting Memory Read, at          26605395000
 test master 1 - Starting Memory Read, at          26605725000
 test master 1 - Starting Memory Read, at          26606265000
 test master 1 - Starting Memory Read, at          26606595000
 test master 2 - Starting Memory Write, at          26608575000
 test master 2 - Starting Memory Write, at          26609805000
 test master 2 - Starting Memory Write, at          26611065000
 test master 2 - Starting Memory Write, at          26612325000
 test master 2 - Starting Memory Write, at          26614905000
 test master 2 - Starting Memory Write, at          26616165000
 test master 2 - Starting Memory Write, at          26617425000
 test master 2 - Starting Memory Write, at          26618685000
 test master 2 - Starting Memory Write, at          26621265000
 test master 2 - Starting Memory Write, at          26623635000
 test master 2 - Starting Memory Write, at          26625975000
 test master 2 - Starting Memory Write, at          26628315000
 test master 2 - Starting Memory Write, at          26631975000
 test master 2 - Starting Memory Write, at          26634615000
 test master 2 - Starting Memory Write, at          26637255000
 test master 2 - Starting Memory Write, at          26639895000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          26644665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26644695000
 test master 1 - Starting Memory Read, at          26647185000
 test master 1 - Starting Memory Read, at          26647545000
 test master 1 - Starting Memory Read, at          26648925000
 test master 1 - Starting Memory Read, at          26649285000
 test master 1 - Starting Memory Read Line, at          26650665000
 test master 1 - Starting Memory Read Line, at          26651025000
 test master 1 - Starting Memory Read Line, at          26652405000
 test master 1 - Starting Memory Read Line, at          26652825000
 test master 1 - Starting Memory Read Line, at          26654265000
 test master 1 - Starting Memory Read Line, at          26654865000
 test master 1 - Starting Memory Read Line, at          26656425000
 test master 1 - Starting Memory Read Line, at          26657025000
 test master 1 - Starting Memory Read Line Multiple, at          26658585000
 test master 1 - Starting Memory Read Line Multiple, at          26659425000
 test master 1 - Starting Memory Read Line Multiple, at          26661165000
 test master 1 - Starting Memory Read Line Multiple, at          26662005000
 test master 1 - Starting Memory Read Line, at          26663745000
 test master 1 - Starting Memory Read Line, at          26664345000
 test master 1 - Starting Memory Read, at          26667165000
 test master 1 - Starting Memory Read, at          26667525000
 test target 1 - Starting Config Write, at          26671335000
 test master 1 - Starting Memory Write, at          26672025000
 test master 1 - Starting Memory Write, at          26675805000
 test master 1 - Starting Memory Write, at          26680875000
 test master 1 - Starting Memory Write, at          26684415000
 test master 1 - Starting Memory Write, at          26689335000
 test master 1 - Starting Memory Read Line, at          26693115000
 test master 1 - Starting Memory Write, at          26698575000
 test master 1 - Starting Memory Read Line, at          26702355000
 test target 1 - Starting Config Write, at          26709795000
 test master 1 - Starting Memory Write, at          26710485000
 test master 1 - Starting Memory Write, at          26710605000
 test master 1 - Starting Memory Write, at          26710905000
 test master 1 - Starting Memory Read, at          26711025000
 test master 1 - Starting Memory Write, at          26711385000
 test master 1 - Starting Memory Read, at          26711505000
 test master 1 - Starting Memory Write, at          26713455000
 test master 1 - Starting Memory Write, at          26722275000
 test master 2 - Starting Memory Read Line, at          26731215000
 test master 2 - Starting Memory Read Line, at          26731785000
 test master 2 - Starting Memory Read Line, at          26732175000
 test master 2 - Starting Memory Read Line, at          26732745000
 test master 1 - Starting Memory Write, at          26733225000
 test master 1 - Starting Memory Write, at          26733525000
 test master 1 - Starting Memory Write, at          26733825000
 test master 2 - Starting Memory Read Line, at          26734245000
 test master 2 - Starting Memory Read Line, at          26734605000
 test master 2 - Starting Memory Read Line, at          26734845000
 test master 2 - Starting Memory Read Line, at          26735205000
 test master 2 - Starting Memory Read Line Multiple, at          26735475000
 test master 2 - Starting Memory Read Line Multiple, at          26735835000
 test master 1 - Starting Memory Write, at          26738025000
 test master 1 - Starting Memory Write, at          26738325000
 test master 2 - Starting Memory Read, at          26738745000
 test master 2 - Starting Memory Read, at          26739105000
 test master 2 - Starting Memory Read, at          26739345000
 test master 2 - Starting Memory Read, at          26739705000
 test master 1 - Starting Memory Write, at          26741595000
 test master 1 - Starting Memory Read, at          26741775000
 test master 1 - Starting Memory Write, at          26741955000
 test master 1 - Starting Memory Read, at          26742165000
 test master 1 - Starting Memory Write, at          26742375000
 test master 1 - Starting Memory Read, at          26742555000
 test master 1 - Starting Memory Read, at          26742765000
 test master 1 - Starting Memory Write, at          26742975000
 test master 1 - Starting Memory Write, at          26743155000
 test master 1 - Starting Memory Read, at          26743335000
 test master 1 - Starting Memory Write, at          26743515000
 test master 1 - Starting Memory Write, at          26743725000
 test master 1 - Starting Memory Write, at          26743935000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          26749155000
 test target 1 - Starting Memory Write, at          26749395000
 test master 1 - Starting Memory Write, at          26749605000
 test target 1 - Starting Memory Write, at          26749785000
 test target 1 - Starting Memory Write, at          26750025000
 test target 1 - Starting Memory Write, at          26750265000
 test master 1 - Starting Memory Write, at          26750595000
 test target 1 - Starting Memory Write, at          26751165000
 test target 1 - Starting Memory Write, at          26751795000
 test target 1 - Starting Memory Write, at          26752065000
 test master 1 - Starting Memory Write, at          26752305000
 test target 1 - Starting Memory Write, at          26752605000
 test target 1 - Starting Memory Write, at          26752875000
 test target 1 - Starting Memory Write, at          26753145000
 test master 1 - Starting Memory Write, at          26753595000
 test target 1 - Starting Memory Write, at          26754435000
 test target 1 - Starting Memory Write, at          26755395000
 test target 1 - Starting Memory Write, at          26755635000
 test master 1 - Starting Memory Read, at          26755845000
 test target 1 - Starting Memory Write, at          26756025000
 test master 1 - Starting Memory Read, at          26756235000
 test target 1 - Starting Memory Write, at          26756415000
 test master 1 - Starting Memory Read, at          26756625000
 test target 1 - Starting Memory Write, at          26756805000
 test master 1 - Starting Memory Read, at          26757015000
 test target 1 - Starting Memory Write, at          26757195000
 test master 1 - Starting Memory Read, at          26757405000
 test target 1 - Starting Memory Write, at          26757585000
 test master 1 - Starting Memory Write, at          26757795000
 test target 1 - Starting Memory Write, at          26757975000
 test target 1 - Starting Memory Write, at          26758215000
 test target 1 - Starting Memory Write, at          26758455000
 test target 1 - Starting Memory Read, at          26758755000
 test master 1 - Starting Memory Write, at          26759085000
 test master 1 - Starting Memory Read, at          26759295000
 test target 1 - Starting Memory Write, at          26759805000
 test master 1 - Starting Memory Write, at          26760195000
 test target 1 - Starting Memory Read, at          26760645000
 test target 1 - Starting Memory Write, at          26761455000
 test master 1 - Starting Memory Read, at          26761785000
 test master 1 - Starting Memory Write, at          26762175000
 test master 1 - Starting Memory Write, at          26762535000
 test master 1 - Starting Memory Read, at          26762835000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          26765685000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          26766825000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          26794155000
 test target 1 - Starting Config Write, at          26795205000
 test target 1 - Starting Config Write, at          26796225000
 test target 2 - Starting Config Write, at          26797275000
 test target 2 - Starting Config Write, at          26798325000
 test target 2 - Starting Config Write, at          26799345000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          26801625000
 test target 1 - Starting Memory Read, at          26801835000
 test target 1 - Starting Memory Write, at          26802585000
 test target 1 - Starting Memory Read, at          26802795000
 test target 1 - Starting Memory Write, at          26804175000
 test target 1 - Starting Memory Read, at          26805015000
 test target 1 - Starting Memory Read, at          26805555000
 test target 1 - Starting Memory Read, at          26806245000
 test target 1 - Starting Memory Read, at          26806755000
 test target 1 - Starting Memory Read, at          26807595000
 test target 1 - Starting Memory Read, at          26808675000
 test target 1 - Starting Memory Read, at          26809695000
 test target 1 - Starting Memory Read, at          26810775000
 test target 1 - Starting Memory Read, at          26811795000
 test target 1 - Starting Memory Read, at          26813265000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          26820525000
 test target 1 - Starting Memory Read, at          26820735000
 test target 1 - Starting Memory Write, at          26821485000
 test target 1 - Starting Memory Read, at          26821695000
 test target 1 - Starting Memory Write, at          26823075000
 test target 1 - Starting Memory Read, at          26823915000
 test target 1 - Starting Memory Read, at          26824455000
 test target 1 - Starting Memory Read, at          26825145000
 test target 1 - Starting Memory Read, at          26825655000
 test target 1 - Starting Memory Read, at          26826495000
 test target 1 - Starting Memory Read, at          26827575000
 test target 1 - Starting Memory Read, at          26828595000
 test target 1 - Starting Memory Read, at          26829675000
 test target 1 - Starting Memory Read, at          26830695000
 test target 1 - Starting Memory Read, at          26832165000
 test target 1 - Starting Memory Write, at          26839425000
 test target 1 - Starting Memory Read, at          26839635000
 test target 1 - Starting Memory Write, at          26840385000
 test target 1 - Starting Memory Read, at          26840595000
 test target 1 - Starting Memory Write, at          26841975000
 test target 1 - Starting Memory Read, at          26842815000
 test target 1 - Starting Memory Read, at          26843355000
 test target 1 - Starting Memory Read, at          26844045000
 test target 1 - Starting Memory Read, at          26844555000
 test target 1 - Starting Memory Read, at          26845395000
 test target 1 - Starting Memory Read, at          26846475000
 test target 1 - Starting Memory Read, at          26847495000
 test target 1 - Starting Memory Read, at          26848575000
 test target 1 - Starting Memory Read, at          26849595000
 test target 1 - Starting Memory Read, at          26851065000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          26865705000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          26873235000
 test target 1 - Starting Memory Write, at          26874255000
 test target 1 - Starting Memory Read, at          26874525000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          26875785000
 test target 1 - Starting Config Write, at          26877945000
 test target 1 - Starting Memory Read, at          26878695000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          26880435000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          26882895000
 test target 1 - Starting Memory Write, at          26884245000
 test target 1 - Starting Memory Write, at          26884485000
 test target 1 - Starting Memory Read, at          26884695000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          26887695000
 test target 1 - Starting Memory Write, at          26891295000
 test target 1 - Starting Memory Write, at          26891715000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          26896245000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          26898555000
 test target 1 - Starting Memory Read, at          26900115000
 test target 1 - Starting Memory Read, at          26901075000
 test target 1 - Starting Memory Read, at          26902815000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          26909805000
 test target 2 - Starting Config Write, at          26910825000
 test target 1 - Starting Memory Write, at          26911575000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          26911695000
 test target 1 - Starting Memory Write, at          26912865000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          26912985000
 test target 1 - Starting Memory Write, at          26914155000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          26915715000
 test target 1 - Starting Memory Read, at          26918295000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          26918415000
 test target 1 - Starting Memory Read, at          26920935000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          26922975000
 test master 2 - Starting Memory Write, at          26922975000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          26923035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26923965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26923995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26924295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26924325000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26925345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26925375000
 test target 1 - Starting Memory Write, at          26927445000
 test master 2 - Starting Memory Write, at          26927445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26929395000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26929425000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26931375000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26931405000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26933355000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26933385000
 test target 1 - Starting Memory Write, at          26935755000
 test master 2 - Starting Memory Write, at          26935755000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          26935815000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26937675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26937705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26938005000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26938035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26939055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          26939085000
 test target 1 - Starting Memory Write, at          26940405000
 test master 2 - Starting Memory Write, at          26940405000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          26943855000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          26945745000
 test master 1 - Starting Memory Read, at          26946045000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          26946195000
 test target 1 - Starting Config Write, at          26949225000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          26952045000
 test target 1 - Starting Memory Write, at          26952195000
 test target 1 - Starting Memory Write, at          26952345000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          26952885000
 test target 1 - Starting Memory Write, at          26953065000
 test target 1 - Starting Memory Write, at          26953245000
 test target 1 - Starting Memory Write, at          26953785000
 test target 1 - Starting Memory Write, at          26953965000
 test target 1 - Starting Memory Write, at          26954505000
 test target 1 - Starting Memory Write, at          26955195000
 test target 1 - Starting Memory Write, at          26955375000
 test target 1 - Starting Memory Write, at          26956065000
 test target 1 - Starting Memory Write, at          26956275000
 test target 1 - Starting Memory Write, at          26956935000
 test target 1 - Starting Memory Write, at          26964795000
 test target 1 - Starting Memory Write, at          26964975000
 test target 1 - Starting Memory Write, at          26965155000
 test target 1 - Starting Memory Write, at          26965365000
 test target 1 - Starting Memory Write, at          26965575000
 test target 1 - Starting Memory Read, at          26967495000
 test target 1 - Starting Memory Read, at          26968545000
 test target 1 - Starting Memory Read, at          26969595000
 test target 1 - Starting Memory Read, at          26970675000
 test target 1 - Starting Memory Read, at          26971725000
 test target 1 - Starting Memory Read, at          26972775000
 test target 1 - Starting Memory Read, at          26973855000
 test target 1 - Starting Memory Read, at          26974905000
 test target 1 - Starting Memory Read, at          26975955000
 test target 1 - Starting Memory Read, at          26977035000
 test target 1 - Starting Memory Read, at          26978085000
 test target 1 - Starting Memory Read, at          26979135000
 test target 1 - Starting Memory Read, at          26980215000
 test target 1 - Starting Memory Read, at          26981265000
 test target 1 - Starting Memory Read, at          26982315000
 test target 1 - Starting Memory Read, at          26983395000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          26984235000
 test target 1 - Starting Memory Read, at          26984385000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          26986995000
 test target 1 - Starting Memory Read, at          26987655000
 test target 1 - Starting Memory Read, at          26988315000
 test target 1 - Starting Memory Read, at          26989065000
 test target 1 - Starting Memory Read, at          26989725000
 test target 1 - Starting Memory Read, at          26990535000
 test target 1 - Starting Memory Read, at          26991675000
 test target 1 - Starting Memory Read, at          26992725000
 test target 1 - Starting Memory Read, at          26993775000
 test target 1 - Starting Memory Read, at          26996415000
 test target 1 - Starting Memory Read, at          26998035000
 test target 1 - Starting Memory Read, at          26998875000
 test target 1 - Starting Memory Read, at          26999715000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          27001215000
 test master 1 - Starting Memory Write, at          27001425000
 test target 1 - Starting Memory Write, at          27001425000
 test target 1 - Starting Memory Write, at          27001575000
 test target 1 - Starting Memory Read, at          27001815000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          27003555000
 test master 1 - Starting Memory Write, at          27003765000
 test target 1 - Starting Memory Write, at          27003765000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          27009225000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          27010365000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          27037695000
 test target 1 - Starting Config Write, at          27038745000
 test target 1 - Starting Config Write, at          27039765000
 test target 2 - Starting Config Write, at          27040815000
 test target 2 - Starting Config Write, at          27041865000
 test target 2 - Starting Config Write, at          27042885000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          27045165000
 test target 1 - Starting Memory Read, at          27045405000
 test target 1 - Starting Memory Write, at          27046125000
 test target 1 - Starting Memory Read, at          27046365000
 test target 1 - Starting Memory Write, at          27047715000
 test target 1 - Starting Memory Read, at          27048555000
 test target 1 - Starting Memory Read, at          27049275000
 test target 1 - Starting Memory Read, at          27049965000
 test target 1 - Starting Memory Read, at          27050655000
 test target 1 - Starting Memory Read, at          27051675000
 test target 1 - Starting Memory Read, at          27052755000
 test target 1 - Starting Memory Read, at          27053775000
 test target 1 - Starting Memory Read, at          27054855000
 test target 1 - Starting Memory Read, at          27055875000
 test target 1 - Starting Memory Read, at          27057345000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          27064605000
 test target 1 - Starting Memory Read, at          27064845000
 test target 1 - Starting Memory Write, at          27065565000
 test target 1 - Starting Memory Read, at          27065805000
 test target 1 - Starting Memory Write, at          27067155000
 test target 1 - Starting Memory Read, at          27067995000
 test target 1 - Starting Memory Read, at          27068715000
 test target 1 - Starting Memory Read, at          27069405000
 test target 1 - Starting Memory Read, at          27070095000
 test target 1 - Starting Memory Read, at          27071115000
 test target 1 - Starting Memory Read, at          27072195000
 test target 1 - Starting Memory Read, at          27073215000
 test target 1 - Starting Memory Read, at          27074295000
 test target 1 - Starting Memory Read, at          27075315000
 test target 1 - Starting Memory Read, at          27076785000
 test target 1 - Starting Memory Write, at          27084045000
 test target 1 - Starting Memory Read, at          27084285000
 test target 1 - Starting Memory Write, at          27085005000
 test target 1 - Starting Memory Read, at          27085245000
 test target 1 - Starting Memory Write, at          27086595000
 test target 1 - Starting Memory Read, at          27087435000
 test target 1 - Starting Memory Read, at          27088155000
 test target 1 - Starting Memory Read, at          27088845000
 test target 1 - Starting Memory Read, at          27089535000
 test target 1 - Starting Memory Read, at          27090555000
 test target 1 - Starting Memory Read, at          27091635000
 test target 1 - Starting Memory Read, at          27092655000
 test target 1 - Starting Memory Read, at          27093735000
 test target 1 - Starting Memory Read, at          27094755000
 test target 1 - Starting Memory Read, at          27096225000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          27110865000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          27118395000
 test target 1 - Starting Memory Write, at          27119415000
 test target 1 - Starting Memory Read, at          27119715000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          27120945000
 test target 1 - Starting Config Write, at          27123105000
 test target 1 - Starting Memory Read, at          27123855000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          27125595000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          27128055000
 test target 1 - Starting Memory Write, at          27129405000
 test target 1 - Starting Memory Write, at          27129675000
 test target 1 - Starting Memory Read, at          27129915000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          27132855000
 test target 1 - Starting Memory Write, at          27136515000
 test target 1 - Starting Memory Write, at          27136935000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          27141525000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          27143835000
 test target 1 - Starting Memory Read, at          27145395000
 test target 1 - Starting Memory Read, at          27146355000
 test target 1 - Starting Memory Read, at          27148095000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          27155085000
 test target 2 - Starting Config Write, at          27156105000
 test target 1 - Starting Memory Write, at          27156855000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          27157005000
 test target 1 - Starting Memory Write, at          27158175000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          27158325000
 test target 1 - Starting Memory Write, at          27159495000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          27161115000
 test target 1 - Starting Memory Read, at          27163695000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          27163845000
 test target 1 - Starting Memory Read, at          27166335000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          27168375000
 test master 2 - Starting Memory Write, at          27168375000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          27168435000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27169395000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27169425000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27169725000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27169755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27170775000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27170805000
 test target 1 - Starting Memory Write, at          27172875000
 test master 2 - Starting Memory Write, at          27172875000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27174855000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27174885000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27176835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27176865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27178815000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27178845000
 test target 1 - Starting Memory Write, at          27181215000
 test master 2 - Starting Memory Write, at          27181215000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          27181275000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27183165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27183195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27183495000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27183525000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27184545000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27184575000
 test target 1 - Starting Memory Write, at          27185895000
 test master 2 - Starting Memory Write, at          27185895000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          27189375000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          27191265000
 test master 1 - Starting Memory Read, at          27191565000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          27191715000
 test target 1 - Starting Config Write, at          27194745000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          27197565000
 test target 1 - Starting Memory Write, at          27197745000
 test target 1 - Starting Memory Write, at          27197925000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          27198495000
 test target 1 - Starting Memory Write, at          27198705000
 test target 1 - Starting Memory Write, at          27198915000
 test target 1 - Starting Memory Write, at          27199485000
 test target 1 - Starting Memory Write, at          27199695000
 test target 1 - Starting Memory Write, at          27200265000
 test target 1 - Starting Memory Write, at          27200985000
 test target 1 - Starting Memory Write, at          27201195000
 test target 1 - Starting Memory Write, at          27201915000
 test target 1 - Starting Memory Write, at          27202155000
 test target 1 - Starting Memory Write, at          27202845000
 test target 1 - Starting Memory Write, at          27210735000
 test target 1 - Starting Memory Write, at          27210945000
 test target 1 - Starting Memory Write, at          27211155000
 test target 1 - Starting Memory Write, at          27211395000
 test target 1 - Starting Memory Write, at          27211635000
 test target 1 - Starting Memory Read, at          27213585000
 test target 1 - Starting Memory Read, at          27214665000
 test target 1 - Starting Memory Read, at          27215715000
 test target 1 - Starting Memory Read, at          27216795000
 test target 1 - Starting Memory Read, at          27217845000
 test target 1 - Starting Memory Read, at          27218895000
 test target 1 - Starting Memory Read, at          27219975000
 test target 1 - Starting Memory Read, at          27221025000
 test target 1 - Starting Memory Read, at          27222075000
 test target 1 - Starting Memory Read, at          27223155000
 test target 1 - Starting Memory Read, at          27224205000
 test target 1 - Starting Memory Read, at          27225255000
 test target 1 - Starting Memory Read, at          27226335000
 test target 1 - Starting Memory Read, at          27227385000
 test target 1 - Starting Memory Read, at          27228435000
 test target 1 - Starting Memory Read, at          27229515000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          27230355000
 test target 1 - Starting Memory Read, at          27230535000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          27233115000
 test target 1 - Starting Memory Read, at          27233805000
 test target 1 - Starting Memory Read, at          27234435000
 test target 1 - Starting Memory Read, at          27235185000
 test target 1 - Starting Memory Read, at          27236025000
 test target 1 - Starting Memory Read, at          27236805000
 test target 1 - Starting Memory Read, at          27237915000
 test target 1 - Starting Memory Read, at          27238995000
 test target 1 - Starting Memory Read, at          27240015000
 test target 1 - Starting Memory Read, at          27242655000
 test target 1 - Starting Memory Read, at          27244335000
 test target 1 - Starting Memory Read, at          27245355000
 test target 1 - Starting Memory Read, at          27246375000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          27248055000
 test master 1 - Starting Memory Write, at          27248265000
 test target 1 - Starting Memory Write, at          27248265000
 test target 1 - Starting Memory Write, at          27248445000
 test target 1 - Starting Memory Read, at          27248745000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          27250395000
 test master 1 - Starting Memory Write, at          27250605000
 test target 1 - Starting Memory Write, at          27250605000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          27256065000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          27257205000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          27284535000
 test target 1 - Starting Config Write, at          27285585000
 test target 1 - Starting Config Write, at          27286605000
 test target 2 - Starting Config Write, at          27287655000
 test target 2 - Starting Config Write, at          27288705000
 test target 2 - Starting Config Write, at          27289725000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          27292005000
 test target 1 - Starting Memory Read, at          27292275000
 test target 1 - Starting Memory Write, at          27292965000
 test target 1 - Starting Memory Read, at          27293235000
 test target 1 - Starting Memory Write, at          27294555000
 test target 1 - Starting Memory Read, at          27295455000
 test target 1 - Starting Memory Read, at          27296175000
 test target 1 - Starting Memory Read, at          27296865000
 test target 1 - Starting Memory Read, at          27297555000
 test target 1 - Starting Memory Read, at          27298575000
 test target 1 - Starting Memory Read, at          27299655000
 test target 1 - Starting Memory Read, at          27300675000
 test target 1 - Starting Memory Read, at          27301755000
 test target 1 - Starting Memory Read, at          27302775000
 test target 1 - Starting Memory Read, at          27304245000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          27311505000
 test target 1 - Starting Memory Read, at          27311775000
 test target 1 - Starting Memory Write, at          27312465000
 test target 1 - Starting Memory Read, at          27312735000
 test target 1 - Starting Memory Write, at          27314055000
 test target 1 - Starting Memory Read, at          27314955000
 test target 1 - Starting Memory Read, at          27315675000
 test target 1 - Starting Memory Read, at          27316365000
 test target 1 - Starting Memory Read, at          27317055000
 test target 1 - Starting Memory Read, at          27318075000
 test target 1 - Starting Memory Read, at          27319155000
 test target 1 - Starting Memory Read, at          27320175000
 test target 1 - Starting Memory Read, at          27321255000
 test target 1 - Starting Memory Read, at          27322275000
 test target 1 - Starting Memory Read, at          27323745000
 test target 1 - Starting Memory Write, at          27331005000
 test target 1 - Starting Memory Read, at          27331275000
 test target 1 - Starting Memory Write, at          27331965000
 test target 1 - Starting Memory Read, at          27332235000
 test target 1 - Starting Memory Write, at          27333555000
 test target 1 - Starting Memory Read, at          27334455000
 test target 1 - Starting Memory Read, at          27335175000
 test target 1 - Starting Memory Read, at          27335865000
 test target 1 - Starting Memory Read, at          27336555000
 test target 1 - Starting Memory Read, at          27337575000
 test target 1 - Starting Memory Read, at          27338655000
 test target 1 - Starting Memory Read, at          27339675000
 test target 1 - Starting Memory Read, at          27340755000
 test target 1 - Starting Memory Read, at          27341775000
 test target 1 - Starting Memory Read, at          27343245000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          27357885000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          27365415000
 test target 1 - Starting Memory Write, at          27366435000
 test target 1 - Starting Memory Read, at          27366765000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          27368145000
 test target 1 - Starting Config Write, at          27370305000
 test target 1 - Starting Memory Read, at          27371055000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          27372795000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          27375255000
 test target 1 - Starting Memory Write, at          27376605000
 test target 1 - Starting Memory Write, at          27376905000
 test target 1 - Starting Memory Read, at          27377175000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          27380055000
 test target 1 - Starting Memory Write, at          27383715000
 test target 1 - Starting Memory Write, at          27384135000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          27388725000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          27391035000
 test target 1 - Starting Memory Read, at          27392595000
 test target 1 - Starting Memory Read, at          27393555000
 test target 1 - Starting Memory Read, at          27395295000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          27402285000
 test target 2 - Starting Config Write, at          27403305000
 test target 1 - Starting Memory Write, at          27404055000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          27404235000
 test target 1 - Starting Memory Write, at          27405405000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          27405585000
 test target 1 - Starting Memory Write, at          27406755000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          27408375000
 test target 1 - Starting Memory Read, at          27410955000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          27411135000
 test target 1 - Starting Memory Read, at          27413595000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          27415635000
 test master 2 - Starting Memory Write, at          27415635000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          27415695000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27416685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27416715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27417015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27417045000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27418065000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27418095000
 test target 1 - Starting Memory Write, at          27420165000
 test master 2 - Starting Memory Write, at          27420165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27422175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27422205000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27424155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27424185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27426135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27426165000
 test target 1 - Starting Memory Write, at          27428535000
 test master 2 - Starting Memory Write, at          27428535000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          27428595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27430515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27430545000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27430845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27430875000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27431895000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27431925000
 test target 1 - Starting Memory Write, at          27433245000
 test master 2 - Starting Memory Write, at          27433245000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          27436755000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          27438645000
 test master 1 - Starting Memory Read, at          27438945000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          27439095000
 test target 1 - Starting Config Write, at          27442125000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          27445185000
 test target 1 - Starting Memory Write, at          27445395000
 test target 1 - Starting Memory Write, at          27445605000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          27446205000
 test target 1 - Starting Memory Write, at          27446445000
 test target 1 - Starting Memory Write, at          27446685000
 test target 1 - Starting Memory Write, at          27447285000
 test target 1 - Starting Memory Write, at          27447525000
 test target 1 - Starting Memory Write, at          27448125000
 test target 1 - Starting Memory Write, at          27448875000
 test target 1 - Starting Memory Write, at          27449115000
 test target 1 - Starting Memory Write, at          27449865000
 test target 1 - Starting Memory Write, at          27450135000
 test target 1 - Starting Memory Write, at          27450855000
 test target 1 - Starting Memory Write, at          27458775000
 test target 1 - Starting Memory Write, at          27459015000
 test target 1 - Starting Memory Write, at          27459255000
 test target 1 - Starting Memory Write, at          27459525000
 test target 1 - Starting Memory Write, at          27459795000
 test target 1 - Starting Memory Read, at          27461775000
 test target 1 - Starting Memory Read, at          27462885000
 test target 1 - Starting Memory Read, at          27463935000
 test target 1 - Starting Memory Read, at          27465015000
 test target 1 - Starting Memory Read, at          27466065000
 test target 1 - Starting Memory Read, at          27467115000
 test target 1 - Starting Memory Read, at          27468195000
 test target 1 - Starting Memory Read, at          27469245000
 test target 1 - Starting Memory Read, at          27470295000
 test target 1 - Starting Memory Read, at          27471375000
 test target 1 - Starting Memory Read, at          27472425000
 test target 1 - Starting Memory Read, at          27473475000
 test target 1 - Starting Memory Read, at          27474555000
 test target 1 - Starting Memory Read, at          27475605000
 test target 1 - Starting Memory Read, at          27476655000
 test target 1 - Starting Memory Read, at          27477735000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          27478575000
 test target 1 - Starting Memory Read, at          27478785000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          27481335000
 test target 1 - Starting Memory Read, at          27482055000
 test target 1 - Starting Memory Read, at          27482895000
 test target 1 - Starting Memory Read, at          27483645000
 test target 1 - Starting Memory Read, at          27484485000
 test target 1 - Starting Memory Read, at          27485265000
 test target 1 - Starting Memory Read, at          27486375000
 test target 1 - Starting Memory Read, at          27487455000
 test target 1 - Starting Memory Read, at          27488475000
 test target 1 - Starting Memory Read, at          27491295000
 test target 1 - Starting Memory Read, at          27492915000
 test target 1 - Starting Memory Read, at          27493935000
 test target 1 - Starting Memory Read, at          27494955000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          27496635000
 test master 1 - Starting Memory Write, at          27496845000
 test target 1 - Starting Memory Write, at          27496845000
 test target 1 - Starting Memory Write, at          27497055000
 test target 1 - Starting Memory Read, at          27497415000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          27499155000
 test master 1 - Starting Memory Write, at          27499365000
 test target 1 - Starting Memory Write, at          27499365000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          27504825000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          27505965000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          27533295000
 test target 1 - Starting Config Write, at          27534345000
 test target 1 - Starting Config Write, at          27535365000
 test target 2 - Starting Config Write, at          27536415000
 test target 2 - Starting Config Write, at          27537465000
 test target 2 - Starting Config Write, at          27538485000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          27540765000
 test target 1 - Starting Memory Read, at          27541065000
 test target 1 - Starting Memory Write, at          27541965000
 test target 1 - Starting Memory Read, at          27542265000
 test target 1 - Starting Memory Write, at          27543795000
 test target 1 - Starting Memory Read, at          27544695000
 test target 1 - Starting Memory Read, at          27545415000
 test target 1 - Starting Memory Read, at          27546105000
 test target 1 - Starting Memory Read, at          27546795000
 test target 1 - Starting Memory Read, at          27547815000
 test target 1 - Starting Memory Read, at          27548895000
 test target 1 - Starting Memory Read, at          27549915000
 test target 1 - Starting Memory Read, at          27550995000
 test target 1 - Starting Memory Read, at          27552015000
 test target 1 - Starting Memory Read, at          27553485000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          27560985000
 test target 1 - Starting Memory Read, at          27561285000
 test target 1 - Starting Memory Write, at          27562185000
 test target 1 - Starting Memory Read, at          27562485000
 test target 1 - Starting Memory Write, at          27564015000
 test target 1 - Starting Memory Read, at          27564915000
 test target 1 - Starting Memory Read, at          27565635000
 test target 1 - Starting Memory Read, at          27566325000
 test target 1 - Starting Memory Read, at          27567015000
 test target 1 - Starting Memory Read, at          27568035000
 test target 1 - Starting Memory Read, at          27569115000
 test target 1 - Starting Memory Read, at          27570135000
 test target 1 - Starting Memory Read, at          27571215000
 test target 1 - Starting Memory Read, at          27572235000
 test target 1 - Starting Memory Read, at          27573705000
 test target 1 - Starting Memory Write, at          27581205000
 test target 1 - Starting Memory Read, at          27581505000
 test target 1 - Starting Memory Write, at          27582405000
 test target 1 - Starting Memory Read, at          27582705000
 test target 1 - Starting Memory Write, at          27584235000
 test target 1 - Starting Memory Read, at          27585135000
 test target 1 - Starting Memory Read, at          27585855000
 test target 1 - Starting Memory Read, at          27586545000
 test target 1 - Starting Memory Read, at          27587235000
 test target 1 - Starting Memory Read, at          27588255000
 test target 1 - Starting Memory Read, at          27589335000
 test target 1 - Starting Memory Read, at          27590355000
 test target 1 - Starting Memory Read, at          27591435000
 test target 1 - Starting Memory Read, at          27592455000
 test target 1 - Starting Memory Read, at          27593925000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          27608805000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          27616335000
 test target 1 - Starting Memory Write, at          27617355000
 test target 1 - Starting Memory Read, at          27617715000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          27619065000
 test target 1 - Starting Config Write, at          27621225000
 test target 1 - Starting Memory Read, at          27621975000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          27623715000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          27626175000
 test target 1 - Starting Memory Write, at          27627525000
 test target 1 - Starting Memory Write, at          27627855000
 test target 1 - Starting Memory Read, at          27628155000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          27631215000
 test target 1 - Starting Memory Write, at          27634935000
 test target 1 - Starting Memory Write, at          27635355000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          27640005000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          27642315000
 test target 1 - Starting Memory Read, at          27643875000
 test target 1 - Starting Memory Read, at          27645015000
 test target 1 - Starting Memory Read, at          27646935000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          27653925000
 test target 2 - Starting Config Write, at          27654945000
 test target 1 - Starting Memory Write, at          27655695000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          27655905000
 test target 1 - Starting Memory Write, at          27657075000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          27657285000
 test target 1 - Starting Memory Write, at          27658455000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          27660135000
 test target 1 - Starting Memory Read, at          27662715000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          27662925000
 test target 1 - Starting Memory Read, at          27665355000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          27667395000
 test master 2 - Starting Memory Write, at          27667395000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          27667455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27668475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27668505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27668805000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27668835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27669855000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27669885000
 test target 1 - Starting Memory Write, at          27671955000
 test master 2 - Starting Memory Write, at          27671955000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27673995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27674025000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27675975000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27676005000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27677955000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27677985000
 test target 1 - Starting Memory Write, at          27680355000
 test master 2 - Starting Memory Write, at          27680355000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          27680415000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27682365000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27682395000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27682695000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27682725000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27683745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27683775000
 test target 1 - Starting Memory Write, at          27685095000
 test master 2 - Starting Memory Write, at          27685095000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          27688635000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          27690525000
 test master 1 - Starting Memory Read, at          27690825000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          27690975000
 test target 1 - Starting Config Write, at          27694005000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          27697065000
 test target 1 - Starting Memory Write, at          27697305000
 test target 1 - Starting Memory Write, at          27697545000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          27698175000
 test target 1 - Starting Memory Write, at          27698445000
 test target 1 - Starting Memory Write, at          27698715000
 test target 1 - Starting Memory Write, at          27699345000
 test target 1 - Starting Memory Write, at          27699615000
 test target 1 - Starting Memory Write, at          27700245000
 test target 1 - Starting Memory Write, at          27701025000
 test target 1 - Starting Memory Write, at          27701295000
 test target 1 - Starting Memory Write, at          27702075000
 test target 1 - Starting Memory Write, at          27702375000
 test target 1 - Starting Memory Write, at          27703125000
 test target 1 - Starting Memory Write, at          27711075000
 test target 1 - Starting Memory Write, at          27711345000
 test target 1 - Starting Memory Write, at          27711615000
 test target 1 - Starting Memory Write, at          27711915000
 test target 1 - Starting Memory Write, at          27712215000
 test target 1 - Starting Memory Read, at          27714225000
 test target 1 - Starting Memory Read, at          27715365000
 test target 1 - Starting Memory Read, at          27716415000
 test target 1 - Starting Memory Read, at          27717495000
 test target 1 - Starting Memory Read, at          27718725000
 test target 1 - Starting Memory Read, at          27719775000
 test target 1 - Starting Memory Read, at          27720855000
 test target 1 - Starting Memory Read, at          27722085000
 test target 1 - Starting Memory Read, at          27723135000
 test target 1 - Starting Memory Read, at          27724215000
 test target 1 - Starting Memory Read, at          27725445000
 test target 1 - Starting Memory Read, at          27726495000
 test target 1 - Starting Memory Read, at          27727575000
 test target 1 - Starting Memory Read, at          27728805000
 test target 1 - Starting Memory Read, at          27729855000
 test target 1 - Starting Memory Read, at          27730935000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          27731955000
 test target 1 - Starting Memory Read, at          27732195000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          27734715000
 test target 1 - Starting Memory Read, at          27735465000
 test target 1 - Starting Memory Read, at          27736275000
 test target 1 - Starting Memory Read, at          27737025000
 test target 1 - Starting Memory Read, at          27737865000
 test target 1 - Starting Memory Read, at          27738645000
 test target 1 - Starting Memory Read, at          27739755000
 test target 1 - Starting Memory Read, at          27740835000
 test target 1 - Starting Memory Read, at          27741855000
 test target 1 - Starting Memory Read, at          27744675000
 test target 1 - Starting Memory Read, at          27746295000
 test target 1 - Starting Memory Read, at          27747315000
 test target 1 - Starting Memory Read, at          27748335000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          27750015000
 test master 1 - Starting Memory Write, at          27750255000
 test target 1 - Starting Memory Write, at          27750255000
 test target 1 - Starting Memory Write, at          27750495000
 test target 1 - Starting Memory Read, at          27750885000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          27752565000
 test master 1 - Starting Memory Write, at          27752805000
 test target 1 - Starting Memory Write, at          27752805000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27758895000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          27759135000
 test master 2 - Starting Memory Read, at          27759315000
 test master 2 - Starting Memory Read, at          27759495000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27761115000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          27761415000
 test master 2 - Starting Memory Read, at          27761595000
 test master 2 - Starting Memory Read, at          27761775000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27763335000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27763665000
 test master 2 - Starting Memory Read Line Multiple, at          27763845000
 test master 2 - Starting Memory Read Line Multiple, at          27764085000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27765795000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27769095000
 test master 2 - Starting Memory Read Line Multiple, at          27769275000
 test master 2 - Starting Memory Read Line Multiple, at          27769545000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27769905000
 test master 2 - Starting Memory Read Line Multiple, at          27770085000
 test master 2 - Starting Memory Read Line Multiple, at          27770325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27770685000
 test master 2 - Starting Memory Read Line Multiple, at          27770865000
 test master 2 - Starting Memory Read Line Multiple, at          27771105000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27771465000
 test master 2 - Starting Memory Read Line Multiple, at          27771645000
 test master 2 - Starting Memory Read Line Multiple, at          27771885000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27772245000
 test master 2 - Starting Memory Read Line Multiple, at          27772425000
 test master 2 - Starting Memory Read Line Multiple, at          27772665000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27773025000
 test master 2 - Starting Memory Read Line Multiple, at          27773205000
 test master 2 - Starting Memory Read Line Multiple, at          27773445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27773805000
 test master 2 - Starting Memory Read Line Multiple, at          27773985000
 test master 2 - Starting Memory Read Line Multiple, at          27774225000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27774585000
 test master 2 - Starting Memory Read Line Multiple, at          27774765000
 test master 2 - Starting Memory Read Line Multiple, at          27775005000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          27775365000
 test master 2 - Starting Memory Read Line, at          27775545000
 test master 2 - Starting Memory Read Line, at          27775725000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          27775995000
 test master 2 - Starting Memory Read Line, at          27776175000
 test master 2 - Starting Memory Read Line, at          27776355000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27777615000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27779415000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27782715000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27784575000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          27789525000
 test master 2 - Starting Memory Write, at          27789765000
 test master 2 - Starting Memory Write, at          27790005000
 test master 2 - Starting Memory Write, at          27790245000
 test master 2 - Starting Memory Write, at          27790485000
 test master 1 - Starting Memory Read, at          27790845000
 test master 1 - Starting Memory Read, at          27791115000
 test master 1 - Starting Memory Read, at          27791655000
 test master 1 - Starting Memory Read, at          27791925000
 test master 1 - Starting Memory Read, at          27792465000
 test master 1 - Starting Memory Read, at          27792735000
 test master 2 - Starting Memory Write, at          27794145000
 test master 2 - Starting Memory Write, at          27794385000
 test master 2 - Starting Memory Write, at          27794625000
 test master 2 - Starting Memory Write, at          27794865000
 test master 2 - Starting Memory Write, at          27795105000
 test master 1 - Starting Memory Read, at          27795465000
 test master 1 - Starting Memory Read, at          27795735000
 test master 1 - Starting Memory Read, at          27796275000
 test master 1 - Starting Memory Read, at          27796545000
 test master 1 - Starting Memory Read, at          27797085000
 test master 1 - Starting Memory Read, at          27797355000
 test master 2 - Starting Memory Write, at          27799395000
 test master 2 - Starting Memory Write, at          27800595000
 test master 2 - Starting Memory Write, at          27801795000
 test master 2 - Starting Memory Write, at          27802995000
 test master 2 - Starting Memory Write, at          27805575000
 test master 2 - Starting Memory Write, at          27806775000
 test master 2 - Starting Memory Write, at          27807975000
 test master 2 - Starting Memory Write, at          27809175000
 test master 2 - Starting Memory Write, at          27811755000
 test master 2 - Starting Memory Write, at          27814155000
 test master 2 - Starting Memory Write, at          27816555000
 test master 2 - Starting Memory Write, at          27818955000
 test master 2 - Starting Memory Write, at          27822735000
 test master 2 - Starting Memory Write, at          27825435000
 test master 2 - Starting Memory Write, at          27828135000
 test master 2 - Starting Memory Write, at          27830835000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          27835665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27835695000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27838215000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          27838455000
 test master 2 - Starting Memory Read, at          27838635000
 test master 2 - Starting Memory Read, at          27838815000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27840435000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          27840735000
 test master 2 - Starting Memory Read, at          27840915000
 test master 2 - Starting Memory Read, at          27841095000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27842655000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27842985000
 test master 2 - Starting Memory Read Line Multiple, at          27843165000
 test master 2 - Starting Memory Read Line Multiple, at          27843405000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27845115000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27848415000
 test master 2 - Starting Memory Read Line Multiple, at          27848595000
 test master 2 - Starting Memory Read Line Multiple, at          27848865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27849225000
 test master 2 - Starting Memory Read Line Multiple, at          27849405000
 test master 2 - Starting Memory Read Line Multiple, at          27849645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27850005000
 test master 2 - Starting Memory Read Line Multiple, at          27850185000
 test master 2 - Starting Memory Read Line Multiple, at          27850425000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27850785000
 test master 2 - Starting Memory Read Line Multiple, at          27850965000
 test master 2 - Starting Memory Read Line Multiple, at          27851205000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27851565000
 test master 2 - Starting Memory Read Line Multiple, at          27851745000
 test master 2 - Starting Memory Read Line Multiple, at          27851985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27852345000
 test master 2 - Starting Memory Read Line Multiple, at          27852525000
 test master 2 - Starting Memory Read Line Multiple, at          27852765000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27853125000
 test master 2 - Starting Memory Read Line Multiple, at          27853305000
 test master 2 - Starting Memory Read Line Multiple, at          27853545000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27853905000
 test master 2 - Starting Memory Read Line Multiple, at          27854085000
 test master 2 - Starting Memory Read Line Multiple, at          27854325000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          27854685000
 test master 2 - Starting Memory Read Line, at          27854865000
 test master 2 - Starting Memory Read Line, at          27855045000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          27855315000
 test master 2 - Starting Memory Read Line, at          27855495000
 test master 2 - Starting Memory Read Line, at          27855675000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27856935000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27858735000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27862035000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27863895000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          27868845000
 test master 2 - Starting Memory Write, at          27869085000
 test master 2 - Starting Memory Write, at          27869325000
 test master 2 - Starting Memory Write, at          27869565000
 test master 2 - Starting Memory Write, at          27869805000
 test master 1 - Starting Memory Read, at          27870165000
 test master 1 - Starting Memory Read, at          27870435000
 test master 1 - Starting Memory Read, at          27870975000
 test master 1 - Starting Memory Read, at          27871245000
 test master 1 - Starting Memory Read, at          27871785000
 test master 1 - Starting Memory Read, at          27872055000
 test master 2 - Starting Memory Write, at          27873465000
 test master 2 - Starting Memory Write, at          27873705000
 test master 2 - Starting Memory Write, at          27873945000
 test master 2 - Starting Memory Write, at          27874185000
 test master 2 - Starting Memory Write, at          27874425000
 test master 1 - Starting Memory Read, at          27874785000
 test master 1 - Starting Memory Read, at          27875055000
 test master 1 - Starting Memory Read, at          27875595000
 test master 1 - Starting Memory Read, at          27875865000
 test master 1 - Starting Memory Read, at          27876405000
 test master 1 - Starting Memory Read, at          27876675000
 test master 2 - Starting Memory Write, at          27878715000
 test master 2 - Starting Memory Write, at          27879915000
 test master 2 - Starting Memory Write, at          27881115000
 test master 2 - Starting Memory Write, at          27882315000
 test master 2 - Starting Memory Write, at          27884895000
 test master 2 - Starting Memory Write, at          27886095000
 test master 2 - Starting Memory Write, at          27887295000
 test master 2 - Starting Memory Write, at          27888495000
 test master 2 - Starting Memory Write, at          27891075000
 test master 2 - Starting Memory Write, at          27893475000
 test master 2 - Starting Memory Write, at          27895875000
 test master 2 - Starting Memory Write, at          27898275000
 test master 2 - Starting Memory Write, at          27902055000
 test master 2 - Starting Memory Write, at          27904755000
 test master 2 - Starting Memory Write, at          27907455000
 test master 2 - Starting Memory Write, at          27910155000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          27914985000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27915015000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27917535000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          27917775000
 test master 2 - Starting Memory Read, at          27917955000
 test master 2 - Starting Memory Read, at          27918135000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27919755000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          27920055000
 test master 2 - Starting Memory Read, at          27920235000
 test master 2 - Starting Memory Read, at          27920415000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27921975000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27922305000
 test master 2 - Starting Memory Read Line Multiple, at          27922485000
 test master 2 - Starting Memory Read Line Multiple, at          27922725000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27924435000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27927735000
 test master 2 - Starting Memory Read Line Multiple, at          27927915000
 test master 2 - Starting Memory Read Line Multiple, at          27928185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27928545000
 test master 2 - Starting Memory Read Line Multiple, at          27928725000
 test master 2 - Starting Memory Read Line Multiple, at          27928965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27929325000
 test master 2 - Starting Memory Read Line Multiple, at          27929505000
 test master 2 - Starting Memory Read Line Multiple, at          27929745000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27930105000
 test master 2 - Starting Memory Read Line Multiple, at          27930285000
 test master 2 - Starting Memory Read Line Multiple, at          27930525000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27930885000
 test master 2 - Starting Memory Read Line Multiple, at          27931065000
 test master 2 - Starting Memory Read Line Multiple, at          27931305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27931665000
 test master 2 - Starting Memory Read Line Multiple, at          27931845000
 test master 2 - Starting Memory Read Line Multiple, at          27932085000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27932445000
 test master 2 - Starting Memory Read Line Multiple, at          27932625000
 test master 2 - Starting Memory Read Line Multiple, at          27932865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          27933225000
 test master 2 - Starting Memory Read Line Multiple, at          27933405000
 test master 2 - Starting Memory Read Line Multiple, at          27933645000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          27934005000
 test master 2 - Starting Memory Read Line, at          27934185000
 test master 2 - Starting Memory Read Line, at          27934365000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          27934635000
 test master 2 - Starting Memory Read Line, at          27934815000
 test master 2 - Starting Memory Read Line, at          27934995000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27936255000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27938055000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27941355000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27943215000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          27948165000
 test master 2 - Starting Memory Write, at          27948405000
 test master 2 - Starting Memory Write, at          27948645000
 test master 2 - Starting Memory Write, at          27948885000
 test master 2 - Starting Memory Write, at          27949125000
 test master 1 - Starting Memory Read, at          27949485000
 test master 1 - Starting Memory Read, at          27949755000
 test master 1 - Starting Memory Read, at          27950295000
 test master 1 - Starting Memory Read, at          27950565000
 test master 1 - Starting Memory Read, at          27951105000
 test master 1 - Starting Memory Read, at          27951375000
 test master 2 - Starting Memory Write, at          27952785000
 test master 2 - Starting Memory Write, at          27953025000
 test master 2 - Starting Memory Write, at          27953265000
 test master 2 - Starting Memory Write, at          27953505000
 test master 2 - Starting Memory Write, at          27953745000
 test master 1 - Starting Memory Read, at          27954105000
 test master 1 - Starting Memory Read, at          27954375000
 test master 1 - Starting Memory Read, at          27954915000
 test master 1 - Starting Memory Read, at          27955185000
 test master 1 - Starting Memory Read, at          27955725000
 test master 1 - Starting Memory Read, at          27955995000
 test master 2 - Starting Memory Write, at          27958035000
 test master 2 - Starting Memory Write, at          27959235000
 test master 2 - Starting Memory Write, at          27960435000
 test master 2 - Starting Memory Write, at          27961635000
 test master 2 - Starting Memory Write, at          27964215000
 test master 2 - Starting Memory Write, at          27965415000
 test master 2 - Starting Memory Write, at          27966615000
 test master 2 - Starting Memory Write, at          27967815000
 test master 2 - Starting Memory Write, at          27970395000
 test master 2 - Starting Memory Write, at          27972795000
 test master 2 - Starting Memory Write, at          27975195000
 test master 2 - Starting Memory Write, at          27977595000
 test master 2 - Starting Memory Write, at          27981375000
 test master 2 - Starting Memory Write, at          27984075000
 test master 2 - Starting Memory Write, at          27986775000
 test master 2 - Starting Memory Write, at          27989475000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          27994305000
*** monitor - CBE Bus Changed when TRDY Desserted, at          27994335000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27996855000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          27997095000
 test master 2 - Starting Memory Read, at          27997275000
 test master 2 - Starting Memory Read, at          27997455000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          27999075000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          27999375000
 test master 2 - Starting Memory Read, at          27999555000
 test master 2 - Starting Memory Read, at          27999735000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          28001295000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          28001625000
 test master 2 - Starting Memory Read Line Multiple, at          28001805000
 test master 2 - Starting Memory Read Line Multiple, at          28002045000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          28003755000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          28007055000
 test master 2 - Starting Memory Read Line Multiple, at          28007235000
 test master 2 - Starting Memory Read Line Multiple, at          28007505000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          28007865000
 test master 2 - Starting Memory Read Line Multiple, at          28008045000
 test master 2 - Starting Memory Read Line Multiple, at          28008285000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          28008645000
 test master 2 - Starting Memory Read Line Multiple, at          28008825000
 test master 2 - Starting Memory Read Line Multiple, at          28009065000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          28009425000
 test master 2 - Starting Memory Read Line Multiple, at          28009605000
 test master 2 - Starting Memory Read Line Multiple, at          28009845000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          28010205000
 test master 2 - Starting Memory Read Line Multiple, at          28010385000
 test master 2 - Starting Memory Read Line Multiple, at          28010625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          28010985000
 test master 2 - Starting Memory Read Line Multiple, at          28011165000
 test master 2 - Starting Memory Read Line Multiple, at          28011405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          28011765000
 test master 2 - Starting Memory Read Line Multiple, at          28011945000
 test master 2 - Starting Memory Read Line Multiple, at          28012185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          28012545000
 test master 2 - Starting Memory Read Line Multiple, at          28012725000
 test master 2 - Starting Memory Read Line Multiple, at          28012965000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          28013325000
 test master 2 - Starting Memory Read Line, at          28013505000
 test master 2 - Starting Memory Read Line, at          28013685000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          28013955000
 test master 2 - Starting Memory Read Line, at          28014135000
 test master 2 - Starting Memory Read Line, at          28014315000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          28015575000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          28017375000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          28020675000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          28022535000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          28027485000
 test master 2 - Starting Memory Write, at          28027725000
 test master 2 - Starting Memory Write, at          28027965000
 test master 2 - Starting Memory Write, at          28028205000
 test master 2 - Starting Memory Write, at          28028445000
 test master 1 - Starting Memory Read, at          28028805000
 test master 1 - Starting Memory Read, at          28029075000
 test master 1 - Starting Memory Read, at          28029615000
 test master 1 - Starting Memory Read, at          28029885000
 test master 1 - Starting Memory Read, at          28030425000
 test master 1 - Starting Memory Read, at          28030695000
 test master 2 - Starting Memory Write, at          28032105000
 test master 2 - Starting Memory Write, at          28032345000
 test master 2 - Starting Memory Write, at          28032585000
 test master 2 - Starting Memory Write, at          28032825000
 test master 2 - Starting Memory Write, at          28033065000
 test master 1 - Starting Memory Read, at          28033425000
 test master 1 - Starting Memory Read, at          28033695000
 test master 1 - Starting Memory Read, at          28034235000
 test master 1 - Starting Memory Read, at          28034505000
 test master 1 - Starting Memory Read, at          28035045000
 test master 1 - Starting Memory Read, at          28035315000
 test master 2 - Starting Memory Write, at          28037355000
 test master 2 - Starting Memory Write, at          28038555000
 test master 2 - Starting Memory Write, at          28039755000
 test master 2 - Starting Memory Write, at          28040955000
 test master 2 - Starting Memory Write, at          28043535000
 test master 2 - Starting Memory Write, at          28044735000
 test master 2 - Starting Memory Write, at          28045935000
 test master 2 - Starting Memory Write, at          28047135000
 test master 2 - Starting Memory Write, at          28049715000
 test master 2 - Starting Memory Write, at          28052115000
 test master 2 - Starting Memory Write, at          28054515000
 test master 2 - Starting Memory Write, at          28056915000
 test master 2 - Starting Memory Write, at          28060695000
 test master 2 - Starting Memory Write, at          28063395000
 test master 2 - Starting Memory Write, at          28066095000
 test master 2 - Starting Memory Write, at          28068795000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          28073625000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28073655000
 test master 1 - Starting Memory Read, at          28076175000
 test master 1 - Starting Memory Read, at          28076475000
 test master 1 - Starting Memory Read, at          28077885000
 test master 1 - Starting Memory Read, at          28078185000
 test master 1 - Starting Memory Read Line, at          28079625000
 test master 1 - Starting Memory Read Line, at          28079925000
 test master 1 - Starting Memory Read Line, at          28081365000
 test master 1 - Starting Memory Read Line, at          28081665000
 test master 1 - Starting Memory Read Line, at          28083165000
 test master 1 - Starting Memory Read Line, at          28083525000
 test master 1 - Starting Memory Read Line, at          28085025000
 test master 1 - Starting Memory Read Line, at          28085385000
 test master 1 - Starting Memory Read Line Multiple, at          28086945000
 test master 1 - Starting Memory Read Line Multiple, at          28087365000
 test master 1 - Starting Memory Read Line Multiple, at          28088985000
 test master 1 - Starting Memory Read Line Multiple, at          28089405000
 test master 1 - Starting Memory Read Line, at          28091025000
 test master 1 - Starting Memory Read Line, at          28091385000
 test master 1 - Starting Memory Read, at          28094175000
 test master 1 - Starting Memory Read, at          28094475000
 test target 1 - Starting Config Write, at          28098345000
 test master 1 - Starting Memory Write, at          28099095000
 test master 1 - Starting Memory Write, at          28101045000
 test master 1 - Starting Memory Write, at          28102395000
 test master 1 - Starting Memory Write, at          28104225000
 test master 1 - Starting Memory Write, at          28105575000
 test master 1 - Starting Memory Read Line, at          28107525000
 test master 1 - Starting Memory Write, at          28109025000
 test master 1 - Starting Memory Read Line, at          28110975000
 test target 1 - Starting Config Write, at          28114785000
 test master 1 - Starting Memory Write, at          28115535000
 test master 1 - Starting Memory Write, at          28115655000
 test master 1 - Starting Memory Write, at          28115895000
 test master 1 - Starting Memory Read, at          28116015000
 test master 1 - Starting Memory Write, at          28116315000
 test master 1 - Starting Memory Read, at          28116435000
 test master 1 - Starting Memory Write, at          28118415000
 test master 1 - Starting Memory Write, at          28121715000
 test master 2 - Starting Memory Read Line, at          28125135000
 test master 2 - Starting Memory Read Line, at          28125465000
 test master 2 - Starting Memory Read Line, at          28125765000
 test master 2 - Starting Memory Read Line, at          28126095000
 test master 1 - Starting Memory Write, at          28126485000
 test master 1 - Starting Memory Write, at          28126725000
 test master 1 - Starting Memory Write, at          28126965000
 test master 2 - Starting Memory Read Line, at          28127325000
 test master 2 - Starting Memory Read Line, at          28127625000
 test master 2 - Starting Memory Read Line, at          28127835000
 test master 2 - Starting Memory Read Line, at          28128135000
 test master 2 - Starting Memory Read Line Multiple, at          28128375000
 test master 2 - Starting Memory Read Line Multiple, at          28128675000
 test master 1 - Starting Memory Write, at          28130835000
 test master 1 - Starting Memory Write, at          28131075000
 test master 2 - Starting Memory Read, at          28131435000
 test master 2 - Starting Memory Read, at          28131735000
 test master 2 - Starting Memory Read, at          28131945000
 test master 2 - Starting Memory Read, at          28132245000
 test master 1 - Starting Memory Write, at          28134135000
 test master 1 - Starting Memory Read, at          28134315000
 test master 1 - Starting Memory Write, at          28134495000
 test master 1 - Starting Memory Read, at          28134705000
 test master 1 - Starting Memory Write, at          28134915000
 test master 1 - Starting Memory Read, at          28135095000
 test master 1 - Starting Memory Read, at          28135305000
 test master 1 - Starting Memory Write, at          28135515000
 test master 1 - Starting Memory Write, at          28135695000
 test master 1 - Starting Memory Read, at          28135875000
 test master 1 - Starting Memory Write, at          28136055000
 test master 1 - Starting Memory Write, at          28136265000
 test master 1 - Starting Memory Write, at          28136475000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          28141785000
 test target 1 - Starting Memory Write, at          28142025000
 test master 1 - Starting Memory Write, at          28142235000
 test target 1 - Starting Memory Write, at          28142415000
 test target 1 - Starting Memory Write, at          28142655000
 test target 1 - Starting Memory Write, at          28142895000
 test master 1 - Starting Memory Write, at          28143225000
 test target 1 - Starting Memory Write, at          28143735000
 test target 1 - Starting Memory Write, at          28144305000
 test target 1 - Starting Memory Write, at          28144575000
 test master 1 - Starting Memory Write, at          28144815000
 test target 1 - Starting Memory Write, at          28145055000
 test target 1 - Starting Memory Write, at          28145325000
 test target 1 - Starting Memory Write, at          28145595000
 test master 1 - Starting Memory Write, at          28145985000
 test target 1 - Starting Memory Write, at          28146705000
 test target 1 - Starting Memory Write, at          28147305000
 test target 1 - Starting Memory Write, at          28147545000
 test master 1 - Starting Memory Read, at          28147755000
 test target 1 - Starting Memory Write, at          28147935000
 test master 1 - Starting Memory Read, at          28148145000
 test target 1 - Starting Memory Write, at          28148325000
 test master 1 - Starting Memory Read, at          28148535000
 test target 1 - Starting Memory Write, at          28148715000
 test master 1 - Starting Memory Read, at          28148925000
 test target 1 - Starting Memory Write, at          28149105000
 test master 1 - Starting Memory Read, at          28149315000
 test target 1 - Starting Memory Write, at          28149495000
 test master 1 - Starting Memory Write, at          28149705000
 test target 1 - Starting Memory Write, at          28149885000
 test target 1 - Starting Memory Write, at          28150125000
 test target 1 - Starting Memory Write, at          28150365000
 test target 1 - Starting Memory Read, at          28150665000
 test master 1 - Starting Memory Write, at          28150995000
 test master 1 - Starting Memory Read, at          28151235000
 test target 1 - Starting Memory Write, at          28151745000
 test master 1 - Starting Memory Write, at          28152135000
 test target 1 - Starting Memory Read, at          28152585000
 test target 1 - Starting Memory Write, at          28153395000
 test master 1 - Starting Memory Read, at          28153725000
 test master 1 - Starting Memory Write, at          28154025000
 test master 1 - Starting Memory Write, at          28154385000
 test master 1 - Starting Memory Read, at          28154625000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          28157145000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          28158225000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          28183305000
 test target 1 - Starting Config Write, at          28184085000
 test target 1 - Starting Config Write, at          28184895000
 test target 2 - Starting Config Write, at          28185705000
 test target 2 - Starting Config Write, at          28186485000
 test target 2 - Starting Config Write, at          28187295000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          28189095000
 test target 1 - Starting Memory Read, at          28189275000
 test target 1 - Starting Memory Write, at          28189995000
 test target 1 - Starting Memory Read, at          28190175000
 test target 1 - Starting Memory Write, at          28191105000
 test target 1 - Starting Memory Read, at          28192485000
 test target 1 - Starting Memory Read, at          28193025000
 test target 1 - Starting Memory Read, at          28193625000
 test target 1 - Starting Memory Read, at          28194195000
 test target 1 - Starting Memory Read, at          28195065000
 test target 1 - Starting Memory Read, at          28196265000
 test target 1 - Starting Memory Read, at          28197045000
 test target 1 - Starting Memory Read, at          28198245000
 test target 1 - Starting Memory Read, at          28199025000
 test target 1 - Starting Memory Read, at          28201845000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          28208475000
 test target 1 - Starting Memory Read, at          28208655000
 test target 1 - Starting Memory Write, at          28209375000
 test target 1 - Starting Memory Read, at          28209555000
 test target 1 - Starting Memory Write, at          28210485000
 test target 1 - Starting Memory Read, at          28211865000
 test target 1 - Starting Memory Read, at          28212405000
 test target 1 - Starting Memory Read, at          28213005000
 test target 1 - Starting Memory Read, at          28213575000
 test target 1 - Starting Memory Read, at          28214445000
 test target 1 - Starting Memory Read, at          28215645000
 test target 1 - Starting Memory Read, at          28216425000
 test target 1 - Starting Memory Read, at          28217625000
 test target 1 - Starting Memory Read, at          28218405000
 test target 1 - Starting Memory Read, at          28221225000
 test target 1 - Starting Memory Write, at          28227855000
 test target 1 - Starting Memory Read, at          28228035000
 test target 1 - Starting Memory Write, at          28228755000
 test target 1 - Starting Memory Read, at          28228935000
 test target 1 - Starting Memory Write, at          28229865000
 test target 1 - Starting Memory Read, at          28231245000
 test target 1 - Starting Memory Read, at          28231785000
 test target 1 - Starting Memory Read, at          28232385000
 test target 1 - Starting Memory Read, at          28232955000
 test target 1 - Starting Memory Read, at          28233825000
 test target 1 - Starting Memory Read, at          28235025000
 test target 1 - Starting Memory Read, at          28235805000
 test target 1 - Starting Memory Read, at          28237005000
 test target 1 - Starting Memory Read, at          28237785000
 test target 1 - Starting Memory Read, at          28240605000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          28253205000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          28259625000
 test target 1 - Starting Memory Write, at          28260285000
 test target 1 - Starting Memory Read, at          28260765000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          28262145000
 test target 1 - Starting Config Write, at          28264005000
 test target 1 - Starting Memory Read, at          28264575000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          28266165000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          28268265000
 test target 1 - Starting Memory Write, at          28269315000
 test target 1 - Starting Memory Write, at          28269555000
 test target 1 - Starting Memory Read, at          28269735000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          28272165000
 test target 1 - Starting Memory Write, at          28275255000
 test target 1 - Starting Memory Write, at          28275615000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          28279815000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          28281885000
 test target 1 - Starting Memory Read, at          28283295000
 test target 1 - Starting Memory Read, at          28284375000
 test target 1 - Starting Memory Read, at          28286175000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          28292325000
 test target 2 - Starting Config Write, at          28293135000
 test target 1 - Starting Memory Write, at          28293705000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          28293795000
 test target 1 - Starting Memory Write, at          28294875000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          28294965000
 test target 1 - Starting Memory Write, at          28296045000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          28297425000
 test target 1 - Starting Memory Read, at          28299555000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          28299675000
 test target 1 - Starting Memory Read, at          28301745000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          28303335000
 test master 2 - Starting Memory Write, at          28303335000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          28303395000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28304175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28304205000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28304505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28304535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28305435000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28305465000
 test target 1 - Starting Memory Write, at          28307295000
 test master 2 - Starting Memory Write, at          28307295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28308975000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28309005000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28310715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28310745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28312455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28312485000
 test target 1 - Starting Memory Write, at          28314555000
 test master 2 - Starting Memory Write, at          28314555000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          28314615000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28316205000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28316235000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28316535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28316565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28317465000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28317495000
 test target 1 - Starting Memory Write, at          28318695000
 test master 2 - Starting Memory Write, at          28318695000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          28321575000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          28323225000
 test master 1 - Starting Memory Read, at          28323525000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          28323675000
 test target 1 - Starting Config Write, at          28326285000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          28328715000
 test target 1 - Starting Memory Write, at          28328835000
 test target 1 - Starting Memory Write, at          28328955000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          28329405000
 test target 1 - Starting Memory Write, at          28329555000
 test target 1 - Starting Memory Write, at          28329705000
 test target 1 - Starting Memory Write, at          28330155000
 test target 1 - Starting Memory Write, at          28330425000
 test target 1 - Starting Memory Write, at          28330875000
 test target 1 - Starting Memory Write, at          28331505000
 test target 1 - Starting Memory Write, at          28331655000
 test target 1 - Starting Memory Write, at          28332285000
 test target 1 - Starting Memory Write, at          28332585000
 test target 1 - Starting Memory Write, at          28333065000
 test target 1 - Starting Memory Write, at          28336215000
 test target 1 - Starting Memory Write, at          28336365000
 test target 1 - Starting Memory Write, at          28336515000
 test target 1 - Starting Memory Write, at          28336815000
 test target 1 - Starting Memory Write, at          28337115000
 test target 1 - Starting Memory Read, at          28345845000
 test target 1 - Starting Memory Read, at          28346955000
 test target 1 - Starting Memory Read, at          28348065000
 test target 1 - Starting Memory Read, at          28349145000
 test target 1 - Starting Memory Read, at          28350255000
 test target 1 - Starting Memory Read, at          28351365000
 test target 1 - Starting Memory Read, at          28352445000
 test target 1 - Starting Memory Read, at          28353555000
 test target 1 - Starting Memory Read, at          28354665000
 test target 1 - Starting Memory Read, at          28355745000
 test target 1 - Starting Memory Read, at          28356855000
 test target 1 - Starting Memory Read, at          28357965000
 test target 1 - Starting Memory Read, at          28359045000
 test target 1 - Starting Memory Read, at          28360155000
 test target 1 - Starting Memory Read, at          28361265000
 test target 1 - Starting Memory Read, at          28362345000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          28363425000
 test target 1 - Starting Memory Read, at          28363575000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          28364775000
 test target 1 - Starting Memory Read, at          28367205000
 test target 1 - Starting Memory Read, at          28367775000
 test target 1 - Starting Memory Read, at          28368345000
 test target 1 - Starting Memory Read, at          28369155000
 test target 1 - Starting Memory Read, at          28369965000
 test target 1 - Starting Memory Read, at          28371345000
 test target 1 - Starting Memory Read, at          28372545000
 test target 1 - Starting Memory Read, at          28373325000
 test target 1 - Starting Memory Read, at          28376565000
 test target 1 - Starting Memory Read, at          28379745000
 test target 1 - Starting Memory Read, at          28380585000
 test target 1 - Starting Memory Read, at          28381425000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          28382505000
 test master 1 - Starting Memory Write, at          28382895000
 test target 1 - Starting Memory Write, at          28382895000
 test target 1 - Starting Memory Write, at          28383045000
 test target 1 - Starting Memory Read, at          28383525000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          28386465000
 test master 1 - Starting Memory Write, at          28386885000
 test target 1 - Starting Memory Write, at          28386885000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          28391805000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          28392885000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          28417965000
 test target 1 - Starting Config Write, at          28418955000
 test target 1 - Starting Config Write, at          28419945000
 test target 2 - Starting Config Write, at          28420785000
 test target 2 - Starting Config Write, at          28421775000
 test target 2 - Starting Config Write, at          28422765000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          28424595000
 test target 1 - Starting Memory Read, at          28424805000
 test target 1 - Starting Memory Write, at          28425495000
 test target 1 - Starting Memory Read, at          28425705000
 test target 1 - Starting Memory Write, at          28426605000
 test target 1 - Starting Memory Read, at          28427985000
 test target 1 - Starting Memory Read, at          28428525000
 test target 1 - Starting Memory Read, at          28429125000
 test target 1 - Starting Memory Read, at          28429695000
 test target 1 - Starting Memory Read, at          28430565000
 test target 1 - Starting Memory Read, at          28431765000
 test target 1 - Starting Memory Read, at          28432545000
 test target 1 - Starting Memory Read, at          28433745000
 test target 1 - Starting Memory Read, at          28434525000
 test target 1 - Starting Memory Read, at          28437345000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          28443975000
 test target 1 - Starting Memory Read, at          28444185000
 test target 1 - Starting Memory Write, at          28444875000
 test target 1 - Starting Memory Read, at          28445085000
 test target 1 - Starting Memory Write, at          28445985000
 test target 1 - Starting Memory Read, at          28447365000
 test target 1 - Starting Memory Read, at          28447905000
 test target 1 - Starting Memory Read, at          28448505000
 test target 1 - Starting Memory Read, at          28449075000
 test target 1 - Starting Memory Read, at          28449945000
 test target 1 - Starting Memory Read, at          28451145000
 test target 1 - Starting Memory Read, at          28451925000
 test target 1 - Starting Memory Read, at          28453125000
 test target 1 - Starting Memory Read, at          28453905000
 test target 1 - Starting Memory Read, at          28456725000
 test target 1 - Starting Memory Write, at          28463355000
 test target 1 - Starting Memory Read, at          28463565000
 test target 1 - Starting Memory Write, at          28464255000
 test target 1 - Starting Memory Read, at          28464465000
 test target 1 - Starting Memory Write, at          28465365000
 test target 1 - Starting Memory Read, at          28466745000
 test target 1 - Starting Memory Read, at          28467285000
 test target 1 - Starting Memory Read, at          28467885000
 test target 1 - Starting Memory Read, at          28468455000
 test target 1 - Starting Memory Read, at          28469325000
 test target 1 - Starting Memory Read, at          28470525000
 test target 1 - Starting Memory Read, at          28471305000
 test target 1 - Starting Memory Read, at          28472505000
 test target 1 - Starting Memory Read, at          28473285000
 test target 1 - Starting Memory Read, at          28476105000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          28488705000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          28495125000
 test target 1 - Starting Memory Write, at          28495995000
 test target 1 - Starting Memory Read, at          28496505000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          28497825000
 test target 1 - Starting Config Write, at          28499715000
 test target 1 - Starting Memory Read, at          28500465000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          28501845000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          28503945000
 test target 1 - Starting Memory Write, at          28505235000
 test target 1 - Starting Memory Write, at          28505505000
 test target 1 - Starting Memory Read, at          28505715000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          28508085000
 test target 1 - Starting Memory Write, at          28511175000
 test target 1 - Starting Memory Write, at          28511565000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          28515795000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          28517865000
 test target 1 - Starting Memory Read, at          28519275000
 test target 1 - Starting Memory Read, at          28520355000
 test target 1 - Starting Memory Read, at          28522155000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          28528305000
 test target 2 - Starting Config Write, at          28529115000
 test target 1 - Starting Memory Write, at          28529895000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          28530015000
 test target 1 - Starting Memory Write, at          28531095000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          28531215000
 test target 1 - Starting Memory Write, at          28532295000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          28533705000
 test target 1 - Starting Memory Read, at          28535835000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          28535955000
 test target 1 - Starting Memory Read, at          28538025000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          28539615000
 test master 2 - Starting Memory Write, at          28539615000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          28539675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28540485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28540515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28540815000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28540845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28541745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28541775000
 test target 1 - Starting Memory Write, at          28543605000
 test master 2 - Starting Memory Write, at          28543605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28545315000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28545345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28547055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28547085000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28548795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28548825000
 test target 1 - Starting Memory Write, at          28550895000
 test master 2 - Starting Memory Write, at          28550895000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          28550955000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28552575000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28552605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28552905000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28552935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28553835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28553865000
 test target 1 - Starting Memory Write, at          28555065000
 test master 2 - Starting Memory Write, at          28555065000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          28557975000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          28559625000
 test master 1 - Starting Memory Read, at          28559925000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          28560075000
 test target 1 - Starting Config Write, at          28562685000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          28565115000
 test target 1 - Starting Memory Write, at          28565265000
 test target 1 - Starting Memory Write, at          28565415000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          28565895000
 test target 1 - Starting Memory Write, at          28566075000
 test target 1 - Starting Memory Write, at          28566255000
 test target 1 - Starting Memory Write, at          28566735000
 test target 1 - Starting Memory Write, at          28567035000
 test target 1 - Starting Memory Write, at          28567515000
 test target 1 - Starting Memory Write, at          28568175000
 test target 1 - Starting Memory Write, at          28568355000
 test target 1 - Starting Memory Write, at          28569015000
 test target 1 - Starting Memory Write, at          28569345000
 test target 1 - Starting Memory Write, at          28569855000
 test target 1 - Starting Memory Write, at          28573035000
 test target 1 - Starting Memory Write, at          28573215000
 test target 1 - Starting Memory Write, at          28573395000
 test target 1 - Starting Memory Write, at          28573725000
 test target 1 - Starting Memory Write, at          28574055000
 test target 1 - Starting Memory Read, at          28582815000
 test target 1 - Starting Memory Read, at          28583985000
 test target 1 - Starting Memory Read, at          28585065000
 test target 1 - Starting Memory Read, at          28586175000
 test target 1 - Starting Memory Read, at          28587285000
 test target 1 - Starting Memory Read, at          28588365000
 test target 1 - Starting Memory Read, at          28589475000
 test target 1 - Starting Memory Read, at          28590585000
 test target 1 - Starting Memory Read, at          28591665000
 test target 1 - Starting Memory Read, at          28592775000
 test target 1 - Starting Memory Read, at          28593885000
 test target 1 - Starting Memory Read, at          28594965000
 test target 1 - Starting Memory Read, at          28596075000
 test target 1 - Starting Memory Read, at          28597185000
 test target 1 - Starting Memory Read, at          28598265000
 test target 1 - Starting Memory Read, at          28599375000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          28600425000
 test target 1 - Starting Memory Read, at          28600575000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          28601775000
 test target 1 - Starting Memory Read, at          28604235000
 test target 1 - Starting Memory Read, at          28604805000
 test target 1 - Starting Memory Read, at          28605345000
 test target 1 - Starting Memory Read, at          28606185000
 test target 1 - Starting Memory Read, at          28606995000
 test target 1 - Starting Memory Read, at          28608345000
 test target 1 - Starting Memory Read, at          28609545000
 test target 1 - Starting Memory Read, at          28610325000
 test target 1 - Starting Memory Read, at          28613565000
 test target 1 - Starting Memory Read, at          28616745000
 test target 1 - Starting Memory Read, at          28617585000
 test target 1 - Starting Memory Read, at          28618425000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          28619505000
 test master 1 - Starting Memory Write, at          28619925000
 test target 1 - Starting Memory Write, at          28619925000
 test target 1 - Starting Memory Write, at          28620075000
 test target 1 - Starting Memory Read, at          28620585000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          28623495000
 test master 1 - Starting Memory Write, at          28623915000
 test target 1 - Starting Memory Write, at          28623915000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          28628865000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          28629945000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          28655025000
 test target 1 - Starting Config Write, at          28656015000
 test target 1 - Starting Config Write, at          28657005000
 test target 2 - Starting Config Write, at          28658025000
 test target 2 - Starting Config Write, at          28659015000
 test target 2 - Starting Config Write, at          28660005000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          28662015000
 test target 1 - Starting Memory Read, at          28662255000
 test target 1 - Starting Memory Write, at          28662915000
 test target 1 - Starting Memory Read, at          28663155000
 test target 1 - Starting Memory Write, at          28664025000
 test target 1 - Starting Memory Read, at          28665465000
 test target 1 - Starting Memory Read, at          28666005000
 test target 1 - Starting Memory Read, at          28666605000
 test target 1 - Starting Memory Read, at          28667175000
 test target 1 - Starting Memory Read, at          28668045000
 test target 1 - Starting Memory Read, at          28669245000
 test target 1 - Starting Memory Read, at          28670205000
 test target 1 - Starting Memory Read, at          28671405000
 test target 1 - Starting Memory Read, at          28672365000
 test target 1 - Starting Memory Read, at          28675185000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          28681815000
 test target 1 - Starting Memory Read, at          28682055000
 test target 1 - Starting Memory Write, at          28682715000
 test target 1 - Starting Memory Read, at          28682955000
 test target 1 - Starting Memory Write, at          28683825000
 test target 1 - Starting Memory Read, at          28685265000
 test target 1 - Starting Memory Read, at          28685805000
 test target 1 - Starting Memory Read, at          28686405000
 test target 1 - Starting Memory Read, at          28686975000
 test target 1 - Starting Memory Read, at          28687845000
 test target 1 - Starting Memory Read, at          28689045000
 test target 1 - Starting Memory Read, at          28690005000
 test target 1 - Starting Memory Read, at          28691205000
 test target 1 - Starting Memory Read, at          28692165000
 test target 1 - Starting Memory Read, at          28694985000
 test target 1 - Starting Memory Write, at          28701615000
 test target 1 - Starting Memory Read, at          28701855000
 test target 1 - Starting Memory Write, at          28702515000
 test target 1 - Starting Memory Read, at          28702755000
 test target 1 - Starting Memory Write, at          28703625000
 test target 1 - Starting Memory Read, at          28705065000
 test target 1 - Starting Memory Read, at          28705605000
 test target 1 - Starting Memory Read, at          28706205000
 test target 1 - Starting Memory Read, at          28706775000
 test target 1 - Starting Memory Read, at          28707645000
 test target 1 - Starting Memory Read, at          28708845000
 test target 1 - Starting Memory Read, at          28709805000
 test target 1 - Starting Memory Read, at          28711005000
 test target 1 - Starting Memory Read, at          28711965000
 test target 1 - Starting Memory Read, at          28714785000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          28727385000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          28733985000
 test target 1 - Starting Memory Write, at          28734855000
 test target 1 - Starting Memory Read, at          28735395000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          28736805000
 test target 1 - Starting Config Write, at          28738875000
 test target 1 - Starting Memory Read, at          28739625000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          28741185000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          28743465000
 test target 1 - Starting Memory Write, at          28744755000
 test target 1 - Starting Memory Write, at          28745055000
 test target 1 - Starting Memory Read, at          28745295000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          28747605000
 test target 1 - Starting Memory Write, at          28750755000
 test target 1 - Starting Memory Write, at          28751175000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          28755435000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          28757505000
 test target 1 - Starting Memory Read, at          28758915000
 test target 1 - Starting Memory Read, at          28760085000
 test target 1 - Starting Memory Read, at          28761885000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          28768125000
 test target 2 - Starting Config Write, at          28769145000
 test target 1 - Starting Memory Write, at          28769895000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          28770045000
 test target 1 - Starting Memory Write, at          28771125000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          28771275000
 test target 1 - Starting Memory Write, at          28772355000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          28773825000
 test target 1 - Starting Memory Read, at          28776135000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          28776285000
 test target 1 - Starting Memory Read, at          28778505000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          28780275000
 test master 2 - Starting Memory Write, at          28780275000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          28780335000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28781175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28781205000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28781505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28781535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28782435000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28782465000
 test target 1 - Starting Memory Write, at          28784295000
 test master 2 - Starting Memory Write, at          28784295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28786035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28786065000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28787775000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28787805000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28789515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28789545000
 test target 1 - Starting Memory Write, at          28791615000
 test master 2 - Starting Memory Write, at          28791615000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          28791675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28793325000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28793355000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28793655000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28793685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28794585000
*** monitor - CBE Bus Changed when TRDY Desserted, at          28794615000
 test target 1 - Starting Memory Write, at          28795815000
 test master 2 - Starting Memory Write, at          28795815000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          28798755000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          28800405000
 test master 1 - Starting Memory Read, at          28800705000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          28800855000
 test target 1 - Starting Config Write, at          28803465000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          28805895000
 test target 1 - Starting Memory Write, at          28806075000
 test target 1 - Starting Memory Write, at          28806255000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          28806765000
 test target 1 - Starting Memory Write, at          28806975000
 test target 1 - Starting Memory Write, at          28807185000
 test target 1 - Starting Memory Write, at          28807695000
 test target 1 - Starting Memory Write, at          28808025000
 test target 1 - Starting Memory Write, at          28808535000
 test target 1 - Starting Memory Write, at          28809225000
 test target 1 - Starting Memory Write, at          28809435000
 test target 1 - Starting Memory Write, at          28810125000
 test target 1 - Starting Memory Write, at          28810485000
 test target 1 - Starting Memory Write, at          28811025000
 test target 1 - Starting Memory Write, at          28814235000
 test target 1 - Starting Memory Write, at          28814445000
 test target 1 - Starting Memory Write, at          28814655000
 test target 1 - Starting Memory Write, at          28815015000
 test target 1 - Starting Memory Write, at          28815375000
 test target 1 - Starting Memory Read, at          28824165000
 test target 1 - Starting Memory Read, at          28825275000
 test target 1 - Starting Memory Read, at          28826475000
 test target 1 - Starting Memory Read, at          28827675000
 test target 1 - Starting Memory Read, at          28828875000
 test target 1 - Starting Memory Read, at          28830075000
 test target 1 - Starting Memory Read, at          28831275000
 test target 1 - Starting Memory Read, at          28832475000
 test target 1 - Starting Memory Read, at          28833675000
 test target 1 - Starting Memory Read, at          28834875000
 test target 1 - Starting Memory Read, at          28836075000
 test target 1 - Starting Memory Read, at          28837275000
 test target 1 - Starting Memory Read, at          28838475000
 test target 1 - Starting Memory Read, at          28839675000
 test target 1 - Starting Memory Read, at          28840875000
 test target 1 - Starting Memory Read, at          28842075000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          28843245000
 test target 1 - Starting Memory Read, at          28843425000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          28844775000
 test target 1 - Starting Memory Read, at          28847265000
 test target 1 - Starting Memory Read, at          28847955000
 test target 1 - Starting Memory Read, at          28848705000
 test target 1 - Starting Memory Read, at          28849515000
 test target 1 - Starting Memory Read, at          28850325000
 test target 1 - Starting Memory Read, at          28851705000
 test target 1 - Starting Memory Read, at          28852905000
 test target 1 - Starting Memory Read, at          28853865000
 test target 1 - Starting Memory Read, at          28857105000
 test target 1 - Starting Memory Read, at          28860285000
 test target 1 - Starting Memory Read, at          28861125000
 test target 1 - Starting Memory Read, at          28861965000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          28863045000
 test master 1 - Starting Memory Write, at          28863495000
 test target 1 - Starting Memory Write, at          28863495000
 test target 1 - Starting Memory Write, at          28863675000
 test target 1 - Starting Memory Read, at          28864215000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          28867155000
 test master 1 - Starting Memory Write, at          28867605000
 test target 1 - Starting Memory Write, at          28867605000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          28872525000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          28873605000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          28898685000
 test target 1 - Starting Config Write, at          28899675000
 test target 1 - Starting Config Write, at          28900665000
 test target 2 - Starting Config Write, at          28901685000
 test target 2 - Starting Config Write, at          28902675000
 test target 2 - Starting Config Write, at          28903665000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          28905675000
 test target 1 - Starting Memory Read, at          28905945000
 test target 1 - Starting Memory Write, at          28906575000
 test target 1 - Starting Memory Read, at          28906845000
 test target 1 - Starting Memory Write, at          28907685000
 test target 1 - Starting Memory Read, at          28909125000
 test target 1 - Starting Memory Read, at          28909785000
 test target 1 - Starting Memory Read, at          28910355000
 test target 1 - Starting Memory Read, at          28910925000
 test target 1 - Starting Memory Read, at          28911795000
 test target 1 - Starting Memory Read, at          28912995000
 test target 1 - Starting Memory Read, at          28913985000
 test target 1 - Starting Memory Read, at          28915185000
 test target 1 - Starting Memory Read, at          28916145000
 test target 1 - Starting Memory Read, at          28919055000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          28925715000
 test target 1 - Starting Memory Read, at          28925985000
 test target 1 - Starting Memory Write, at          28926615000
 test target 1 - Starting Memory Read, at          28926885000
 test target 1 - Starting Memory Write, at          28927725000
 test target 1 - Starting Memory Read, at          28929165000
 test target 1 - Starting Memory Read, at          28929825000
 test target 1 - Starting Memory Read, at          28930395000
 test target 1 - Starting Memory Read, at          28930965000
 test target 1 - Starting Memory Read, at          28931835000
 test target 1 - Starting Memory Read, at          28933035000
 test target 1 - Starting Memory Read, at          28934025000
 test target 1 - Starting Memory Read, at          28935225000
 test target 1 - Starting Memory Read, at          28936185000
 test target 1 - Starting Memory Read, at          28939095000
 test target 1 - Starting Memory Write, at          28945755000
 test target 1 - Starting Memory Read, at          28946025000
 test target 1 - Starting Memory Write, at          28946655000
 test target 1 - Starting Memory Read, at          28946925000
 test target 1 - Starting Memory Write, at          28947765000
 test target 1 - Starting Memory Read, at          28949205000
 test target 1 - Starting Memory Read, at          28949865000
 test target 1 - Starting Memory Read, at          28950435000
 test target 1 - Starting Memory Read, at          28951005000
 test target 1 - Starting Memory Read, at          28951875000
 test target 1 - Starting Memory Read, at          28953075000
 test target 1 - Starting Memory Read, at          28954065000
 test target 1 - Starting Memory Read, at          28955265000
 test target 1 - Starting Memory Read, at          28956225000
 test target 1 - Starting Memory Read, at          28959135000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          28971765000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          28978365000
 test target 1 - Starting Memory Write, at          28979235000
 test target 1 - Starting Memory Read, at          28979805000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          28981275000
 test target 1 - Starting Config Write, at          28983345000
 test target 1 - Starting Memory Read, at          28984095000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          28985685000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          28987965000
 test target 1 - Starting Memory Write, at          28989255000
 test target 1 - Starting Memory Write, at          28989585000
 test target 1 - Starting Memory Read, at          28989855000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          28992285000
 test target 1 - Starting Memory Write, at          28995435000
 test target 1 - Starting Memory Write, at          28995885000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          29000175000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          29002245000
 test target 1 - Starting Memory Read, at          29003655000
 test target 1 - Starting Memory Read, at          29004825000
 test target 1 - Starting Memory Read, at          29006625000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          29012865000
 test target 2 - Starting Config Write, at          29013885000
 test target 1 - Starting Memory Write, at          29014635000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          29014815000
 test target 1 - Starting Memory Write, at          29015895000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          29016075000
 test target 1 - Starting Memory Write, at          29017155000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          29018625000
 test target 1 - Starting Memory Read, at          29020935000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          29021115000
 test target 1 - Starting Memory Read, at          29023305000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          29025075000
 test master 2 - Starting Memory Write, at          29025075000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          29025135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29026005000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29026035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29026335000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29026365000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29027265000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29027295000
 test target 1 - Starting Memory Write, at          29029125000
 test master 2 - Starting Memory Write, at          29029125000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29030895000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29030925000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29032635000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29032665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29034375000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29034405000
 test target 1 - Starting Memory Write, at          29036475000
 test master 2 - Starting Memory Write, at          29036475000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          29036535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29038215000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29038245000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29038545000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29038575000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29039475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29039505000
 test target 1 - Starting Memory Write, at          29040705000
 test master 2 - Starting Memory Write, at          29040705000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          29043675000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          29045325000
 test master 1 - Starting Memory Read, at          29045625000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          29045775000
 test target 1 - Starting Config Write, at          29048385000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          29050815000
 test target 1 - Starting Memory Write, at          29051025000
 test target 1 - Starting Memory Write, at          29051235000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          29051775000
 test target 1 - Starting Memory Write, at          29052015000
 test target 1 - Starting Memory Write, at          29052255000
 test target 1 - Starting Memory Write, at          29052795000
 test target 1 - Starting Memory Write, at          29053155000
 test target 1 - Starting Memory Write, at          29053695000
 test target 1 - Starting Memory Write, at          29054415000
 test target 1 - Starting Memory Write, at          29054655000
 test target 1 - Starting Memory Write, at          29055375000
 test target 1 - Starting Memory Write, at          29055765000
 test target 1 - Starting Memory Write, at          29056335000
 test target 1 - Starting Memory Write, at          29059575000
 test target 1 - Starting Memory Write, at          29059815000
 test target 1 - Starting Memory Write, at          29060055000
 test target 1 - Starting Memory Write, at          29060445000
 test target 1 - Starting Memory Write, at          29060835000
 test target 1 - Starting Memory Read, at          29069655000
 test target 1 - Starting Memory Read, at          29070825000
 test target 1 - Starting Memory Read, at          29072025000
 test target 1 - Starting Memory Read, at          29073225000
 test target 1 - Starting Memory Read, at          29074425000
 test target 1 - Starting Memory Read, at          29075625000
 test target 1 - Starting Memory Read, at          29076825000
 test target 1 - Starting Memory Read, at          29078025000
 test target 1 - Starting Memory Read, at          29079225000
 test target 1 - Starting Memory Read, at          29080425000
 test target 1 - Starting Memory Read, at          29081625000
 test target 1 - Starting Memory Read, at          29082825000
 test target 1 - Starting Memory Read, at          29084025000
 test target 1 - Starting Memory Read, at          29085225000
 test target 1 - Starting Memory Read, at          29086425000
 test target 1 - Starting Memory Read, at          29087625000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          29088765000
 test target 1 - Starting Memory Read, at          29088975000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          29090295000
 test target 1 - Starting Memory Read, at          29092815000
 test target 1 - Starting Memory Read, at          29093505000
 test target 1 - Starting Memory Read, at          29094225000
 test target 1 - Starting Memory Read, at          29095065000
 test target 1 - Starting Memory Read, at          29095875000
 test target 1 - Starting Memory Read, at          29097225000
 test target 1 - Starting Memory Read, at          29098425000
 test target 1 - Starting Memory Read, at          29099385000
 test target 1 - Starting Memory Read, at          29102625000
 test target 1 - Starting Memory Read, at          29105925000
 test target 1 - Starting Memory Read, at          29106855000
 test target 1 - Starting Memory Read, at          29107785000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          29108955000
 test master 1 - Starting Memory Write, at          29109285000
 test target 1 - Starting Memory Write, at          29109285000
 test target 1 - Starting Memory Write, at          29109495000
 test target 1 - Starting Memory Read, at          29110215000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          29113155000
 test master 1 - Starting Memory Write, at          29113485000
 test target 1 - Starting Memory Write, at          29113485000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29118675000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          29118915000
 test master 2 - Starting Memory Read, at          29119095000
 test master 2 - Starting Memory Read, at          29119275000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29121015000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          29121435000
 test master 2 - Starting Memory Read, at          29121615000
 test master 2 - Starting Memory Read, at          29121795000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29123235000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29123805000
 test master 2 - Starting Memory Read Line Multiple, at          29123985000
 test master 2 - Starting Memory Read Line Multiple, at          29124225000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29126415000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29137035000
 test master 2 - Starting Memory Read Line Multiple, at          29137215000
 test master 2 - Starting Memory Read Line Multiple, at          29137485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29138565000
 test master 2 - Starting Memory Read Line Multiple, at          29138745000
 test master 2 - Starting Memory Read Line Multiple, at          29138985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29140065000
 test master 2 - Starting Memory Read Line Multiple, at          29140245000
 test master 2 - Starting Memory Read Line Multiple, at          29140485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29141565000
 test master 2 - Starting Memory Read Line Multiple, at          29141745000
 test master 2 - Starting Memory Read Line Multiple, at          29141985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29143065000
 test master 2 - Starting Memory Read Line Multiple, at          29143245000
 test master 2 - Starting Memory Read Line Multiple, at          29143485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29144565000
 test master 2 - Starting Memory Read Line Multiple, at          29144745000
 test master 2 - Starting Memory Read Line Multiple, at          29144985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29146065000
 test master 2 - Starting Memory Read Line Multiple, at          29146245000
 test master 2 - Starting Memory Read Line Multiple, at          29146485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29147565000
 test master 2 - Starting Memory Read Line Multiple, at          29147745000
 test master 2 - Starting Memory Read Line Multiple, at          29147985000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          29149065000
 test master 2 - Starting Memory Read Line, at          29149245000
 test master 2 - Starting Memory Read Line, at          29149425000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          29150055000
 test master 2 - Starting Memory Read Line, at          29150235000
 test master 2 - Starting Memory Read Line, at          29150415000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29151615000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29153175000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29156115000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29157975000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          29163045000
 test master 2 - Starting Memory Write, at          29163285000
 test master 2 - Starting Memory Write, at          29163525000
 test master 2 - Starting Memory Write, at          29163765000
 test master 2 - Starting Memory Write, at          29164005000
 test master 1 - Starting Memory Read, at          29164365000
 test master 1 - Starting Memory Read, at          29164635000
 test master 1 - Starting Memory Read, at          29165175000
 test master 1 - Starting Memory Read, at          29165445000
 test master 1 - Starting Memory Read, at          29165985000
 test master 1 - Starting Memory Read, at          29166255000
 test master 2 - Starting Memory Write, at          29167545000
 test master 2 - Starting Memory Write, at          29167785000
 test master 2 - Starting Memory Write, at          29168025000
 test master 2 - Starting Memory Write, at          29168265000
 test master 2 - Starting Memory Write, at          29168505000
 test master 1 - Starting Memory Read, at          29168865000
 test master 1 - Starting Memory Read, at          29169135000
 test master 1 - Starting Memory Read, at          29169675000
 test master 1 - Starting Memory Read, at          29169945000
 test master 1 - Starting Memory Read, at          29170485000
 test master 1 - Starting Memory Read, at          29170755000
 test master 2 - Starting Memory Write, at          29172555000
 test master 2 - Starting Memory Write, at          29173635000
 test master 2 - Starting Memory Write, at          29174715000
 test master 2 - Starting Memory Write, at          29175795000
 test master 2 - Starting Memory Write, at          29178015000
 test master 2 - Starting Memory Write, at          29179095000
 test master 2 - Starting Memory Write, at          29180175000
 test master 2 - Starting Memory Write, at          29181255000
 test master 2 - Starting Memory Write, at          29183475000
 test master 2 - Starting Memory Write, at          29185575000
 test master 2 - Starting Memory Write, at          29187675000
 test master 2 - Starting Memory Write, at          29189775000
 test master 2 - Starting Memory Write, at          29193015000
 test master 2 - Starting Memory Write, at          29195355000
 test master 2 - Starting Memory Write, at          29197695000
 test master 2 - Starting Memory Write, at          29200035000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          29204505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29204535000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29206635000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          29206875000
 test master 2 - Starting Memory Read, at          29207055000
 test master 2 - Starting Memory Read, at          29207235000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29208975000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          29209395000
 test master 2 - Starting Memory Read, at          29209575000
 test master 2 - Starting Memory Read, at          29209755000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29211195000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29211765000
 test master 2 - Starting Memory Read Line Multiple, at          29211945000
 test master 2 - Starting Memory Read Line Multiple, at          29212185000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29214375000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29224995000
 test master 2 - Starting Memory Read Line Multiple, at          29225175000
 test master 2 - Starting Memory Read Line Multiple, at          29225445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29226525000
 test master 2 - Starting Memory Read Line Multiple, at          29226705000
 test master 2 - Starting Memory Read Line Multiple, at          29226945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29228025000
 test master 2 - Starting Memory Read Line Multiple, at          29228205000
 test master 2 - Starting Memory Read Line Multiple, at          29228445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29229525000
 test master 2 - Starting Memory Read Line Multiple, at          29229705000
 test master 2 - Starting Memory Read Line Multiple, at          29229945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29231025000
 test master 2 - Starting Memory Read Line Multiple, at          29231205000
 test master 2 - Starting Memory Read Line Multiple, at          29231445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29232525000
 test master 2 - Starting Memory Read Line Multiple, at          29232705000
 test master 2 - Starting Memory Read Line Multiple, at          29232945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29234025000
 test master 2 - Starting Memory Read Line Multiple, at          29234205000
 test master 2 - Starting Memory Read Line Multiple, at          29234445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29235525000
 test master 2 - Starting Memory Read Line Multiple, at          29235705000
 test master 2 - Starting Memory Read Line Multiple, at          29235945000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          29237025000
 test master 2 - Starting Memory Read Line, at          29237205000
 test master 2 - Starting Memory Read Line, at          29237385000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          29238015000
 test master 2 - Starting Memory Read Line, at          29238195000
 test master 2 - Starting Memory Read Line, at          29238375000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29239575000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29241135000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29244075000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29245935000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          29251005000
 test master 2 - Starting Memory Write, at          29251245000
 test master 2 - Starting Memory Write, at          29251485000
 test master 2 - Starting Memory Write, at          29251725000
 test master 2 - Starting Memory Write, at          29251965000
 test master 1 - Starting Memory Read, at          29252325000
 test master 1 - Starting Memory Read, at          29252595000
 test master 1 - Starting Memory Read, at          29253135000
 test master 1 - Starting Memory Read, at          29253405000
 test master 1 - Starting Memory Read, at          29253945000
 test master 1 - Starting Memory Read, at          29254215000
 test master 2 - Starting Memory Write, at          29255505000
 test master 2 - Starting Memory Write, at          29255745000
 test master 2 - Starting Memory Write, at          29255985000
 test master 2 - Starting Memory Write, at          29256225000
 test master 2 - Starting Memory Write, at          29256465000
 test master 1 - Starting Memory Read, at          29256825000
 test master 1 - Starting Memory Read, at          29257095000
 test master 1 - Starting Memory Read, at          29257635000
 test master 1 - Starting Memory Read, at          29257905000
 test master 1 - Starting Memory Read, at          29258445000
 test master 1 - Starting Memory Read, at          29258715000
 test master 2 - Starting Memory Write, at          29260515000
 test master 2 - Starting Memory Write, at          29261595000
 test master 2 - Starting Memory Write, at          29262675000
 test master 2 - Starting Memory Write, at          29263755000
 test master 2 - Starting Memory Write, at          29265975000
 test master 2 - Starting Memory Write, at          29267055000
 test master 2 - Starting Memory Write, at          29268135000
 test master 2 - Starting Memory Write, at          29269215000
 test master 2 - Starting Memory Write, at          29271435000
 test master 2 - Starting Memory Write, at          29273535000
 test master 2 - Starting Memory Write, at          29275635000
 test master 2 - Starting Memory Write, at          29277735000
 test master 2 - Starting Memory Write, at          29280975000
 test master 2 - Starting Memory Write, at          29283315000
 test master 2 - Starting Memory Write, at          29285655000
 test master 2 - Starting Memory Write, at          29287995000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          29292465000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29292495000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29294595000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          29294835000
 test master 2 - Starting Memory Read, at          29295015000
 test master 2 - Starting Memory Read, at          29295195000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29296935000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          29297355000
 test master 2 - Starting Memory Read, at          29297535000
 test master 2 - Starting Memory Read, at          29297715000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29299155000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29299725000
 test master 2 - Starting Memory Read Line Multiple, at          29299905000
 test master 2 - Starting Memory Read Line Multiple, at          29300145000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29302335000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29312955000
 test master 2 - Starting Memory Read Line Multiple, at          29313135000
 test master 2 - Starting Memory Read Line Multiple, at          29313405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29314485000
 test master 2 - Starting Memory Read Line Multiple, at          29314665000
 test master 2 - Starting Memory Read Line Multiple, at          29314905000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29315985000
 test master 2 - Starting Memory Read Line Multiple, at          29316165000
 test master 2 - Starting Memory Read Line Multiple, at          29316405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29317485000
 test master 2 - Starting Memory Read Line Multiple, at          29317665000
 test master 2 - Starting Memory Read Line Multiple, at          29317905000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29318985000
 test master 2 - Starting Memory Read Line Multiple, at          29319165000
 test master 2 - Starting Memory Read Line Multiple, at          29319405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29320485000
 test master 2 - Starting Memory Read Line Multiple, at          29320665000
 test master 2 - Starting Memory Read Line Multiple, at          29320905000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29321985000
 test master 2 - Starting Memory Read Line Multiple, at          29322165000
 test master 2 - Starting Memory Read Line Multiple, at          29322405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29323485000
 test master 2 - Starting Memory Read Line Multiple, at          29323665000
 test master 2 - Starting Memory Read Line Multiple, at          29323905000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          29324985000
 test master 2 - Starting Memory Read Line, at          29325165000
 test master 2 - Starting Memory Read Line, at          29325345000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          29325975000
 test master 2 - Starting Memory Read Line, at          29326155000
 test master 2 - Starting Memory Read Line, at          29326335000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29327535000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29329095000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29332035000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29333895000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          29338965000
 test master 2 - Starting Memory Write, at          29339205000
 test master 2 - Starting Memory Write, at          29339445000
 test master 2 - Starting Memory Write, at          29339685000
 test master 2 - Starting Memory Write, at          29339925000
 test master 1 - Starting Memory Read, at          29340285000
 test master 1 - Starting Memory Read, at          29340555000
 test master 1 - Starting Memory Read, at          29341095000
 test master 1 - Starting Memory Read, at          29341365000
 test master 1 - Starting Memory Read, at          29341905000
 test master 1 - Starting Memory Read, at          29342175000
 test master 2 - Starting Memory Write, at          29343465000
 test master 2 - Starting Memory Write, at          29343705000
 test master 2 - Starting Memory Write, at          29343945000
 test master 2 - Starting Memory Write, at          29344185000
 test master 2 - Starting Memory Write, at          29344425000
 test master 1 - Starting Memory Read, at          29344785000
 test master 1 - Starting Memory Read, at          29345055000
 test master 1 - Starting Memory Read, at          29345595000
 test master 1 - Starting Memory Read, at          29345865000
 test master 1 - Starting Memory Read, at          29346405000
 test master 1 - Starting Memory Read, at          29346675000
 test master 2 - Starting Memory Write, at          29348475000
 test master 2 - Starting Memory Write, at          29349555000
 test master 2 - Starting Memory Write, at          29350635000
 test master 2 - Starting Memory Write, at          29351715000
 test master 2 - Starting Memory Write, at          29353935000
 test master 2 - Starting Memory Write, at          29355015000
 test master 2 - Starting Memory Write, at          29356095000
 test master 2 - Starting Memory Write, at          29357175000
 test master 2 - Starting Memory Write, at          29359395000
 test master 2 - Starting Memory Write, at          29361495000
 test master 2 - Starting Memory Write, at          29363595000
 test master 2 - Starting Memory Write, at          29365695000
 test master 2 - Starting Memory Write, at          29368935000
 test master 2 - Starting Memory Write, at          29371275000
 test master 2 - Starting Memory Write, at          29373615000
 test master 2 - Starting Memory Write, at          29375955000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          29380425000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29380455000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29382555000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          29382795000
 test master 2 - Starting Memory Read, at          29382975000
 test master 2 - Starting Memory Read, at          29383155000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29384895000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          29385315000
 test master 2 - Starting Memory Read, at          29385495000
 test master 2 - Starting Memory Read, at          29385675000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29387115000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29387685000
 test master 2 - Starting Memory Read Line Multiple, at          29387865000
 test master 2 - Starting Memory Read Line Multiple, at          29388105000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29390295000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29400915000
 test master 2 - Starting Memory Read Line Multiple, at          29401095000
 test master 2 - Starting Memory Read Line Multiple, at          29401365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29402445000
 test master 2 - Starting Memory Read Line Multiple, at          29402625000
 test master 2 - Starting Memory Read Line Multiple, at          29402865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29403945000
 test master 2 - Starting Memory Read Line Multiple, at          29404125000
 test master 2 - Starting Memory Read Line Multiple, at          29404365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29405445000
 test master 2 - Starting Memory Read Line Multiple, at          29405625000
 test master 2 - Starting Memory Read Line Multiple, at          29405865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29406945000
 test master 2 - Starting Memory Read Line Multiple, at          29407125000
 test master 2 - Starting Memory Read Line Multiple, at          29407365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29408445000
 test master 2 - Starting Memory Read Line Multiple, at          29408625000
 test master 2 - Starting Memory Read Line Multiple, at          29408865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29409945000
 test master 2 - Starting Memory Read Line Multiple, at          29410125000
 test master 2 - Starting Memory Read Line Multiple, at          29410365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          29411445000
 test master 2 - Starting Memory Read Line Multiple, at          29411625000
 test master 2 - Starting Memory Read Line Multiple, at          29411865000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          29412945000
 test master 2 - Starting Memory Read Line, at          29413125000
 test master 2 - Starting Memory Read Line, at          29413305000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          29413935000
 test master 2 - Starting Memory Read Line, at          29414115000
 test master 2 - Starting Memory Read Line, at          29414295000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29415495000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29417055000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29419995000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          29421855000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          29426925000
 test master 2 - Starting Memory Write, at          29427165000
 test master 2 - Starting Memory Write, at          29427405000
 test master 2 - Starting Memory Write, at          29427645000
 test master 2 - Starting Memory Write, at          29427885000
 test master 1 - Starting Memory Read, at          29428245000
 test master 1 - Starting Memory Read, at          29428515000
 test master 1 - Starting Memory Read, at          29429055000
 test master 1 - Starting Memory Read, at          29429325000
 test master 1 - Starting Memory Read, at          29429865000
 test master 1 - Starting Memory Read, at          29430135000
 test master 2 - Starting Memory Write, at          29431425000
 test master 2 - Starting Memory Write, at          29431665000
 test master 2 - Starting Memory Write, at          29431905000
 test master 2 - Starting Memory Write, at          29432145000
 test master 2 - Starting Memory Write, at          29432385000
 test master 1 - Starting Memory Read, at          29432745000
 test master 1 - Starting Memory Read, at          29433015000
 test master 1 - Starting Memory Read, at          29433555000
 test master 1 - Starting Memory Read, at          29433825000
 test master 1 - Starting Memory Read, at          29434365000
 test master 1 - Starting Memory Read, at          29434635000
 test master 2 - Starting Memory Write, at          29436435000
 test master 2 - Starting Memory Write, at          29437515000
 test master 2 - Starting Memory Write, at          29438595000
 test master 2 - Starting Memory Write, at          29439675000
 test master 2 - Starting Memory Write, at          29441895000
 test master 2 - Starting Memory Write, at          29442975000
 test master 2 - Starting Memory Write, at          29444055000
 test master 2 - Starting Memory Write, at          29445135000
 test master 2 - Starting Memory Write, at          29447355000
 test master 2 - Starting Memory Write, at          29449455000
 test master 2 - Starting Memory Write, at          29451555000
 test master 2 - Starting Memory Write, at          29453655000
 test master 2 - Starting Memory Write, at          29456895000
 test master 2 - Starting Memory Write, at          29459235000
 test master 2 - Starting Memory Write, at          29461575000
 test master 2 - Starting Memory Write, at          29463915000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          29468385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29468415000
 test master 1 - Starting Memory Read, at          29470515000
 test master 1 - Starting Memory Read, at          29470815000
 test master 1 - Starting Memory Read, at          29472045000
 test master 1 - Starting Memory Read, at          29472345000
 test master 1 - Starting Memory Read Line, at          29473605000
 test master 1 - Starting Memory Read Line, at          29473905000
 test master 1 - Starting Memory Read Line, at          29475165000
 test master 1 - Starting Memory Read Line, at          29475465000
 test master 1 - Starting Memory Read Line, at          29476785000
 test master 1 - Starting Memory Read Line, at          29477145000
 test master 1 - Starting Memory Read Line, at          29478765000
 test master 1 - Starting Memory Read Line, at          29479125000
 test master 1 - Starting Memory Read Line Multiple, at          29480745000
 test master 1 - Starting Memory Read Line Multiple, at          29481165000
 test master 1 - Starting Memory Read Line Multiple, at          29483205000
 test master 1 - Starting Memory Read Line Multiple, at          29483625000
 test master 1 - Starting Memory Read Line, at          29485665000
 test master 1 - Starting Memory Read Line, at          29486025000
 test master 1 - Starting Memory Read, at          29488575000
 test master 1 - Starting Memory Read, at          29488875000
 test target 1 - Starting Config Write, at          29492145000
 test master 1 - Starting Memory Write, at          29492655000
 test master 1 - Starting Memory Write, at          29501925000
 test master 1 - Starting Memory Write, at          29503275000
 test master 1 - Starting Memory Write, at          29511945000
 test master 1 - Starting Memory Write, at          29513295000
 test master 1 - Starting Memory Read Line, at          29522565000
 test master 1 - Starting Memory Write, at          29524065000
 test master 1 - Starting Memory Read Line, at          29533335000
 test target 1 - Starting Config Write, at          29536725000
 test master 1 - Starting Memory Write, at          29537235000
 test master 1 - Starting Memory Write, at          29537355000
 test master 1 - Starting Memory Write, at          29537595000
 test master 1 - Starting Memory Read, at          29537715000
 test master 1 - Starting Memory Write, at          29538015000
 test master 1 - Starting Memory Read, at          29538135000
 test master 1 - Starting Memory Write, at          29539755000
 test master 1 - Starting Memory Write, at          29550375000
 test master 2 - Starting Memory Read Line, at          29561115000
 test master 2 - Starting Memory Read Line, at          29561445000
 test master 2 - Starting Memory Read Line, at          29562105000
 test master 2 - Starting Memory Read Line, at          29562435000
 test master 1 - Starting Memory Write, at          29563185000
 test master 1 - Starting Memory Write, at          29563515000
 test master 1 - Starting Memory Write, at          29563875000
 test master 2 - Starting Memory Read Line, at          29564355000
 test master 2 - Starting Memory Read Line, at          29564655000
 test master 2 - Starting Memory Read Line, at          29564985000
 test master 2 - Starting Memory Read Line, at          29565285000
 test master 2 - Starting Memory Read Line Multiple, at          29565645000
 test master 2 - Starting Memory Read Line Multiple, at          29565945000
 test master 1 - Starting Memory Write, at          29567895000
 test master 1 - Starting Memory Write, at          29568225000
 test master 2 - Starting Memory Read, at          29568705000
 test master 2 - Starting Memory Read, at          29569005000
 test master 2 - Starting Memory Read, at          29569335000
 test master 2 - Starting Memory Read, at          29569635000
 test master 1 - Starting Memory Write, at          29571315000
 test master 1 - Starting Memory Read, at          29571495000
 test master 1 - Starting Memory Write, at          29571675000
 test master 1 - Starting Memory Read, at          29571885000
 test master 1 - Starting Memory Write, at          29572095000
 test master 1 - Starting Memory Read, at          29572275000
 test master 1 - Starting Memory Read, at          29572485000
 test master 1 - Starting Memory Write, at          29572695000
 test master 1 - Starting Memory Write, at          29572875000
 test master 1 - Starting Memory Read, at          29573055000
 test master 1 - Starting Memory Write, at          29573235000
 test master 1 - Starting Memory Write, at          29573445000
 test master 1 - Starting Memory Write, at          29573655000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          29578065000
 test target 1 - Starting Memory Write, at          29578275000
 test master 1 - Starting Memory Write, at          29578455000
 test target 1 - Starting Memory Write, at          29578635000
 test target 1 - Starting Memory Write, at          29578845000
 test target 1 - Starting Memory Write, at          29579055000
 test master 1 - Starting Memory Write, at          29579355000
 test target 1 - Starting Memory Write, at          29579865000
 test target 1 - Starting Memory Write, at          29580435000
 test target 1 - Starting Memory Write, at          29580675000
 test master 1 - Starting Memory Write, at          29580885000
 test target 1 - Starting Memory Write, at          29581365000
 test target 1 - Starting Memory Write, at          29581605000
 test target 1 - Starting Memory Write, at          29581845000
 test master 1 - Starting Memory Write, at          29582445000
 test target 1 - Starting Memory Write, at          29583405000
 test target 1 - Starting Memory Write, at          29584335000
 test target 1 - Starting Memory Write, at          29584545000
 test master 1 - Starting Memory Read, at          29584725000
 test target 1 - Starting Memory Write, at          29584905000
 test master 1 - Starting Memory Read, at          29585085000
 test target 1 - Starting Memory Write, at          29585265000
 test master 1 - Starting Memory Read, at          29585445000
 test target 1 - Starting Memory Write, at          29585625000
 test master 1 - Starting Memory Read, at          29585805000
 test target 1 - Starting Memory Write, at          29585985000
 test master 1 - Starting Memory Read, at          29586165000
 test target 1 - Starting Memory Write, at          29586345000
 test master 1 - Starting Memory Write, at          29586525000
 test target 1 - Starting Memory Write, at          29586705000
 test target 1 - Starting Memory Write, at          29586915000
 test target 1 - Starting Memory Write, at          29587125000
 test target 1 - Starting Memory Read, at          29587395000
 test master 1 - Starting Memory Write, at          29587695000
 test master 1 - Starting Memory Read, at          29587935000
 test target 1 - Starting Memory Write, at          29588445000
 test master 1 - Starting Memory Write, at          29588835000
 test target 1 - Starting Memory Read, at          29589285000
 test target 1 - Starting Memory Write, at          29590095000
 test master 1 - Starting Memory Read, at          29590395000
 test master 1 - Starting Memory Write, at          29590695000
 test master 1 - Starting Memory Write, at          29591055000
 test master 1 - Starting Memory Read, at          29591295000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          29593965000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          29595075000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          29621205000
 test target 1 - Starting Config Write, at          29622105000
 test target 1 - Starting Config Write, at          29622975000
 test target 2 - Starting Config Write, at          29623845000
 test target 2 - Starting Config Write, at          29624745000
 test target 2 - Starting Config Write, at          29625615000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          29627595000
 test target 1 - Starting Memory Read, at          29627775000
 test target 1 - Starting Memory Write, at          29628375000
 test target 1 - Starting Memory Read, at          29628555000
 test target 1 - Starting Memory Write, at          29629515000
 test target 1 - Starting Memory Read, at          29630745000
 test target 1 - Starting Memory Read, at          29631255000
 test target 1 - Starting Memory Read, at          29631825000
 test target 1 - Starting Memory Read, at          29632425000
 test target 1 - Starting Memory Read, at          29633295000
 test target 1 - Starting Memory Read, at          29634375000
 test target 1 - Starting Memory Read, at          29635245000
 test target 1 - Starting Memory Read, at          29636325000
 test target 1 - Starting Memory Read, at          29637195000
 test target 1 - Starting Memory Read, at          29639625000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          29646675000
 test target 1 - Starting Memory Read, at          29646855000
 test target 1 - Starting Memory Write, at          29647455000
 test target 1 - Starting Memory Read, at          29647635000
 test target 1 - Starting Memory Write, at          29648595000
 test target 1 - Starting Memory Read, at          29649825000
 test target 1 - Starting Memory Read, at          29650335000
 test target 1 - Starting Memory Read, at          29650905000
 test target 1 - Starting Memory Read, at          29651505000
 test target 1 - Starting Memory Read, at          29652375000
 test target 1 - Starting Memory Read, at          29653455000
 test target 1 - Starting Memory Read, at          29654325000
 test target 1 - Starting Memory Read, at          29655405000
 test target 1 - Starting Memory Read, at          29656275000
 test target 1 - Starting Memory Read, at          29658705000
 test target 1 - Starting Memory Write, at          29665755000
 test target 1 - Starting Memory Read, at          29665935000
 test target 1 - Starting Memory Write, at          29666535000
 test target 1 - Starting Memory Read, at          29666715000
 test target 1 - Starting Memory Write, at          29667675000
 test target 1 - Starting Memory Read, at          29668905000
 test target 1 - Starting Memory Read, at          29669415000
 test target 1 - Starting Memory Read, at          29669985000
 test target 1 - Starting Memory Read, at          29670585000
 test target 1 - Starting Memory Read, at          29671455000
 test target 1 - Starting Memory Read, at          29672535000
 test target 1 - Starting Memory Read, at          29673405000
 test target 1 - Starting Memory Read, at          29674485000
 test target 1 - Starting Memory Read, at          29675355000
 test target 1 - Starting Memory Read, at          29677785000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          29691375000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          29698035000
 test target 1 - Starting Memory Write, at          29698815000
 test target 1 - Starting Memory Read, at          29699235000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          29700585000
 test target 1 - Starting Config Write, at          29702625000
 test target 1 - Starting Memory Read, at          29703255000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          29704755000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          29706915000
 test target 1 - Starting Memory Write, at          29708085000
 test target 1 - Starting Memory Write, at          29708325000
 test target 1 - Starting Memory Read, at          29708505000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          29710935000
 test target 1 - Starting Memory Write, at          29714175000
 test target 1 - Starting Memory Write, at          29714505000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          29718735000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          29720715000
 test target 1 - Starting Memory Read, at          29722065000
 test target 1 - Starting Memory Read, at          29723085000
 test target 1 - Starting Memory Read, at          29724825000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          29731275000
 test target 2 - Starting Config Write, at          29732145000
 test target 1 - Starting Memory Write, at          29732775000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          29732865000
 test target 1 - Starting Memory Write, at          29733975000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          29734065000
 test target 1 - Starting Memory Write, at          29735175000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          29736615000
 test target 1 - Starting Memory Read, at          29738865000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          29738985000
 test target 1 - Starting Memory Read, at          29741235000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          29742945000
 test master 2 - Starting Memory Write, at          29742945000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          29743005000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29743815000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29743845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29744145000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29744175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29745135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29745165000
 test target 1 - Starting Memory Write, at          29747055000
 test master 2 - Starting Memory Write, at          29747055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29748795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29748825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29750595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29750625000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29752395000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29752425000
 test target 1 - Starting Memory Write, at          29754585000
 test master 2 - Starting Memory Write, at          29754585000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          29754645000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29756295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29756325000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29756625000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29756655000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29757615000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29757645000
 test target 1 - Starting Memory Write, at          29758875000
 test master 2 - Starting Memory Write, at          29758875000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          29761965000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          29763675000
 test master 1 - Starting Memory Read, at          29764065000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          29764215000
 test target 1 - Starting Config Write, at          29766975000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          29769435000
 test target 1 - Starting Memory Write, at          29769555000
 test target 1 - Starting Memory Write, at          29769675000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          29770155000
 test target 1 - Starting Memory Write, at          29770305000
 test target 1 - Starting Memory Write, at          29770455000
 test target 1 - Starting Memory Write, at          29770935000
 test target 1 - Starting Memory Write, at          29771175000
 test target 1 - Starting Memory Write, at          29771655000
 test target 1 - Starting Memory Write, at          29772315000
 test target 1 - Starting Memory Write, at          29772465000
 test target 1 - Starting Memory Write, at          29773095000
 test target 1 - Starting Memory Write, at          29773365000
 test target 1 - Starting Memory Write, at          29773875000
 test target 1 - Starting Memory Write, at          29778195000
 test target 1 - Starting Memory Write, at          29778345000
 test target 1 - Starting Memory Write, at          29778495000
 test target 1 - Starting Memory Write, at          29778765000
 test target 1 - Starting Memory Write, at          29779035000
 test target 1 - Starting Memory Read, at          29786055000
 test target 1 - Starting Memory Read, at          29787105000
 test target 1 - Starting Memory Read, at          29788245000
 test target 1 - Starting Memory Read, at          29789355000
 test target 1 - Starting Memory Read, at          29790465000
 test target 1 - Starting Memory Read, at          29791605000
 test target 1 - Starting Memory Read, at          29792715000
 test target 1 - Starting Memory Read, at          29793825000
 test target 1 - Starting Memory Read, at          29794965000
 test target 1 - Starting Memory Read, at          29796075000
 test target 1 - Starting Memory Read, at          29797185000
 test target 1 - Starting Memory Read, at          29798325000
 test target 1 - Starting Memory Read, at          29799435000
 test target 1 - Starting Memory Read, at          29800545000
 test target 1 - Starting Memory Read, at          29801685000
 test target 1 - Starting Memory Read, at          29802795000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          29803845000
 test target 1 - Starting Memory Read, at          29803995000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          29805555000
 test target 1 - Starting Memory Read, at          29807535000
 test target 1 - Starting Memory Read, at          29808105000
 test target 1 - Starting Memory Read, at          29808675000
 test target 1 - Starting Memory Read, at          29809515000
 test target 1 - Starting Memory Read, at          29810205000
 test target 1 - Starting Memory Read, at          29811435000
 test target 1 - Starting Memory Read, at          29812515000
 test target 1 - Starting Memory Read, at          29813385000
 test target 1 - Starting Memory Read, at          29816535000
 test target 1 - Starting Memory Read, at          29819295000
 test target 1 - Starting Memory Read, at          29820105000
 test target 1 - Starting Memory Read, at          29820915000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          29822055000
 test master 1 - Starting Memory Write, at          29822385000
 test target 1 - Starting Memory Write, at          29822385000
 test target 1 - Starting Memory Write, at          29822535000
 test target 1 - Starting Memory Read, at          29822955000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          29825565000
 test master 1 - Starting Memory Write, at          29825925000
 test target 1 - Starting Memory Write, at          29825925000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          29831085000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          29832195000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          29858325000
 test target 1 - Starting Config Write, at          29859225000
 test target 1 - Starting Config Write, at          29860095000
 test target 2 - Starting Config Write, at          29860965000
 test target 2 - Starting Config Write, at          29861865000
 test target 2 - Starting Config Write, at          29862735000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          29864715000
 test target 1 - Starting Memory Read, at          29864925000
 test target 1 - Starting Memory Write, at          29865495000
 test target 1 - Starting Memory Read, at          29865705000
 test target 1 - Starting Memory Write, at          29866635000
 test target 1 - Starting Memory Read, at          29867895000
 test target 1 - Starting Memory Read, at          29868405000
 test target 1 - Starting Memory Read, at          29869005000
 test target 1 - Starting Memory Read, at          29869575000
 test target 1 - Starting Memory Read, at          29870445000
 test target 1 - Starting Memory Read, at          29871525000
 test target 1 - Starting Memory Read, at          29872395000
 test target 1 - Starting Memory Read, at          29873475000
 test target 1 - Starting Memory Read, at          29874345000
 test target 1 - Starting Memory Read, at          29876745000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          29883855000
 test target 1 - Starting Memory Read, at          29884065000
 test target 1 - Starting Memory Write, at          29884635000
 test target 1 - Starting Memory Read, at          29884845000
 test target 1 - Starting Memory Write, at          29885775000
 test target 1 - Starting Memory Read, at          29887035000
 test target 1 - Starting Memory Read, at          29887545000
 test target 1 - Starting Memory Read, at          29888145000
 test target 1 - Starting Memory Read, at          29888715000
 test target 1 - Starting Memory Read, at          29889585000
 test target 1 - Starting Memory Read, at          29890665000
 test target 1 - Starting Memory Read, at          29891535000
 test target 1 - Starting Memory Read, at          29892615000
 test target 1 - Starting Memory Read, at          29893485000
 test target 1 - Starting Memory Read, at          29895885000
 test target 1 - Starting Memory Write, at          29902995000
 test target 1 - Starting Memory Read, at          29903205000
 test target 1 - Starting Memory Write, at          29903775000
 test target 1 - Starting Memory Read, at          29903985000
 test target 1 - Starting Memory Write, at          29904915000
 test target 1 - Starting Memory Read, at          29906175000
 test target 1 - Starting Memory Read, at          29906685000
 test target 1 - Starting Memory Read, at          29907285000
 test target 1 - Starting Memory Read, at          29907855000
 test target 1 - Starting Memory Read, at          29908725000
 test target 1 - Starting Memory Read, at          29909805000
 test target 1 - Starting Memory Read, at          29910675000
 test target 1 - Starting Memory Read, at          29911755000
 test target 1 - Starting Memory Read, at          29912625000
 test target 1 - Starting Memory Read, at          29915025000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          29928675000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          29935335000
 test target 1 - Starting Memory Write, at          29936115000
 test target 1 - Starting Memory Read, at          29936565000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          29937885000
 test target 1 - Starting Config Write, at          29939925000
 test target 1 - Starting Memory Read, at          29940555000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          29942055000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          29944215000
 test target 1 - Starting Memory Write, at          29945385000
 test target 1 - Starting Memory Write, at          29945655000
 test target 1 - Starting Memory Read, at          29945865000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          29948235000
 test target 1 - Starting Memory Write, at          29951475000
 test target 1 - Starting Memory Write, at          29951835000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          29956095000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          29958075000
 test target 1 - Starting Memory Read, at          29959425000
 test target 1 - Starting Memory Read, at          29960445000
 test target 1 - Starting Memory Read, at          29962185000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          29968635000
 test target 2 - Starting Config Write, at          29969505000
 test target 1 - Starting Memory Write, at          29970135000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          29970255000
 test target 1 - Starting Memory Write, at          29971395000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          29971515000
 test target 1 - Starting Memory Write, at          29972655000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          29974155000
 test target 1 - Starting Memory Read, at          29976405000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          29976525000
 test target 1 - Starting Memory Read, at          29978775000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          29980485000
 test master 2 - Starting Memory Write, at          29980485000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          29980545000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29981415000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29981445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29981745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29981775000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29982735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29982765000
 test target 1 - Starting Memory Write, at          29984655000
 test master 2 - Starting Memory Write, at          29984655000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29986455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29986485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29988255000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29988285000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29990055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29990085000
 test target 1 - Starting Memory Write, at          29992245000
 test master 2 - Starting Memory Write, at          29992245000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          29992305000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29994015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29994045000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29994345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29994375000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29995335000
*** monitor - CBE Bus Changed when TRDY Desserted, at          29995365000
 test target 1 - Starting Memory Write, at          29996595000
 test master 2 - Starting Memory Write, at          29996595000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          29999685000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          30001395000
 test master 1 - Starting Memory Read, at          30001785000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          30001935000
 test target 1 - Starting Config Write, at          30004695000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          30007395000
 test target 1 - Starting Memory Write, at          30007545000
 test target 1 - Starting Memory Write, at          30007695000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          30008175000
 test target 1 - Starting Memory Write, at          30008355000
 test target 1 - Starting Memory Write, at          30008535000
 test target 1 - Starting Memory Write, at          30009015000
 test target 1 - Starting Memory Write, at          30009285000
 test target 1 - Starting Memory Write, at          30009795000
 test target 1 - Starting Memory Write, at          30010455000
 test target 1 - Starting Memory Write, at          30010635000
 test target 1 - Starting Memory Write, at          30011295000
 test target 1 - Starting Memory Write, at          30011595000
 test target 1 - Starting Memory Write, at          30012135000
 test target 1 - Starting Memory Write, at          30016485000
 test target 1 - Starting Memory Write, at          30016665000
 test target 1 - Starting Memory Write, at          30016845000
 test target 1 - Starting Memory Write, at          30017145000
 test target 1 - Starting Memory Write, at          30017445000
 test target 1 - Starting Memory Read, at          30024495000
 test target 1 - Starting Memory Read, at          30025635000
 test target 1 - Starting Memory Read, at          30026745000
 test target 1 - Starting Memory Read, at          30027885000
 test target 1 - Starting Memory Read, at          30028995000
 test target 1 - Starting Memory Read, at          30030105000
 test target 1 - Starting Memory Read, at          30031245000
 test target 1 - Starting Memory Read, at          30032355000
 test target 1 - Starting Memory Read, at          30033465000
 test target 1 - Starting Memory Read, at          30034605000
 test target 1 - Starting Memory Read, at          30035715000
 test target 1 - Starting Memory Read, at          30036825000
 test target 1 - Starting Memory Read, at          30037965000
 test target 1 - Starting Memory Read, at          30039075000
 test target 1 - Starting Memory Read, at          30040185000
 test target 1 - Starting Memory Read, at          30041325000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          30042345000
 test target 1 - Starting Memory Read, at          30042495000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          30044085000
 test target 1 - Starting Memory Read, at          30046095000
 test target 1 - Starting Memory Read, at          30046815000
 test target 1 - Starting Memory Read, at          30047385000
 test target 1 - Starting Memory Read, at          30048225000
 test target 1 - Starting Memory Read, at          30048915000
 test target 1 - Starting Memory Read, at          30050145000
 test target 1 - Starting Memory Read, at          30051225000
 test target 1 - Starting Memory Read, at          30052095000
 test target 1 - Starting Memory Read, at          30055245000
 test target 1 - Starting Memory Read, at          30058035000
 test target 1 - Starting Memory Read, at          30058845000
 test target 1 - Starting Memory Read, at          30059655000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          30060795000
 test master 1 - Starting Memory Write, at          30061155000
 test target 1 - Starting Memory Write, at          30061155000
 test target 1 - Starting Memory Write, at          30061305000
 test target 1 - Starting Memory Read, at          30061755000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          30064305000
 test master 1 - Starting Memory Write, at          30064665000
 test target 1 - Starting Memory Write, at          30064665000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          30069765000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          30070875000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          30097005000
 test target 1 - Starting Config Write, at          30097905000
 test target 1 - Starting Config Write, at          30098985000
 test target 2 - Starting Config Write, at          30099885000
 test target 2 - Starting Config Write, at          30100785000
 test target 2 - Starting Config Write, at          30101865000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          30103875000
 test target 1 - Starting Memory Read, at          30104115000
 test target 1 - Starting Memory Write, at          30104865000
 test target 1 - Starting Memory Read, at          30105105000
 test target 1 - Starting Memory Write, at          30106185000
 test target 1 - Starting Memory Read, at          30107475000
 test target 1 - Starting Memory Read, at          30108105000
 test target 1 - Starting Memory Read, at          30108705000
 test target 1 - Starting Memory Read, at          30109275000
 test target 1 - Starting Memory Read, at          30110145000
 test target 1 - Starting Memory Read, at          30111345000
 test target 1 - Starting Memory Read, at          30112215000
 test target 1 - Starting Memory Read, at          30113415000
 test target 1 - Starting Memory Read, at          30114285000
 test target 1 - Starting Memory Read, at          30116805000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          30123915000
 test target 1 - Starting Memory Read, at          30124155000
 test target 1 - Starting Memory Write, at          30124905000
 test target 1 - Starting Memory Read, at          30125145000
 test target 1 - Starting Memory Write, at          30126225000
 test target 1 - Starting Memory Read, at          30127515000
 test target 1 - Starting Memory Read, at          30128145000
 test target 1 - Starting Memory Read, at          30128745000
 test target 1 - Starting Memory Read, at          30129315000
 test target 1 - Starting Memory Read, at          30130185000
 test target 1 - Starting Memory Read, at          30131385000
 test target 1 - Starting Memory Read, at          30132255000
 test target 1 - Starting Memory Read, at          30133455000
 test target 1 - Starting Memory Read, at          30134325000
 test target 1 - Starting Memory Read, at          30136845000
 test target 1 - Starting Memory Write, at          30143955000
 test target 1 - Starting Memory Read, at          30144195000
 test target 1 - Starting Memory Write, at          30144945000
 test target 1 - Starting Memory Read, at          30145185000
 test target 1 - Starting Memory Write, at          30146265000
 test target 1 - Starting Memory Read, at          30147555000
 test target 1 - Starting Memory Read, at          30148185000
 test target 1 - Starting Memory Read, at          30148785000
 test target 1 - Starting Memory Read, at          30149355000
 test target 1 - Starting Memory Read, at          30150225000
 test target 1 - Starting Memory Read, at          30151425000
 test target 1 - Starting Memory Read, at          30152295000
 test target 1 - Starting Memory Read, at          30153495000
 test target 1 - Starting Memory Read, at          30154365000
 test target 1 - Starting Memory Read, at          30156885000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          30170535000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          30177195000
 test target 1 - Starting Memory Write, at          30177975000
 test target 1 - Starting Memory Read, at          30178455000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          30179865000
 test target 1 - Starting Config Write, at          30181905000
 test target 1 - Starting Memory Read, at          30182535000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          30184035000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          30186195000
 test target 1 - Starting Memory Write, at          30187365000
 test target 1 - Starting Memory Write, at          30187665000
 test target 1 - Starting Memory Read, at          30187905000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          30190455000
 test target 1 - Starting Memory Write, at          30193755000
 test target 1 - Starting Memory Write, at          30194145000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          30198435000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          30200655000
 test target 1 - Starting Memory Read, at          30202125000
 test target 1 - Starting Memory Read, at          30203265000
 test target 1 - Starting Memory Read, at          30205125000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          30211695000
 test target 2 - Starting Config Write, at          30212565000
 test target 1 - Starting Memory Write, at          30213195000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          30213345000
 test target 1 - Starting Memory Write, at          30214455000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          30214605000
 test target 1 - Starting Memory Write, at          30215715000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          30217215000
 test target 1 - Starting Memory Read, at          30219465000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          30219615000
 test target 1 - Starting Memory Read, at          30221835000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          30223545000
 test master 2 - Starting Memory Write, at          30223545000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          30223605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30224475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30224505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30224805000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30224835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30225795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30225825000
 test target 1 - Starting Memory Write, at          30227715000
 test master 2 - Starting Memory Write, at          30227715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30229515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30229545000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30231315000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30231345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30233115000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30233145000
 test target 1 - Starting Memory Write, at          30235305000
 test master 2 - Starting Memory Write, at          30235305000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          30235365000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30237075000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30237105000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30237405000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30237435000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30238395000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30238425000
 test target 1 - Starting Memory Write, at          30239655000
 test master 2 - Starting Memory Write, at          30239655000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          30242805000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          30244515000
 test master 1 - Starting Memory Read, at          30244905000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          30245055000
 test target 1 - Starting Config Write, at          30247815000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          30250515000
 test target 1 - Starting Memory Write, at          30250695000
 test target 1 - Starting Memory Write, at          30250875000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          30251415000
 test target 1 - Starting Memory Write, at          30251625000
 test target 1 - Starting Memory Write, at          30251835000
 test target 1 - Starting Memory Write, at          30252375000
 test target 1 - Starting Memory Write, at          30252675000
 test target 1 - Starting Memory Write, at          30253215000
 test target 1 - Starting Memory Write, at          30253935000
 test target 1 - Starting Memory Write, at          30254145000
 test target 1 - Starting Memory Write, at          30254835000
 test target 1 - Starting Memory Write, at          30255165000
 test target 1 - Starting Memory Write, at          30255735000
 test target 1 - Starting Memory Write, at          30260115000
 test target 1 - Starting Memory Write, at          30260325000
 test target 1 - Starting Memory Write, at          30260535000
 test target 1 - Starting Memory Write, at          30260865000
 test target 1 - Starting Memory Write, at          30261195000
 test target 1 - Starting Memory Read, at          30268275000
 test target 1 - Starting Memory Read, at          30269385000
 test target 1 - Starting Memory Read, at          30270525000
 test target 1 - Starting Memory Read, at          30271635000
 test target 1 - Starting Memory Read, at          30272745000
 test target 1 - Starting Memory Read, at          30273885000
 test target 1 - Starting Memory Read, at          30274995000
 test target 1 - Starting Memory Read, at          30276105000
 test target 1 - Starting Memory Read, at          30277245000
 test target 1 - Starting Memory Read, at          30278355000
 test target 1 - Starting Memory Read, at          30279465000
 test target 1 - Starting Memory Read, at          30280605000
 test target 1 - Starting Memory Read, at          30281715000
 test target 1 - Starting Memory Read, at          30282825000
 test target 1 - Starting Memory Read, at          30283965000
 test target 1 - Starting Memory Read, at          30285075000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          30286125000
 test target 1 - Starting Memory Read, at          30286305000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          30287835000
 test target 1 - Starting Memory Read, at          30289875000
 test target 1 - Starting Memory Read, at          30290595000
 test target 1 - Starting Memory Read, at          30291345000
 test target 1 - Starting Memory Read, at          30292185000
 test target 1 - Starting Memory Read, at          30293055000
 test target 1 - Starting Memory Read, at          30294405000
 test target 1 - Starting Memory Read, at          30295605000
 test target 1 - Starting Memory Read, at          30296475000
 test target 1 - Starting Memory Read, at          30299625000
 test target 1 - Starting Memory Read, at          30302535000
 test target 1 - Starting Memory Read, at          30303465000
 test target 1 - Starting Memory Read, at          30304395000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          30305655000
 test master 1 - Starting Memory Write, at          30306045000
 test target 1 - Starting Memory Write, at          30306045000
 test target 1 - Starting Memory Write, at          30306225000
 test target 1 - Starting Memory Read, at          30306705000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          30309345000
 test master 1 - Starting Memory Write, at          30309735000
 test target 1 - Starting Memory Write, at          30309735000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          30314865000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          30315975000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          30342105000
 test target 1 - Starting Config Write, at          30343215000
 test target 1 - Starting Config Write, at          30344325000
 test target 2 - Starting Config Write, at          30345405000
 test target 2 - Starting Config Write, at          30346515000
 test target 2 - Starting Config Write, at          30347625000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          30349815000
 test target 1 - Starting Memory Read, at          30350085000
 test target 1 - Starting Memory Write, at          30350805000
 test target 1 - Starting Memory Read, at          30351075000
 test target 1 - Starting Memory Write, at          30352125000
 test target 1 - Starting Memory Read, at          30353445000
 test target 1 - Starting Memory Read, at          30354075000
 test target 1 - Starting Memory Read, at          30354645000
 test target 1 - Starting Memory Read, at          30355245000
 test target 1 - Starting Memory Read, at          30356115000
 test target 1 - Starting Memory Read, at          30357315000
 test target 1 - Starting Memory Read, at          30358395000
 test target 1 - Starting Memory Read, at          30359595000
 test target 1 - Starting Memory Read, at          30360675000
 test target 1 - Starting Memory Read, at          30363225000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          30370515000
 test target 1 - Starting Memory Read, at          30370785000
 test target 1 - Starting Memory Write, at          30371505000
 test target 1 - Starting Memory Read, at          30371775000
 test target 1 - Starting Memory Write, at          30372825000
 test target 1 - Starting Memory Read, at          30374145000
 test target 1 - Starting Memory Read, at          30374775000
 test target 1 - Starting Memory Read, at          30375345000
 test target 1 - Starting Memory Read, at          30375945000
 test target 1 - Starting Memory Read, at          30376815000
 test target 1 - Starting Memory Read, at          30378015000
 test target 1 - Starting Memory Read, at          30379095000
 test target 1 - Starting Memory Read, at          30380295000
 test target 1 - Starting Memory Read, at          30381375000
 test target 1 - Starting Memory Read, at          30383925000
 test target 1 - Starting Memory Write, at          30391215000
 test target 1 - Starting Memory Read, at          30391485000
 test target 1 - Starting Memory Write, at          30392205000
 test target 1 - Starting Memory Read, at          30392475000
 test target 1 - Starting Memory Write, at          30393525000
 test target 1 - Starting Memory Read, at          30394845000
 test target 1 - Starting Memory Read, at          30395475000
 test target 1 - Starting Memory Read, at          30396045000
 test target 1 - Starting Memory Read, at          30396645000
 test target 1 - Starting Memory Read, at          30397515000
 test target 1 - Starting Memory Read, at          30398715000
 test target 1 - Starting Memory Read, at          30399795000
 test target 1 - Starting Memory Read, at          30400995000
 test target 1 - Starting Memory Read, at          30402075000
 test target 1 - Starting Memory Read, at          30404625000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          30418455000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          30425355000
 test target 1 - Starting Memory Write, at          30426345000
 test target 1 - Starting Memory Read, at          30426855000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          30428265000
 test target 1 - Starting Config Write, at          30430545000
 test target 1 - Starting Memory Read, at          30431355000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          30433095000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          30435495000
 test target 1 - Starting Memory Write, at          30436905000
 test target 1 - Starting Memory Write, at          30437235000
 test target 1 - Starting Memory Read, at          30437505000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          30439995000
 test target 1 - Starting Memory Write, at          30443295000
 test target 1 - Starting Memory Write, at          30443715000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          30448035000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          30450255000
 test target 1 - Starting Memory Read, at          30451725000
 test target 1 - Starting Memory Read, at          30452865000
 test target 1 - Starting Memory Read, at          30454725000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          30461295000
 test target 2 - Starting Config Write, at          30462405000
 test target 1 - Starting Memory Write, at          30463245000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          30463425000
 test target 1 - Starting Memory Write, at          30464535000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          30464715000
 test target 1 - Starting Memory Write, at          30465855000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          30467415000
 test target 1 - Starting Memory Read, at          30469905000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          30470085000
 test target 1 - Starting Memory Read, at          30472455000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          30474405000
 test master 2 - Starting Memory Write, at          30474405000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          30474465000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30475395000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30475425000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30475725000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30475755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30476715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30476745000
 test target 1 - Starting Memory Write, at          30478635000
 test master 2 - Starting Memory Write, at          30478635000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30480495000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30480525000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30482295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30482325000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30484095000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30484125000
 test target 1 - Starting Memory Write, at          30486285000
 test master 2 - Starting Memory Write, at          30486285000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          30486345000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30488115000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30488145000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30488445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30488475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30489435000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30489465000
 test target 1 - Starting Memory Write, at          30490695000
 test master 2 - Starting Memory Write, at          30490695000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          30493845000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          30495555000
 test master 1 - Starting Memory Read, at          30495945000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          30496095000
 test target 1 - Starting Config Write, at          30498855000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          30501555000
 test target 1 - Starting Memory Write, at          30501765000
 test target 1 - Starting Memory Write, at          30501975000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          30502515000
 test target 1 - Starting Memory Write, at          30502755000
 test target 1 - Starting Memory Write, at          30502995000
 test target 1 - Starting Memory Write, at          30503535000
 test target 1 - Starting Memory Write, at          30503865000
 test target 1 - Starting Memory Write, at          30504435000
 test target 1 - Starting Memory Write, at          30505155000
 test target 1 - Starting Memory Write, at          30505395000
 test target 1 - Starting Memory Write, at          30506115000
 test target 1 - Starting Memory Write, at          30506475000
 test target 1 - Starting Memory Write, at          30507075000
 test target 1 - Starting Memory Write, at          30511485000
 test target 1 - Starting Memory Write, at          30511725000
 test target 1 - Starting Memory Write, at          30511965000
 test target 1 - Starting Memory Write, at          30512325000
 test target 1 - Starting Memory Write, at          30512685000
 test target 1 - Starting Memory Read, at          30519795000
 test target 1 - Starting Memory Read, at          30520995000
 test target 1 - Starting Memory Read, at          30522105000
 test target 1 - Starting Memory Read, at          30523245000
 test target 1 - Starting Memory Read, at          30524355000
 test target 1 - Starting Memory Read, at          30525465000
 test target 1 - Starting Memory Read, at          30526605000
 test target 1 - Starting Memory Read, at          30527715000
 test target 1 - Starting Memory Read, at          30528825000
 test target 1 - Starting Memory Read, at          30529965000
 test target 1 - Starting Memory Read, at          30531075000
 test target 1 - Starting Memory Read, at          30532185000
 test target 1 - Starting Memory Read, at          30533325000
 test target 1 - Starting Memory Read, at          30534435000
 test target 1 - Starting Memory Read, at          30535545000
 test target 1 - Starting Memory Read, at          30536685000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          30537705000
 test target 1 - Starting Memory Read, at          30537915000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          30539655000
 test target 1 - Starting Memory Read, at          30541725000
 test target 1 - Starting Memory Read, at          30542385000
 test target 1 - Starting Memory Read, at          30543135000
 test target 1 - Starting Memory Read, at          30543975000
 test target 1 - Starting Memory Read, at          30544875000
 test target 1 - Starting Memory Read, at          30546225000
 test target 1 - Starting Memory Read, at          30547425000
 test target 1 - Starting Memory Read, at          30548505000
 test target 1 - Starting Memory Read, at          30551655000
 test target 1 - Starting Memory Read, at          30554535000
 test target 1 - Starting Memory Read, at          30555465000
 test target 1 - Starting Memory Read, at          30556395000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          30557655000
 test master 1 - Starting Memory Write, at          30557955000
 test target 1 - Starting Memory Write, at          30557955000
 test target 1 - Starting Memory Write, at          30558165000
 test target 1 - Starting Memory Read, at          30558795000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          30561465000
 test master 1 - Starting Memory Write, at          30561765000
 test target 1 - Starting Memory Write, at          30561765000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30567345000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          30567645000
 test master 2 - Starting Memory Read, at          30567825000
 test master 2 - Starting Memory Read, at          30568005000
 test master 2 - Starting Memory Read, at          30568245000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30570015000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          30570495000
 test master 2 - Starting Memory Read, at          30570675000
 test master 2 - Starting Memory Read, at          30571095000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30572595000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30573285000
 test master 2 - Starting Memory Read Line Multiple, at          30573465000
 test master 2 - Starting Memory Read Line Multiple, at          30573645000
 test master 2 - Starting Memory Read Line Multiple, at          30573825000
 test master 2 - Starting Memory Read Line Multiple, at          30574125000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30576255000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30588735000
 test master 2 - Starting Memory Read Line Multiple, at          30588915000
 test master 2 - Starting Memory Read Line Multiple, at          30589095000
 test master 2 - Starting Memory Read Line Multiple, at          30589275000
 test master 2 - Starting Memory Read Line Multiple, at          30589605000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30590505000
 test master 2 - Starting Memory Read Line Multiple, at          30590685000
 test master 2 - Starting Memory Read Line Multiple, at          30590865000
 test master 2 - Starting Memory Read Line Multiple, at          30591045000
 test master 2 - Starting Memory Read Line Multiple, at          30591345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30592245000
 test master 2 - Starting Memory Read Line Multiple, at          30592425000
 test master 2 - Starting Memory Read Line Multiple, at          30592605000
 test master 2 - Starting Memory Read Line Multiple, at          30592785000
 test master 2 - Starting Memory Read Line Multiple, at          30593085000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30593985000
 test master 2 - Starting Memory Read Line Multiple, at          30594165000
 test master 2 - Starting Memory Read Line Multiple, at          30594345000
 test master 2 - Starting Memory Read Line Multiple, at          30594525000
 test master 2 - Starting Memory Read Line Multiple, at          30594825000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30595725000
 test master 2 - Starting Memory Read Line Multiple, at          30595905000
 test master 2 - Starting Memory Read Line Multiple, at          30596085000
 test master 2 - Starting Memory Read Line Multiple, at          30596265000
 test master 2 - Starting Memory Read Line Multiple, at          30596565000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30597465000
 test master 2 - Starting Memory Read Line Multiple, at          30597645000
 test master 2 - Starting Memory Read Line Multiple, at          30597825000
 test master 2 - Starting Memory Read Line Multiple, at          30598005000
 test master 2 - Starting Memory Read Line Multiple, at          30598305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30599205000
 test master 2 - Starting Memory Read Line Multiple, at          30599385000
 test master 2 - Starting Memory Read Line Multiple, at          30599565000
 test master 2 - Starting Memory Read Line Multiple, at          30599745000
 test master 2 - Starting Memory Read Line Multiple, at          30600045000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30600945000
 test master 2 - Starting Memory Read Line Multiple, at          30601125000
 test master 2 - Starting Memory Read Line Multiple, at          30601305000
 test master 2 - Starting Memory Read Line Multiple, at          30601485000
 test master 2 - Starting Memory Read Line Multiple, at          30601785000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          30602685000
 test master 2 - Starting Memory Read Line, at          30602865000
 test master 2 - Starting Memory Read Line, at          30603045000
 test master 2 - Starting Memory Read Line, at          30603285000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          30603825000
 test master 2 - Starting Memory Read Line, at          30604005000
 test master 2 - Starting Memory Read Line, at          30604425000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30605685000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30607365000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30610485000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30612525000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          30618075000
 test master 2 - Starting Memory Write, at          30618375000
 test master 2 - Starting Memory Write, at          30618675000
 test master 2 - Starting Memory Write, at          30618975000
 test master 2 - Starting Memory Write, at          30619275000
 test master 1 - Starting Memory Read, at          30619695000
 test master 1 - Starting Memory Read, at          30620025000
 test master 1 - Starting Memory Read, at          30620565000
 test master 1 - Starting Memory Read, at          30620895000
 test master 1 - Starting Memory Read, at          30621435000
 test master 1 - Starting Memory Read, at          30621765000
 test master 2 - Starting Memory Write, at          30623115000
 test master 2 - Starting Memory Write, at          30623415000
 test master 2 - Starting Memory Write, at          30623715000
 test master 2 - Starting Memory Write, at          30624015000
 test master 2 - Starting Memory Write, at          30624315000
 test master 1 - Starting Memory Read, at          30624735000
 test master 1 - Starting Memory Read, at          30625065000
 test master 1 - Starting Memory Read, at          30625605000
 test master 1 - Starting Memory Read, at          30625935000
 test master 1 - Starting Memory Read, at          30626475000
 test master 1 - Starting Memory Read, at          30626805000
 test master 2 - Starting Memory Write, at          30628695000
 test master 2 - Starting Memory Write, at          30629865000
 test master 2 - Starting Memory Write, at          30631065000
 test master 2 - Starting Memory Write, at          30632265000
 test master 2 - Starting Memory Write, at          30634695000
 test master 2 - Starting Memory Write, at          30635865000
 test master 2 - Starting Memory Write, at          30637065000
 test master 2 - Starting Memory Write, at          30638265000
 test master 2 - Starting Memory Write, at          30640695000
 test master 2 - Starting Memory Write, at          30642885000
 test master 2 - Starting Memory Write, at          30645105000
 test master 2 - Starting Memory Write, at          30647325000
 test master 2 - Starting Memory Write, at          30650775000
 test master 2 - Starting Memory Write, at          30653235000
 test master 2 - Starting Memory Write, at          30655695000
 test master 2 - Starting Memory Write, at          30658155000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          30662745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30662775000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30665055000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          30665355000
 test master 2 - Starting Memory Read, at          30665535000
 test master 2 - Starting Memory Read, at          30665715000
 test master 2 - Starting Memory Read, at          30665955000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30667695000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          30668175000
 test master 2 - Starting Memory Read, at          30668355000
 test master 2 - Starting Memory Read, at          30668775000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30670275000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30670965000
 test master 2 - Starting Memory Read Line Multiple, at          30671145000
 test master 2 - Starting Memory Read Line Multiple, at          30671325000
 test master 2 - Starting Memory Read Line Multiple, at          30671505000
 test master 2 - Starting Memory Read Line Multiple, at          30671805000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30673935000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30686415000
 test master 2 - Starting Memory Read Line Multiple, at          30686595000
 test master 2 - Starting Memory Read Line Multiple, at          30686775000
 test master 2 - Starting Memory Read Line Multiple, at          30686955000
 test master 2 - Starting Memory Read Line Multiple, at          30687285000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30688185000
 test master 2 - Starting Memory Read Line Multiple, at          30688365000
 test master 2 - Starting Memory Read Line Multiple, at          30688545000
 test master 2 - Starting Memory Read Line Multiple, at          30688725000
 test master 2 - Starting Memory Read Line Multiple, at          30689025000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30689925000
 test master 2 - Starting Memory Read Line Multiple, at          30690105000
 test master 2 - Starting Memory Read Line Multiple, at          30690285000
 test master 2 - Starting Memory Read Line Multiple, at          30690465000
 test master 2 - Starting Memory Read Line Multiple, at          30690765000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30691665000
 test master 2 - Starting Memory Read Line Multiple, at          30691845000
 test master 2 - Starting Memory Read Line Multiple, at          30692025000
 test master 2 - Starting Memory Read Line Multiple, at          30692205000
 test master 2 - Starting Memory Read Line Multiple, at          30692505000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30693405000
 test master 2 - Starting Memory Read Line Multiple, at          30693585000
 test master 2 - Starting Memory Read Line Multiple, at          30693765000
 test master 2 - Starting Memory Read Line Multiple, at          30693945000
 test master 2 - Starting Memory Read Line Multiple, at          30694245000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30695145000
 test master 2 - Starting Memory Read Line Multiple, at          30695325000
 test master 2 - Starting Memory Read Line Multiple, at          30695505000
 test master 2 - Starting Memory Read Line Multiple, at          30695685000
 test master 2 - Starting Memory Read Line Multiple, at          30695985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30696885000
 test master 2 - Starting Memory Read Line Multiple, at          30697065000
 test master 2 - Starting Memory Read Line Multiple, at          30697245000
 test master 2 - Starting Memory Read Line Multiple, at          30697425000
 test master 2 - Starting Memory Read Line Multiple, at          30697725000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30698625000
 test master 2 - Starting Memory Read Line Multiple, at          30698805000
 test master 2 - Starting Memory Read Line Multiple, at          30698985000
 test master 2 - Starting Memory Read Line Multiple, at          30699165000
 test master 2 - Starting Memory Read Line Multiple, at          30699465000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          30700365000
 test master 2 - Starting Memory Read Line, at          30700545000
 test master 2 - Starting Memory Read Line, at          30700725000
 test master 2 - Starting Memory Read Line, at          30700965000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          30701505000
 test master 2 - Starting Memory Read Line, at          30701685000
 test master 2 - Starting Memory Read Line, at          30702105000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30703365000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30705045000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30708165000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30710205000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          30715755000
 test master 2 - Starting Memory Write, at          30716055000
 test master 2 - Starting Memory Write, at          30716355000
 test master 2 - Starting Memory Write, at          30716655000
 test master 2 - Starting Memory Write, at          30716955000
 test master 1 - Starting Memory Read, at          30717375000
 test master 1 - Starting Memory Read, at          30717705000
 test master 1 - Starting Memory Read, at          30718245000
 test master 1 - Starting Memory Read, at          30718575000
 test master 1 - Starting Memory Read, at          30719115000
 test master 1 - Starting Memory Read, at          30719445000
 test master 2 - Starting Memory Write, at          30720795000
 test master 2 - Starting Memory Write, at          30721095000
 test master 2 - Starting Memory Write, at          30721395000
 test master 2 - Starting Memory Write, at          30721695000
 test master 2 - Starting Memory Write, at          30721995000
 test master 1 - Starting Memory Read, at          30722415000
 test master 1 - Starting Memory Read, at          30722745000
 test master 1 - Starting Memory Read, at          30723285000
 test master 1 - Starting Memory Read, at          30723615000
 test master 1 - Starting Memory Read, at          30724155000
 test master 1 - Starting Memory Read, at          30724485000
 test master 2 - Starting Memory Write, at          30726375000
 test master 2 - Starting Memory Write, at          30727545000
 test master 2 - Starting Memory Write, at          30728745000
 test master 2 - Starting Memory Write, at          30729945000
 test master 2 - Starting Memory Write, at          30732375000
 test master 2 - Starting Memory Write, at          30733545000
 test master 2 - Starting Memory Write, at          30734745000
 test master 2 - Starting Memory Write, at          30735945000
 test master 2 - Starting Memory Write, at          30738375000
 test master 2 - Starting Memory Write, at          30740565000
 test master 2 - Starting Memory Write, at          30742785000
 test master 2 - Starting Memory Write, at          30745005000
 test master 2 - Starting Memory Write, at          30748455000
 test master 2 - Starting Memory Write, at          30750915000
 test master 2 - Starting Memory Write, at          30753375000
 test master 2 - Starting Memory Write, at          30755835000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          30760425000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30760455000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30762735000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          30763035000
 test master 2 - Starting Memory Read, at          30763215000
 test master 2 - Starting Memory Read, at          30763395000
 test master 2 - Starting Memory Read, at          30763635000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30765375000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          30765855000
 test master 2 - Starting Memory Read, at          30766035000
 test master 2 - Starting Memory Read, at          30766455000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30767955000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30768645000
 test master 2 - Starting Memory Read Line Multiple, at          30768825000
 test master 2 - Starting Memory Read Line Multiple, at          30769005000
 test master 2 - Starting Memory Read Line Multiple, at          30769185000
 test master 2 - Starting Memory Read Line Multiple, at          30769485000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30771615000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30784095000
 test master 2 - Starting Memory Read Line Multiple, at          30784275000
 test master 2 - Starting Memory Read Line Multiple, at          30784455000
 test master 2 - Starting Memory Read Line Multiple, at          30784635000
 test master 2 - Starting Memory Read Line Multiple, at          30784965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30785865000
 test master 2 - Starting Memory Read Line Multiple, at          30786045000
 test master 2 - Starting Memory Read Line Multiple, at          30786225000
 test master 2 - Starting Memory Read Line Multiple, at          30786405000
 test master 2 - Starting Memory Read Line Multiple, at          30786705000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30787605000
 test master 2 - Starting Memory Read Line Multiple, at          30787785000
 test master 2 - Starting Memory Read Line Multiple, at          30787965000
 test master 2 - Starting Memory Read Line Multiple, at          30788145000
 test master 2 - Starting Memory Read Line Multiple, at          30788445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30789345000
 test master 2 - Starting Memory Read Line Multiple, at          30789525000
 test master 2 - Starting Memory Read Line Multiple, at          30789705000
 test master 2 - Starting Memory Read Line Multiple, at          30789885000
 test master 2 - Starting Memory Read Line Multiple, at          30790185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30791085000
 test master 2 - Starting Memory Read Line Multiple, at          30791265000
 test master 2 - Starting Memory Read Line Multiple, at          30791445000
 test master 2 - Starting Memory Read Line Multiple, at          30791625000
 test master 2 - Starting Memory Read Line Multiple, at          30791925000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30792825000
 test master 2 - Starting Memory Read Line Multiple, at          30793005000
 test master 2 - Starting Memory Read Line Multiple, at          30793185000
 test master 2 - Starting Memory Read Line Multiple, at          30793365000
 test master 2 - Starting Memory Read Line Multiple, at          30793665000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30794565000
 test master 2 - Starting Memory Read Line Multiple, at          30794745000
 test master 2 - Starting Memory Read Line Multiple, at          30794925000
 test master 2 - Starting Memory Read Line Multiple, at          30795105000
 test master 2 - Starting Memory Read Line Multiple, at          30795405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30796305000
 test master 2 - Starting Memory Read Line Multiple, at          30796485000
 test master 2 - Starting Memory Read Line Multiple, at          30796665000
 test master 2 - Starting Memory Read Line Multiple, at          30796845000
 test master 2 - Starting Memory Read Line Multiple, at          30797145000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          30798045000
 test master 2 - Starting Memory Read Line, at          30798225000
 test master 2 - Starting Memory Read Line, at          30798405000
 test master 2 - Starting Memory Read Line, at          30798645000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          30799185000
 test master 2 - Starting Memory Read Line, at          30799365000
 test master 2 - Starting Memory Read Line, at          30799785000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30801045000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30802725000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30805845000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30807885000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          30813435000
 test master 2 - Starting Memory Write, at          30813735000
 test master 2 - Starting Memory Write, at          30814035000
 test master 2 - Starting Memory Write, at          30814335000
 test master 2 - Starting Memory Write, at          30814635000
 test master 1 - Starting Memory Read, at          30815055000
 test master 1 - Starting Memory Read, at          30815385000
 test master 1 - Starting Memory Read, at          30815925000
 test master 1 - Starting Memory Read, at          30816255000
 test master 1 - Starting Memory Read, at          30816795000
 test master 1 - Starting Memory Read, at          30817125000
 test master 2 - Starting Memory Write, at          30818475000
 test master 2 - Starting Memory Write, at          30818775000
 test master 2 - Starting Memory Write, at          30819075000
 test master 2 - Starting Memory Write, at          30819375000
 test master 2 - Starting Memory Write, at          30819675000
 test master 1 - Starting Memory Read, at          30820095000
 test master 1 - Starting Memory Read, at          30820425000
 test master 1 - Starting Memory Read, at          30820965000
 test master 1 - Starting Memory Read, at          30821295000
 test master 1 - Starting Memory Read, at          30821835000
 test master 1 - Starting Memory Read, at          30822165000
 test master 2 - Starting Memory Write, at          30824055000
 test master 2 - Starting Memory Write, at          30825225000
 test master 2 - Starting Memory Write, at          30826425000
 test master 2 - Starting Memory Write, at          30827625000
 test master 2 - Starting Memory Write, at          30830055000
 test master 2 - Starting Memory Write, at          30831225000
 test master 2 - Starting Memory Write, at          30832425000
 test master 2 - Starting Memory Write, at          30833625000
 test master 2 - Starting Memory Write, at          30836055000
 test master 2 - Starting Memory Write, at          30838245000
 test master 2 - Starting Memory Write, at          30840465000
 test master 2 - Starting Memory Write, at          30842685000
 test master 2 - Starting Memory Write, at          30846135000
 test master 2 - Starting Memory Write, at          30848595000
 test master 2 - Starting Memory Write, at          30851055000
 test master 2 - Starting Memory Write, at          30853515000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          30858105000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30858135000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30860415000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          30860715000
 test master 2 - Starting Memory Read, at          30860895000
 test master 2 - Starting Memory Read, at          30861075000
 test master 2 - Starting Memory Read, at          30861315000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30863055000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          30863535000
 test master 2 - Starting Memory Read, at          30863715000
 test master 2 - Starting Memory Read, at          30864135000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30865635000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30866325000
 test master 2 - Starting Memory Read Line Multiple, at          30866505000
 test master 2 - Starting Memory Read Line Multiple, at          30866685000
 test master 2 - Starting Memory Read Line Multiple, at          30866865000
 test master 2 - Starting Memory Read Line Multiple, at          30867165000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30869295000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30881775000
 test master 2 - Starting Memory Read Line Multiple, at          30881955000
 test master 2 - Starting Memory Read Line Multiple, at          30882135000
 test master 2 - Starting Memory Read Line Multiple, at          30882315000
 test master 2 - Starting Memory Read Line Multiple, at          30882645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30883545000
 test master 2 - Starting Memory Read Line Multiple, at          30883725000
 test master 2 - Starting Memory Read Line Multiple, at          30883905000
 test master 2 - Starting Memory Read Line Multiple, at          30884085000
 test master 2 - Starting Memory Read Line Multiple, at          30884385000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30885285000
 test master 2 - Starting Memory Read Line Multiple, at          30885465000
 test master 2 - Starting Memory Read Line Multiple, at          30885645000
 test master 2 - Starting Memory Read Line Multiple, at          30885825000
 test master 2 - Starting Memory Read Line Multiple, at          30886125000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30887025000
 test master 2 - Starting Memory Read Line Multiple, at          30887205000
 test master 2 - Starting Memory Read Line Multiple, at          30887385000
 test master 2 - Starting Memory Read Line Multiple, at          30887565000
 test master 2 - Starting Memory Read Line Multiple, at          30887865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30888765000
 test master 2 - Starting Memory Read Line Multiple, at          30888945000
 test master 2 - Starting Memory Read Line Multiple, at          30889125000
 test master 2 - Starting Memory Read Line Multiple, at          30889305000
 test master 2 - Starting Memory Read Line Multiple, at          30889605000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30890505000
 test master 2 - Starting Memory Read Line Multiple, at          30890685000
 test master 2 - Starting Memory Read Line Multiple, at          30890865000
 test master 2 - Starting Memory Read Line Multiple, at          30891045000
 test master 2 - Starting Memory Read Line Multiple, at          30891345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30892245000
 test master 2 - Starting Memory Read Line Multiple, at          30892425000
 test master 2 - Starting Memory Read Line Multiple, at          30892605000
 test master 2 - Starting Memory Read Line Multiple, at          30892785000
 test master 2 - Starting Memory Read Line Multiple, at          30893085000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          30893985000
 test master 2 - Starting Memory Read Line Multiple, at          30894165000
 test master 2 - Starting Memory Read Line Multiple, at          30894345000
 test master 2 - Starting Memory Read Line Multiple, at          30894525000
 test master 2 - Starting Memory Read Line Multiple, at          30894825000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          30895725000
 test master 2 - Starting Memory Read Line, at          30895905000
 test master 2 - Starting Memory Read Line, at          30896085000
 test master 2 - Starting Memory Read Line, at          30896325000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          30896865000
 test master 2 - Starting Memory Read Line, at          30897045000
 test master 2 - Starting Memory Read Line, at          30897465000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30898725000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30900405000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30903525000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          30905565000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          30911115000
 test master 2 - Starting Memory Write, at          30911415000
 test master 2 - Starting Memory Write, at          30911715000
 test master 2 - Starting Memory Write, at          30912015000
 test master 2 - Starting Memory Write, at          30912315000
 test master 1 - Starting Memory Read, at          30912735000
 test master 1 - Starting Memory Read, at          30913065000
 test master 1 - Starting Memory Read, at          30913605000
 test master 1 - Starting Memory Read, at          30913935000
 test master 1 - Starting Memory Read, at          30914475000
 test master 1 - Starting Memory Read, at          30914805000
 test master 2 - Starting Memory Write, at          30916155000
 test master 2 - Starting Memory Write, at          30916455000
 test master 2 - Starting Memory Write, at          30916755000
 test master 2 - Starting Memory Write, at          30917055000
 test master 2 - Starting Memory Write, at          30917355000
 test master 1 - Starting Memory Read, at          30917775000
 test master 1 - Starting Memory Read, at          30918105000
 test master 1 - Starting Memory Read, at          30918645000
 test master 1 - Starting Memory Read, at          30918975000
 test master 1 - Starting Memory Read, at          30919515000
 test master 1 - Starting Memory Read, at          30919845000
 test master 2 - Starting Memory Write, at          30921735000
 test master 2 - Starting Memory Write, at          30922905000
 test master 2 - Starting Memory Write, at          30924105000
 test master 2 - Starting Memory Write, at          30925305000
 test master 2 - Starting Memory Write, at          30927735000
 test master 2 - Starting Memory Write, at          30928905000
 test master 2 - Starting Memory Write, at          30930105000
 test master 2 - Starting Memory Write, at          30931305000
 test master 2 - Starting Memory Write, at          30933735000
 test master 2 - Starting Memory Write, at          30935925000
 test master 2 - Starting Memory Write, at          30938145000
 test master 2 - Starting Memory Write, at          30940365000
 test master 2 - Starting Memory Write, at          30943815000
 test master 2 - Starting Memory Write, at          30946275000
 test master 2 - Starting Memory Write, at          30948735000
 test master 2 - Starting Memory Write, at          30951195000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          30955785000
*** monitor - CBE Bus Changed when TRDY Desserted, at          30955815000
 test master 1 - Starting Memory Read, at          30958095000
 test master 1 - Starting Memory Read, at          30958455000
 test master 1 - Starting Memory Read, at          30959715000
 test master 1 - Starting Memory Read, at          30960075000
 test master 1 - Starting Memory Read Line, at          30961395000
 test master 1 - Starting Memory Read Line, at          30961755000
 test master 1 - Starting Memory Read Line, at          30963075000
 test master 1 - Starting Memory Read Line, at          30963525000
 test master 1 - Starting Memory Read Line, at          30964875000
 test master 1 - Starting Memory Read Line, at          30965475000
 test master 1 - Starting Memory Read Line, at          30967035000
 test master 1 - Starting Memory Read Line, at          30967635000
 test master 1 - Starting Memory Read Line Multiple, at          30969195000
 test master 1 - Starting Memory Read Line Multiple, at          30970035000
 test master 1 - Starting Memory Read Line Multiple, at          30971955000
 test master 1 - Starting Memory Read Line Multiple, at          30972795000
 test master 1 - Starting Memory Read Line, at          30974715000
 test master 1 - Starting Memory Read Line, at          30975315000
 test master 1 - Starting Memory Read, at          30978015000
 test master 1 - Starting Memory Read, at          30978375000
 test target 1 - Starting Config Write, at          30981885000
 test master 1 - Starting Memory Write, at          30982485000
 test master 1 - Starting Memory Write, at          30989925000
 test master 1 - Starting Memory Write, at          30994995000
 test master 1 - Starting Memory Write, at          31001955000
 test master 1 - Starting Memory Write, at          31006875000
 test master 1 - Starting Memory Read Line, at          31014315000
 test master 1 - Starting Memory Write, at          31019775000
 test master 1 - Starting Memory Read Line, at          31027215000
 test target 1 - Starting Config Write, at          31034505000
 test master 1 - Starting Memory Write, at          31035105000
 test master 1 - Starting Memory Write, at          31035225000
 test master 1 - Starting Memory Write, at          31035525000
 test master 1 - Starting Memory Read, at          31035645000
 test master 1 - Starting Memory Write, at          31036005000
 test master 1 - Starting Memory Read, at          31036125000
 test master 1 - Starting Memory Write, at          31037895000
 test master 1 - Starting Memory Write, at          31050375000
 test master 2 - Starting Memory Read Line, at          31062975000
 test master 2 - Starting Memory Read Line, at          31063545000
 test master 2 - Starting Memory Read Line, at          31064115000
 test master 2 - Starting Memory Read Line, at          31064685000
 test master 1 - Starting Memory Write, at          31065345000
 test master 1 - Starting Memory Write, at          31065645000
 test master 1 - Starting Memory Write, at          31065975000
 test master 2 - Starting Memory Read Line, at          31066425000
 test master 2 - Starting Memory Read Line, at          31066785000
 test master 2 - Starting Memory Read Line, at          31067085000
 test master 2 - Starting Memory Read Line, at          31067445000
 test master 2 - Starting Memory Read Line Multiple, at          31067775000
 test master 2 - Starting Memory Read Line Multiple, at          31068135000
 test master 1 - Starting Memory Write, at          31070205000
 test master 1 - Starting Memory Write, at          31070505000
 test master 2 - Starting Memory Read, at          31070955000
 test master 2 - Starting Memory Read, at          31071315000
 test master 2 - Starting Memory Read, at          31071615000
 test master 2 - Starting Memory Read, at          31071975000
 test master 1 - Starting Memory Write, at          31073775000
 test master 1 - Starting Memory Read, at          31073955000
 test master 1 - Starting Memory Write, at          31074135000
 test master 1 - Starting Memory Read, at          31074345000
 test master 1 - Starting Memory Write, at          31074555000
 test master 1 - Starting Memory Read, at          31074735000
 test master 1 - Starting Memory Read, at          31074945000
 test master 1 - Starting Memory Write, at          31075155000
 test master 1 - Starting Memory Write, at          31075335000
 test master 1 - Starting Memory Read, at          31075515000
 test master 1 - Starting Memory Write, at          31075695000
 test master 1 - Starting Memory Write, at          31075905000
 test master 1 - Starting Memory Write, at          31076115000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          31080915000
 test target 1 - Starting Memory Write, at          31081125000
 test master 1 - Starting Memory Write, at          31081305000
 test target 1 - Starting Memory Write, at          31081485000
 test target 1 - Starting Memory Write, at          31081695000
 test target 1 - Starting Memory Write, at          31081905000
 test master 1 - Starting Memory Write, at          31082205000
 test target 1 - Starting Memory Write, at          31082775000
 test target 1 - Starting Memory Write, at          31083435000
 test target 1 - Starting Memory Write, at          31083675000
 test master 1 - Starting Memory Write, at          31083885000
 test target 1 - Starting Memory Write, at          31084305000
 test target 1 - Starting Memory Write, at          31084545000
 test target 1 - Starting Memory Write, at          31084785000
 test target 1 - Starting Memory Write, at          31085025000
 test master 1 - Starting Memory Write, at          31085565000
 test target 1 - Starting Memory Write, at          31086525000
 test target 1 - Starting Memory Write, at          31087575000
 test target 1 - Starting Memory Write, at          31087785000
 test master 1 - Starting Memory Read, at          31087965000
 test target 1 - Starting Memory Write, at          31088145000
 test master 1 - Starting Memory Read, at          31088325000
 test target 1 - Starting Memory Write, at          31088505000
 test master 1 - Starting Memory Read, at          31088685000
 test target 1 - Starting Memory Write, at          31088865000
 test master 1 - Starting Memory Read, at          31089045000
 test target 1 - Starting Memory Write, at          31089225000
 test master 1 - Starting Memory Read, at          31089405000
 test target 1 - Starting Memory Write, at          31089585000
 test master 1 - Starting Memory Write, at          31089765000
 test target 1 - Starting Memory Write, at          31089945000
 test target 1 - Starting Memory Write, at          31090155000
 test target 1 - Starting Memory Write, at          31090365000
 test target 1 - Starting Memory Read, at          31090635000
 test master 1 - Starting Memory Write, at          31090935000
 test master 1 - Starting Memory Read, at          31091175000
 test target 1 - Starting Memory Write, at          31091685000
 test master 1 - Starting Memory Write, at          31092075000
 test target 1 - Starting Memory Read, at          31092525000
 test target 1 - Starting Memory Write, at          31093335000
 test master 1 - Starting Memory Read, at          31093635000
 test master 1 - Starting Memory Write, at          31094055000
 test master 1 - Starting Memory Write, at          31094415000
 test master 1 - Starting Memory Read, at          31094715000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          31097475000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          31098585000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          31125345000
 test target 1 - Starting Config Write, at          31126305000
 test target 1 - Starting Config Write, at          31127265000
 test target 2 - Starting Config Write, at          31128225000
 test target 2 - Starting Config Write, at          31129185000
 test target 2 - Starting Config Write, at          31130145000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          31132335000
 test target 1 - Starting Memory Read, at          31132515000
 test target 1 - Starting Memory Write, at          31133205000
 test target 1 - Starting Memory Read, at          31133415000
 test target 1 - Starting Memory Write, at          31134495000
 test target 1 - Starting Memory Read, at          31135605000
 test target 1 - Starting Memory Read, at          31136175000
 test target 1 - Starting Memory Read, at          31136715000
 test target 1 - Starting Memory Read, at          31137255000
 test target 1 - Starting Memory Read, at          31138125000
 test target 1 - Starting Memory Read, at          31139235000
 test target 1 - Starting Memory Read, at          31140195000
 test target 1 - Starting Memory Read, at          31141335000
 test target 1 - Starting Memory Read, at          31142265000
 test target 1 - Starting Memory Read, at          31144365000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          31151415000
 test target 1 - Starting Memory Read, at          31151595000
 test target 1 - Starting Memory Write, at          31152285000
 test target 1 - Starting Memory Read, at          31152495000
 test target 1 - Starting Memory Write, at          31153575000
 test target 1 - Starting Memory Read, at          31154685000
 test target 1 - Starting Memory Read, at          31155255000
 test target 1 - Starting Memory Read, at          31155795000
 test target 1 - Starting Memory Read, at          31156335000
 test target 1 - Starting Memory Read, at          31157205000
 test target 1 - Starting Memory Read, at          31158315000
 test target 1 - Starting Memory Read, at          31159275000
 test target 1 - Starting Memory Read, at          31160415000
 test target 1 - Starting Memory Read, at          31161345000
 test target 1 - Starting Memory Read, at          31163445000
 test target 1 - Starting Memory Write, at          31170495000
 test target 1 - Starting Memory Read, at          31170675000
 test target 1 - Starting Memory Write, at          31171365000
 test target 1 - Starting Memory Read, at          31171575000
 test target 1 - Starting Memory Write, at          31172655000
 test target 1 - Starting Memory Read, at          31173765000
 test target 1 - Starting Memory Read, at          31174335000
 test target 1 - Starting Memory Read, at          31174875000
 test target 1 - Starting Memory Read, at          31175415000
 test target 1 - Starting Memory Read, at          31176285000
 test target 1 - Starting Memory Read, at          31177395000
 test target 1 - Starting Memory Read, at          31178355000
 test target 1 - Starting Memory Read, at          31179495000
 test target 1 - Starting Memory Read, at          31180425000
 test target 1 - Starting Memory Read, at          31182525000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          31196655000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          31203795000
 test target 1 - Starting Memory Write, at          31204665000
 test target 1 - Starting Memory Read, at          31205025000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          31206405000
 test target 1 - Starting Config Write, at          31208445000
 test target 1 - Starting Memory Read, at          31209105000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          31210755000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          31213005000
 test target 1 - Starting Memory Write, at          31214295000
 test target 1 - Starting Memory Write, at          31214535000
 test target 1 - Starting Memory Read, at          31214715000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          31217415000
 test target 1 - Starting Memory Write, at          31220865000
 test target 1 - Starting Memory Write, at          31221195000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          31225635000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          31227795000
 test target 1 - Starting Memory Read, at          31229325000
 test target 1 - Starting Memory Read, at          31230375000
 test target 1 - Starting Memory Read, at          31232175000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          31239075000
 test target 2 - Starting Config Write, at          31240035000
 test target 1 - Starting Memory Write, at          31240725000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          31240815000
 test target 1 - Starting Memory Write, at          31241985000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          31242075000
 test target 1 - Starting Memory Write, at          31243245000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          31244775000
 test target 1 - Starting Memory Read, at          31247205000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          31247325000
 test target 1 - Starting Memory Read, at          31249755000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          31251645000
 test master 2 - Starting Memory Write, at          31251645000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          31251705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31252575000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31252605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31252905000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31252935000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31253925000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31253955000
 test target 1 - Starting Memory Write, at          31255965000
 test master 2 - Starting Memory Write, at          31255965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31257825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31257855000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31259745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31259775000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31261665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31261695000
 test target 1 - Starting Memory Write, at          31264005000
 test master 2 - Starting Memory Write, at          31264005000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          31264065000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31265835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31265865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31266165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31266195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31267185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31267215000
 test target 1 - Starting Memory Write, at          31268505000
 test master 2 - Starting Memory Write, at          31268505000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          31271835000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          31273665000
 test master 1 - Starting Memory Read, at          31273965000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          31274115000
 test target 1 - Starting Config Write, at          31277055000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          31279785000
 test target 1 - Starting Memory Write, at          31279905000
 test target 1 - Starting Memory Write, at          31280025000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          31280505000
 test target 1 - Starting Memory Write, at          31280655000
 test target 1 - Starting Memory Write, at          31280805000
 test target 1 - Starting Memory Write, at          31281285000
 test target 1 - Starting Memory Write, at          31281495000
 test target 1 - Starting Memory Write, at          31281975000
 test target 1 - Starting Memory Write, at          31282635000
 test target 1 - Starting Memory Write, at          31282785000
 test target 1 - Starting Memory Write, at          31283445000
 test target 1 - Starting Memory Write, at          31283685000
 test target 1 - Starting Memory Write, at          31284255000
 test target 1 - Starting Memory Write, at          31289775000
 test target 1 - Starting Memory Write, at          31289925000
 test target 1 - Starting Memory Write, at          31290075000
 test target 1 - Starting Memory Write, at          31290315000
 test target 1 - Starting Memory Write, at          31290555000
 test target 1 - Starting Memory Read, at          31295865000
 test target 1 - Starting Memory Read, at          31296915000
 test target 1 - Starting Memory Read, at          31297965000
 test target 1 - Starting Memory Read, at          31299045000
 test target 1 - Starting Memory Read, at          31300095000
 test target 1 - Starting Memory Read, at          31301145000
 test target 1 - Starting Memory Read, at          31302225000
 test target 1 - Starting Memory Read, at          31303275000
 test target 1 - Starting Memory Read, at          31304325000
 test target 1 - Starting Memory Read, at          31305405000
 test target 1 - Starting Memory Read, at          31306455000
 test target 1 - Starting Memory Read, at          31307505000
 test target 1 - Starting Memory Read, at          31308585000
 test target 1 - Starting Memory Read, at          31309635000
 test target 1 - Starting Memory Read, at          31310685000
 test target 1 - Starting Memory Read, at          31311765000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          31312695000
 test target 1 - Starting Memory Read, at          31312845000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          31314795000
 test target 1 - Starting Memory Read, at          31316325000
 test target 1 - Starting Memory Read, at          31316925000
 test target 1 - Starting Memory Read, at          31317525000
 test target 1 - Starting Memory Read, at          31318365000
 test target 1 - Starting Memory Read, at          31319115000
 test target 1 - Starting Memory Read, at          31320375000
 test target 1 - Starting Memory Read, at          31321515000
 test target 1 - Starting Memory Read, at          31322445000
 test target 1 - Starting Memory Read, at          31325325000
 test target 1 - Starting Memory Read, at          31327785000
 test target 1 - Starting Memory Read, at          31328685000
 test target 1 - Starting Memory Read, at          31329585000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          31330935000
 test master 1 - Starting Memory Write, at          31331205000
 test target 1 - Starting Memory Write, at          31331205000
 test target 1 - Starting Memory Write, at          31331355000
 test target 1 - Starting Memory Read, at          31331715000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          31334025000
 test master 1 - Starting Memory Write, at          31334325000
 test target 1 - Starting Memory Write, at          31334325000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          31339605000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          31340715000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          31367475000
 test target 1 - Starting Config Write, at          31368435000
 test target 1 - Starting Config Write, at          31369395000
 test target 2 - Starting Config Write, at          31370355000
 test target 2 - Starting Config Write, at          31371315000
 test target 2 - Starting Config Write, at          31372275000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          31374465000
 test target 1 - Starting Memory Read, at          31374675000
 test target 1 - Starting Memory Write, at          31375335000
 test target 1 - Starting Memory Read, at          31375545000
 test target 1 - Starting Memory Write, at          31376655000
 test target 1 - Starting Memory Read, at          31377795000
 test target 1 - Starting Memory Read, at          31378365000
 test target 1 - Starting Memory Read, at          31378905000
 test target 1 - Starting Memory Read, at          31379445000
 test target 1 - Starting Memory Read, at          31380315000
 test target 1 - Starting Memory Read, at          31381455000
 test target 1 - Starting Memory Read, at          31382385000
 test target 1 - Starting Memory Read, at          31383495000
 test target 1 - Starting Memory Read, at          31384455000
 test target 1 - Starting Memory Read, at          31386585000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          31393605000
 test target 1 - Starting Memory Read, at          31393815000
 test target 1 - Starting Memory Write, at          31394475000
 test target 1 - Starting Memory Read, at          31394685000
 test target 1 - Starting Memory Write, at          31395795000
 test target 1 - Starting Memory Read, at          31396935000
 test target 1 - Starting Memory Read, at          31397505000
 test target 1 - Starting Memory Read, at          31398045000
 test target 1 - Starting Memory Read, at          31398585000
 test target 1 - Starting Memory Read, at          31399455000
 test target 1 - Starting Memory Read, at          31400595000
 test target 1 - Starting Memory Read, at          31401525000
 test target 1 - Starting Memory Read, at          31402635000
 test target 1 - Starting Memory Read, at          31403595000
 test target 1 - Starting Memory Read, at          31405725000
 test target 1 - Starting Memory Write, at          31412745000
 test target 1 - Starting Memory Read, at          31412955000
 test target 1 - Starting Memory Write, at          31413615000
 test target 1 - Starting Memory Read, at          31413825000
 test target 1 - Starting Memory Write, at          31414935000
 test target 1 - Starting Memory Read, at          31416075000
 test target 1 - Starting Memory Read, at          31416645000
 test target 1 - Starting Memory Read, at          31417185000
 test target 1 - Starting Memory Read, at          31417725000
 test target 1 - Starting Memory Read, at          31418595000
 test target 1 - Starting Memory Read, at          31419735000
 test target 1 - Starting Memory Read, at          31420665000
 test target 1 - Starting Memory Read, at          31421775000
 test target 1 - Starting Memory Read, at          31422735000
 test target 1 - Starting Memory Read, at          31424865000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          31438965000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          31446135000
 test target 1 - Starting Memory Write, at          31447005000
 test target 1 - Starting Memory Read, at          31447395000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          31448745000
 test target 1 - Starting Config Write, at          31450785000
 test target 1 - Starting Memory Read, at          31451445000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          31453095000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          31455345000
 test target 1 - Starting Memory Write, at          31456635000
 test target 1 - Starting Memory Write, at          31456905000
 test target 1 - Starting Memory Read, at          31457115000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          31459755000
 test target 1 - Starting Memory Write, at          31463235000
 test target 1 - Starting Memory Write, at          31463595000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          31468095000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          31470255000
 test target 1 - Starting Memory Read, at          31471785000
 test target 1 - Starting Memory Read, at          31472835000
 test target 1 - Starting Memory Read, at          31474635000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          31481535000
 test target 2 - Starting Config Write, at          31482495000
 test target 1 - Starting Memory Write, at          31483185000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          31483305000
 test target 1 - Starting Memory Write, at          31484475000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          31484595000
 test target 1 - Starting Memory Write, at          31485765000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          31487325000
 test target 1 - Starting Memory Read, at          31489755000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          31489875000
 test target 1 - Starting Memory Read, at          31492305000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          31494195000
 test master 2 - Starting Memory Write, at          31494195000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          31494255000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31495155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31495185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31495485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31495515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31496505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31496535000
 test target 1 - Starting Memory Write, at          31498545000
 test master 2 - Starting Memory Write, at          31498545000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31500435000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31500465000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31502355000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31502385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31504275000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31504305000
 test target 1 - Starting Memory Write, at          31506615000
 test master 2 - Starting Memory Write, at          31506615000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          31506675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31508475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31508505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31508805000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31508835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31509825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31509855000
 test target 1 - Starting Memory Write, at          31511145000
 test master 2 - Starting Memory Write, at          31511145000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          31514505000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          31516335000
 test master 1 - Starting Memory Read, at          31516665000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          31516815000
 test target 1 - Starting Config Write, at          31519755000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          31522485000
 test target 1 - Starting Memory Write, at          31522635000
 test target 1 - Starting Memory Write, at          31522785000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          31523295000
 test target 1 - Starting Memory Write, at          31523475000
 test target 1 - Starting Memory Write, at          31523655000
 test target 1 - Starting Memory Write, at          31524165000
 test target 1 - Starting Memory Write, at          31524405000
 test target 1 - Starting Memory Write, at          31524915000
 test target 1 - Starting Memory Write, at          31525605000
 test target 1 - Starting Memory Write, at          31525785000
 test target 1 - Starting Memory Write, at          31526475000
 test target 1 - Starting Memory Write, at          31526745000
 test target 1 - Starting Memory Write, at          31527345000
 test target 1 - Starting Memory Write, at          31532895000
 test target 1 - Starting Memory Write, at          31533075000
 test target 1 - Starting Memory Write, at          31533255000
 test target 1 - Starting Memory Write, at          31533525000
 test target 1 - Starting Memory Write, at          31533795000
 test target 1 - Starting Memory Read, at          31539135000
 test target 1 - Starting Memory Read, at          31540185000
 test target 1 - Starting Memory Read, at          31541235000
 test target 1 - Starting Memory Read, at          31542285000
 test target 1 - Starting Memory Read, at          31543365000
 test target 1 - Starting Memory Read, at          31544415000
 test target 1 - Starting Memory Read, at          31545465000
 test target 1 - Starting Memory Read, at          31546545000
 test target 1 - Starting Memory Read, at          31547595000
 test target 1 - Starting Memory Read, at          31548645000
 test target 1 - Starting Memory Read, at          31549725000
 test target 1 - Starting Memory Read, at          31550775000
 test target 1 - Starting Memory Read, at          31551825000
 test target 1 - Starting Memory Read, at          31552905000
 test target 1 - Starting Memory Read, at          31553955000
 test target 1 - Starting Memory Read, at          31555005000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          31555965000
 test target 1 - Starting Memory Read, at          31556115000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          31558065000
 test target 1 - Starting Memory Read, at          31559625000
 test target 1 - Starting Memory Read, at          31560405000
 test target 1 - Starting Memory Read, at          31561005000
 test target 1 - Starting Memory Read, at          31561845000
 test target 1 - Starting Memory Read, at          31562595000
 test target 1 - Starting Memory Read, at          31563855000
 test target 1 - Starting Memory Read, at          31564995000
 test target 1 - Starting Memory Read, at          31565925000
 test target 1 - Starting Memory Read, at          31568805000
 test target 1 - Starting Memory Read, at          31571265000
 test target 1 - Starting Memory Read, at          31572165000
 test target 1 - Starting Memory Read, at          31573065000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          31574415000
 test master 1 - Starting Memory Write, at          31574715000
 test target 1 - Starting Memory Write, at          31574715000
 test target 1 - Starting Memory Write, at          31574865000
 test target 1 - Starting Memory Read, at          31575255000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          31577535000
 test master 1 - Starting Memory Write, at          31577835000
 test target 1 - Starting Memory Write, at          31577835000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          31583115000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          31584225000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          31610985000
 test target 1 - Starting Config Write, at          31611945000
 test target 1 - Starting Config Write, at          31612905000
 test target 2 - Starting Config Write, at          31613865000
 test target 2 - Starting Config Write, at          31614825000
 test target 2 - Starting Config Write, at          31615785000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          31617975000
 test target 1 - Starting Memory Read, at          31618215000
 test target 1 - Starting Memory Write, at          31618845000
 test target 1 - Starting Memory Read, at          31619085000
 test target 1 - Starting Memory Write, at          31620135000
 test target 1 - Starting Memory Read, at          31621305000
 test target 1 - Starting Memory Read, at          31621875000
 test target 1 - Starting Memory Read, at          31622415000
 test target 1 - Starting Memory Read, at          31622955000
 test target 1 - Starting Memory Read, at          31623825000
 test target 1 - Starting Memory Read, at          31624935000
 test target 1 - Starting Memory Read, at          31625895000
 test target 1 - Starting Memory Read, at          31627035000
 test target 1 - Starting Memory Read, at          31627965000
 test target 1 - Starting Memory Read, at          31630065000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          31637115000
 test target 1 - Starting Memory Read, at          31637355000
 test target 1 - Starting Memory Write, at          31637985000
 test target 1 - Starting Memory Read, at          31638225000
 test target 1 - Starting Memory Write, at          31639275000
 test target 1 - Starting Memory Read, at          31640445000
 test target 1 - Starting Memory Read, at          31641015000
 test target 1 - Starting Memory Read, at          31641555000
 test target 1 - Starting Memory Read, at          31642095000
 test target 1 - Starting Memory Read, at          31642965000
 test target 1 - Starting Memory Read, at          31644075000
 test target 1 - Starting Memory Read, at          31645035000
 test target 1 - Starting Memory Read, at          31646175000
 test target 1 - Starting Memory Read, at          31647105000
 test target 1 - Starting Memory Read, at          31649205000
 test target 1 - Starting Memory Write, at          31656255000
 test target 1 - Starting Memory Read, at          31656495000
 test target 1 - Starting Memory Write, at          31657125000
 test target 1 - Starting Memory Read, at          31657365000
 test target 1 - Starting Memory Write, at          31658415000
 test target 1 - Starting Memory Read, at          31659585000
 test target 1 - Starting Memory Read, at          31660155000
 test target 1 - Starting Memory Read, at          31660695000
 test target 1 - Starting Memory Read, at          31661235000
 test target 1 - Starting Memory Read, at          31662105000
 test target 1 - Starting Memory Read, at          31663215000
 test target 1 - Starting Memory Read, at          31664175000
 test target 1 - Starting Memory Read, at          31665315000
 test target 1 - Starting Memory Read, at          31666245000
 test target 1 - Starting Memory Read, at          31668345000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          31682475000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          31689615000
 test target 1 - Starting Memory Write, at          31690485000
 test target 1 - Starting Memory Read, at          31690905000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          31692225000
 test target 1 - Starting Config Write, at          31694265000
 test target 1 - Starting Memory Read, at          31694925000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          31696575000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          31698825000
 test target 1 - Starting Memory Write, at          31700115000
 test target 1 - Starting Memory Write, at          31700415000
 test target 1 - Starting Memory Read, at          31700655000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          31703235000
 test target 1 - Starting Memory Write, at          31706745000
 test target 1 - Starting Memory Write, at          31707105000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          31711635000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          31713795000
 test target 1 - Starting Memory Read, at          31715325000
 test target 1 - Starting Memory Read, at          31716375000
 test target 1 - Starting Memory Read, at          31718175000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          31725075000
 test target 2 - Starting Config Write, at          31726035000
 test target 1 - Starting Memory Write, at          31726725000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          31726875000
 test target 1 - Starting Memory Write, at          31728045000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          31728195000
 test target 1 - Starting Memory Write, at          31729365000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          31730955000
 test target 1 - Starting Memory Read, at          31733385000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          31733535000
 test target 1 - Starting Memory Read, at          31735935000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          31737825000
 test master 2 - Starting Memory Write, at          31737825000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          31737885000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31738815000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31738845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31739145000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31739175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31740165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31740195000
 test target 1 - Starting Memory Write, at          31742205000
 test master 2 - Starting Memory Write, at          31742205000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31744125000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31744155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31746045000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31746075000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31747965000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31747995000
 test target 1 - Starting Memory Write, at          31750305000
 test master 2 - Starting Memory Write, at          31750305000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          31750365000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31752195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31752225000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31752525000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31752555000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31753545000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31753575000
 test target 1 - Starting Memory Write, at          31754865000
 test master 2 - Starting Memory Write, at          31754865000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          31758255000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          31760085000
 test master 1 - Starting Memory Read, at          31760385000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          31760535000
 test target 1 - Starting Config Write, at          31763475000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          31766445000
 test target 1 - Starting Memory Write, at          31766625000
 test target 1 - Starting Memory Write, at          31766805000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          31767345000
 test target 1 - Starting Memory Write, at          31767555000
 test target 1 - Starting Memory Write, at          31767765000
 test target 1 - Starting Memory Write, at          31768305000
 test target 1 - Starting Memory Write, at          31768575000
 test target 1 - Starting Memory Write, at          31769115000
 test target 1 - Starting Memory Write, at          31769835000
 test target 1 - Starting Memory Write, at          31770045000
 test target 1 - Starting Memory Write, at          31770765000
 test target 1 - Starting Memory Write, at          31771065000
 test target 1 - Starting Memory Write, at          31771695000
 test target 1 - Starting Memory Write, at          31777275000
 test target 1 - Starting Memory Write, at          31777485000
 test target 1 - Starting Memory Write, at          31777695000
 test target 1 - Starting Memory Write, at          31777995000
 test target 1 - Starting Memory Write, at          31778295000
 test target 1 - Starting Memory Read, at          31783665000
 test target 1 - Starting Memory Read, at          31784835000
 test target 1 - Starting Memory Read, at          31785885000
 test target 1 - Starting Memory Read, at          31786965000
 test target 1 - Starting Memory Read, at          31788015000
 test target 1 - Starting Memory Read, at          31789065000
 test target 1 - Starting Memory Read, at          31790145000
 test target 1 - Starting Memory Read, at          31791195000
 test target 1 - Starting Memory Read, at          31792245000
 test target 1 - Starting Memory Read, at          31793325000
 test target 1 - Starting Memory Read, at          31794375000
 test target 1 - Starting Memory Read, at          31795425000
 test target 1 - Starting Memory Read, at          31796505000
 test target 1 - Starting Memory Read, at          31797555000
 test target 1 - Starting Memory Read, at          31798605000
 test target 1 - Starting Memory Read, at          31799685000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          31800615000
 test target 1 - Starting Memory Read, at          31800795000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          31802715000
 test target 1 - Starting Memory Read, at          31804305000
 test target 1 - Starting Memory Read, at          31805055000
 test target 1 - Starting Memory Read, at          31805835000
 test target 1 - Starting Memory Read, at          31806705000
 test target 1 - Starting Memory Read, at          31807455000
 test target 1 - Starting Memory Read, at          31808685000
 test target 1 - Starting Memory Read, at          31809795000
 test target 1 - Starting Memory Read, at          31810755000
 test target 1 - Starting Memory Read, at          31813845000
 test target 1 - Starting Memory Read, at          31816305000
 test target 1 - Starting Memory Read, at          31817205000
 test target 1 - Starting Memory Read, at          31818105000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          31819455000
 test master 1 - Starting Memory Write, at          31819785000
 test target 1 - Starting Memory Write, at          31819785000
 test target 1 - Starting Memory Write, at          31819965000
 test target 1 - Starting Memory Read, at          31820385000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          31822755000
 test master 1 - Starting Memory Write, at          31823085000
 test target 1 - Starting Memory Write, at          31823085000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          31828455000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          31829565000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          31856325000
 test target 1 - Starting Config Write, at          31857285000
 test target 1 - Starting Config Write, at          31858245000
 test target 2 - Starting Config Write, at          31859205000
 test target 2 - Starting Config Write, at          31860165000
 test target 2 - Starting Config Write, at          31861125000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          31863315000
 test target 1 - Starting Memory Read, at          31863585000
 test target 1 - Starting Memory Write, at          31864395000
 test target 1 - Starting Memory Read, at          31864665000
 test target 1 - Starting Memory Write, at          31865925000
 test target 1 - Starting Memory Read, at          31867125000
 test target 1 - Starting Memory Read, at          31867695000
 test target 1 - Starting Memory Read, at          31868385000
 test target 1 - Starting Memory Read, at          31869045000
 test target 1 - Starting Memory Read, at          31870065000
 test target 1 - Starting Memory Read, at          31871175000
 test target 1 - Starting Memory Read, at          31872135000
 test target 1 - Starting Memory Read, at          31873275000
 test target 1 - Starting Memory Read, at          31874205000
 test target 1 - Starting Memory Read, at          31876305000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          31883355000
 test target 1 - Starting Memory Read, at          31883625000
 test target 1 - Starting Memory Write, at          31884435000
 test target 1 - Starting Memory Read, at          31884705000
 test target 1 - Starting Memory Write, at          31885965000
 test target 1 - Starting Memory Read, at          31887165000
 test target 1 - Starting Memory Read, at          31887735000
 test target 1 - Starting Memory Read, at          31888425000
 test target 1 - Starting Memory Read, at          31889085000
 test target 1 - Starting Memory Read, at          31890105000
 test target 1 - Starting Memory Read, at          31891215000
 test target 1 - Starting Memory Read, at          31892175000
 test target 1 - Starting Memory Read, at          31893315000
 test target 1 - Starting Memory Read, at          31894245000
 test target 1 - Starting Memory Read, at          31896345000
 test target 1 - Starting Memory Write, at          31903395000
 test target 1 - Starting Memory Read, at          31903665000
 test target 1 - Starting Memory Write, at          31904475000
 test target 1 - Starting Memory Read, at          31904745000
 test target 1 - Starting Memory Write, at          31906005000
 test target 1 - Starting Memory Read, at          31907205000
 test target 1 - Starting Memory Read, at          31907775000
 test target 1 - Starting Memory Read, at          31908465000
 test target 1 - Starting Memory Read, at          31909125000
 test target 1 - Starting Memory Read, at          31910145000
 test target 1 - Starting Memory Read, at          31911255000
 test target 1 - Starting Memory Read, at          31912215000
 test target 1 - Starting Memory Read, at          31913355000
 test target 1 - Starting Memory Read, at          31914285000
 test target 1 - Starting Memory Read, at          31916385000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          31930515000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          31937655000
 test target 1 - Starting Memory Write, at          31938525000
 test target 1 - Starting Memory Read, at          31938975000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          31940415000
 test target 1 - Starting Config Write, at          31942425000
 test target 1 - Starting Memory Read, at          31943085000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          31944735000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          31946985000
 test target 1 - Starting Memory Write, at          31948275000
 test target 1 - Starting Memory Write, at          31948605000
 test target 1 - Starting Memory Read, at          31948875000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          31951635000
 test target 1 - Starting Memory Write, at          31955175000
 test target 1 - Starting Memory Write, at          31955565000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          31960095000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          31962255000
 test target 1 - Starting Memory Read, at          31963785000
 test target 1 - Starting Memory Read, at          31964835000
 test target 1 - Starting Memory Read, at          31966635000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          31973535000
 test target 2 - Starting Config Write, at          31974495000
 test target 1 - Starting Memory Write, at          31975185000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          31975365000
 test target 1 - Starting Memory Write, at          31976535000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          31976715000
 test target 1 - Starting Memory Write, at          31977885000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          31979505000
 test target 1 - Starting Memory Read, at          31981935000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          31982115000
 test target 1 - Starting Memory Read, at          31984485000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          31986375000
 test master 2 - Starting Memory Write, at          31986375000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          31986435000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31987395000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31987425000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31987725000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31987755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31988745000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31988775000
 test target 1 - Starting Memory Write, at          31990785000
 test master 2 - Starting Memory Write, at          31990785000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31992735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31992765000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31994655000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31994685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31996575000
*** monitor - CBE Bus Changed when TRDY Desserted, at          31996605000
 test target 1 - Starting Memory Write, at          31998915000
 test master 2 - Starting Memory Write, at          31998915000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          31998975000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32000835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32000865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32001165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32001195000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32002185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32002215000
 test target 1 - Starting Memory Write, at          32003505000
 test master 2 - Starting Memory Write, at          32003505000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          32006925000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          32008755000
 test master 1 - Starting Memory Read, at          32009085000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          32009235000
 test target 1 - Starting Config Write, at          32012175000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          32015145000
 test target 1 - Starting Memory Write, at          32015355000
 test target 1 - Starting Memory Write, at          32015565000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          32016135000
 test target 1 - Starting Memory Write, at          32016375000
 test target 1 - Starting Memory Write, at          32016615000
 test target 1 - Starting Memory Write, at          32017185000
 test target 1 - Starting Memory Write, at          32017485000
 test target 1 - Starting Memory Write, at          32018055000
 test target 1 - Starting Memory Write, at          32018805000
 test target 1 - Starting Memory Write, at          32019045000
 test target 1 - Starting Memory Write, at          32019795000
 test target 1 - Starting Memory Write, at          32020125000
 test target 1 - Starting Memory Write, at          32020785000
 test target 1 - Starting Memory Write, at          32026395000
 test target 1 - Starting Memory Write, at          32026635000
 test target 1 - Starting Memory Write, at          32026875000
 test target 1 - Starting Memory Write, at          32027205000
 test target 1 - Starting Memory Write, at          32027535000
 test target 1 - Starting Memory Read, at          32032935000
 test target 1 - Starting Memory Read, at          32034105000
 test target 1 - Starting Memory Read, at          32035305000
 test target 1 - Starting Memory Read, at          32036505000
 test target 1 - Starting Memory Read, at          32037705000
 test target 1 - Starting Memory Read, at          32038905000
 test target 1 - Starting Memory Read, at          32040105000
 test target 1 - Starting Memory Read, at          32041305000
 test target 1 - Starting Memory Read, at          32042505000
 test target 1 - Starting Memory Read, at          32043705000
 test target 1 - Starting Memory Read, at          32044905000
 test target 1 - Starting Memory Read, at          32046105000
 test target 1 - Starting Memory Read, at          32047305000
 test target 1 - Starting Memory Read, at          32048505000
 test target 1 - Starting Memory Read, at          32049705000
 test target 1 - Starting Memory Read, at          32050905000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          32051985000
 test target 1 - Starting Memory Read, at          32052195000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          32054085000
 test target 1 - Starting Memory Read, at          32055705000
 test target 1 - Starting Memory Read, at          32056425000
 test target 1 - Starting Memory Read, at          32057205000
 test target 1 - Starting Memory Read, at          32058045000
 test target 1 - Starting Memory Read, at          32058795000
 test target 1 - Starting Memory Read, at          32060055000
 test target 1 - Starting Memory Read, at          32061195000
 test target 1 - Starting Memory Read, at          32062125000
 test target 1 - Starting Memory Read, at          32065185000
 test target 1 - Starting Memory Read, at          32067645000
 test target 1 - Starting Memory Read, at          32068545000
 test target 1 - Starting Memory Read, at          32069445000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          32070795000
 test master 1 - Starting Memory Write, at          32071065000
 test target 1 - Starting Memory Write, at          32071065000
 test target 1 - Starting Memory Write, at          32071275000
 test target 1 - Starting Memory Read, at          32071815000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          32074185000
 test master 1 - Starting Memory Write, at          32074455000
 test target 1 - Starting Memory Write, at          32074455000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32080335000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          32080575000
 test master 2 - Starting Memory Read, at          32080755000
 test master 2 - Starting Memory Read, at          32080935000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32082705000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          32083035000
 test master 2 - Starting Memory Read, at          32083215000
 test master 2 - Starting Memory Read, at          32083395000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32084985000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32085435000
 test master 2 - Starting Memory Read Line Multiple, at          32085615000
 test master 2 - Starting Memory Read Line Multiple, at          32085855000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32087895000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32094855000
 test master 2 - Starting Memory Read Line Multiple, at          32095035000
 test master 2 - Starting Memory Read Line Multiple, at          32095305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32096025000
 test master 2 - Starting Memory Read Line Multiple, at          32096205000
 test master 2 - Starting Memory Read Line Multiple, at          32096445000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32097165000
 test master 2 - Starting Memory Read Line Multiple, at          32097345000
 test master 2 - Starting Memory Read Line Multiple, at          32097585000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32098305000
 test master 2 - Starting Memory Read Line Multiple, at          32098485000
 test master 2 - Starting Memory Read Line Multiple, at          32098725000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32099445000
 test master 2 - Starting Memory Read Line Multiple, at          32099625000
 test master 2 - Starting Memory Read Line Multiple, at          32099865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32100585000
 test master 2 - Starting Memory Read Line Multiple, at          32100765000
 test master 2 - Starting Memory Read Line Multiple, at          32101005000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32101725000
 test master 2 - Starting Memory Read Line Multiple, at          32101905000
 test master 2 - Starting Memory Read Line Multiple, at          32102145000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32102865000
 test master 2 - Starting Memory Read Line Multiple, at          32103045000
 test master 2 - Starting Memory Read Line Multiple, at          32103285000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          32104005000
 test master 2 - Starting Memory Read Line, at          32104185000
 test master 2 - Starting Memory Read Line, at          32104365000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          32104815000
 test master 2 - Starting Memory Read Line, at          32104995000
 test master 2 - Starting Memory Read Line, at          32105175000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32106465000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32108175000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32111415000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32113335000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          32118555000
 test master 2 - Starting Memory Write, at          32118795000
 test master 2 - Starting Memory Write, at          32119035000
 test master 2 - Starting Memory Write, at          32119275000
 test master 2 - Starting Memory Write, at          32119515000
 test master 1 - Starting Memory Read, at          32119875000
 test master 1 - Starting Memory Read, at          32120145000
 test master 1 - Starting Memory Read, at          32120685000
 test master 1 - Starting Memory Read, at          32120955000
 test master 1 - Starting Memory Read, at          32121495000
 test master 1 - Starting Memory Read, at          32121765000
 test master 2 - Starting Memory Write, at          32123145000
 test master 2 - Starting Memory Write, at          32123385000
 test master 2 - Starting Memory Write, at          32123625000
 test master 2 - Starting Memory Write, at          32123865000
 test master 2 - Starting Memory Write, at          32124105000
 test master 1 - Starting Memory Read, at          32124465000
 test master 1 - Starting Memory Read, at          32124735000
 test master 1 - Starting Memory Read, at          32125275000
 test master 1 - Starting Memory Read, at          32125545000
 test master 1 - Starting Memory Read, at          32126085000
 test master 1 - Starting Memory Read, at          32126355000
 test master 2 - Starting Memory Write, at          32128335000
 test master 2 - Starting Memory Write, at          32129505000
 test master 2 - Starting Memory Write, at          32130705000
 test master 2 - Starting Memory Write, at          32131905000
 test master 2 - Starting Memory Write, at          32134425000
 test master 2 - Starting Memory Write, at          32135625000
 test master 2 - Starting Memory Write, at          32136825000
 test master 2 - Starting Memory Write, at          32138025000
 test master 2 - Starting Memory Write, at          32140545000
 test master 2 - Starting Memory Write, at          32142855000
 test master 2 - Starting Memory Write, at          32145135000
 test master 2 - Starting Memory Write, at          32147415000
 test master 2 - Starting Memory Write, at          32151015000
 test master 2 - Starting Memory Write, at          32153595000
 test master 2 - Starting Memory Write, at          32156175000
 test master 2 - Starting Memory Write, at          32158755000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          32163465000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32163495000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32165985000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          32166225000
 test master 2 - Starting Memory Read, at          32166405000
 test master 2 - Starting Memory Read, at          32166585000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32168355000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          32168715000
 test master 2 - Starting Memory Read, at          32168895000
 test master 2 - Starting Memory Read, at          32169075000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32170665000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32171115000
 test master 2 - Starting Memory Read Line Multiple, at          32171295000
 test master 2 - Starting Memory Read Line Multiple, at          32171535000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32173575000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32180535000
 test master 2 - Starting Memory Read Line Multiple, at          32180715000
 test master 2 - Starting Memory Read Line Multiple, at          32180985000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32181705000
 test master 2 - Starting Memory Read Line Multiple, at          32181885000
 test master 2 - Starting Memory Read Line Multiple, at          32182125000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32182845000
 test master 2 - Starting Memory Read Line Multiple, at          32183025000
 test master 2 - Starting Memory Read Line Multiple, at          32183265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32183985000
 test master 2 - Starting Memory Read Line Multiple, at          32184165000
 test master 2 - Starting Memory Read Line Multiple, at          32184405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32185125000
 test master 2 - Starting Memory Read Line Multiple, at          32185305000
 test master 2 - Starting Memory Read Line Multiple, at          32185545000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32186265000
 test master 2 - Starting Memory Read Line Multiple, at          32186445000
 test master 2 - Starting Memory Read Line Multiple, at          32186685000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32187405000
 test master 2 - Starting Memory Read Line Multiple, at          32187585000
 test master 2 - Starting Memory Read Line Multiple, at          32187825000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32188545000
 test master 2 - Starting Memory Read Line Multiple, at          32188725000
 test master 2 - Starting Memory Read Line Multiple, at          32188965000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          32189685000
 test master 2 - Starting Memory Read Line, at          32189865000
 test master 2 - Starting Memory Read Line, at          32190045000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          32190495000
 test master 2 - Starting Memory Read Line, at          32190675000
 test master 2 - Starting Memory Read Line, at          32190855000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32192145000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32193855000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32197095000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32199015000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          32204235000
 test master 2 - Starting Memory Write, at          32204475000
 test master 2 - Starting Memory Write, at          32204715000
 test master 2 - Starting Memory Write, at          32204955000
 test master 2 - Starting Memory Write, at          32205195000
 test master 1 - Starting Memory Read, at          32205555000
 test master 1 - Starting Memory Read, at          32205825000
 test master 1 - Starting Memory Read, at          32206365000
 test master 1 - Starting Memory Read, at          32206635000
 test master 1 - Starting Memory Read, at          32207175000
 test master 1 - Starting Memory Read, at          32207445000
 test master 2 - Starting Memory Write, at          32208825000
 test master 2 - Starting Memory Write, at          32209065000
 test master 2 - Starting Memory Write, at          32209305000
 test master 2 - Starting Memory Write, at          32209545000
 test master 2 - Starting Memory Write, at          32209785000
 test master 1 - Starting Memory Read, at          32210145000
 test master 1 - Starting Memory Read, at          32210415000
 test master 1 - Starting Memory Read, at          32210955000
 test master 1 - Starting Memory Read, at          32211225000
 test master 1 - Starting Memory Read, at          32211765000
 test master 1 - Starting Memory Read, at          32212035000
 test master 2 - Starting Memory Write, at          32214015000
 test master 2 - Starting Memory Write, at          32215185000
 test master 2 - Starting Memory Write, at          32216385000
 test master 2 - Starting Memory Write, at          32217585000
 test master 2 - Starting Memory Write, at          32220105000
 test master 2 - Starting Memory Write, at          32221305000
 test master 2 - Starting Memory Write, at          32222505000
 test master 2 - Starting Memory Write, at          32223705000
 test master 2 - Starting Memory Write, at          32226225000
 test master 2 - Starting Memory Write, at          32228535000
 test master 2 - Starting Memory Write, at          32230815000
 test master 2 - Starting Memory Write, at          32233095000
 test master 2 - Starting Memory Write, at          32236695000
 test master 2 - Starting Memory Write, at          32239275000
 test master 2 - Starting Memory Write, at          32241855000
 test master 2 - Starting Memory Write, at          32244435000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          32249145000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32249175000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32251665000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          32251905000
 test master 2 - Starting Memory Read, at          32252085000
 test master 2 - Starting Memory Read, at          32252265000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32254035000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          32254395000
 test master 2 - Starting Memory Read, at          32254575000
 test master 2 - Starting Memory Read, at          32254755000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32256345000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32256795000
 test master 2 - Starting Memory Read Line Multiple, at          32256975000
 test master 2 - Starting Memory Read Line Multiple, at          32257215000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32259255000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32266215000
 test master 2 - Starting Memory Read Line Multiple, at          32266395000
 test master 2 - Starting Memory Read Line Multiple, at          32266665000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32267385000
 test master 2 - Starting Memory Read Line Multiple, at          32267565000
 test master 2 - Starting Memory Read Line Multiple, at          32267805000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32268525000
 test master 2 - Starting Memory Read Line Multiple, at          32268705000
 test master 2 - Starting Memory Read Line Multiple, at          32268945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32269665000
 test master 2 - Starting Memory Read Line Multiple, at          32269845000
 test master 2 - Starting Memory Read Line Multiple, at          32270085000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32270805000
 test master 2 - Starting Memory Read Line Multiple, at          32270985000
 test master 2 - Starting Memory Read Line Multiple, at          32271225000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32271945000
 test master 2 - Starting Memory Read Line Multiple, at          32272125000
 test master 2 - Starting Memory Read Line Multiple, at          32272365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32273085000
 test master 2 - Starting Memory Read Line Multiple, at          32273265000
 test master 2 - Starting Memory Read Line Multiple, at          32273505000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32274225000
 test master 2 - Starting Memory Read Line Multiple, at          32274405000
 test master 2 - Starting Memory Read Line Multiple, at          32274645000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          32275365000
 test master 2 - Starting Memory Read Line, at          32275545000
 test master 2 - Starting Memory Read Line, at          32275725000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          32276175000
 test master 2 - Starting Memory Read Line, at          32276355000
 test master 2 - Starting Memory Read Line, at          32276535000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32277825000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32279535000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32282775000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32284695000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          32289915000
 test master 2 - Starting Memory Write, at          32290155000
 test master 2 - Starting Memory Write, at          32290395000
 test master 2 - Starting Memory Write, at          32290635000
 test master 2 - Starting Memory Write, at          32290875000
 test master 1 - Starting Memory Read, at          32291235000
 test master 1 - Starting Memory Read, at          32291505000
 test master 1 - Starting Memory Read, at          32292045000
 test master 1 - Starting Memory Read, at          32292315000
 test master 1 - Starting Memory Read, at          32292855000
 test master 1 - Starting Memory Read, at          32293125000
 test master 2 - Starting Memory Write, at          32294505000
 test master 2 - Starting Memory Write, at          32294745000
 test master 2 - Starting Memory Write, at          32294985000
 test master 2 - Starting Memory Write, at          32295225000
 test master 2 - Starting Memory Write, at          32295465000
 test master 1 - Starting Memory Read, at          32295825000
 test master 1 - Starting Memory Read, at          32296095000
 test master 1 - Starting Memory Read, at          32296635000
 test master 1 - Starting Memory Read, at          32296905000
 test master 1 - Starting Memory Read, at          32297445000
 test master 1 - Starting Memory Read, at          32297715000
 test master 2 - Starting Memory Write, at          32299695000
 test master 2 - Starting Memory Write, at          32300865000
 test master 2 - Starting Memory Write, at          32302065000
 test master 2 - Starting Memory Write, at          32303265000
 test master 2 - Starting Memory Write, at          32305785000
 test master 2 - Starting Memory Write, at          32306985000
 test master 2 - Starting Memory Write, at          32308185000
 test master 2 - Starting Memory Write, at          32309385000
 test master 2 - Starting Memory Write, at          32311905000
 test master 2 - Starting Memory Write, at          32314215000
 test master 2 - Starting Memory Write, at          32316495000
 test master 2 - Starting Memory Write, at          32318775000
 test master 2 - Starting Memory Write, at          32322375000
 test master 2 - Starting Memory Write, at          32324955000
 test master 2 - Starting Memory Write, at          32327535000
 test master 2 - Starting Memory Write, at          32330115000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          32334825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32334855000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32337345000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          32337585000
 test master 2 - Starting Memory Read, at          32337765000
 test master 2 - Starting Memory Read, at          32337945000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32339715000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          32340075000
 test master 2 - Starting Memory Read, at          32340255000
 test master 2 - Starting Memory Read, at          32340435000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32342025000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32342475000
 test master 2 - Starting Memory Read Line Multiple, at          32342655000
 test master 2 - Starting Memory Read Line Multiple, at          32342895000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32344935000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32351895000
 test master 2 - Starting Memory Read Line Multiple, at          32352075000
 test master 2 - Starting Memory Read Line Multiple, at          32352345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32353065000
 test master 2 - Starting Memory Read Line Multiple, at          32353245000
 test master 2 - Starting Memory Read Line Multiple, at          32353485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32354205000
 test master 2 - Starting Memory Read Line Multiple, at          32354385000
 test master 2 - Starting Memory Read Line Multiple, at          32354625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32355345000
 test master 2 - Starting Memory Read Line Multiple, at          32355525000
 test master 2 - Starting Memory Read Line Multiple, at          32355765000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32356485000
 test master 2 - Starting Memory Read Line Multiple, at          32356665000
 test master 2 - Starting Memory Read Line Multiple, at          32356905000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32357625000
 test master 2 - Starting Memory Read Line Multiple, at          32357805000
 test master 2 - Starting Memory Read Line Multiple, at          32358045000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32358765000
 test master 2 - Starting Memory Read Line Multiple, at          32358945000
 test master 2 - Starting Memory Read Line Multiple, at          32359185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          32359905000
 test master 2 - Starting Memory Read Line Multiple, at          32360085000
 test master 2 - Starting Memory Read Line Multiple, at          32360325000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          32361045000
 test master 2 - Starting Memory Read Line, at          32361225000
 test master 2 - Starting Memory Read Line, at          32361405000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          32361855000
 test master 2 - Starting Memory Read Line, at          32362035000
 test master 2 - Starting Memory Read Line, at          32362215000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32363505000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32365215000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32368455000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          32370375000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          32375595000
 test master 2 - Starting Memory Write, at          32375835000
 test master 2 - Starting Memory Write, at          32376075000
 test master 2 - Starting Memory Write, at          32376315000
 test master 2 - Starting Memory Write, at          32376555000
 test master 1 - Starting Memory Read, at          32376915000
 test master 1 - Starting Memory Read, at          32377185000
 test master 1 - Starting Memory Read, at          32377725000
 test master 1 - Starting Memory Read, at          32377995000
 test master 1 - Starting Memory Read, at          32378535000
 test master 1 - Starting Memory Read, at          32378805000
 test master 2 - Starting Memory Write, at          32380185000
 test master 2 - Starting Memory Write, at          32380425000
 test master 2 - Starting Memory Write, at          32380665000
 test master 2 - Starting Memory Write, at          32380905000
 test master 2 - Starting Memory Write, at          32381145000
 test master 1 - Starting Memory Read, at          32381505000
 test master 1 - Starting Memory Read, at          32381775000
 test master 1 - Starting Memory Read, at          32382315000
 test master 1 - Starting Memory Read, at          32382585000
 test master 1 - Starting Memory Read, at          32383125000
 test master 1 - Starting Memory Read, at          32383395000
 test master 2 - Starting Memory Write, at          32385375000
 test master 2 - Starting Memory Write, at          32386545000
 test master 2 - Starting Memory Write, at          32387745000
 test master 2 - Starting Memory Write, at          32388945000
 test master 2 - Starting Memory Write, at          32391465000
 test master 2 - Starting Memory Write, at          32392665000
 test master 2 - Starting Memory Write, at          32393865000
 test master 2 - Starting Memory Write, at          32395065000
 test master 2 - Starting Memory Write, at          32397585000
 test master 2 - Starting Memory Write, at          32399895000
 test master 2 - Starting Memory Write, at          32402175000
 test master 2 - Starting Memory Write, at          32404455000
 test master 2 - Starting Memory Write, at          32408055000
 test master 2 - Starting Memory Write, at          32410635000
 test master 2 - Starting Memory Write, at          32413215000
 test master 2 - Starting Memory Write, at          32415795000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          32420505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32420535000
 test master 1 - Starting Memory Read, at          32423025000
 test master 1 - Starting Memory Read, at          32423325000
 test master 1 - Starting Memory Read, at          32424705000
 test master 1 - Starting Memory Read, at          32425005000
 test master 1 - Starting Memory Read Line, at          32426385000
 test master 1 - Starting Memory Read Line, at          32426685000
 test master 1 - Starting Memory Read Line, at          32428065000
 test master 1 - Starting Memory Read Line, at          32428365000
 test master 1 - Starting Memory Read Line, at          32429805000
 test master 1 - Starting Memory Read Line, at          32430165000
 test master 1 - Starting Memory Read Line, at          32431785000
 test master 1 - Starting Memory Read Line, at          32432145000
 test master 1 - Starting Memory Read Line Multiple, at          32433765000
 test master 1 - Starting Memory Read Line Multiple, at          32434185000
 test master 1 - Starting Memory Read Line Multiple, at          32436045000
 test master 1 - Starting Memory Read Line Multiple, at          32436465000
 test master 1 - Starting Memory Read Line, at          32438325000
 test master 1 - Starting Memory Read Line, at          32438685000
 test master 1 - Starting Memory Read, at          32441565000
 test master 1 - Starting Memory Read, at          32441865000
 test target 1 - Starting Config Write, at          32445705000
 test master 1 - Starting Memory Write, at          32446365000
 test master 1 - Starting Memory Write, at          32451975000
 test master 1 - Starting Memory Write, at          32453295000
 test master 1 - Starting Memory Write, at          32458545000
 test master 1 - Starting Memory Write, at          32459895000
 test master 1 - Starting Memory Read Line, at          32465505000
 test master 1 - Starting Memory Write, at          32467005000
 test master 1 - Starting Memory Read Line, at          32472615000
 test target 1 - Starting Config Write, at          32476365000
 test master 1 - Starting Memory Write, at          32477025000
 test master 1 - Starting Memory Write, at          32477145000
 test master 1 - Starting Memory Write, at          32477385000
 test master 1 - Starting Memory Read, at          32477505000
 test master 1 - Starting Memory Write, at          32477805000
 test master 1 - Starting Memory Read, at          32477925000
 test master 1 - Starting Memory Write, at          32479875000
 test master 1 - Starting Memory Write, at          32486835000
 test master 2 - Starting Memory Read Line, at          32493915000
 test master 2 - Starting Memory Read Line, at          32494245000
 test master 2 - Starting Memory Read Line, at          32494725000
 test master 2 - Starting Memory Read Line, at          32495055000
 test master 1 - Starting Memory Write, at          32495625000
 test master 1 - Starting Memory Write, at          32495895000
 test master 1 - Starting Memory Write, at          32496195000
 test master 2 - Starting Memory Read Line, at          32496615000
 test master 2 - Starting Memory Read Line, at          32496915000
 test master 2 - Starting Memory Read Line, at          32497185000
 test master 2 - Starting Memory Read Line, at          32497485000
 test master 2 - Starting Memory Read Line Multiple, at          32497785000
 test master 2 - Starting Memory Read Line Multiple, at          32498085000
 test master 1 - Starting Memory Write, at          32500305000
 test master 1 - Starting Memory Write, at          32500575000
 test master 2 - Starting Memory Read, at          32500995000
 test master 2 - Starting Memory Read, at          32501295000
 test master 2 - Starting Memory Read, at          32501565000
 test master 2 - Starting Memory Read, at          32501865000
 test master 1 - Starting Memory Write, at          32503785000
 test master 1 - Starting Memory Read, at          32503965000
 test master 1 - Starting Memory Write, at          32504145000
 test master 1 - Starting Memory Read, at          32504355000
 test master 1 - Starting Memory Write, at          32504565000
 test master 1 - Starting Memory Read, at          32504745000
 test master 1 - Starting Memory Read, at          32504955000
 test master 1 - Starting Memory Write, at          32505165000
 test master 1 - Starting Memory Write, at          32505345000
 test master 1 - Starting Memory Read, at          32505525000
 test master 1 - Starting Memory Write, at          32505705000
 test master 1 - Starting Memory Write, at          32505915000
 test master 1 - Starting Memory Write, at          32506125000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          32511345000
 test target 1 - Starting Memory Write, at          32511555000
 test master 1 - Starting Memory Write, at          32511735000
 test target 1 - Starting Memory Write, at          32511915000
 test target 1 - Starting Memory Write, at          32512125000
 test target 1 - Starting Memory Write, at          32512335000
 test master 1 - Starting Memory Write, at          32512635000
 test target 1 - Starting Memory Write, at          32513145000
 test target 1 - Starting Memory Write, at          32513715000
 test target 1 - Starting Memory Write, at          32513955000
 test master 1 - Starting Memory Write, at          32514165000
 test target 1 - Starting Memory Write, at          32514525000
 test target 1 - Starting Memory Write, at          32514765000
 test target 1 - Starting Memory Write, at          32515005000
 test master 1 - Starting Memory Write, at          32515485000
 test target 1 - Starting Memory Write, at          32516325000
 test target 1 - Starting Memory Write, at          32517075000
 test target 1 - Starting Memory Write, at          32517285000
 test master 1 - Starting Memory Read, at          32517465000
 test target 1 - Starting Memory Write, at          32517645000
 test master 1 - Starting Memory Read, at          32517825000
 test target 1 - Starting Memory Write, at          32518005000
 test master 1 - Starting Memory Read, at          32518185000
 test target 1 - Starting Memory Write, at          32518365000
 test master 1 - Starting Memory Read, at          32518545000
 test target 1 - Starting Memory Write, at          32518725000
 test master 1 - Starting Memory Read, at          32518905000
 test target 1 - Starting Memory Write, at          32519085000
 test master 1 - Starting Memory Write, at          32519265000
 test target 1 - Starting Memory Write, at          32519445000
 test target 1 - Starting Memory Write, at          32519655000
 test target 1 - Starting Memory Write, at          32519865000
 test target 1 - Starting Memory Read, at          32520135000
 test master 1 - Starting Memory Write, at          32520435000
 test master 1 - Starting Memory Read, at          32520675000
 test target 1 - Starting Memory Write, at          32521185000
 test master 1 - Starting Memory Write, at          32521575000
 test target 1 - Starting Memory Read, at          32522025000
 test target 1 - Starting Memory Write, at          32522835000
 test master 1 - Starting Memory Read, at          32523135000
 test master 1 - Starting Memory Write, at          32523435000
 test master 1 - Starting Memory Write, at          32523795000
 test master 1 - Starting Memory Read, at          32524035000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          32526885000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          32528025000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          32555385000
 test target 1 - Starting Config Write, at          32556405000
 test target 1 - Starting Config Write, at          32557455000
 test target 2 - Starting Config Write, at          32558505000
 test target 2 - Starting Config Write, at          32559525000
 test target 2 - Starting Config Write, at          32560575000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          32562855000
 test target 1 - Starting Memory Read, at          32563065000
 test target 1 - Starting Memory Write, at          32563815000
 test target 1 - Starting Memory Read, at          32564025000
 test target 1 - Starting Memory Write, at          32565285000
 test target 1 - Starting Memory Read, at          32566245000
 test target 1 - Starting Memory Read, at          32566875000
 test target 1 - Starting Memory Read, at          32567505000
 test target 1 - Starting Memory Read, at          32568105000
 test target 1 - Starting Memory Read, at          32569065000
 test target 1 - Starting Memory Read, at          32570175000
 test target 1 - Starting Memory Read, at          32571225000
 test target 1 - Starting Memory Read, at          32572335000
 test target 1 - Starting Memory Read, at          32573385000
 test target 1 - Starting Memory Read, at          32575155000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          32582475000
 test target 1 - Starting Memory Read, at          32582685000
 test target 1 - Starting Memory Write, at          32583435000
 test target 1 - Starting Memory Read, at          32583645000
 test target 1 - Starting Memory Write, at          32584905000
 test target 1 - Starting Memory Read, at          32585865000
 test target 1 - Starting Memory Read, at          32586495000
 test target 1 - Starting Memory Read, at          32587125000
 test target 1 - Starting Memory Read, at          32587725000
 test target 1 - Starting Memory Read, at          32588685000
 test target 1 - Starting Memory Read, at          32589795000
 test target 1 - Starting Memory Read, at          32590845000
 test target 1 - Starting Memory Read, at          32591955000
 test target 1 - Starting Memory Read, at          32593005000
 test target 1 - Starting Memory Read, at          32594775000
 test target 1 - Starting Memory Write, at          32602095000
 test target 1 - Starting Memory Read, at          32602305000
 test target 1 - Starting Memory Write, at          32603055000
 test target 1 - Starting Memory Read, at          32603265000
 test target 1 - Starting Memory Write, at          32604525000
 test target 1 - Starting Memory Read, at          32605485000
 test target 1 - Starting Memory Read, at          32606115000
 test target 1 - Starting Memory Read, at          32606745000
 test target 1 - Starting Memory Read, at          32607345000
 test target 1 - Starting Memory Read, at          32608305000
 test target 1 - Starting Memory Read, at          32609415000
 test target 1 - Starting Memory Read, at          32610465000
 test target 1 - Starting Memory Read, at          32611575000
 test target 1 - Starting Memory Read, at          32612625000
 test target 1 - Starting Memory Read, at          32614395000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          32629125000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          32636685000
 test target 1 - Starting Memory Write, at          32637645000
 test target 1 - Starting Memory Read, at          32637945000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          32639265000
 test target 1 - Starting Config Write, at          32641455000
 test target 1 - Starting Memory Read, at          32642175000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          32643945000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          32646345000
 test target 1 - Starting Memory Write, at          32647755000
 test target 1 - Starting Memory Write, at          32647995000
 test target 1 - Starting Memory Read, at          32648175000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          32651145000
 test target 1 - Starting Memory Write, at          32654775000
 test target 1 - Starting Memory Write, at          32655165000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          32659755000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          32662065000
 test target 1 - Starting Memory Read, at          32663535000
 test target 1 - Starting Memory Read, at          32664585000
 test target 1 - Starting Memory Read, at          32666415000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          32673525000
 test target 2 - Starting Config Write, at          32674575000
 test target 1 - Starting Memory Write, at          32675325000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          32675415000
 test target 1 - Starting Memory Write, at          32676615000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          32676705000
 test target 1 - Starting Memory Write, at          32677905000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          32679465000
 test target 1 - Starting Memory Read, at          32682015000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          32682135000
 test target 1 - Starting Memory Read, at          32684685000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          32686695000
 test master 2 - Starting Memory Write, at          32686695000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          32686755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32687655000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32687685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32687985000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32688015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32689035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32689065000
 test target 1 - Starting Memory Write, at          32691135000
 test master 2 - Starting Memory Write, at          32691135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32693055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32693085000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32695035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32695065000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32697015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32697045000
 test target 1 - Starting Memory Write, at          32699415000
 test master 2 - Starting Memory Write, at          32699415000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          32699475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32701305000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32701335000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32701635000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32701665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32702685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32702715000
 test target 1 - Starting Memory Write, at          32704035000
 test master 2 - Starting Memory Write, at          32704035000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          32707455000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          32709345000
 test master 1 - Starting Memory Read, at          32709705000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          32709855000
 test target 1 - Starting Config Write, at          32712885000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          32715735000
 test target 1 - Starting Memory Write, at          32715855000
 test target 1 - Starting Memory Write, at          32715975000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          32716485000
 test target 1 - Starting Memory Write, at          32716635000
 test target 1 - Starting Memory Write, at          32716785000
 test target 1 - Starting Memory Write, at          32717295000
 test target 1 - Starting Memory Write, at          32717475000
 test target 1 - Starting Memory Write, at          32717985000
 test target 1 - Starting Memory Write, at          32718645000
 test target 1 - Starting Memory Write, at          32718795000
 test target 1 - Starting Memory Write, at          32719455000
 test target 1 - Starting Memory Write, at          32719665000
 test target 1 - Starting Memory Write, at          32720265000
 test target 1 - Starting Memory Write, at          32726955000
 test target 1 - Starting Memory Write, at          32727105000
 test target 1 - Starting Memory Write, at          32727255000
 test target 1 - Starting Memory Write, at          32727465000
 test target 1 - Starting Memory Write, at          32727675000
 test target 1 - Starting Memory Read, at          32731275000
 test target 1 - Starting Memory Read, at          32732385000
 test target 1 - Starting Memory Read, at          32733465000
 test target 1 - Starting Memory Read, at          32734545000
 test target 1 - Starting Memory Read, at          32735625000
 test target 1 - Starting Memory Read, at          32736705000
 test target 1 - Starting Memory Read, at          32737785000
 test target 1 - Starting Memory Read, at          32738865000
 test target 1 - Starting Memory Read, at          32739945000
 test target 1 - Starting Memory Read, at          32741025000
 test target 1 - Starting Memory Read, at          32742105000
 test target 1 - Starting Memory Read, at          32743185000
 test target 1 - Starting Memory Read, at          32744265000
 test target 1 - Starting Memory Read, at          32745345000
 test target 1 - Starting Memory Read, at          32746425000
 test target 1 - Starting Memory Read, at          32747505000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          32748405000
 test target 1 - Starting Memory Read, at          32748555000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          32750895000
 test target 1 - Starting Memory Read, at          32751975000
 test target 1 - Starting Memory Read, at          32752725000
 test target 1 - Starting Memory Read, at          32753325000
 test target 1 - Starting Memory Read, at          32754045000
 test target 1 - Starting Memory Read, at          32754855000
 test target 1 - Starting Memory Read, at          32756085000
 test target 1 - Starting Memory Read, at          32757195000
 test target 1 - Starting Memory Read, at          32758245000
 test target 1 - Starting Memory Read, at          32761065000
 test target 1 - Starting Memory Read, at          32763165000
 test target 1 - Starting Memory Read, at          32764125000
 test target 1 - Starting Memory Read, at          32765085000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          32766585000
 test master 1 - Starting Memory Write, at          32766855000
 test target 1 - Starting Memory Write, at          32766855000
 test target 1 - Starting Memory Write, at          32767005000
 test target 1 - Starting Memory Read, at          32767245000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          32769255000
 test master 1 - Starting Memory Write, at          32769495000
 test target 1 - Starting Memory Write, at          32769495000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          32775045000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          32776185000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          32803545000
 test target 1 - Starting Config Write, at          32804565000
 test target 1 - Starting Config Write, at          32805615000
 test target 2 - Starting Config Write, at          32806665000
 test target 2 - Starting Config Write, at          32807685000
 test target 2 - Starting Config Write, at          32808735000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          32811015000
 test target 1 - Starting Memory Read, at          32811225000
 test target 1 - Starting Memory Write, at          32811975000
 test target 1 - Starting Memory Read, at          32812185000
 test target 1 - Starting Memory Write, at          32813445000
 test target 1 - Starting Memory Read, at          32814465000
 test target 1 - Starting Memory Read, at          32815095000
 test target 1 - Starting Memory Read, at          32815725000
 test target 1 - Starting Memory Read, at          32816325000
 test target 1 - Starting Memory Read, at          32817285000
 test target 1 - Starting Memory Read, at          32818395000
 test target 1 - Starting Memory Read, at          32819445000
 test target 1 - Starting Memory Read, at          32820555000
 test target 1 - Starting Memory Read, at          32821605000
 test target 1 - Starting Memory Read, at          32823375000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          32830695000
 test target 1 - Starting Memory Read, at          32830905000
 test target 1 - Starting Memory Write, at          32831655000
 test target 1 - Starting Memory Read, at          32831865000
 test target 1 - Starting Memory Write, at          32833125000
 test target 1 - Starting Memory Read, at          32834145000
 test target 1 - Starting Memory Read, at          32834775000
 test target 1 - Starting Memory Read, at          32835405000
 test target 1 - Starting Memory Read, at          32836005000
 test target 1 - Starting Memory Read, at          32836965000
 test target 1 - Starting Memory Read, at          32838075000
 test target 1 - Starting Memory Read, at          32839125000
 test target 1 - Starting Memory Read, at          32840235000
 test target 1 - Starting Memory Read, at          32841285000
 test target 1 - Starting Memory Read, at          32843055000
 test target 1 - Starting Memory Write, at          32850375000
 test target 1 - Starting Memory Read, at          32850585000
 test target 1 - Starting Memory Write, at          32851335000
 test target 1 - Starting Memory Read, at          32851545000
 test target 1 - Starting Memory Write, at          32852805000
 test target 1 - Starting Memory Read, at          32853825000
 test target 1 - Starting Memory Read, at          32854455000
 test target 1 - Starting Memory Read, at          32855085000
 test target 1 - Starting Memory Read, at          32855685000
 test target 1 - Starting Memory Read, at          32856645000
 test target 1 - Starting Memory Read, at          32857755000
 test target 1 - Starting Memory Read, at          32858805000
 test target 1 - Starting Memory Read, at          32859915000
 test target 1 - Starting Memory Read, at          32860965000
 test target 1 - Starting Memory Read, at          32862735000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          32877465000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          32885025000
 test target 1 - Starting Memory Write, at          32885985000
 test target 1 - Starting Memory Read, at          32886315000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          32887605000
 test target 1 - Starting Config Write, at          32889795000
 test target 1 - Starting Memory Read, at          32890515000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          32892285000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          32894685000
 test target 1 - Starting Memory Write, at          32896095000
 test target 1 - Starting Memory Write, at          32896365000
 test target 1 - Starting Memory Read, at          32896575000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          32899485000
 test target 1 - Starting Memory Write, at          32903115000
 test target 1 - Starting Memory Write, at          32903505000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          32908155000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          32910465000
 test target 1 - Starting Memory Read, at          32911935000
 test target 1 - Starting Memory Read, at          32912985000
 test target 1 - Starting Memory Read, at          32914815000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          32921925000
 test target 2 - Starting Config Write, at          32922975000
 test target 1 - Starting Memory Write, at          32923725000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          32923845000
 test target 1 - Starting Memory Write, at          32925045000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          32925165000
 test target 1 - Starting Memory Write, at          32926365000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          32927985000
 test target 1 - Starting Memory Read, at          32930535000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          32930655000
 test target 1 - Starting Memory Read, at          32933205000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          32935215000
 test master 2 - Starting Memory Write, at          32935215000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          32935275000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32936205000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32936235000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32936535000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32936565000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32937585000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32937615000
 test target 1 - Starting Memory Write, at          32939685000
 test master 2 - Starting Memory Write, at          32939685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32941635000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32941665000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32943615000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32943645000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32945595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32945625000
 test target 1 - Starting Memory Write, at          32947995000
 test master 2 - Starting Memory Write, at          32947995000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          32948055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32949915000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32949945000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32950245000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32950275000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32951295000
*** monitor - CBE Bus Changed when TRDY Desserted, at          32951325000
 test target 1 - Starting Memory Write, at          32952645000
 test master 2 - Starting Memory Write, at          32952645000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          32956095000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          32957985000
 test master 1 - Starting Memory Read, at          32958345000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          32958495000
 test target 1 - Starting Config Write, at          32961525000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          32964375000
 test target 1 - Starting Memory Write, at          32964525000
 test target 1 - Starting Memory Write, at          32964675000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          32965215000
 test target 1 - Starting Memory Write, at          32965395000
 test target 1 - Starting Memory Write, at          32965575000
 test target 1 - Starting Memory Write, at          32966115000
 test target 1 - Starting Memory Write, at          32966325000
 test target 1 - Starting Memory Write, at          32966865000
 test target 1 - Starting Memory Write, at          32967555000
 test target 1 - Starting Memory Write, at          32967735000
 test target 1 - Starting Memory Write, at          32968425000
 test target 1 - Starting Memory Write, at          32968665000
 test target 1 - Starting Memory Write, at          32969295000
 test target 1 - Starting Memory Write, at          32976015000
 test target 1 - Starting Memory Write, at          32976195000
 test target 1 - Starting Memory Write, at          32976375000
 test target 1 - Starting Memory Write, at          32976615000
 test target 1 - Starting Memory Write, at          32976855000
 test target 1 - Starting Memory Read, at          32980485000
 test target 1 - Starting Memory Read, at          32981595000
 test target 1 - Starting Memory Read, at          32982675000
 test target 1 - Starting Memory Read, at          32983755000
 test target 1 - Starting Memory Read, at          32984835000
 test target 1 - Starting Memory Read, at          32985915000
 test target 1 - Starting Memory Read, at          32986995000
 test target 1 - Starting Memory Read, at          32988075000
 test target 1 - Starting Memory Read, at          32989155000
 test target 1 - Starting Memory Read, at          32990235000
 test target 1 - Starting Memory Read, at          32991315000
 test target 1 - Starting Memory Read, at          32992395000
 test target 1 - Starting Memory Read, at          32993475000
 test target 1 - Starting Memory Read, at          32994555000
 test target 1 - Starting Memory Read, at          32995635000
 test target 1 - Starting Memory Read, at          32996715000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          32997645000
 test target 1 - Starting Memory Read, at          32997795000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          33000135000
 test target 1 - Starting Memory Read, at          33001245000
 test target 1 - Starting Memory Read, at          33001935000
 test target 1 - Starting Memory Read, at          33002565000
 test target 1 - Starting Memory Read, at          33003255000
 test target 1 - Starting Memory Read, at          33004065000
 test target 1 - Starting Memory Read, at          33005295000
 test target 1 - Starting Memory Read, at          33006435000
 test target 1 - Starting Memory Read, at          33007455000
 test target 1 - Starting Memory Read, at          33010275000
 test target 1 - Starting Memory Read, at          33012345000
 test target 1 - Starting Memory Read, at          33013305000
 test target 1 - Starting Memory Read, at          33014265000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          33015765000
 test master 1 - Starting Memory Write, at          33016005000
 test target 1 - Starting Memory Write, at          33016005000
 test target 1 - Starting Memory Write, at          33016155000
 test target 1 - Starting Memory Read, at          33016485000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          33018405000
 test master 1 - Starting Memory Write, at          33018645000
 test target 1 - Starting Memory Write, at          33018645000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          33024045000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          33025185000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          33052545000
 test target 1 - Starting Config Write, at          33053565000
 test target 1 - Starting Config Write, at          33054615000
 test target 2 - Starting Config Write, at          33055665000
 test target 2 - Starting Config Write, at          33056685000
 test target 2 - Starting Config Write, at          33057735000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          33060015000
 test target 1 - Starting Memory Read, at          33060255000
 test target 1 - Starting Memory Write, at          33060975000
 test target 1 - Starting Memory Read, at          33061215000
 test target 1 - Starting Memory Write, at          33062445000
 test target 1 - Starting Memory Read, at          33063465000
 test target 1 - Starting Memory Read, at          33064095000
 test target 1 - Starting Memory Read, at          33064725000
 test target 1 - Starting Memory Read, at          33065325000
 test target 1 - Starting Memory Read, at          33066285000
 test target 1 - Starting Memory Read, at          33067395000
 test target 1 - Starting Memory Read, at          33068445000
 test target 1 - Starting Memory Read, at          33069555000
 test target 1 - Starting Memory Read, at          33070605000
 test target 1 - Starting Memory Read, at          33072375000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          33079695000
 test target 1 - Starting Memory Read, at          33079935000
 test target 1 - Starting Memory Write, at          33080655000
 test target 1 - Starting Memory Read, at          33080895000
 test target 1 - Starting Memory Write, at          33082125000
 test target 1 - Starting Memory Read, at          33083145000
 test target 1 - Starting Memory Read, at          33083775000
 test target 1 - Starting Memory Read, at          33084405000
 test target 1 - Starting Memory Read, at          33085005000
 test target 1 - Starting Memory Read, at          33085965000
 test target 1 - Starting Memory Read, at          33087075000
 test target 1 - Starting Memory Read, at          33088125000
 test target 1 - Starting Memory Read, at          33089235000
 test target 1 - Starting Memory Read, at          33090285000
 test target 1 - Starting Memory Read, at          33092055000
 test target 1 - Starting Memory Write, at          33099375000
 test target 1 - Starting Memory Read, at          33099615000
 test target 1 - Starting Memory Write, at          33100335000
 test target 1 - Starting Memory Read, at          33100575000
 test target 1 - Starting Memory Write, at          33101805000
 test target 1 - Starting Memory Read, at          33102825000
 test target 1 - Starting Memory Read, at          33103455000
 test target 1 - Starting Memory Read, at          33104085000
 test target 1 - Starting Memory Read, at          33104685000
 test target 1 - Starting Memory Read, at          33105645000
 test target 1 - Starting Memory Read, at          33106755000
 test target 1 - Starting Memory Read, at          33107805000
 test target 1 - Starting Memory Read, at          33108915000
 test target 1 - Starting Memory Read, at          33109965000
 test target 1 - Starting Memory Read, at          33111735000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          33126465000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          33134025000
 test target 1 - Starting Memory Write, at          33134985000
 test target 1 - Starting Memory Read, at          33135345000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          33136605000
 test target 1 - Starting Config Write, at          33138795000
 test target 1 - Starting Memory Read, at          33139515000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          33141285000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          33143685000
 test target 1 - Starting Memory Write, at          33145095000
 test target 1 - Starting Memory Write, at          33145395000
 test target 1 - Starting Memory Read, at          33145635000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          33148485000
 test target 1 - Starting Memory Write, at          33152175000
 test target 1 - Starting Memory Write, at          33152565000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          33157215000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          33159525000
 test target 1 - Starting Memory Read, at          33160995000
 test target 1 - Starting Memory Read, at          33162045000
 test target 1 - Starting Memory Read, at          33163875000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          33170985000
 test target 2 - Starting Config Write, at          33172035000
 test target 1 - Starting Memory Write, at          33172785000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          33172935000
 test target 1 - Starting Memory Write, at          33174135000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          33174285000
 test target 1 - Starting Memory Write, at          33175485000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          33177105000
 test target 1 - Starting Memory Read, at          33179655000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          33179805000
 test target 1 - Starting Memory Read, at          33182325000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          33184335000
 test master 2 - Starting Memory Write, at          33184335000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          33184395000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33185355000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33185385000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33185685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33185715000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33186735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33186765000
 test target 1 - Starting Memory Write, at          33188835000
 test master 2 - Starting Memory Write, at          33188835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33190815000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33190845000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33192795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33192825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33194775000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33194805000
 test target 1 - Starting Memory Write, at          33197175000
 test master 2 - Starting Memory Write, at          33197175000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          33197235000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33199125000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33199155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33199455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33199485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33200505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33200535000
 test target 1 - Starting Memory Write, at          33201855000
 test master 2 - Starting Memory Write, at          33201855000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          33205335000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          33207225000
 test master 1 - Starting Memory Read, at          33207585000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          33207735000
 test target 1 - Starting Config Write, at          33210765000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          33213615000
 test target 1 - Starting Memory Write, at          33213795000
 test target 1 - Starting Memory Write, at          33213975000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          33214545000
 test target 1 - Starting Memory Write, at          33214755000
 test target 1 - Starting Memory Write, at          33214965000
 test target 1 - Starting Memory Write, at          33215535000
 test target 1 - Starting Memory Write, at          33215775000
 test target 1 - Starting Memory Write, at          33216345000
 test target 1 - Starting Memory Write, at          33217065000
 test target 1 - Starting Memory Write, at          33217275000
 test target 1 - Starting Memory Write, at          33217995000
 test target 1 - Starting Memory Write, at          33218265000
 test target 1 - Starting Memory Write, at          33218925000
 test target 1 - Starting Memory Write, at          33225675000
 test target 1 - Starting Memory Write, at          33225885000
 test target 1 - Starting Memory Write, at          33226095000
 test target 1 - Starting Memory Write, at          33226365000
 test target 1 - Starting Memory Write, at          33226635000
 test target 1 - Starting Memory Read, at          33230295000
 test target 1 - Starting Memory Read, at          33231405000
 test target 1 - Starting Memory Read, at          33232485000
 test target 1 - Starting Memory Read, at          33233565000
 test target 1 - Starting Memory Read, at          33234645000
 test target 1 - Starting Memory Read, at          33235725000
 test target 1 - Starting Memory Read, at          33236805000
 test target 1 - Starting Memory Read, at          33237885000
 test target 1 - Starting Memory Read, at          33238965000
 test target 1 - Starting Memory Read, at          33240045000
 test target 1 - Starting Memory Read, at          33241125000
 test target 1 - Starting Memory Read, at          33242205000
 test target 1 - Starting Memory Read, at          33243285000
 test target 1 - Starting Memory Read, at          33244365000
 test target 1 - Starting Memory Read, at          33245445000
 test target 1 - Starting Memory Read, at          33246525000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          33247455000
 test target 1 - Starting Memory Read, at          33247635000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          33249945000
 test target 1 - Starting Memory Read, at          33251085000
 test target 1 - Starting Memory Read, at          33251775000
 test target 1 - Starting Memory Read, at          33252555000
 test target 1 - Starting Memory Read, at          33253245000
 test target 1 - Starting Memory Read, at          33254055000
 test target 1 - Starting Memory Read, at          33255285000
 test target 1 - Starting Memory Read, at          33256395000
 test target 1 - Starting Memory Read, at          33257445000
 test target 1 - Starting Memory Read, at          33260265000
 test target 1 - Starting Memory Read, at          33262365000
 test target 1 - Starting Memory Read, at          33263325000
 test target 1 - Starting Memory Read, at          33264285000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          33265785000
 test master 1 - Starting Memory Write, at          33266055000
 test target 1 - Starting Memory Write, at          33266055000
 test target 1 - Starting Memory Write, at          33266235000
 test target 1 - Starting Memory Read, at          33266595000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          33268605000
 test master 1 - Starting Memory Write, at          33268875000
 test target 1 - Starting Memory Write, at          33268875000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          33274425000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          33275565000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          33302925000
 test target 1 - Starting Config Write, at          33303945000
 test target 1 - Starting Config Write, at          33304995000
 test target 2 - Starting Config Write, at          33306045000
 test target 2 - Starting Config Write, at          33307065000
 test target 2 - Starting Config Write, at          33308115000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          33310395000
 test target 1 - Starting Memory Read, at          33310665000
 test target 1 - Starting Memory Write, at          33311355000
 test target 1 - Starting Memory Read, at          33311625000
 test target 1 - Starting Memory Write, at          33312825000
 test target 1 - Starting Memory Read, at          33313905000
 test target 1 - Starting Memory Read, at          33314535000
 test target 1 - Starting Memory Read, at          33315165000
 test target 1 - Starting Memory Read, at          33315765000
 test target 1 - Starting Memory Read, at          33316725000
 test target 1 - Starting Memory Read, at          33317835000
 test target 1 - Starting Memory Read, at          33318885000
 test target 1 - Starting Memory Read, at          33319995000
 test target 1 - Starting Memory Read, at          33321045000
 test target 1 - Starting Memory Read, at          33322815000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          33330135000
 test target 1 - Starting Memory Read, at          33330405000
 test target 1 - Starting Memory Write, at          33331095000
 test target 1 - Starting Memory Read, at          33331365000
 test target 1 - Starting Memory Write, at          33332565000
 test target 1 - Starting Memory Read, at          33333645000
 test target 1 - Starting Memory Read, at          33334275000
 test target 1 - Starting Memory Read, at          33334905000
 test target 1 - Starting Memory Read, at          33335505000
 test target 1 - Starting Memory Read, at          33336465000
 test target 1 - Starting Memory Read, at          33337575000
 test target 1 - Starting Memory Read, at          33338625000
 test target 1 - Starting Memory Read, at          33339735000
 test target 1 - Starting Memory Read, at          33340785000
 test target 1 - Starting Memory Read, at          33342555000
 test target 1 - Starting Memory Write, at          33349875000
 test target 1 - Starting Memory Read, at          33350145000
 test target 1 - Starting Memory Write, at          33350835000
 test target 1 - Starting Memory Read, at          33351105000
 test target 1 - Starting Memory Write, at          33352305000
 test target 1 - Starting Memory Read, at          33353385000
 test target 1 - Starting Memory Read, at          33354015000
 test target 1 - Starting Memory Read, at          33354645000
 test target 1 - Starting Memory Read, at          33355245000
 test target 1 - Starting Memory Read, at          33356205000
 test target 1 - Starting Memory Read, at          33357315000
 test target 1 - Starting Memory Read, at          33358365000
 test target 1 - Starting Memory Read, at          33359475000
 test target 1 - Starting Memory Read, at          33360525000
 test target 1 - Starting Memory Read, at          33362295000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          33377025000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          33384585000
 test target 1 - Starting Memory Write, at          33385545000
 test target 1 - Starting Memory Read, at          33385935000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          33387345000
 test target 1 - Starting Config Write, at          33389505000
 test target 1 - Starting Memory Read, at          33390255000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          33392025000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          33394425000
 test target 1 - Starting Memory Write, at          33395835000
 test target 1 - Starting Memory Write, at          33396165000
 test target 1 - Starting Memory Read, at          33396435000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          33399465000
 test target 1 - Starting Memory Write, at          33403155000
 test target 1 - Starting Memory Write, at          33403545000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          33408255000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          33410565000
 test target 1 - Starting Memory Read, at          33412035000
 test target 1 - Starting Memory Read, at          33413085000
 test target 1 - Starting Memory Read, at          33414915000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          33422025000
 test target 2 - Starting Config Write, at          33423075000
 test target 1 - Starting Memory Write, at          33423825000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          33424005000
 test target 1 - Starting Memory Write, at          33425205000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          33425385000
 test target 1 - Starting Memory Write, at          33426585000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          33428265000
 test target 1 - Starting Memory Read, at          33430815000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          33430995000
 test target 1 - Starting Memory Read, at          33433485000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          33435495000
 test master 2 - Starting Memory Write, at          33435495000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          33435555000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33436545000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33436575000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33436875000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33436905000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33437925000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33437955000
 test target 1 - Starting Memory Write, at          33440025000
 test master 2 - Starting Memory Write, at          33440025000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33442035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33442065000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33444015000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33444045000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33445995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33446025000
 test target 1 - Starting Memory Write, at          33448395000
 test master 2 - Starting Memory Write, at          33448395000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          33448455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33450375000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33450405000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33450705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33450735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33451755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33451785000
 test target 1 - Starting Memory Write, at          33453105000
 test master 2 - Starting Memory Write, at          33453105000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          33456615000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          33458505000
 test master 1 - Starting Memory Read, at          33458865000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          33459015000
 test target 1 - Starting Config Write, at          33462045000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          33464895000
 test target 1 - Starting Memory Write, at          33465105000
 test target 1 - Starting Memory Write, at          33465315000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          33465915000
 test target 1 - Starting Memory Write, at          33466155000
 test target 1 - Starting Memory Write, at          33466395000
 test target 1 - Starting Memory Write, at          33466995000
 test target 1 - Starting Memory Write, at          33467265000
 test target 1 - Starting Memory Write, at          33467865000
 test target 1 - Starting Memory Write, at          33468615000
 test target 1 - Starting Memory Write, at          33468855000
 test target 1 - Starting Memory Write, at          33469605000
 test target 1 - Starting Memory Write, at          33469905000
 test target 1 - Starting Memory Write, at          33470595000
 test target 1 - Starting Memory Write, at          33477375000
 test target 1 - Starting Memory Write, at          33477615000
 test target 1 - Starting Memory Write, at          33477855000
 test target 1 - Starting Memory Write, at          33478155000
 test target 1 - Starting Memory Write, at          33478455000
 test target 1 - Starting Memory Read, at          33482145000
 test target 1 - Starting Memory Read, at          33483285000
 test target 1 - Starting Memory Read, at          33484365000
 test target 1 - Starting Memory Read, at          33485445000
 test target 1 - Starting Memory Read, at          33486525000
 test target 1 - Starting Memory Read, at          33487605000
 test target 1 - Starting Memory Read, at          33488685000
 test target 1 - Starting Memory Read, at          33489765000
 test target 1 - Starting Memory Read, at          33490845000
 test target 1 - Starting Memory Read, at          33491925000
 test target 1 - Starting Memory Read, at          33493005000
 test target 1 - Starting Memory Read, at          33494085000
 test target 1 - Starting Memory Read, at          33495165000
 test target 1 - Starting Memory Read, at          33496245000
 test target 1 - Starting Memory Read, at          33497325000
 test target 1 - Starting Memory Read, at          33498405000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          33499305000
 test target 1 - Starting Memory Read, at          33499515000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          33501795000
 test target 1 - Starting Memory Read, at          33502965000
 test target 1 - Starting Memory Read, at          33503625000
 test target 1 - Starting Memory Read, at          33504405000
 test target 1 - Starting Memory Read, at          33505305000
 test target 1 - Starting Memory Read, at          33506115000
 test target 1 - Starting Memory Read, at          33507345000
 test target 1 - Starting Memory Read, at          33508455000
 test target 1 - Starting Memory Read, at          33509505000
 test target 1 - Starting Memory Read, at          33512325000
 test target 1 - Starting Memory Read, at          33514425000
 test target 1 - Starting Memory Read, at          33515385000
 test target 1 - Starting Memory Read, at          33516345000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          33517845000
 test master 1 - Starting Memory Write, at          33518085000
 test target 1 - Starting Memory Write, at          33518085000
 test target 1 - Starting Memory Write, at          33518295000
 test target 1 - Starting Memory Read, at          33518745000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          33520815000
 test master 1 - Starting Memory Write, at          33521055000
 test target 1 - Starting Memory Write, at          33521055000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33527235000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          33527535000
 test master 2 - Starting Memory Read, at          33527715000
 test master 2 - Starting Memory Read, at          33527895000
 test master 2 - Starting Memory Read, at          33528135000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33529875000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          33530295000
 test master 2 - Starting Memory Read, at          33530475000
 test master 2 - Starting Memory Read, at          33530895000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33532515000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33533085000
 test master 2 - Starting Memory Read Line Multiple, at          33533265000
 test master 2 - Starting Memory Read Line Multiple, at          33533445000
 test master 2 - Starting Memory Read Line Multiple, at          33533625000
 test master 2 - Starting Memory Read Line Multiple, at          33533925000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33535815000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33544635000
 test master 2 - Starting Memory Read Line Multiple, at          33544815000
 test master 2 - Starting Memory Read Line Multiple, at          33544995000
 test master 2 - Starting Memory Read Line Multiple, at          33545175000
 test master 2 - Starting Memory Read Line Multiple, at          33545505000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33546045000
 test master 2 - Starting Memory Read Line Multiple, at          33546225000
 test master 2 - Starting Memory Read Line Multiple, at          33546405000
 test master 2 - Starting Memory Read Line Multiple, at          33546585000
 test master 2 - Starting Memory Read Line Multiple, at          33546885000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33547425000
 test master 2 - Starting Memory Read Line Multiple, at          33547605000
 test master 2 - Starting Memory Read Line Multiple, at          33547785000
 test master 2 - Starting Memory Read Line Multiple, at          33547965000
 test master 2 - Starting Memory Read Line Multiple, at          33548265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33548805000
 test master 2 - Starting Memory Read Line Multiple, at          33548985000
 test master 2 - Starting Memory Read Line Multiple, at          33549165000
 test master 2 - Starting Memory Read Line Multiple, at          33549345000
 test master 2 - Starting Memory Read Line Multiple, at          33549645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33550185000
 test master 2 - Starting Memory Read Line Multiple, at          33550365000
 test master 2 - Starting Memory Read Line Multiple, at          33550545000
 test master 2 - Starting Memory Read Line Multiple, at          33550725000
 test master 2 - Starting Memory Read Line Multiple, at          33551025000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33551565000
 test master 2 - Starting Memory Read Line Multiple, at          33551745000
 test master 2 - Starting Memory Read Line Multiple, at          33551925000
 test master 2 - Starting Memory Read Line Multiple, at          33552105000
 test master 2 - Starting Memory Read Line Multiple, at          33552405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33552945000
 test master 2 - Starting Memory Read Line Multiple, at          33553125000
 test master 2 - Starting Memory Read Line Multiple, at          33553305000
 test master 2 - Starting Memory Read Line Multiple, at          33553485000
 test master 2 - Starting Memory Read Line Multiple, at          33553785000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33554325000
 test master 2 - Starting Memory Read Line Multiple, at          33554505000
 test master 2 - Starting Memory Read Line Multiple, at          33554685000
 test master 2 - Starting Memory Read Line Multiple, at          33554865000
 test master 2 - Starting Memory Read Line Multiple, at          33555165000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          33555705000
 test master 2 - Starting Memory Read Line, at          33555885000
 test master 2 - Starting Memory Read Line, at          33556065000
 test master 2 - Starting Memory Read Line, at          33556305000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          33556665000
 test master 2 - Starting Memory Read Line, at          33556845000
 test master 2 - Starting Memory Read Line, at          33557265000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33558555000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33560415000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33563835000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33565935000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          33571545000
 test master 2 - Starting Memory Write, at          33571845000
 test master 2 - Starting Memory Write, at          33572145000
 test master 2 - Starting Memory Write, at          33572445000
 test master 2 - Starting Memory Write, at          33572745000
 test master 1 - Starting Memory Read, at          33573165000
 test master 1 - Starting Memory Read, at          33573495000
 test master 1 - Starting Memory Read, at          33574035000
 test master 1 - Starting Memory Read, at          33574365000
 test master 1 - Starting Memory Read, at          33574905000
 test master 1 - Starting Memory Read, at          33575235000
 test master 2 - Starting Memory Write, at          33576645000
 test master 2 - Starting Memory Write, at          33576945000
 test master 2 - Starting Memory Write, at          33577245000
 test master 2 - Starting Memory Write, at          33577545000
 test master 2 - Starting Memory Write, at          33577845000
 test master 1 - Starting Memory Read, at          33578265000
 test master 1 - Starting Memory Read, at          33578595000
 test master 1 - Starting Memory Read, at          33579135000
 test master 1 - Starting Memory Read, at          33579465000
 test master 1 - Starting Memory Read, at          33580005000
 test master 1 - Starting Memory Read, at          33580335000
 test master 2 - Starting Memory Write, at          33582375000
 test master 2 - Starting Memory Write, at          33583635000
 test master 2 - Starting Memory Write, at          33584895000
 test master 2 - Starting Memory Write, at          33586155000
 test master 2 - Starting Memory Write, at          33588795000
 test master 2 - Starting Memory Write, at          33590055000
 test master 2 - Starting Memory Write, at          33591315000
 test master 2 - Starting Memory Write, at          33592575000
 test master 2 - Starting Memory Write, at          33595215000
 test master 2 - Starting Memory Write, at          33597675000
 test master 2 - Starting Memory Write, at          33600135000
 test master 2 - Starting Memory Write, at          33602595000
 test master 2 - Starting Memory Write, at          33606435000
 test master 2 - Starting Memory Write, at          33609195000
 test master 2 - Starting Memory Write, at          33611955000
 test master 2 - Starting Memory Write, at          33614715000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          33619605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33619635000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33622155000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          33622455000
 test master 2 - Starting Memory Read, at          33622635000
 test master 2 - Starting Memory Read, at          33622815000
 test master 2 - Starting Memory Read, at          33623055000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33624795000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          33625215000
 test master 2 - Starting Memory Read, at          33625395000
 test master 2 - Starting Memory Read, at          33625815000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33627435000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33628005000
 test master 2 - Starting Memory Read Line Multiple, at          33628185000
 test master 2 - Starting Memory Read Line Multiple, at          33628365000
 test master 2 - Starting Memory Read Line Multiple, at          33628545000
 test master 2 - Starting Memory Read Line Multiple, at          33628845000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33630735000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33639555000
 test master 2 - Starting Memory Read Line Multiple, at          33639735000
 test master 2 - Starting Memory Read Line Multiple, at          33639915000
 test master 2 - Starting Memory Read Line Multiple, at          33640095000
 test master 2 - Starting Memory Read Line Multiple, at          33640425000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33640965000
 test master 2 - Starting Memory Read Line Multiple, at          33641145000
 test master 2 - Starting Memory Read Line Multiple, at          33641325000
 test master 2 - Starting Memory Read Line Multiple, at          33641505000
 test master 2 - Starting Memory Read Line Multiple, at          33641805000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33642345000
 test master 2 - Starting Memory Read Line Multiple, at          33642525000
 test master 2 - Starting Memory Read Line Multiple, at          33642705000
 test master 2 - Starting Memory Read Line Multiple, at          33642885000
 test master 2 - Starting Memory Read Line Multiple, at          33643185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33643725000
 test master 2 - Starting Memory Read Line Multiple, at          33643905000
 test master 2 - Starting Memory Read Line Multiple, at          33644085000
 test master 2 - Starting Memory Read Line Multiple, at          33644265000
 test master 2 - Starting Memory Read Line Multiple, at          33644565000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33645105000
 test master 2 - Starting Memory Read Line Multiple, at          33645285000
 test master 2 - Starting Memory Read Line Multiple, at          33645465000
 test master 2 - Starting Memory Read Line Multiple, at          33645645000
 test master 2 - Starting Memory Read Line Multiple, at          33645945000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33646485000
 test master 2 - Starting Memory Read Line Multiple, at          33646665000
 test master 2 - Starting Memory Read Line Multiple, at          33646845000
 test master 2 - Starting Memory Read Line Multiple, at          33647025000
 test master 2 - Starting Memory Read Line Multiple, at          33647325000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33647865000
 test master 2 - Starting Memory Read Line Multiple, at          33648045000
 test master 2 - Starting Memory Read Line Multiple, at          33648225000
 test master 2 - Starting Memory Read Line Multiple, at          33648405000
 test master 2 - Starting Memory Read Line Multiple, at          33648705000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33649245000
 test master 2 - Starting Memory Read Line Multiple, at          33649425000
 test master 2 - Starting Memory Read Line Multiple, at          33649605000
 test master 2 - Starting Memory Read Line Multiple, at          33649785000
 test master 2 - Starting Memory Read Line Multiple, at          33650085000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          33650625000
 test master 2 - Starting Memory Read Line, at          33650805000
 test master 2 - Starting Memory Read Line, at          33650985000
 test master 2 - Starting Memory Read Line, at          33651225000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          33651585000
 test master 2 - Starting Memory Read Line, at          33651765000
 test master 2 - Starting Memory Read Line, at          33652185000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33653475000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33655335000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33658755000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33660855000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          33666465000
 test master 2 - Starting Memory Write, at          33666765000
 test master 2 - Starting Memory Write, at          33667065000
 test master 2 - Starting Memory Write, at          33667365000
 test master 2 - Starting Memory Write, at          33667665000
 test master 1 - Starting Memory Read, at          33668085000
 test master 1 - Starting Memory Read, at          33668415000
 test master 1 - Starting Memory Read, at          33668955000
 test master 1 - Starting Memory Read, at          33669285000
 test master 1 - Starting Memory Read, at          33669825000
 test master 1 - Starting Memory Read, at          33670155000
 test master 2 - Starting Memory Write, at          33671565000
 test master 2 - Starting Memory Write, at          33671865000
 test master 2 - Starting Memory Write, at          33672165000
 test master 2 - Starting Memory Write, at          33672465000
 test master 2 - Starting Memory Write, at          33672765000
 test master 1 - Starting Memory Read, at          33673185000
 test master 1 - Starting Memory Read, at          33673515000
 test master 1 - Starting Memory Read, at          33674055000
 test master 1 - Starting Memory Read, at          33674385000
 test master 1 - Starting Memory Read, at          33674925000
 test master 1 - Starting Memory Read, at          33675255000
 test master 2 - Starting Memory Write, at          33677295000
 test master 2 - Starting Memory Write, at          33678555000
 test master 2 - Starting Memory Write, at          33679815000
 test master 2 - Starting Memory Write, at          33681075000
 test master 2 - Starting Memory Write, at          33683715000
 test master 2 - Starting Memory Write, at          33684975000
 test master 2 - Starting Memory Write, at          33686235000
 test master 2 - Starting Memory Write, at          33687495000
 test master 2 - Starting Memory Write, at          33690135000
 test master 2 - Starting Memory Write, at          33692595000
 test master 2 - Starting Memory Write, at          33695055000
 test master 2 - Starting Memory Write, at          33697515000
 test master 2 - Starting Memory Write, at          33701355000
 test master 2 - Starting Memory Write, at          33704115000
 test master 2 - Starting Memory Write, at          33706875000
 test master 2 - Starting Memory Write, at          33709635000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          33714525000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33714555000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33717075000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          33717375000
 test master 2 - Starting Memory Read, at          33717555000
 test master 2 - Starting Memory Read, at          33717735000
 test master 2 - Starting Memory Read, at          33717975000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33719715000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          33720135000
 test master 2 - Starting Memory Read, at          33720315000
 test master 2 - Starting Memory Read, at          33720735000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33722355000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33722925000
 test master 2 - Starting Memory Read Line Multiple, at          33723105000
 test master 2 - Starting Memory Read Line Multiple, at          33723285000
 test master 2 - Starting Memory Read Line Multiple, at          33723465000
 test master 2 - Starting Memory Read Line Multiple, at          33723765000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33725655000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33734475000
 test master 2 - Starting Memory Read Line Multiple, at          33734655000
 test master 2 - Starting Memory Read Line Multiple, at          33734835000
 test master 2 - Starting Memory Read Line Multiple, at          33735015000
 test master 2 - Starting Memory Read Line Multiple, at          33735345000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33735885000
 test master 2 - Starting Memory Read Line Multiple, at          33736065000
 test master 2 - Starting Memory Read Line Multiple, at          33736245000
 test master 2 - Starting Memory Read Line Multiple, at          33736425000
 test master 2 - Starting Memory Read Line Multiple, at          33736725000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33737265000
 test master 2 - Starting Memory Read Line Multiple, at          33737445000
 test master 2 - Starting Memory Read Line Multiple, at          33737625000
 test master 2 - Starting Memory Read Line Multiple, at          33737805000
 test master 2 - Starting Memory Read Line Multiple, at          33738105000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33738645000
 test master 2 - Starting Memory Read Line Multiple, at          33738825000
 test master 2 - Starting Memory Read Line Multiple, at          33739005000
 test master 2 - Starting Memory Read Line Multiple, at          33739185000
 test master 2 - Starting Memory Read Line Multiple, at          33739485000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33740025000
 test master 2 - Starting Memory Read Line Multiple, at          33740205000
 test master 2 - Starting Memory Read Line Multiple, at          33740385000
 test master 2 - Starting Memory Read Line Multiple, at          33740565000
 test master 2 - Starting Memory Read Line Multiple, at          33740865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33741405000
 test master 2 - Starting Memory Read Line Multiple, at          33741585000
 test master 2 - Starting Memory Read Line Multiple, at          33741765000
 test master 2 - Starting Memory Read Line Multiple, at          33741945000
 test master 2 - Starting Memory Read Line Multiple, at          33742245000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33742785000
 test master 2 - Starting Memory Read Line Multiple, at          33742965000
 test master 2 - Starting Memory Read Line Multiple, at          33743145000
 test master 2 - Starting Memory Read Line Multiple, at          33743325000
 test master 2 - Starting Memory Read Line Multiple, at          33743625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33744165000
 test master 2 - Starting Memory Read Line Multiple, at          33744345000
 test master 2 - Starting Memory Read Line Multiple, at          33744525000
 test master 2 - Starting Memory Read Line Multiple, at          33744705000
 test master 2 - Starting Memory Read Line Multiple, at          33745005000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          33745545000
 test master 2 - Starting Memory Read Line, at          33745725000
 test master 2 - Starting Memory Read Line, at          33745905000
 test master 2 - Starting Memory Read Line, at          33746145000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          33746505000
 test master 2 - Starting Memory Read Line, at          33746685000
 test master 2 - Starting Memory Read Line, at          33747105000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33748395000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33750255000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33753675000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33755775000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          33761385000
 test master 2 - Starting Memory Write, at          33761685000
 test master 2 - Starting Memory Write, at          33761985000
 test master 2 - Starting Memory Write, at          33762285000
 test master 2 - Starting Memory Write, at          33762585000
 test master 1 - Starting Memory Read, at          33763005000
 test master 1 - Starting Memory Read, at          33763335000
 test master 1 - Starting Memory Read, at          33763875000
 test master 1 - Starting Memory Read, at          33764205000
 test master 1 - Starting Memory Read, at          33764745000
 test master 1 - Starting Memory Read, at          33765075000
 test master 2 - Starting Memory Write, at          33766485000
 test master 2 - Starting Memory Write, at          33766785000
 test master 2 - Starting Memory Write, at          33767085000
 test master 2 - Starting Memory Write, at          33767385000
 test master 2 - Starting Memory Write, at          33767685000
 test master 1 - Starting Memory Read, at          33768105000
 test master 1 - Starting Memory Read, at          33768435000
 test master 1 - Starting Memory Read, at          33768975000
 test master 1 - Starting Memory Read, at          33769305000
 test master 1 - Starting Memory Read, at          33769845000
 test master 1 - Starting Memory Read, at          33770175000
 test master 2 - Starting Memory Write, at          33772215000
 test master 2 - Starting Memory Write, at          33773475000
 test master 2 - Starting Memory Write, at          33774735000
 test master 2 - Starting Memory Write, at          33775995000
 test master 2 - Starting Memory Write, at          33778635000
 test master 2 - Starting Memory Write, at          33779895000
 test master 2 - Starting Memory Write, at          33781155000
 test master 2 - Starting Memory Write, at          33782415000
 test master 2 - Starting Memory Write, at          33785055000
 test master 2 - Starting Memory Write, at          33787515000
 test master 2 - Starting Memory Write, at          33789975000
 test master 2 - Starting Memory Write, at          33792435000
 test master 2 - Starting Memory Write, at          33796275000
 test master 2 - Starting Memory Write, at          33799035000
 test master 2 - Starting Memory Write, at          33801795000
 test master 2 - Starting Memory Write, at          33804555000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          33809445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33809475000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33811995000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          33812295000
 test master 2 - Starting Memory Read, at          33812475000
 test master 2 - Starting Memory Read, at          33812655000
 test master 2 - Starting Memory Read, at          33812895000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33814635000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          33815055000
 test master 2 - Starting Memory Read, at          33815235000
 test master 2 - Starting Memory Read, at          33815655000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33817275000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33817845000
 test master 2 - Starting Memory Read Line Multiple, at          33818025000
 test master 2 - Starting Memory Read Line Multiple, at          33818205000
 test master 2 - Starting Memory Read Line Multiple, at          33818385000
 test master 2 - Starting Memory Read Line Multiple, at          33818685000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33820575000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33829395000
 test master 2 - Starting Memory Read Line Multiple, at          33829575000
 test master 2 - Starting Memory Read Line Multiple, at          33829755000
 test master 2 - Starting Memory Read Line Multiple, at          33829935000
 test master 2 - Starting Memory Read Line Multiple, at          33830265000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33830805000
 test master 2 - Starting Memory Read Line Multiple, at          33830985000
 test master 2 - Starting Memory Read Line Multiple, at          33831165000
 test master 2 - Starting Memory Read Line Multiple, at          33831345000
 test master 2 - Starting Memory Read Line Multiple, at          33831645000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33832185000
 test master 2 - Starting Memory Read Line Multiple, at          33832365000
 test master 2 - Starting Memory Read Line Multiple, at          33832545000
 test master 2 - Starting Memory Read Line Multiple, at          33832725000
 test master 2 - Starting Memory Read Line Multiple, at          33833025000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33833565000
 test master 2 - Starting Memory Read Line Multiple, at          33833745000
 test master 2 - Starting Memory Read Line Multiple, at          33833925000
 test master 2 - Starting Memory Read Line Multiple, at          33834105000
 test master 2 - Starting Memory Read Line Multiple, at          33834405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33834945000
 test master 2 - Starting Memory Read Line Multiple, at          33835125000
 test master 2 - Starting Memory Read Line Multiple, at          33835305000
 test master 2 - Starting Memory Read Line Multiple, at          33835485000
 test master 2 - Starting Memory Read Line Multiple, at          33835785000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33836325000
 test master 2 - Starting Memory Read Line Multiple, at          33836505000
 test master 2 - Starting Memory Read Line Multiple, at          33836685000
 test master 2 - Starting Memory Read Line Multiple, at          33836865000
 test master 2 - Starting Memory Read Line Multiple, at          33837165000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33837705000
 test master 2 - Starting Memory Read Line Multiple, at          33837885000
 test master 2 - Starting Memory Read Line Multiple, at          33838065000
 test master 2 - Starting Memory Read Line Multiple, at          33838245000
 test master 2 - Starting Memory Read Line Multiple, at          33838545000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          33839085000
 test master 2 - Starting Memory Read Line Multiple, at          33839265000
 test master 2 - Starting Memory Read Line Multiple, at          33839445000
 test master 2 - Starting Memory Read Line Multiple, at          33839625000
 test master 2 - Starting Memory Read Line Multiple, at          33839925000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          33840465000
 test master 2 - Starting Memory Read Line, at          33840645000
 test master 2 - Starting Memory Read Line, at          33840825000
 test master 2 - Starting Memory Read Line, at          33841065000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          33841425000
 test master 2 - Starting Memory Read Line, at          33841605000
 test master 2 - Starting Memory Read Line, at          33842025000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33843315000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33845175000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33848595000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          33850695000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          33856305000
 test master 2 - Starting Memory Write, at          33856605000
 test master 2 - Starting Memory Write, at          33856905000
 test master 2 - Starting Memory Write, at          33857205000
 test master 2 - Starting Memory Write, at          33857505000
 test master 1 - Starting Memory Read, at          33857925000
 test master 1 - Starting Memory Read, at          33858255000
 test master 1 - Starting Memory Read, at          33858795000
 test master 1 - Starting Memory Read, at          33859125000
 test master 1 - Starting Memory Read, at          33859665000
 test master 1 - Starting Memory Read, at          33859995000
 test master 2 - Starting Memory Write, at          33861405000
 test master 2 - Starting Memory Write, at          33861705000
 test master 2 - Starting Memory Write, at          33862005000
 test master 2 - Starting Memory Write, at          33862305000
 test master 2 - Starting Memory Write, at          33862605000
 test master 1 - Starting Memory Read, at          33863025000
 test master 1 - Starting Memory Read, at          33863355000
 test master 1 - Starting Memory Read, at          33863895000
 test master 1 - Starting Memory Read, at          33864225000
 test master 1 - Starting Memory Read, at          33864765000
 test master 1 - Starting Memory Read, at          33865095000
 test master 2 - Starting Memory Write, at          33867135000
 test master 2 - Starting Memory Write, at          33868395000
 test master 2 - Starting Memory Write, at          33869655000
 test master 2 - Starting Memory Write, at          33870915000
 test master 2 - Starting Memory Write, at          33873555000
 test master 2 - Starting Memory Write, at          33874815000
 test master 2 - Starting Memory Write, at          33876075000
 test master 2 - Starting Memory Write, at          33877335000
 test master 2 - Starting Memory Write, at          33879975000
 test master 2 - Starting Memory Write, at          33882435000
 test master 2 - Starting Memory Write, at          33884895000
 test master 2 - Starting Memory Write, at          33887355000
 test master 2 - Starting Memory Write, at          33891195000
 test master 2 - Starting Memory Write, at          33893955000
 test master 2 - Starting Memory Write, at          33896715000
 test master 2 - Starting Memory Write, at          33899475000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          33904365000
*** monitor - CBE Bus Changed when TRDY Desserted, at          33904395000
 test master 1 - Starting Memory Read, at          33906915000
 test master 1 - Starting Memory Read, at          33907275000
 test master 1 - Starting Memory Read, at          33908685000
 test master 1 - Starting Memory Read, at          33909045000
 test master 1 - Starting Memory Read Line, at          33910485000
 test master 1 - Starting Memory Read Line, at          33910845000
 test master 1 - Starting Memory Read Line, at          33912285000
 test master 1 - Starting Memory Read Line, at          33912705000
 test master 1 - Starting Memory Read Line, at          33914205000
 test master 1 - Starting Memory Read Line, at          33914805000
 test master 1 - Starting Memory Read Line, at          33916425000
 test master 1 - Starting Memory Read Line, at          33917025000
 test master 1 - Starting Memory Read Line Multiple, at          33918645000
 test master 1 - Starting Memory Read Line Multiple, at          33919485000
 test master 1 - Starting Memory Read Line Multiple, at          33921285000
 test master 1 - Starting Memory Read Line Multiple, at          33922125000
 test master 1 - Starting Memory Read Line, at          33923925000
 test master 1 - Starting Memory Read Line, at          33924525000
 test master 1 - Starting Memory Read, at          33927375000
 test master 1 - Starting Memory Read, at          33927735000
 test target 1 - Starting Config Write, at          33931605000
 test master 1 - Starting Memory Write, at          33932115000
 test master 1 - Starting Memory Write, at          33935895000
 test master 1 - Starting Memory Write, at          33940935000
 test master 1 - Starting Memory Write, at          33944475000
 test master 1 - Starting Memory Write, at          33949395000
 test master 1 - Starting Memory Read Line, at          33953175000
 test master 1 - Starting Memory Write, at          33958635000
 test master 1 - Starting Memory Read Line, at          33962415000
 test target 1 - Starting Config Write, at          33969945000
 test master 1 - Starting Memory Write, at          33970455000
 test master 1 - Starting Memory Write, at          33970575000
 test master 1 - Starting Memory Write, at          33970875000
 test master 1 - Starting Memory Read, at          33970995000
 test master 1 - Starting Memory Write, at          33971355000
 test master 1 - Starting Memory Read, at          33971475000
 test master 1 - Starting Memory Write, at          33973455000
 test master 1 - Starting Memory Write, at          33982275000
 test master 2 - Starting Memory Read Line, at          33991215000
 test master 2 - Starting Memory Read Line, at          33991785000
 test master 2 - Starting Memory Read Line, at          33992175000
 test master 2 - Starting Memory Read Line, at          33992745000
 test master 1 - Starting Memory Write, at          33993225000
 test master 1 - Starting Memory Write, at          33993525000
 test master 1 - Starting Memory Write, at          33993825000
 test master 2 - Starting Memory Read Line, at          33994245000
 test master 2 - Starting Memory Read Line, at          33994605000
 test master 2 - Starting Memory Read Line, at          33994845000
 test master 2 - Starting Memory Read Line, at          33995205000
 test master 2 - Starting Memory Read Line Multiple, at          33995475000
 test master 2 - Starting Memory Read Line Multiple, at          33995835000
 test master 1 - Starting Memory Write, at          33998055000
 test master 1 - Starting Memory Write, at          33998355000
 test master 2 - Starting Memory Read, at          33998775000
 test master 2 - Starting Memory Read, at          33999135000
 test master 2 - Starting Memory Read, at          33999375000
 test master 2 - Starting Memory Read, at          33999735000
 test master 1 - Starting Memory Write, at          34001655000
 test master 1 - Starting Memory Read, at          34001835000
 test master 1 - Starting Memory Write, at          34002015000
 test master 1 - Starting Memory Read, at          34002225000
 test master 1 - Starting Memory Write, at          34002435000
 test master 1 - Starting Memory Read, at          34002615000
 test master 1 - Starting Memory Read, at          34002825000
 test master 1 - Starting Memory Write, at          34003035000
 test master 1 - Starting Memory Write, at          34003215000
 test master 1 - Starting Memory Read, at          34003395000
 test master 1 - Starting Memory Write, at          34003575000
 test master 1 - Starting Memory Write, at          34003785000
 test master 1 - Starting Memory Write, at          34003995000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          34009305000
 test target 1 - Starting Memory Write, at          34009515000
 test master 1 - Starting Memory Write, at          34009695000
 test target 1 - Starting Memory Write, at          34009875000
 test target 1 - Starting Memory Write, at          34010085000
 test target 1 - Starting Memory Write, at          34010295000
 test master 1 - Starting Memory Write, at          34010595000
 test target 1 - Starting Memory Write, at          34011165000
 test target 1 - Starting Memory Write, at          34011795000
 test target 1 - Starting Memory Write, at          34012035000
 test master 1 - Starting Memory Write, at          34012245000
 test target 1 - Starting Memory Write, at          34012545000
 test target 1 - Starting Memory Write, at          34012785000
 test target 1 - Starting Memory Write, at          34013025000
 test target 1 - Starting Memory Write, at          34013265000
 test master 1 - Starting Memory Write, at          34013685000
 test target 1 - Starting Memory Write, at          34014525000
 test target 1 - Starting Memory Write, at          34015395000
 test target 1 - Starting Memory Write, at          34015605000
 test master 1 - Starting Memory Read, at          34015785000
 test target 1 - Starting Memory Write, at          34015965000
 test master 1 - Starting Memory Read, at          34016145000
 test target 1 - Starting Memory Write, at          34016325000
 test master 1 - Starting Memory Read, at          34016505000
 test target 1 - Starting Memory Write, at          34016685000
 test master 1 - Starting Memory Read, at          34016865000
 test target 1 - Starting Memory Write, at          34017045000
 test master 1 - Starting Memory Read, at          34017225000
 test target 1 - Starting Memory Write, at          34017405000
 test master 1 - Starting Memory Write, at          34017585000
 test target 1 - Starting Memory Write, at          34017765000
 test target 1 - Starting Memory Write, at          34017975000
 test target 1 - Starting Memory Write, at          34018185000
 test target 1 - Starting Memory Read, at          34018455000
 test master 1 - Starting Memory Write, at          34018755000
 test master 1 - Starting Memory Read, at          34018995000
 test target 1 - Starting Memory Write, at          34019505000
 test master 1 - Starting Memory Write, at          34019895000
 test target 1 - Starting Memory Read, at          34020345000
 test target 1 - Starting Memory Write, at          34021155000
 test master 1 - Starting Memory Read, at          34021455000
 test master 1 - Starting Memory Write, at          34021875000
 test master 1 - Starting Memory Write, at          34022235000
 test master 1 - Starting Memory Read, at          34022535000
 
PCI transaction ordering tests finished!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          34025505000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          34026675000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          34055085000
 test target 1 - Starting Config Write, at          34056225000
 test target 1 - Starting Config Write, at          34057335000
 test target 2 - Starting Config Write, at          34058445000
 test target 2 - Starting Config Write, at          34059585000
 test target 2 - Starting Config Write, at          34060695000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          34063155000
 test target 1 - Starting Memory Read, at          34063395000
 test target 1 - Starting Memory Write, at          34064175000
 test target 1 - Starting Memory Read, at          34064415000
 test target 1 - Starting Memory Write, at          34065855000
 test target 1 - Starting Memory Read, at          34066695000
 test target 1 - Starting Memory Read, at          34067235000
 test target 1 - Starting Memory Read, at          34067925000
 test target 1 - Starting Memory Read, at          34068435000
 test target 1 - Starting Memory Read, at          34069305000
 test target 1 - Starting Memory Read, at          34070385000
 test target 1 - Starting Memory Read, at          34071495000
 test target 1 - Starting Memory Read, at          34072575000
 test target 1 - Starting Memory Read, at          34073685000
 test target 1 - Starting Memory Read, at          34075125000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          34082985000
 test target 1 - Starting Memory Read, at          34083225000
 test target 1 - Starting Memory Write, at          34084035000
 test target 1 - Starting Memory Read, at          34084275000
 test target 1 - Starting Memory Write, at          34085685000
 test target 1 - Starting Memory Read, at          34086525000
 test target 1 - Starting Memory Read, at          34087035000
 test target 1 - Starting Memory Read, at          34087575000
 test target 1 - Starting Memory Read, at          34088265000
 test target 1 - Starting Memory Read, at          34089135000
 test target 1 - Starting Memory Read, at          34090215000
 test target 1 - Starting Memory Read, at          34091325000
 test target 1 - Starting Memory Read, at          34092405000
 test target 1 - Starting Memory Read, at          34093515000
 test target 1 - Starting Memory Read, at          34094985000
 test target 1 - Starting Memory Write, at          34102815000
 test target 1 - Starting Memory Read, at          34103055000
 test target 1 - Starting Memory Write, at          34103835000
 test target 1 - Starting Memory Read, at          34104075000
 test target 1 - Starting Memory Write, at          34105515000
 test target 1 - Starting Memory Read, at          34106355000
 test target 1 - Starting Memory Read, at          34106895000
 test target 1 - Starting Memory Read, at          34107585000
 test target 1 - Starting Memory Read, at          34108095000
 test target 1 - Starting Memory Read, at          34108965000
 test target 1 - Starting Memory Read, at          34110045000
 test target 1 - Starting Memory Read, at          34111155000
 test target 1 - Starting Memory Read, at          34112235000
 test target 1 - Starting Memory Read, at          34113345000
 test target 1 - Starting Memory Read, at          34114785000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          34130625000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          34138455000
 test target 1 - Starting Memory Write, at          34139535000
 test target 1 - Starting Memory Read, at          34139775000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          34141125000
 test target 1 - Starting Config Write, at          34143465000
 test target 1 - Starting Memory Read, at          34144275000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          34146135000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          34148715000
 test target 1 - Starting Memory Write, at          34150185000
 test target 1 - Starting Memory Write, at          34150425000
 test target 1 - Starting Memory Read, at          34150605000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          34153515000
 test target 1 - Starting Memory Write, at          34157295000
 test target 1 - Starting Memory Write, at          34157715000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          34162395000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          34164795000
 test target 1 - Starting Memory Read, at          34166385000
 test target 1 - Starting Memory Read, at          34167345000
 test target 1 - Starting Memory Read, at          34169205000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          34176555000
 test target 2 - Starting Config Write, at          34177665000
 test target 1 - Starting Memory Write, at          34178475000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          34178565000
 test target 1 - Starting Memory Write, at          34179795000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          34179885000
 test target 1 - Starting Memory Write, at          34181115000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          34182735000
 test target 1 - Starting Memory Read, at          34185405000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          34185525000
 test target 1 - Starting Memory Read, at          34188255000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          34190385000
 test master 2 - Starting Memory Write, at          34190385000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          34190445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34191375000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34191405000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34191705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34191735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34192815000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34192845000
 test target 1 - Starting Memory Write, at          34194975000
 test master 2 - Starting Memory Write, at          34194975000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34196955000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34196985000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34198995000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34199025000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34201035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34201065000
 test target 1 - Starting Memory Write, at          34203525000
 test master 2 - Starting Memory Write, at          34203525000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          34203585000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34205475000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34205505000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34205805000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34205835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34206915000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34206945000
 test target 1 - Starting Memory Write, at          34208295000
 test master 2 - Starting Memory Write, at          34208295000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          34211925000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          34213875000
 test master 1 - Starting Memory Read, at          34214205000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          34214355000
 test target 1 - Starting Config Write, at          34217535000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          34220595000
 test target 1 - Starting Memory Write, at          34220715000
 test target 1 - Starting Memory Write, at          34220835000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          34221375000
 test target 1 - Starting Memory Write, at          34221525000
 test target 1 - Starting Memory Write, at          34221675000
 test target 1 - Starting Memory Write, at          34222215000
 test target 1 - Starting Memory Write, at          34222365000
 test target 1 - Starting Memory Write, at          34222875000
 test target 1 - Starting Memory Write, at          34223535000
 test target 1 - Starting Memory Write, at          34223685000
 test target 1 - Starting Memory Write, at          34224375000
 test target 1 - Starting Memory Write, at          34224555000
 test target 1 - Starting Memory Write, at          34225215000
 test target 1 - Starting Memory Write, at          34233075000
 test target 1 - Starting Memory Write, at          34233225000
 test target 1 - Starting Memory Write, at          34233375000
 test target 1 - Starting Memory Write, at          34233555000
 test target 1 - Starting Memory Write, at          34233735000
 test target 1 - Starting Memory Read, at          34235625000
 test target 1 - Starting Memory Read, at          34236675000
 test target 1 - Starting Memory Read, at          34237725000
 test target 1 - Starting Memory Read, at          34238775000
 test target 1 - Starting Memory Read, at          34239855000
 test target 1 - Starting Memory Read, at          34240905000
 test target 1 - Starting Memory Read, at          34241955000
 test target 1 - Starting Memory Read, at          34243035000
 test target 1 - Starting Memory Read, at          34244085000
 test target 1 - Starting Memory Read, at          34245135000
 test target 1 - Starting Memory Read, at          34246215000
 test target 1 - Starting Memory Read, at          34247265000
 test target 1 - Starting Memory Read, at          34248315000
 test target 1 - Starting Memory Read, at          34249395000
 test target 1 - Starting Memory Read, at          34250445000
 test target 1 - Starting Memory Read, at          34251495000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          34252365000
 test target 1 - Starting Memory Read, at          34252515000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          34255215000
 test target 1 - Starting Memory Read, at          34255845000
 test target 1 - Starting Memory Read, at          34256655000
 test target 1 - Starting Memory Read, at          34257285000
 test target 1 - Starting Memory Read, at          34258005000
 test target 1 - Starting Memory Read, at          34258875000
 test target 1 - Starting Memory Read, at          34260045000
 test target 1 - Starting Memory Read, at          34261125000
 test target 1 - Starting Memory Read, at          34262235000
 test target 1 - Starting Memory Read, at          34264995000
 test target 1 - Starting Memory Read, at          34266735000
 test target 1 - Starting Memory Read, at          34267605000
 test target 1 - Starting Memory Read, at          34268475000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          34269975000
 test master 1 - Starting Memory Write, at          34270185000
 test target 1 - Starting Memory Write, at          34270185000
 test target 1 - Starting Memory Write, at          34270335000
 test target 1 - Starting Memory Read, at          34270515000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          34272165000
 test master 1 - Starting Memory Write, at          34272375000
 test target 1 - Starting Memory Write, at          34272375000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          34277985000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          34279155000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          34307565000
 test target 1 - Starting Config Write, at          34308705000
 test target 1 - Starting Config Write, at          34309815000
 test target 2 - Starting Config Write, at          34310925000
 test target 2 - Starting Config Write, at          34312065000
 test target 2 - Starting Config Write, at          34313175000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          34315635000
 test target 1 - Starting Memory Read, at          34315875000
 test target 1 - Starting Memory Write, at          34316655000
 test target 1 - Starting Memory Read, at          34316895000
 test target 1 - Starting Memory Write, at          34318335000
 test target 1 - Starting Memory Read, at          34319205000
 test target 1 - Starting Memory Read, at          34319715000
 test target 1 - Starting Memory Read, at          34320255000
 test target 1 - Starting Memory Read, at          34320945000
 test target 1 - Starting Memory Read, at          34321815000
 test target 1 - Starting Memory Read, at          34322895000
 test target 1 - Starting Memory Read, at          34324005000
 test target 1 - Starting Memory Read, at          34325085000
 test target 1 - Starting Memory Read, at          34326195000
 test target 1 - Starting Memory Read, at          34327665000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          34335495000
 test target 1 - Starting Memory Read, at          34335735000
 test target 1 - Starting Memory Write, at          34336515000
 test target 1 - Starting Memory Read, at          34336755000
 test target 1 - Starting Memory Write, at          34338195000
 test target 1 - Starting Memory Read, at          34339065000
 test target 1 - Starting Memory Read, at          34339575000
 test target 1 - Starting Memory Read, at          34340115000
 test target 1 - Starting Memory Read, at          34340805000
 test target 1 - Starting Memory Read, at          34341675000
 test target 1 - Starting Memory Read, at          34342755000
 test target 1 - Starting Memory Read, at          34343865000
 test target 1 - Starting Memory Read, at          34344945000
 test target 1 - Starting Memory Read, at          34346055000
 test target 1 - Starting Memory Read, at          34347525000
 test target 1 - Starting Memory Write, at          34355355000
 test target 1 - Starting Memory Read, at          34355595000
 test target 1 - Starting Memory Write, at          34356375000
 test target 1 - Starting Memory Read, at          34356615000
 test target 1 - Starting Memory Write, at          34358055000
 test target 1 - Starting Memory Read, at          34358925000
 test target 1 - Starting Memory Read, at          34359435000
 test target 1 - Starting Memory Read, at          34359975000
 test target 1 - Starting Memory Read, at          34360665000
 test target 1 - Starting Memory Read, at          34361535000
 test target 1 - Starting Memory Read, at          34362615000
 test target 1 - Starting Memory Read, at          34363725000
 test target 1 - Starting Memory Read, at          34364805000
 test target 1 - Starting Memory Read, at          34365915000
 test target 1 - Starting Memory Read, at          34367385000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          34383195000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          34390995000
 test target 1 - Starting Memory Write, at          34392075000
 test target 1 - Starting Memory Read, at          34392345000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          34393665000
 test target 1 - Starting Config Write, at          34396005000
 test target 1 - Starting Memory Read, at          34396815000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          34398675000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          34401255000
 test target 1 - Starting Memory Write, at          34402725000
 test target 1 - Starting Memory Write, at          34402995000
 test target 1 - Starting Memory Read, at          34403205000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          34406055000
 test target 1 - Starting Memory Write, at          34409835000
 test target 1 - Starting Memory Write, at          34410255000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          34414935000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          34417335000
 test target 1 - Starting Memory Read, at          34418925000
 test target 1 - Starting Memory Read, at          34419885000
 test target 1 - Starting Memory Read, at          34421745000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          34429095000
 test target 2 - Starting Config Write, at          34430205000
 test target 1 - Starting Memory Write, at          34431015000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          34431135000
 test target 1 - Starting Memory Write, at          34432395000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          34432515000
 test target 1 - Starting Memory Write, at          34433775000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          34435455000
 test target 1 - Starting Memory Read, at          34438125000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          34438245000
 test target 1 - Starting Memory Read, at          34440975000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          34443105000
 test master 2 - Starting Memory Write, at          34443105000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          34443165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34444155000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34444185000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34444485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34444515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34445595000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34445625000
 test target 1 - Starting Memory Write, at          34447755000
 test master 2 - Starting Memory Write, at          34447755000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34449795000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34449825000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34451835000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34451865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34453875000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34453905000
 test target 1 - Starting Memory Write, at          34456365000
 test master 2 - Starting Memory Write, at          34456365000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          34456425000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34458375000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34458405000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34458705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34458735000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34459815000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34459845000
 test target 1 - Starting Memory Write, at          34461195000
 test master 2 - Starting Memory Write, at          34461195000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          34464825000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          34466775000
 test master 1 - Starting Memory Read, at          34467105000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          34467255000
 test target 1 - Starting Config Write, at          34470435000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          34473495000
 test target 1 - Starting Memory Write, at          34473645000
 test target 1 - Starting Memory Write, at          34473795000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          34474335000
 test target 1 - Starting Memory Write, at          34474515000
 test target 1 - Starting Memory Write, at          34474695000
 test target 1 - Starting Memory Write, at          34475235000
 test target 1 - Starting Memory Write, at          34475415000
 test target 1 - Starting Memory Write, at          34475955000
 test target 1 - Starting Memory Write, at          34476675000
 test target 1 - Starting Memory Write, at          34476855000
 test target 1 - Starting Memory Write, at          34477575000
 test target 1 - Starting Memory Write, at          34477785000
 test target 1 - Starting Memory Write, at          34478475000
 test target 1 - Starting Memory Write, at          34486365000
 test target 1 - Starting Memory Write, at          34486545000
 test target 1 - Starting Memory Write, at          34486725000
 test target 1 - Starting Memory Write, at          34486935000
 test target 1 - Starting Memory Write, at          34487145000
 test target 1 - Starting Memory Read, at          34489065000
 test target 1 - Starting Memory Read, at          34490115000
 test target 1 - Starting Memory Read, at          34491195000
 test target 1 - Starting Memory Read, at          34492245000
 test target 1 - Starting Memory Read, at          34493295000
 test target 1 - Starting Memory Read, at          34494375000
 test target 1 - Starting Memory Read, at          34495425000
 test target 1 - Starting Memory Read, at          34496475000
 test target 1 - Starting Memory Read, at          34497555000
 test target 1 - Starting Memory Read, at          34498605000
 test target 1 - Starting Memory Read, at          34499655000
 test target 1 - Starting Memory Read, at          34500735000
 test target 1 - Starting Memory Read, at          34501785000
 test target 1 - Starting Memory Read, at          34502835000
 test target 1 - Starting Memory Read, at          34503915000
 test target 1 - Starting Memory Read, at          34504965000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          34505805000
 test target 1 - Starting Memory Read, at          34505955000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          34508415000
 test target 1 - Starting Memory Read, at          34509075000
 test target 1 - Starting Memory Read, at          34509855000
 test target 1 - Starting Memory Read, at          34510485000
 test target 1 - Starting Memory Read, at          34511205000
 test target 1 - Starting Memory Read, at          34512075000
 test target 1 - Starting Memory Read, at          34513245000
 test target 1 - Starting Memory Read, at          34514325000
 test target 1 - Starting Memory Read, at          34515435000
 test target 1 - Starting Memory Read, at          34518195000
 test target 1 - Starting Memory Read, at          34519935000
 test target 1 - Starting Memory Read, at          34520805000
 test target 1 - Starting Memory Read, at          34521675000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          34523175000
 test master 1 - Starting Memory Write, at          34523385000
 test target 1 - Starting Memory Write, at          34523385000
 test target 1 - Starting Memory Write, at          34523535000
 test target 1 - Starting Memory Read, at          34523775000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          34525365000
 test master 1 - Starting Memory Write, at          34525575000
 test target 1 - Starting Memory Write, at          34525575000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          34531185000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          34532355000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          34560765000
 test target 1 - Starting Config Write, at          34561905000
 test target 1 - Starting Config Write, at          34563015000
 test target 2 - Starting Config Write, at          34564125000
 test target 2 - Starting Config Write, at          34565265000
 test target 2 - Starting Config Write, at          34566375000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          34568835000
 test target 1 - Starting Memory Read, at          34569075000
 test target 1 - Starting Memory Write, at          34569855000
 test target 1 - Starting Memory Read, at          34570095000
 test target 1 - Starting Memory Write, at          34571535000
 test target 1 - Starting Memory Read, at          34572435000
 test target 1 - Starting Memory Read, at          34573155000
 test target 1 - Starting Memory Read, at          34573845000
 test target 1 - Starting Memory Read, at          34574535000
 test target 1 - Starting Memory Read, at          34575585000
 test target 1 - Starting Memory Read, at          34576665000
 test target 1 - Starting Memory Read, at          34577775000
 test target 1 - Starting Memory Read, at          34578855000
 test target 1 - Starting Memory Read, at          34579965000
 test target 1 - Starting Memory Read, at          34581405000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          34589265000
 test target 1 - Starting Memory Read, at          34589505000
 test target 1 - Starting Memory Write, at          34590315000
 test target 1 - Starting Memory Read, at          34590555000
 test target 1 - Starting Memory Write, at          34591965000
 test target 1 - Starting Memory Read, at          34592865000
 test target 1 - Starting Memory Read, at          34593555000
 test target 1 - Starting Memory Read, at          34594275000
 test target 1 - Starting Memory Read, at          34594965000
 test target 1 - Starting Memory Read, at          34596015000
 test target 1 - Starting Memory Read, at          34597095000
 test target 1 - Starting Memory Read, at          34598205000
 test target 1 - Starting Memory Read, at          34599285000
 test target 1 - Starting Memory Read, at          34600395000
 test target 1 - Starting Memory Read, at          34601865000
 test target 1 - Starting Memory Write, at          34609695000
 test target 1 - Starting Memory Read, at          34609935000
 test target 1 - Starting Memory Write, at          34610715000
 test target 1 - Starting Memory Read, at          34610955000
 test target 1 - Starting Memory Write, at          34612395000
 test target 1 - Starting Memory Read, at          34613295000
 test target 1 - Starting Memory Read, at          34614015000
 test target 1 - Starting Memory Read, at          34614705000
 test target 1 - Starting Memory Read, at          34615395000
 test target 1 - Starting Memory Read, at          34616445000
 test target 1 - Starting Memory Read, at          34617525000
 test target 1 - Starting Memory Read, at          34618635000
 test target 1 - Starting Memory Read, at          34619715000
 test target 1 - Starting Memory Read, at          34620825000
 test target 1 - Starting Memory Read, at          34622265000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          34638105000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          34645935000
 test target 1 - Starting Memory Write, at          34647015000
 test target 1 - Starting Memory Read, at          34647315000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          34648605000
 test target 1 - Starting Config Write, at          34650945000
 test target 1 - Starting Memory Read, at          34651755000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          34653615000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          34656195000
 test target 1 - Starting Memory Write, at          34657665000
 test target 1 - Starting Memory Write, at          34657965000
 test target 1 - Starting Memory Read, at          34658205000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          34661235000
 test target 1 - Starting Memory Write, at          34665075000
 test target 1 - Starting Memory Write, at          34665495000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          34670235000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          34672635000
 test target 1 - Starting Memory Read, at          34674225000
 test target 1 - Starting Memory Read, at          34675185000
 test target 1 - Starting Memory Read, at          34677045000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          34684395000
 test target 2 - Starting Config Write, at          34685505000
 test target 1 - Starting Memory Write, at          34686315000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          34686465000
 test target 1 - Starting Memory Write, at          34687695000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          34687845000
 test target 1 - Starting Memory Write, at          34689075000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          34690755000
 test target 1 - Starting Memory Read, at          34693425000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          34693575000
 test target 1 - Starting Memory Read, at          34696275000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          34698405000
 test master 2 - Starting Memory Write, at          34698405000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          34698465000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34699455000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34699485000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34699785000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34699815000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34700895000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34700925000
 test target 1 - Starting Memory Write, at          34703055000
 test master 2 - Starting Memory Write, at          34703055000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34705095000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34705125000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34707135000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34707165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34709175000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34709205000
 test target 1 - Starting Memory Write, at          34711665000
 test master 2 - Starting Memory Write, at          34711665000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          34711725000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34713675000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34713705000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34714005000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34714035000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34715115000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34715145000
 test target 1 - Starting Memory Write, at          34716495000
 test master 2 - Starting Memory Write, at          34716495000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          34720185000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          34722135000
 test master 1 - Starting Memory Read, at          34722465000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          34722615000
 test target 1 - Starting Config Write, at          34725795000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          34728855000
 test target 1 - Starting Memory Write, at          34729035000
 test target 1 - Starting Memory Write, at          34729215000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          34729815000
 test target 1 - Starting Memory Write, at          34730025000
 test target 1 - Starting Memory Write, at          34730235000
 test target 1 - Starting Memory Write, at          34730835000
 test target 1 - Starting Memory Write, at          34731045000
 test target 1 - Starting Memory Write, at          34731615000
 test target 1 - Starting Memory Write, at          34732335000
 test target 1 - Starting Memory Write, at          34732545000
 test target 1 - Starting Memory Write, at          34733295000
 test target 1 - Starting Memory Write, at          34733535000
 test target 1 - Starting Memory Write, at          34734255000
 test target 1 - Starting Memory Write, at          34742175000
 test target 1 - Starting Memory Write, at          34742385000
 test target 1 - Starting Memory Write, at          34742595000
 test target 1 - Starting Memory Write, at          34742835000
 test target 1 - Starting Memory Write, at          34743075000
 test target 1 - Starting Memory Read, at          34745025000
 test target 1 - Starting Memory Read, at          34746135000
 test target 1 - Starting Memory Read, at          34747185000
 test target 1 - Starting Memory Read, at          34748235000
 test target 1 - Starting Memory Read, at          34749315000
 test target 1 - Starting Memory Read, at          34750365000
 test target 1 - Starting Memory Read, at          34751415000
 test target 1 - Starting Memory Read, at          34752495000
 test target 1 - Starting Memory Read, at          34753545000
 test target 1 - Starting Memory Read, at          34754595000
 test target 1 - Starting Memory Read, at          34755675000
 test target 1 - Starting Memory Read, at          34756725000
 test target 1 - Starting Memory Read, at          34757775000
 test target 1 - Starting Memory Read, at          34758855000
 test target 1 - Starting Memory Read, at          34759905000
 test target 1 - Starting Memory Read, at          34760955000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          34761825000
 test target 1 - Starting Memory Read, at          34762005000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          34764675000
 test target 1 - Starting Memory Read, at          34765365000
 test target 1 - Starting Memory Read, at          34766115000
 test target 1 - Starting Memory Read, at          34766925000
 test target 1 - Starting Memory Read, at          34767645000
 test target 1 - Starting Memory Read, at          34768515000
 test target 1 - Starting Memory Read, at          34769685000
 test target 1 - Starting Memory Read, at          34770765000
 test target 1 - Starting Memory Read, at          34771875000
 test target 1 - Starting Memory Read, at          34774635000
 test target 1 - Starting Memory Read, at          34776375000
 test target 1 - Starting Memory Read, at          34777425000
 test target 1 - Starting Memory Read, at          34778475000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          34780155000
 test master 1 - Starting Memory Write, at          34780365000
 test target 1 - Starting Memory Write, at          34780365000
 test target 1 - Starting Memory Write, at          34780545000
 test target 1 - Starting Memory Read, at          34780845000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          34782525000
 test master 1 - Starting Memory Write, at          34782735000
 test target 1 - Starting Memory Write, at          34782735000
 Testing Interrupt Acknowledge cycle generation!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
Device          0 not present on PCI bus!
 test target 1 - Starting Config Read, at          34788345000
Device          1 with device id 0x8001 and vendor id 0xaaaa found on PCI bus!
 test target 2 - Starting Config Read, at          34789515000
Device          2 with device id 0x8002 and vendor id 0xaaaa found on PCI bus!
Device          3 not present on PCI bus!
Device          4 not present on PCI bus!
Device          5 not present on PCI bus!
Device          6 not present on PCI bus!
Device          7 not present on PCI bus!
Device          8 not present on PCI bus!
Device          9 not present on PCI bus!
Device         10 not present on PCI bus!
Device         11 not present on PCI bus!
Device         12 not present on PCI bus!
Device         13 not present on PCI bus!
Device         14 not present on PCI bus!
Device         15 not present on PCI bus!
Device         16 not present on PCI bus!
Device         17 not present on PCI bus!
Device         18 not present on PCI bus!
Device         19 not present on PCI bus!
Device         20 not present on PCI bus!
 test target 1 - Starting Config Write, at          34817925000
 test target 1 - Starting Config Write, at          34819065000
 test target 1 - Starting Config Write, at          34820175000
 test target 2 - Starting Config Write, at          34821285000
 test target 2 - Starting Config Write, at          34822425000
 test target 2 - Starting Config Write, at          34823535000
Testing WISHBONE slave images' features!
 test target 1 - Starting Memory Write, at          34825995000
 test target 1 - Starting Memory Read, at          34826265000
 test target 1 - Starting Memory Write, at          34827015000
 test target 1 - Starting Memory Read, at          34827285000
 test target 1 - Starting Memory Write, at          34828695000
 test target 1 - Starting Memory Read, at          34829625000
 test target 1 - Starting Memory Read, at          34830315000
 test target 1 - Starting Memory Read, at          34831035000
 test target 1 - Starting Memory Read, at          34831725000
 test target 1 - Starting Memory Read, at          34832775000
 test target 1 - Starting Memory Read, at          34833855000
 test target 1 - Starting Memory Read, at          34834965000
 test target 1 - Starting Memory Read, at          34836045000
 test target 1 - Starting Memory Read, at          34837155000
 test target 1 - Starting Memory Read, at          34838625000
 WB IMAGE 2 not implemented! 
 test target 1 - Starting Memory Write, at          34846455000
 test target 1 - Starting Memory Read, at          34846725000
 test target 1 - Starting Memory Write, at          34847475000
 test target 1 - Starting Memory Read, at          34847745000
 test target 1 - Starting Memory Write, at          34849155000
 test target 1 - Starting Memory Read, at          34850085000
 test target 1 - Starting Memory Read, at          34850775000
 test target 1 - Starting Memory Read, at          34851495000
 test target 1 - Starting Memory Read, at          34852185000
 test target 1 - Starting Memory Read, at          34853235000
 test target 1 - Starting Memory Read, at          34854315000
 test target 1 - Starting Memory Read, at          34855425000
 test target 1 - Starting Memory Read, at          34856505000
 test target 1 - Starting Memory Read, at          34857615000
 test target 1 - Starting Memory Read, at          34859085000
 test target 1 - Starting Memory Write, at          34866915000
 test target 1 - Starting Memory Read, at          34867185000
 test target 1 - Starting Memory Write, at          34867935000
 test target 1 - Starting Memory Read, at          34868205000
 test target 1 - Starting Memory Write, at          34869615000
 test target 1 - Starting Memory Read, at          34870545000
 test target 1 - Starting Memory Read, at          34871235000
 test target 1 - Starting Memory Read, at          34871955000
 test target 1 - Starting Memory Read, at          34872645000
 test target 1 - Starting Memory Read, at          34873695000
 test target 1 - Starting Memory Read, at          34874775000
 test target 1 - Starting Memory Read, at          34875885000
 test target 1 - Starting Memory Read, at          34876965000
 test target 1 - Starting Memory Read, at          34878075000
 test target 1 - Starting Memory Read, at          34879545000
 WB IMAGE 5 not implemented! 
************************* Testing WISHBONE Slave's response to erroneous memory accesses **************************
************************* DONE testing WISHBONE Slave's response to erroneous memory accesses **************************
***************************** Testing WISHBONE Slave's response to erroneous IO accesses ******************************
**************************** DONE testing WISHBONE Slave's response to erroneous IO accesses ***************************
************************* Testing WISHBONE Slave's response to erroneous configuration accesses **************************
*********************** DONE testing WISHBONE Slave's response to erroneous configuration accesses ***********************
************************** Testing handling of PCI bus errors *******************************************
Introducing master abort error on single WB to PCI write!
 test target 1 - Starting Config Write, at          34895355000
Introducing master abort error to CAB write!
 test target 1 - Starting Config Write, at          34903155000
 test target 1 - Starting Memory Write, at          34904235000
 test target 1 - Starting Memory Read, at          34904565000
Introducing master abort error to single read!
 test target 1 - Starting Config Write, at          34905825000
 test target 1 - Starting Config Write, at          34908165000
 test target 1 - Starting Memory Read, at          34908975000
Introducing master abort error to CAB read!
 test target 1 - Starting Config Write, at          34910835000
Introducing target abort termination to single write!
 test target 1 - Starting Config Write, at          34913415000
 test target 1 - Starting Memory Write, at          34914885000
 test target 1 - Starting Memory Write, at          34915215000
 test target 1 - Starting Memory Read, at          34915485000
Introducing target abort termination to CAB write!
 test target 1 - Starting Memory Write, at          34918455000
 test target 1 - Starting Memory Write, at          34922295000
 test target 1 - Starting Memory Write, at          34922715000
Introducing Target Abort error to single read!
 test target 1 - Starting Memory Read, at          34927455000
Introducing Target Abort error to CAB read!
 test target 1 - Starting Memory Read, at          34929855000
 test target 1 - Starting Memory Read, at          34931445000
 test target 1 - Starting Memory Read, at          34932405000
 test target 1 - Starting Memory Read, at          34934265000
************************ DONE testing handling of PCI bus errors ****************************************
******************************* Testing Parity Checker functions ********************************
Testing Parity Errors during Master Transactions!
Introducing Parity Erros to Master Writes!
 test target 1 - Starting Config Write, at          34941615000
 test target 2 - Starting Config Write, at          34942725000
 test target 1 - Starting Memory Write, at          34943535000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          34943715000
 test target 1 - Starting Memory Write, at          34944975000
*** monitor - Invalid Write Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h1, at          34945155000
 test target 1 - Starting Memory Write, at          34946415000
 Introducing Parity Errors to Master reads ! 
 test target 1 - Starting Memory Read, at          34948155000
 test target 1 - Starting Memory Read, at          34950825000
*** monitor - Undetected Read Data Parity Error, Address 'h12153524, CBE 'h0, PAR: 'h0, at          34951005000
 test target 1 - Starting Memory Read, at          34953675000
Presenting address parity error on PCI bus!
 test target 1 - Starting Memory Write, at          34955805000
 test master 2 - Starting Memory Write, at          34955805000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          34955865000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34956915000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34956945000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34957245000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34957275000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34958355000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34958385000
 test target 1 - Starting Memory Write, at          34960515000
 test master 2 - Starting Memory Write, at          34960515000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34962615000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34962645000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34964655000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34964685000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34966695000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34966725000
 test target 1 - Starting Memory Write, at          34969185000
 test master 2 - Starting Memory Write, at          34969185000
*** monitor - Undetected Address Parity Error, Address 'hc0000000, CBE 'h7, PAR: 'h0, at          34969245000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34971255000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34971285000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34971585000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34971615000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34972695000
*** monitor - CBE Bus Changed when TRDY Desserted, at          34972725000
 test target 1 - Starting Memory Write, at          34974075000
 test master 2 - Starting Memory Write, at          34974075000
Introducing Data Parity Errors on Bridge's Target references!
Introducing Data Parity Error on Write reference to Bridge's Target!
 test master 1 - Starting Memory Write, at          34977765000
Introducing Data Parity Error on Read reference to Bridge's Target!
 test master 1 - Starting Memory Read, at          34979715000
 test master 1 - Starting Memory Read, at          34980045000
*** monitor - Invalid Read Data Parity Error, Address 'h12345678, CBE 'h0, PAR: 'h1, at          34980195000
 test target 1 - Starting Config Write, at          34983375000
**************************** DONE testing Parity Checker functions ******************************
Checking WB to PCI transaction lengths!
Testing single write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          34986435000
 test target 1 - Starting Memory Write, at          34986645000
 test target 1 - Starting Memory Write, at          34986855000
Testing burst write transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          34987455000
 test target 1 - Starting Memory Write, at          34987695000
 test target 1 - Starting Memory Write, at          34987935000
 test target 1 - Starting Memory Write, at          34988535000
 test target 1 - Starting Memory Write, at          34988775000
 test target 1 - Starting Memory Write, at          34989375000
 test target 1 - Starting Memory Write, at          34990155000
 test target 1 - Starting Memory Write, at          34990395000
 test target 1 - Starting Memory Write, at          34991175000
 test target 1 - Starting Memory Write, at          34991445000
 test target 1 - Starting Memory Write, at          34992195000
 test target 1 - Starting Memory Write, at          35000145000
 test target 1 - Starting Memory Write, at          35000385000
 test target 1 - Starting Memory Write, at          35000625000
 test target 1 - Starting Memory Write, at          35000895000
 test target 1 - Starting Memory Write, at          35001165000
 test target 1 - Starting Memory Read, at          35003145000
 test target 1 - Starting Memory Read, at          35004255000
 test target 1 - Starting Memory Read, at          35005335000
 test target 1 - Starting Memory Read, at          35006385000
 test target 1 - Starting Memory Read, at          35007435000
 test target 1 - Starting Memory Read, at          35008515000
 test target 1 - Starting Memory Read, at          35009565000
 test target 1 - Starting Memory Read, at          35010615000
 test target 1 - Starting Memory Read, at          35011695000
 test target 1 - Starting Memory Read, at          35012745000
 test target 1 - Starting Memory Read, at          35013795000
 test target 1 - Starting Memory Read, at          35014875000
 test target 1 - Starting Memory Read, at          35015925000
 test target 1 - Starting Memory Read, at          35016975000
 test target 1 - Starting Memory Read, at          35018055000
 test target 1 - Starting Memory Read, at          35019105000
Testing single read transaction progress from WB to PCI!
 test target 1 - Starting Memory Read, at          35019945000
 test target 1 - Starting Memory Read, at          35020155000
Testing CAB read transaction progress from WB to PCI!
 test target 1 - Starting Memory Write, at          35022825000
 test target 1 - Starting Memory Read, at          35023545000
 test target 1 - Starting Memory Read, at          35024265000
 test target 1 - Starting Memory Read, at          35025075000
 test target 1 - Starting Memory Read, at          35025795000
 test target 1 - Starting Memory Read, at          35026665000
 test target 1 - Starting Memory Read, at          35027835000
 test target 1 - Starting Memory Read, at          35028915000
 test target 1 - Starting Memory Read, at          35030025000
 test target 1 - Starting Memory Read, at          35032755000
 test target 1 - Starting Memory Read, at          35034495000
 test target 1 - Starting Memory Read, at          35035545000
 test target 1 - Starting Memory Read, at          35036595000
Testing Master's latency timer operation!
Testing Latency timer during Master Writes!
 test target 1 - Starting Memory Write, at          35038275000
 test master 1 - Starting Memory Write, at          35038485000
 test target 1 - Starting Memory Write, at          35038485000
 test target 1 - Starting Memory Write, at          35038695000
 test target 1 - Starting Memory Read, at          35039055000
Testing Latency timer during Master Reads!
 test target 1 - Starting Memory Read, at          35040825000
 test master 1 - Starting Memory Write, at          35041035000
 test target 1 - Starting Memory Write, at          35041035000
 Testing Interrupt Acknowledge cycle generation!
 
WB slave images' tests finished!
########################################################################
########################################################################
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
########################################################################
########################################################################
Testing PCI target images' features!
 bridge target - Enabling master and target operation!
 bridge target - Setting base address P_BA0 to    32'h 10000000 !
 bridge target - Setting base address P_BA1 to    32'h 20000000 !
 bridge target - Setting base address P_BA3 to    32'h 60000000 !
 bridge target - Setting base address P_BA5 to    32'h a0000000 !
PCI bridge implemented as HOST device, PCI image 0 implemented to access WB bus!
 
########################################################################
Setting the IMAGE 0 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35047455000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          35047695000
 test master 2 - Starting Memory Read, at          35047875000
 test master 2 - Starting Memory Read, at          35048055000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35049795000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          35050095000
 test master 2 - Starting Memory Read, at          35050275000
 test master 2 - Starting Memory Read, at          35050455000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35052135000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35052465000
 test master 2 - Starting Memory Read Line Multiple, at          35052645000
 test master 2 - Starting Memory Read Line Multiple, at          35052885000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL0.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35054715000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35058015000
 test master 2 - Starting Memory Read Line Multiple, at          35058195000
 test master 2 - Starting Memory Read Line Multiple, at          35058465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35058825000
 test master 2 - Starting Memory Read Line Multiple, at          35059005000
 test master 2 - Starting Memory Read Line Multiple, at          35059245000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35059605000
 test master 2 - Starting Memory Read Line Multiple, at          35059785000
 test master 2 - Starting Memory Read Line Multiple, at          35060025000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35060385000
 test master 2 - Starting Memory Read Line Multiple, at          35060565000
 test master 2 - Starting Memory Read Line Multiple, at          35060805000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35061165000
 test master 2 - Starting Memory Read Line Multiple, at          35061345000
 test master 2 - Starting Memory Read Line Multiple, at          35061585000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35061945000
 test master 2 - Starting Memory Read Line Multiple, at          35062125000
 test master 2 - Starting Memory Read Line Multiple, at          35062365000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35062725000
 test master 2 - Starting Memory Read Line Multiple, at          35062905000
 test master 2 - Starting Memory Read Line Multiple, at          35063145000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35063505000
 test master 2 - Starting Memory Read Line Multiple, at          35063685000
 test master 2 - Starting Memory Read Line Multiple, at          35063925000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          35064285000
 test master 2 - Starting Memory Read Line, at          35064465000
 test master 2 - Starting Memory Read Line, at          35064645000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          35064915000
 test master 2 - Starting Memory Read Line, at          35065095000
 test master 2 - Starting Memory Read Line, at          35065275000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35066625000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35068485000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 0 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35071905000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 0 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35073825000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          35079015000
 test master 2 - Starting Memory Write, at          35079255000
 test master 2 - Starting Memory Write, at          35079495000
 test master 2 - Starting Memory Write, at          35079735000
 test master 2 - Starting Memory Write, at          35079975000
 test master 1 - Starting Memory Read, at          35080335000
 test master 1 - Starting Memory Read, at          35080605000
 test master 1 - Starting Memory Read, at          35081145000
 test master 1 - Starting Memory Read, at          35081415000
 test master 1 - Starting Memory Read, at          35081955000
 test master 1 - Starting Memory Read, at          35082225000
 test master 2 - Starting Memory Write, at          35083695000
 test master 2 - Starting Memory Write, at          35083935000
 test master 2 - Starting Memory Write, at          35084175000
 test master 2 - Starting Memory Write, at          35084415000
 test master 2 - Starting Memory Write, at          35084655000
 test master 1 - Starting Memory Read, at          35085015000
 test master 1 - Starting Memory Read, at          35085285000
 test master 1 - Starting Memory Read, at          35085825000
 test master 1 - Starting Memory Read, at          35086095000
 test master 1 - Starting Memory Read, at          35086635000
 test master 1 - Starting Memory Read, at          35086905000
 test master 2 - Starting Memory Write, at          35089035000
 test master 2 - Starting Memory Write, at          35090265000
 test master 2 - Starting Memory Write, at          35091525000
 test master 2 - Starting Memory Write, at          35092785000
 test master 2 - Starting Memory Write, at          35095515000
 test master 2 - Starting Memory Write, at          35096745000
 test master 2 - Starting Memory Write, at          35098005000
 test master 2 - Starting Memory Write, at          35099265000
 test master 2 - Starting Memory Write, at          35101995000
 test master 2 - Starting Memory Write, at          35104425000
 test master 2 - Starting Memory Write, at          35106885000
 test master 2 - Starting Memory Write, at          35109345000
 test master 2 - Starting Memory Write, at          35113275000
 test master 2 - Starting Memory Write, at          35116035000
 test master 2 - Starting Memory Write, at          35118795000
 test master 2 - Starting Memory Write, at          35121555000
  
  Master abort testing with unsuported bus command to image 0 (BC is IACK)!
  Master abort testing with unsuported bus command to image 0 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 0 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 0 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          35126445000
*** monitor - CBE Bus Changed when TRDY Desserted, at          35126475000
PCI image 1 is ALWAYS implemented!
 
########################################################################
Setting the IMAGE 1 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35129175000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          35129415000
 test master 2 - Starting Memory Read, at          35129595000
 test master 2 - Starting Memory Read, at          35129775000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35131515000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          35131815000
 test master 2 - Starting Memory Read, at          35131995000
 test master 2 - Starting Memory Read, at          35132175000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35133855000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35134185000
 test master 2 - Starting Memory Read Line Multiple, at          35134365000
 test master 2 - Starting Memory Read Line Multiple, at          35134605000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL1.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35136435000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35139735000
 test master 2 - Starting Memory Read Line Multiple, at          35139915000
 test master 2 - Starting Memory Read Line Multiple, at          35140185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35140545000
 test master 2 - Starting Memory Read Line Multiple, at          35140725000
 test master 2 - Starting Memory Read Line Multiple, at          35140965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35141325000
 test master 2 - Starting Memory Read Line Multiple, at          35141505000
 test master 2 - Starting Memory Read Line Multiple, at          35141745000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35142105000
 test master 2 - Starting Memory Read Line Multiple, at          35142285000
 test master 2 - Starting Memory Read Line Multiple, at          35142525000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35142885000
 test master 2 - Starting Memory Read Line Multiple, at          35143065000
 test master 2 - Starting Memory Read Line Multiple, at          35143305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35143665000
 test master 2 - Starting Memory Read Line Multiple, at          35143845000
 test master 2 - Starting Memory Read Line Multiple, at          35144085000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35144445000
 test master 2 - Starting Memory Read Line Multiple, at          35144625000
 test master 2 - Starting Memory Read Line Multiple, at          35144865000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35145225000
 test master 2 - Starting Memory Read Line Multiple, at          35145405000
 test master 2 - Starting Memory Read Line Multiple, at          35145645000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          35146005000
 test master 2 - Starting Memory Read Line, at          35146185000
 test master 2 - Starting Memory Read Line, at          35146365000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          35146635000
 test master 2 - Starting Memory Read Line, at          35146815000
 test master 2 - Starting Memory Read Line, at          35146995000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35148345000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35150205000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 1 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35153625000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 1 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35155545000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          35160735000
 test master 2 - Starting Memory Write, at          35160975000
 test master 2 - Starting Memory Write, at          35161215000
 test master 2 - Starting Memory Write, at          35161455000
 test master 2 - Starting Memory Write, at          35161695000
 test master 1 - Starting Memory Read, at          35162055000
 test master 1 - Starting Memory Read, at          35162325000
 test master 1 - Starting Memory Read, at          35162865000
 test master 1 - Starting Memory Read, at          35163135000
 test master 1 - Starting Memory Read, at          35163675000
 test master 1 - Starting Memory Read, at          35163945000
 test master 2 - Starting Memory Write, at          35165415000
 test master 2 - Starting Memory Write, at          35165655000
 test master 2 - Starting Memory Write, at          35165895000
 test master 2 - Starting Memory Write, at          35166135000
 test master 2 - Starting Memory Write, at          35166375000
 test master 1 - Starting Memory Read, at          35166735000
 test master 1 - Starting Memory Read, at          35167005000
 test master 1 - Starting Memory Read, at          35167545000
 test master 1 - Starting Memory Read, at          35167815000
 test master 1 - Starting Memory Read, at          35168355000
 test master 1 - Starting Memory Read, at          35168625000
 test master 2 - Starting Memory Write, at          35170755000
 test master 2 - Starting Memory Write, at          35171985000
 test master 2 - Starting Memory Write, at          35173245000
 test master 2 - Starting Memory Write, at          35174505000
 test master 2 - Starting Memory Write, at          35177235000
 test master 2 - Starting Memory Write, at          35178465000
 test master 2 - Starting Memory Write, at          35179725000
 test master 2 - Starting Memory Write, at          35180985000
 test master 2 - Starting Memory Write, at          35183715000
 test master 2 - Starting Memory Write, at          35186145000
 test master 2 - Starting Memory Write, at          35188605000
 test master 2 - Starting Memory Write, at          35191065000
 test master 2 - Starting Memory Write, at          35194995000
 test master 2 - Starting Memory Write, at          35197755000
 test master 2 - Starting Memory Write, at          35200515000
 test master 2 - Starting Memory Write, at          35203275000
  
  Master abort testing with unsuported bus command to image 1 (BC is IACK)!
  Master abort testing with unsuported bus command to image 1 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 1 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 1 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          35208165000
*** monitor - CBE Bus Changed when TRDY Desserted, at          35208195000
PCI image 2 is NOT implemented!
PCI image 3 is implemented!
 
########################################################################
Setting the IMAGE 3 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35210895000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          35211135000
 test master 2 - Starting Memory Read, at          35211315000
 test master 2 - Starting Memory Read, at          35211495000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35213235000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          35213535000
 test master 2 - Starting Memory Read, at          35213715000
 test master 2 - Starting Memory Read, at          35213895000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35215575000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35215905000
 test master 2 - Starting Memory Read Line Multiple, at          35216085000
 test master 2 - Starting Memory Read Line Multiple, at          35216325000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL3.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35218155000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35221455000
 test master 2 - Starting Memory Read Line Multiple, at          35221635000
 test master 2 - Starting Memory Read Line Multiple, at          35221905000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35222265000
 test master 2 - Starting Memory Read Line Multiple, at          35222445000
 test master 2 - Starting Memory Read Line Multiple, at          35222685000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35223045000
 test master 2 - Starting Memory Read Line Multiple, at          35223225000
 test master 2 - Starting Memory Read Line Multiple, at          35223465000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35223825000
 test master 2 - Starting Memory Read Line Multiple, at          35224005000
 test master 2 - Starting Memory Read Line Multiple, at          35224245000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35224605000
 test master 2 - Starting Memory Read Line Multiple, at          35224785000
 test master 2 - Starting Memory Read Line Multiple, at          35225025000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35225385000
 test master 2 - Starting Memory Read Line Multiple, at          35225565000
 test master 2 - Starting Memory Read Line Multiple, at          35225805000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35226165000
 test master 2 - Starting Memory Read Line Multiple, at          35226345000
 test master 2 - Starting Memory Read Line Multiple, at          35226585000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35226945000
 test master 2 - Starting Memory Read Line Multiple, at          35227125000
 test master 2 - Starting Memory Read Line Multiple, at          35227365000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          35227725000
 test master 2 - Starting Memory Read Line, at          35227905000
 test master 2 - Starting Memory Read Line, at          35228085000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          35228355000
 test master 2 - Starting Memory Read Line, at          35228535000
 test master 2 - Starting Memory Read Line, at          35228715000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35230065000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35231925000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 3 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35235345000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 3 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35237265000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          35242455000
 test master 2 - Starting Memory Write, at          35242695000
 test master 2 - Starting Memory Write, at          35242935000
 test master 2 - Starting Memory Write, at          35243175000
 test master 2 - Starting Memory Write, at          35243415000
 test master 1 - Starting Memory Read, at          35243775000
 test master 1 - Starting Memory Read, at          35244045000
 test master 1 - Starting Memory Read, at          35244585000
 test master 1 - Starting Memory Read, at          35244855000
 test master 1 - Starting Memory Read, at          35245395000
 test master 1 - Starting Memory Read, at          35245665000
 test master 2 - Starting Memory Write, at          35247135000
 test master 2 - Starting Memory Write, at          35247375000
 test master 2 - Starting Memory Write, at          35247615000
 test master 2 - Starting Memory Write, at          35247855000
 test master 2 - Starting Memory Write, at          35248095000
 test master 1 - Starting Memory Read, at          35248455000
 test master 1 - Starting Memory Read, at          35248725000
 test master 1 - Starting Memory Read, at          35249265000
 test master 1 - Starting Memory Read, at          35249535000
 test master 1 - Starting Memory Read, at          35250075000
 test master 1 - Starting Memory Read, at          35250345000
 test master 2 - Starting Memory Write, at          35252475000
 test master 2 - Starting Memory Write, at          35253705000
 test master 2 - Starting Memory Write, at          35254965000
 test master 2 - Starting Memory Write, at          35256225000
 test master 2 - Starting Memory Write, at          35258955000
 test master 2 - Starting Memory Write, at          35260185000
 test master 2 - Starting Memory Write, at          35261445000
 test master 2 - Starting Memory Write, at          35262705000
 test master 2 - Starting Memory Write, at          35265435000
 test master 2 - Starting Memory Write, at          35267865000
 test master 2 - Starting Memory Write, at          35270325000
 test master 2 - Starting Memory Write, at          35272785000
 test master 2 - Starting Memory Write, at          35276715000
 test master 2 - Starting Memory Write, at          35279475000
 test master 2 - Starting Memory Write, at          35282235000
 test master 2 - Starting Memory Write, at          35284995000
  
  Master abort testing with unsuported bus command to image 3 (BC is IACK)!
  Master abort testing with unsuported bus command to image 3 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 3 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 3 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          35289885000
*** monitor - CBE Bus Changed when TRDY Desserted, at          35289915000
PCI image 4 is NOT implemented!
PCI image 5 is implemented!
 
########################################################################
Setting the IMAGE 5 configuration registers (P_BA, P_AM, P_TA)
 
Setting the Cache Line Size register to   4 word(s)
Do single WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 0 WAIT states!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35292615000
Memory read through PCI bridge to WB slave!
Read    4 words!
 test master 2 - Starting Memory Read, at          35292855000
 test master 2 - Starting Memory Read, at          35293035000
 test master 2 - Starting Memory Read, at          35293215000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (2 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35294955000
Memory read through PCI bridge to WB slave!
Read    2 words!
 test master 2 - Starting Memory Read, at          35295255000
 test master 2 - Starting Memory Read, at          35295435000
 test master 2 - Starting Memory Read, at          35295615000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   8 word(s)
Do burst (3 words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35297295000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35297625000
 test master 2 - Starting Memory Read Line Multiple, at          35297805000
 test master 2 - Starting Memory Read Line Multiple, at          35298045000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Setting the Cache Line Size register to   4 word(s)
Do burst (full fifo depth words) WR / RD test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported, but they should not occur!
Address translation is NOT implemented for PCI images!
Setting the PRF_EN bit of PCI Image Control register P_IMG_CTRL5.
 - bursts can be performed!
Setting behavioral WB slave parameters: ACK termination and 3 WAIT states!
Memory write (  62 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35299875000
Memory read through PCI bridge to WB slave!
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35303175000
 test master 2 - Starting Memory Read Line Multiple, at          35303355000
 test master 2 - Starting Memory Read Line Multiple, at          35303625000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35303985000
 test master 2 - Starting Memory Read Line Multiple, at          35304165000
 test master 2 - Starting Memory Read Line Multiple, at          35304405000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35304765000
 test master 2 - Starting Memory Read Line Multiple, at          35304945000
 test master 2 - Starting Memory Read Line Multiple, at          35305185000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35305545000
 test master 2 - Starting Memory Read Line Multiple, at          35305725000
 test master 2 - Starting Memory Read Line Multiple, at          35305965000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35306325000
 test master 2 - Starting Memory Read Line Multiple, at          35306505000
 test master 2 - Starting Memory Read Line Multiple, at          35306745000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35307105000
 test master 2 - Starting Memory Read Line Multiple, at          35307285000
 test master 2 - Starting Memory Read Line Multiple, at          35307525000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35307885000
 test master 2 - Starting Memory Read Line Multiple, at          35308065000
 test master 2 - Starting Memory Read Line Multiple, at          35308305000
Read    7 words!
 test master 2 - Starting Memory Read Line Multiple, at          35308665000
 test master 2 - Starting Memory Read Line Multiple, at          35308845000
 test master 2 - Starting Memory Read Line Multiple, at          35309085000
Read    4 words!
 test master 2 - Starting Memory Read Line, at          35309445000
 test master 2 - Starting Memory Read Line, at          35309625000
 test master 2 - Starting Memory Read Line, at          35309805000
Read    2 words!
 test master 2 - Starting Memory Read Line, at          35310075000
 test master 2 - Starting Memory Read Line, at          35310255000
 test master 2 - Starting Memory Read Line, at          35310435000
Reading the ERR_SIG bit of PCI Error Control and Status register P_ERR_CS.
No error was signaled, as expected!
 
Do single erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   1 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35311785000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (2 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with first data!
Memory write (   2 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35313645000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Do burst (3 words) erroneous WR test through the IMAGE 5 !
Clearing the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will NOT be reported when they will occur!
Clearing the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will NOT be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination with last data!
Memory write (   3 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35317065000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and not reported, as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and not reported, as expected!
Interrupt pin INT_O was correctly set to logic '0'!
Error and Interrupt don't need to be cleared!
 
Do burst (8 words) erroneous WR test through the IMAGE 5 !
Setting the ERR_EN bit of PCI Error Control and Status register P_ERR_CS.
 - errors will be reported when they will occur!
Setting the PCI_EINT_EN and WB_EINT_EN bit of Interrupt Control register ICR.
 - interrupt will be reported when error will occur!
Address translation is NOT implemented for PCI images!
ERR termination before last data!
Memory write (   8 words) through PCI bridge to WB slave!
 test master 2 - Starting Memory Write, at          35318985000
Reading the PCI Error Control and Status register P_ERR_CS.
Error was signaled and reported, as expected!
Byte enables written into P_ERR_CS register are as expected!
Bus command written into P_ERR_CS register is as expected!
Reading the PCI Error Data register P_ERR_DATA.
Data written into P_ERR_DATA register is as expected!
Reading the PCI Error Address register P_ERR_ADDR.
Address written into P_ERR_ADDR register is as expected!
Reading the PCI_EINT and WB_EINT bit of Interrupt Status register ISR.
Interrupts was signaled and reported, as expected!
Interrupt pin INT_O was correctly set to logic '1'!
Error and Interrupt must be cleared!
Interrupt pin INT_O was correctly cleared!
 
Setting the Cache Line Size register to   4 word(s)
 test master 2 - Starting Memory Write, at          35324175000
 test master 2 - Starting Memory Write, at          35324415000
 test master 2 - Starting Memory Write, at          35324655000
 test master 2 - Starting Memory Write, at          35324895000
 test master 2 - Starting Memory Write, at          35325135000
 test master 1 - Starting Memory Read, at          35325495000
 test master 1 - Starting Memory Read, at          35325765000
 test master 1 - Starting Memory Read, at          35326305000
 test master 1 - Starting Memory Read, at          35326575000
 test master 1 - Starting Memory Read, at          35327115000
 test master 1 - Starting Memory Read, at          35327385000
 test master 2 - Starting Memory Write, at          35328855000
 test master 2 - Starting Memory Write, at          35329095000
 test master 2 - Starting Memory Write, at          35329335000
 test master 2 - Starting Memory Write, at          35329575000
 test master 2 - Starting Memory Write, at          35329815000
 test master 1 - Starting Memory Read, at          35330175000
 test master 1 - Starting Memory Read, at          35330445000
 test master 1 - Starting Memory Read, at          35330985000
 test master 1 - Starting Memory Read, at          35331255000
 test master 1 - Starting Memory Read, at          35331795000
 test master 1 - Starting Memory Read, at          35332065000
 test master 2 - Starting Memory Write, at          35334195000
 test master 2 - Starting Memory Write, at          35335425000
 test master 2 - Starting Memory Write, at          35336685000
 test master 2 - Starting Memory Write, at          35337945000
 test master 2 - Starting Memory Write, at          35340675000
 test master 2 - Starting Memory Write, at          35341905000
 test master 2 - Starting Memory Write, at          35343165000
 test master 2 - Starting Memory Write, at          35344425000
 test master 2 - Starting Memory Write, at          35347155000
 test master 2 - Starting Memory Write, at          35349585000
 test master 2 - Starting Memory Write, at          35352045000
 test master 2 - Starting Memory Write, at          35354505000
 test master 2 - Starting Memory Write, at          35358435000
 test master 2 - Starting Memory Write, at          35361195000
 test master 2 - Starting Memory Write, at          35363955000
 test master 2 - Starting Memory Write, at          35366715000
  
  Master abort testing with unsuported bus command to image 5 (BC is IACK)!
  Master abort testing with unsuported bus command to image 5 (BC is SPECIAL)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED0)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED1)
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED2)!
  Master abort testing with unsuported bus command to image 5 (BC is RESERVED3)!
PCI monitor will complain twice with 'CBE Bus Changed'; second bus command (MEM_WRITE) and 
    byte enables are different than first bus command (DUAL_ADDR_CYC)!
  Master abort testing with unsuported bus command to image 5 (BC is DUAL_ADDR_CYC)!
*** monitor - CBE Bus Changed when TRDY Desserted, at          35371605000
*** monitor - CBE Bus Changed when TRDY Desserted, at          35371635000
 test master 1 - Starting Memory Read, at          35374335000
 test master 1 - Starting Memory Read, at          35374635000
 test master 1 - Starting Memory Read, at          35376075000
 test master 1 - Starting Memory Read, at          35376375000
 test master 1 - Starting Memory Read Line, at          35377875000
 test master 1 - Starting Memory Read Line, at          35378175000
 test master 1 - Starting Memory Read Line, at          35379675000
 test master 1 - Starting Memory Read Line, at          35380005000
 test master 1 - Starting Memory Read Line, at          35381535000
 test master 1 - Starting Memory Read Line, at          35381895000
 test master 1 - Starting Memory Read Line, at          35383455000
 test master 1 - Starting Memory Read Line, at          35383815000
 test master 1 - Starting Memory Read Line Multiple, at          35385375000
 test master 1 - Starting Memory Read Line Multiple, at          35385795000
 test master 1 - Starting Memory Read Line Multiple, at          35387415000
 test master 1 - Starting Memory Read Line Multiple, at          35387835000
 test master 1 - Starting Memory Read Line, at          35389515000
 test master 1 - Starting Memory Read Line, at          35389875000
 test master 1 - Starting Memory Read, at          35392875000
 test master 1 - Starting Memory Read, at          35393175000
 test target 1 - Starting Config Write, at          35397285000
 test master 1 - Starting Memory Write, at          35397855000
 test master 1 - Starting Memory Write, at          35399805000
 test master 1 - Starting Memory Write, at          35401155000
 test master 1 - Starting Memory Write, at          35402985000
 test master 1 - Starting Memory Write, at          35404335000
 test master 1 - Starting Memory Read Line, at          35406285000
 test master 1 - Starting Memory Write, at          35407785000
 test master 1 - Starting Memory Read Line, at          35409735000
 test target 1 - Starting Config Write, at          35413725000
 test master 1 - Starting Memory Write, at          35414295000
 test master 1 - Starting Memory Write, at          35414415000
 test master 1 - Starting Memory Write, at          35414655000
 test master 1 - Starting Memory Read, at          35414775000
 test master 1 - Starting Memory Write, at          35415075000
 test master 1 - Starting Memory Read, at          35415195000
 test master 1 - Starting Memory Write, at          35417325000
 test master 1 - Starting Memory Write, at          35420595000
 test master 2 - Starting Memory Read Line, at          35424015000
 test master 2 - Starting Memory Read Line, at          35424345000
 test master 2 - Starting Memory Read Line, at          35424645000
 test master 2 - Starting Memory Read Line, at          35424975000
 test master 1 - Starting Memory Write, at          35425365000
 test master 1 - Starting Memory Write, at          35425605000
 test master 1 - Starting Memory Write, at          35425845000
 test master 2 - Starting Memory Read Line, at          35426205000
 test master 2 - Starting Memory Read Line, at          35426505000
 test master 2 - Starting Memory Read Line, at          35426715000
 test master 2 - Starting Memory Read Line, at          35427015000
 test master 2 - Starting Memory Read Line Multiple, at          35427255000
 test master 2 - Starting Memory Read Line Multiple, at          35427555000
 test master 1 - Starting Memory Write, at          35429895000
 test master 1 - Starting Memory Write, at          35430135000
 test master 2 - Starting Memory Read, at          35430495000
 test master 2 - Starting Memory Read, at          35430795000
 test master 2 - Starting Memory Read, at          35431005000
 test master 2 - Starting Memory Read, at          35431305000
 test master 1 - Starting Memory Write, at          35433315000
 test master 1 - Starting Memory Read, at          35433495000
 test master 1 - Starting Memory Write, at          35433675000
 test master 1 - Starting Memory Read, at          35433885000
 test master 1 - Starting Memory Write, at          35434095000
 test master 1 - Starting Memory Read, at          35434275000
 test master 1 - Starting Memory Read, at          35434485000
 test master 1 - Starting Memory Write, at          35434695000
 test master 1 - Starting Memory Write, at          35434875000
 test master 1 - Starting Memory Read, at          35435055000
 test master 1 - Starting Memory Write, at          35435235000
 test master 1 - Starting Memory Write, at          35435445000
 test master 1 - Starting Memory Write, at          35435655000
 
PCI target images' tests finished!
 test target 1 - Starting Memory Write, at          35441355000
 test target 1 - Starting Memory Write, at          35441565000
 test master 1 - Starting Memory Write, at          35441745000
 test target 1 - Starting Memory Write, at          35441925000
 test target 1 - Starting Memory Write, at          35442135000
 test target 1 - Starting Memory Write, at          35442345000
 test master 1 - Starting Memory Write, at          35442645000
 test target 1 - Starting Memory Write, at          35443155000
 test target 1 - Starting Memory Write, at          35443695000
 test target 1 - Starting Memory Write, at          35443935000
 test master 1 - Starting Memory Write, at          35444145000
 test target 1 - Starting Memory Write, at          35444385000
 test target 1 - Starting Memory Write, at          35444625000
 test target 1 - Starting Memory Write, at          35444865000
 test master 1 - Starting Memory Write, at          35445225000
 test target 1 - Starting Memory Write, at          35445945000
 test target 1 - Starting Memory Write, at          35446515000
 test target 1 - Starting Memory Write, at          35446725000
 test master 1 - Starting Memory Read, at          35446905000
 test target 1 - Starting Memory Write, at          35447085000
 test master 1 - Starting Memory Read, at          35447265000
 test target 1 - Starting Memory Write, at          35447445000
 test master 1 - Starting Memory Read, at          35447625000
 test target 1 - Starting Memory Write, at          35447805000
 test master 1 - Starting Memory Read, at          35447985000
 test target 1 - Starting Memory Write, at          35448165000
 test master 1 - Starting Memory Read, at          35448345000
 test target 1 - Starting Memory Write, at          35448525000
 test master 1 - Starting Memory Write, at          35448705000
 test target 1 - Starting Memory Write, at          35448885000
 test target 1 - Starting Memory Write, at          35449095000
 test target 1 - Starting Memory Write, at          35449305000
 test target 1 - Starting Memory Read, at          35449575000
 test master 1 - Starting Memory Write, at          35449875000
 test master 1 - Starting Memory Read, at          35450115000
 test target 1 - Starting Memory Write, at          35450625000
 test master 1 - Starting Memory Write, at          35451015000
 test target 1 - Starting Memory Read, at          35451465000
 test target 1 - Starting Memory Write, at          35452275000
 test master 1 - Starting Memory Read, at          35452575000
 test master 1 - Starting Memory Write, at          35452875000
 test master 1 - Starting Memory Write, at          35453235000
 test master 1 - Starting Memory Read, at          35453475000
 
PCI transaction ordering tests finished!
Simulation stopped via $stop(1) at time 35453520 NS + 1
/projects/pci/tadejm/OpenCores/pci/bench/verilog/system.v:871     $stop ;
ncsim> quit
ncsim: v03.30.(p001): Exiting on Jul 08, 2001 at 12:06:31  (total: 00:37:25)