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[/] [pci/] [tags/] [rel_8/] [apps/] [crt/] [syn/] [out/] [bit/] [fe.log] - Rev 154
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ngdbuild -p xc2s150-5-pq208 -uc pci_crt.ucf -dd .. f:\mihad\fpga_t~1\pci_crt\pci_crt.edf pci_crt.ngdRelease 3.3.08i - ngdbuild D.27Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -p xc2s150-5-pq208 -uc pci_crt.ucf -dd ..f:\mihad\fpga_t~1\pci_crt\pci_crt.edf pci_crt.ngdLauncher: Executing edif2ngd "f:\mihad\fpga_t~1\pci_crt\pci_crt.edf""F:\mihad\fpga_t~1\pci_crt\xproj\ver2\pci_crt.ngo"Release 3.3.08i - edif2ngd D.27Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.Writing the design to "F:/mihad/fpga_t~1/pci_crt/xproj/ver2/pci_crt.ngo"...Reading NGO file "F:/mihad/fpga_t~1/pci_crt/xproj/ver2/pci_crt.ngo" ...Reading component libraries for design expansion...Annotating constraints to design from file "pci_crt.ucf" ...Checking timing specifications ...Checking expanded design ...WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol "CRT/ssvga_pallete", thefollowing properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will beused.WARNING:NgdBuild:526 - On the RAMB4_S8_S16 symbol "CRT/ssvga_fifo/ramb4_s8_1",the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will beused.WARNING:NgdBuild:526 - On the RAMB4_S8_S16 symbol "CRT/ssvga_fifo/ramb4_s8_0",the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will beused.WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol"bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_0", thefollowing properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will beused.WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol"bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_1", thefollowing properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will beused.WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol"bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2", thefollowing properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will beused.NGDBUILD Design Results Summary:Number of errors: 0Number of warnings: 6Writing NGD file "pci_crt.ngd" ...Writing NGDBUILD log file "pci_crt.bld"...NGDBUILD done.==================================================map -p xc2s150-5-pq208 -o map.ncd -pr b pci_crt.ngd pci_crt.pcfRelease 3.3.08i - Map D.27Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.Using target part "2s150pq208-5".Reading NGD file "pci_crt.ngd"...Processing FMAPs...Removing unused or disabled logic...Running cover...Writing file map.ngm...Running directed packing...Running delay-based packing...Running related packing...Writing design file "map.ncd"...Design Summary:Number of errors: 0Number of warnings: 72Number of Slices: 1,402 out of 1,728 81%Number of Slices containingunrelated logic: 0 out of 1,402 0%Number of Slice Flip Flops: 1,135 out of 3,456 32%Total Number 4 input LUTs: 1,863 out of 3,456 53%Number used as LUTs: 1,720Number used as a route-thru: 1Number used for Dual Port RAMs: 142(Two LUTs used per Dual Port RAM)Number of bonded IOBs: 64 out of 140 45%IOB Flip Flops: 147Number of Block RAMs: 6 out of 12 50%Number of GCLKs: 2 out of 4 50%Number of GCLKIOBs: 2 out of 4 50%Total equivalent gate count for design: 129,333Additional JTAG gate count for IOBs: 3,168Removed Logic Summary:11 block(s) removed121 block(s) optimized away1 signal(s) removedMapping completed.See MAP report file "map.mrp" for details.==================================================par -w -ol 2 map.ncd pci_crt.ncd pci_crt.pcfRelease 3.3.08i - Par D.27Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.Constraints file: pci_crt.pcfLoading design for application par from file map.ncd."TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5Loading device for application par from file 'v150.nph' in environmentC:/Foundation.Device speed data version: PRELIMINARY 1.21 2001-04-09.Resolving physical constraints.Finished resolving physical constraints.Device utilization summary:Number of External GCLKIOBs 2 out of 4 50%Number of External IOBs 64 out of 140 45%Number of BLOCKRAMs 6 out of 12 50%Number of SLICEs 1402 out of 1728 81%Number of GCLKs 2 out of 4 50%Overall effort level (-ol): 2 (set by user)Placer effort level (-pl): 2 (set by user)Placer cost table entry (-t): 1Router effort level (-rl): 2 (set by user)Starting initial Timing Analysis. REAL time: 14 secsFinished initial Timing Analysis. REAL time: 40 secsDesign passed SelectIO DRC.Starting the placer. REAL time: 43 secsPlacement pass 1 ...................Placer score = 379658Placement pass 2 .........................Placer score = 368407Placement pass 3 .....................Placer score = 369308Optimizing ...Placer score = 301933Improving the placement. REAL time: 1 mins 15 secsPlacer score = 474349Placer score = 507794Placer score = 471774Placer score = 440616Placer score = 418456Placer score = 403030Placer score = 390280Placer score = 381864Placer score = 372761Placer score = 367215Placer score = 361011Placer score = 356024Placer score = 346592Placer score = 342238Placer score = 339291Placer score = 335589Placer score = 332722Placer score = 328768Placer score = 324807Placer score = 319970Placer score = 316171Placer score = 310589Placer score = 305289Placer score = 300126Placer score = 295734Placer score = 293094Placer score = 290570Placer score = 288768Placer score = 287281Placer score = 285736Placer score = 284379Placer score = 283262Placer score = 282647Placer score = 282077Placer stage completed in real time: 2 mins 38 secsAll IOBs have been constrained to specific sites.Select IO Utilization and Usage Summary_______________________________________NR - means Not Required.Each Group of a specific Standard is listed.IO standard (PCI33_5 Vref=NR Vcco=3.30) occupies 48 pads.IO standard (LVTTL Vref=NR Vcco=3.30) occupies 18 pads.Bank Summary____________If an IOB is placed in a Vref site, it will be indicated by the word 'Vref' atthe end of a summary row. IOBs can be placed in a bank's Vref sites when none ofthe IOBs in the bank require a Vref site.NR - means Not RequiredBank 0 has 17 pads and is 58% utilized.Vref should be set to NR volts.Vcco should be set to 3.30 volts.Name IO Select Std Vref Vcco Pad Pin---- -- ---------- ------ ------ ------ ------AD<28> IO PCI33_5 NR 3.30 PAD2 P206AD<29> IO PCI33_5 NR 3.30 PAD6 P205AD<30> IO PCI33_5 NR 3.30 PAD10 P204AD<31> IO PCI33_5 NR 3.30 PAD11 P203 VrefLED O LVTTL 3.30 PAD12 P202REQ O PCI33_5 3.30 PAD16 P201GNT I PCI33_5 NR PAD18 P200 VrefRST I PCI33_5 NR PAD19 P199INTA O PCI33_5 3.30 PAD20 P195CLK I LVTTL NR GCLKPAD3 P185Bank 1 has 19 pads and is 68% utilized.Vref should be set to NR volts.Vcco should be set to 3.30 volts.Name IO Select Std Vref Vcco Pad Pin---- -- ---------- ------ ------ ------ ------CRT_CLK I LVTTL NR GCLKPAD2 P182RGB<15> O LVTTL 3.30 PAD38 P181RGB<14> O LVTTL 3.30 PAD40 P180RGB<13> O LVTTL 3.30 PAD42 P179RGB<12> O LVTTL 3.30 PAD43 P178 VrefRGB<11> O LVTTL 3.30 PAD44 P176RGB<10> O LVTTL 3.30 PAD45 P175RGB<9> O LVTTL 3.30 PAD48 P174RGB<8> O LVTTL 3.30 PAD52 P173RGB<7> O LVTTL 3.30 PAD53 P172RGB<6> O LVTTL 3.30 PAD54 P168RGB<5> O LVTTL 3.30 PAD55 P167 VrefRGB<4> O LVTTL 3.30 PAD57 P166Bank 4 has 19 pads and is 10% utilized.Vcco should be set to 3.30 volts.Name IO Select Std Vref Vcco Pad Pin---- -- ---------- ------ ------ ------ ------VSYNC O LVTTL 3.30 PAD174 P84 VrefHSYNC O LVTTL 3.30 PAD175 P83Bank 5 has 16 pads and is 43% utilized.Vref should be set to NR volts.Vcco should be set to 3.30 volts.Name IO Select Std Vref Vcco Pad Pin---- -- ---------- ------ ------ ------ ------AD<0> IO PCI33_5 NR 3.30 PAD197 P67AD<1> IO PCI33_5 NR 3.30 PAD198 P63AD<2> IO PCI33_5 NR 3.30 PAD199 P62 VrefAD<3> IO PCI33_5 NR 3.30 PAD201 P61AD<4> IO PCI33_5 NR 3.30 PAD206 P59 VrefAD<5> IO PCI33_5 NR 3.30 PAD207 P58AD<6> IO PCI33_5 NR 3.30 PAD211 P57Bank 6 has 18 pads and is 94% utilized.Vref should be set to NR volts.Vcco should be set to 3.30 volts.Name IO Select Std Vref Vcco Pad Pin---- -- ---------- ------ ------ ------ ------AD<7> IO PCI33_5 NR 3.30 PAD217 P49CBE<0> IO PCI33_5 NR 3.30 PAD218 P48AD<8> IO PCI33_5 NR 3.30 PAD222 P47AD<9> IO PCI33_5 NR 3.30 PAD226 P46AD<10> IO PCI33_5 NR 3.30 PAD227 P45 VrefAD<11> IO PCI33_5 NR 3.30 PAD232 P43AD<12> IO PCI33_5 NR 3.30 PAD234 P42 VrefAD<13> IO PCI33_5 NR 3.30 PAD235 P41AD<14> IO PCI33_5 NR 3.30 PAD236 P37AD<15> IO PCI33_5 NR 3.30 PAD237 P36CBE<1> IO PCI33_5 NR 3.30 PAD241 P35PAR IO PCI33_5 NR 3.30 PAD244 P34SERR O PCI33_5 3.30 PAD245 P33PERR IO PCI33_5 NR 3.30 PAD246 P31 VrefSTOP IO PCI33_5 NR 3.30 PAD247 P30DEVSEL IO PCI33_5 NR 3.30 PAD249 P29TRDY IO PCI33_5 NR 3.30 PAD252 P27Bank 7 has 18 pads and is 94% utilized.Vref should be set to NR volts.Vcco should be set to 3.30 volts.Name IO Select Std Vref Vcco Pad Pin---- -- ---------- ------ ------ ------ ------IRDY IO PCI33_5 NR 3.30 PAD253 P24FRAME IO PCI33_5 NR 3.30 PAD254 P23CBE<2> IO PCI33_5 NR 3.30 PAD256 P22AD<16> IO PCI33_5 NR 3.30 PAD258 P21AD<17> IO PCI33_5 NR 3.30 PAD259 P20 VrefAD<18> IO PCI33_5 NR 3.30 PAD260 P18AD<19> IO PCI33_5 NR 3.30 PAD261 P17AD<20> IO PCI33_5 NR 3.30 PAD264 P16AD<21> IO PCI33_5 NR 3.30 PAD268 P15AD<22> IO PCI33_5 NR 3.30 PAD269 P14AD<23> IO PCI33_5 NR 3.30 PAD270 P10IDSEL I LVTTL NR PAD271 P9 VrefCBE<3> IO PCI33_5 NR 3.30 PAD273 P8AD<24> IO PCI33_5 NR 3.30 PAD278 P6 VrefAD<25> IO PCI33_5 NR 3.30 PAD279 P5AD<26> IO PCI33_5 NR 3.30 PAD283 P4AD<27> IO PCI33_5 NR 3.30 PAD287 P3Placer completed in real time: 2 mins 40 secsDumping design to file pci_crt.ncd.Total REAL time to Placer completion: 2 mins 49 secsTotal CPU time to Placer completion: 2 mins 30 secs0 connection(s) routed; 9789 unrouted active, 56 unrouted PWR/GND.Starting router resource preassignmentCompleted router resource preassignment. REAL time: 3 mins 4 secsStarting iterative routing.Routing active signals......................End of iteration 19845 successful; 0 unrouted; (0) REAL time: 5 mins 31 secsConstraints are met.Total REAL time: 5 mins 36 secsTotal CPU time: 5 minsEnd of route. 9845 routed (100.00%); 0 unrouted.No errors found.Completely routed.Total REAL time to Router completion: 5 mins 43 secsTotal CPU time to Router completion: 5 mins 5 secsGenerating PAR statistics.Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.--------------------------------------------------------------------------------Constraint | Requested | Actual | Logic| | | Levels--------------------------------------------------------------------------------TS_CLK = PERIOD TIMEGRP "CLK" 30 nS HI | 30.000ns | 23.294ns | 8GH 50.000 % | | |--------------------------------------------------------------------------------TS_CRT_CLK = PERIOD TIMEGRP "CRT_CLK" 44 | 44.000ns | 23.360ns | 6nS HIGH 50.000 % | | |--------------------------------------------------------------------------------TS_CLK_2_CRT_CLK = MAXDELAY FROM TIMEGRP | 30.000ns | 21.603ns | 9"CLK" TO TIMEGRP "CRT_CLK" 30 nS | | |--------------------------------------------------------------------------------TS_CRT_CLK_2_CLK = MAXDELAY FROM TIMEGRP | 30.000ns | 16.423ns | 8"CRT_CLK" TO TIMEGRP "CLK" 30 nS | | |--------------------------------------------------------------------------------COMP "REQ" OFFSET = OUT 12 nS AFTER COMP | 12.000ns | 9.486ns | 1"CLK" | | |--------------------------------------------------------------------------------COMP "SERR" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.434ns | 1P "CLK" | | |--------------------------------------------------------------------------------COMP "GNT" OFFSET = IN 10 nS BEFORE COMP | 10.000ns | 9.535ns | 5"CLK" | | |--------------------------------------------------------------------------------COMP "FRAME" OFFSET = IN 7 nS BEFORE COM | 7.000ns | 6.287ns | 4P "CLK" | | |--------------------------------------------------------------------------------COMP "FRAME" OFFSET = OUT 11 nS AFTER CO | 11.000ns | 9.432ns | 1MP "CLK" | | |--------------------------------------------------------------------------------COMP "IRDY" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 6.442ns | 4"CLK" | | |--------------------------------------------------------------------------------COMP "IRDY" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.432ns | 1P "CLK" | | |--------------------------------------------------------------------------------COMP "DEVSEL" OFFSET = IN 7 nS BEFORE CO | 7.000ns | 3.800ns | 3MP "CLK" | | |--------------------------------------------------------------------------------COMP "DEVSEL" OFFSET = OUT 11 nS AFTER C | 11.000ns | 9.432ns | 1OMP "CLK" | | |--------------------------------------------------------------------------------COMP "TRDY" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 6.473ns | 3"CLK" | | |--------------------------------------------------------------------------------COMP "TRDY" OFFSET = OUT 10 nS AFTER COM | 10.000ns | 9.435ns | 1P "CLK" | | |--------------------------------------------------------------------------------COMP "STOP" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 5.665ns | 3"CLK" | | |--------------------------------------------------------------------------------COMP "STOP" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.432ns | 1P "CLK" | | |--------------------------------------------------------------------------------COMP "PAR" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 4.610ns | 4"CLK" | | |--------------------------------------------------------------------------------COMP "PAR" OFFSET = OUT 11 nS AFTER COMP | 11.000ns | 9.434ns | 1"CLK" | | |--------------------------------------------------------------------------------COMP "PERR" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 2.145ns | 2"CLK" | | |--------------------------------------------------------------------------------COMP "PERR" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.434ns | 1P "CLK" | | |--------------------------------------------------------------------------------TIMEGRP "PCI_AD" OFFSET = IN 7 nS BEFORE | 7.000ns | 2.762ns | 1COMP "CLK" | | |--------------------------------------------------------------------------------TIMEGRP "PCI_AD" OFFSET = OUT 11 nS AFTE | 11.000ns | 9.540ns | 1R COMP "CLK" | | |--------------------------------------------------------------------------------TIMEGRP "PCI_CBE" OFFSET = IN 7 nS BEFOR | 7.000ns | 5.437ns | 4E COMP "CLK" | | |--------------------------------------------------------------------------------TIMEGRP "PCI_CBE" OFFSET = OUT 11 nS AFT | 11.000ns | 9.435ns | 1ER COMP "CLK" | | |--------------------------------------------------------------------------------All constraints were met.Dumping design to file pci_crt.ncd.All signals are completely routed.Total REAL time to PAR completion: 7 mins 13 secsTotal CPU time to PAR completion: 6 mins 10 secsPlacement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - No errors found.PAR done.==================================================trce pci_crt.ncd pci_crt.pcf -e 3 -o pci_crt.twr -xml pci_crt_trce.xmlRelease 3.3.08i - Trace D.27Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.Loading design for application trce from file pci_crt.ncd."TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5Loading device for application trce from file 'v150.nph' in environmentC:/Foundation.--------------------------------------------------------------------------------Xilinx TRACE, Version D.27Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.trce pci_crt.ncd pci_crt.pcf -e 3 -o pci_crt.twr -xml pci_crt_trce.xmlDesign file: pci_crt.ncdPhysical constraint file: pci_crt.pcfDevice,speed: xc2s150,-5 (PRELIMINARY 1.21 2001-04-09)Report level: error report--------------------------------------------------------------------------------Timing summary:---------------Timing errors: 0 Score: 0Constraints cover 97754 paths, 0 nets, and 8987 connections (91.8% coverage)Design statistics:Minimum period: 23.360ns (Maximum frequency: 42.808MHz)Maximum path delay from/to any node: 21.603nsMinimum input arrival time before clock: 9.535nsMinimum output required time after clock: 9.540nsAnalysis completed Tue Jan 15 13:36:48 2002--------------------------------------------------------------------------------Total time: 1 mins 6 secs==================================================ngdanno pci_crt.ncdRelease 3.3.08i - ngdanno D.27Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.Loading design for application ngdanno from file pci_crt.ncd."TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5Loading device for application ngdanno from file 'v150.nph' in environmentC:/Foundation.Loading constraints from file "pci_crt.pcf"...WARNING:Anno:12 - Since the .ngm file was not specified, the .nga will becreated from the .ncd.Building NGA image...Annotating NGA image...Distributing delays...Resolving logical and physical hierarchies...Running NGD DRC...WARNING:Ngd:333 - NOTE: This design contains the undriven net "GSR" which youcould drive during simulation to get valid results.WARNING:Ngd:333 - NOTE: This design contains the undriven net "GTS" which youcould drive during simulation to get valid results.Writing .nga file "pci_crt.nga"...1476 physical models annotated==================================================ngd2ver -w pci_crt.nga pci_crt_time_sim.vRelease 3.3.08i - ngd2ver D.27Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.--- Initializing ...--- Reading pci_crt.nga.--- Running prep.--- Initializing module list.--- Processing netlist ...WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[10] not found forwire bus bridge/pciu_err_addr_out[31:0] on block TOP.WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[9] not found forwire bus bridge/pciu_err_addr_out[31:0] on block TOP.WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[8] not found forwire bus bridge/pciu_err_addr_out[31:0] on block TOP.WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[7] not found forwire bus bridge/pciu_err_addr_out[31:0] on block TOP.WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[6] not found forwire bus bridge/pciu_err_addr_out[31:0] on block TOP.WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[5] not found forwire bus bridge/pciu_err_addr_out[31:0] on block TOP.WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[4] not found forwire bus bridge/pciu_err_addr_out[31:0] on block TOP.WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[3] not found forwire bus bridge/pciu_err_addr_out[31:0] on block TOP.WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[2] not found forwire bus bridge/pciu_err_addr_out[31:0] on block TOP.WARNING:NetListWriters:107 - Signal bus bridge/pciu_err_addr_out[31:0] on blockTOP is not reconstructed.WARNING:NetListWriters:106 - Wirebridge/pci_target_unit/pcit_if_pciw_fifo_control_out[1] not found for wirebus bridge/pci_target_unit/pcit_if_pciw_fifo_control_out[2:0] on block TOP.WARNING:NetListWriters:107 - Signal busbridge/pci_target_unit/pcit_if_pciw_fifo_control_out[2:0] on block TOP is notreconstructed.WARNING:NetListWriters:106 - Wirebridge/pci_target_unit/fifos_pciw_control_out[1] not found for wire busbridge/pci_target_unit/fifos_pciw_control_out[2:0] on block TOP.WARNING:NetListWriters:107 - Signal busbridge/pci_target_unit/fifos_pciw_control_out[2:0] on block TOP is notreconstructed.--- Generating ngd2ver output file(s) ...--- Writing sdf file pci_crt_time_sim.sdf.--- Writing netlist file pci_crt_time_sim.v.WARNING:NetListWriters:108 - In order to compile this verilog filesuccessfully, please add $XILINX/verilog/src/glbl.v to your compile command.--- ngd2ver is done !==================================================xcpy pci_crt_time_sim.v f:\mihad\fpga_t~1\pci_crt\pci_crt_time_sim.v==================================================xcpy pci_crt_time_sim.sdf f:\mihad\fpga_t~1\pci_crt\pci_crt_time_sim.sdf==================================================bitgen pci_crt.ncd -l -w -f bitgen.utRelease 3.3.08i - Bitgen D.27Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.Loading design for application Bitgen from file pci_crt.ncd."TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5Loading device for application Bitgen from file 'v150.nph' in environmentC:/Foundation.Opened constraints file pci_crt.pcf.Tue Jan 15 13:40:02 2002Running DRC.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA0 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA1 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA2 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA3 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA6 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA7 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA8 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA9 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA10 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA11 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA12 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA13 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA14 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA15 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB5 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB6 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB7 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB8 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB9 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB10 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB11 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB12 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB13 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB14 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB15 of compbridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is notconnected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB0 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB1 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB2 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB3 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB4 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB5 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB6 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB7 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB8 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB9 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB10 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB11 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB12 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB13 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB14 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB15 of compCRT/ssvga_fifo/ramb4_s8_0 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB0 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB1 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB2 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB3 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB4 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB5 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB6 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB7 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB8 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB9 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB10 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB11 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB12 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB13 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB14 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB15 of compCRT/ssvga_fifo/ramb4_s8_1 is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB0 of compCRT/ssvga_pallete is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB1 of compCRT/ssvga_pallete is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB2 of compCRT/ssvga_pallete is not connected.WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB3 of compCRT/ssvga_pallete is not connected.DRC detected 0 errors and 61 warnings.Saving ll file in "pci_crt.ll".Creating bit map...Saving bit stream in "pci_crt.bit".==================================================xcpy pci_crt.bit f:\mihad\fpga_t~1\pci_crt\pci_crt.bit==================================================xcpy pci_crt.ll f:\mihad\fpga_t~1\pci_crt\pci_crt.ll