Subversion Repositories pci

JDF F
// Created by Project Navigator ver 1.0
PROJECT ise-openpci
DESIGN ise-openpci Normal
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 0
DEVPKG fg456
DEVPKGTIME 1048677217
DEVSPEED -6
DEVSPEEDTIME 1048677217
FLOW XST Verilog
FLOWTIME 0
MODULE ..\apps\crt\rtl\verilog\top.v
MODSTYLE TOP Normal
DEPASSOC TOP pci_crt.ucf SYSTEM
[Normal]
p_xstVeriIncludeDir=xstvlg, spartan2, Schematic.t_synthesize, 1048675664, "..\apps\crt\rtl\verilog ..\rtl\verilog"
p_xstVeriSearchPath=xstvlg, spartan2, Schematic.t_synthesize, 1048676602, "..\apps\crt\rtl\verilog ..\rtl\verilog"
[STRATEGY-LIST]
Normal=True