URL
https://opencores.org/ocsvn/pci/pci/trunk
Subversion Repositories pci
[/] [pci/] [tags/] [rel_WB_B3/] [sim/] [rtl_sim/] [log/] [example_pci_tb.log] - Rev 154
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************************ PCI IP Core Testbench Test results *****************************************************************************************************************At time 98835000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 99300000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 99735000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 100200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 101595000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 102165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 102825000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 103515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 104175000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 105700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 105700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 105700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 105700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 106300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 107700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 107700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 107700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 107700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 108300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 111300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 111300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 111300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 111300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 112000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 112635000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 113220000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 113820000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 114825000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 115420000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 117105000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 117580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 118005000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 118480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 119895000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 120465000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 121125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 121815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 122475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 124000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 124000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 124000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 124000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 124600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 126000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 126000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 126000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 126000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 126600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 129600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 129600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 129600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 129600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 130300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 130935000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 131520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 132120000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 133125000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 133720000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 135405000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 135880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 136305000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 136780000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 138195000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 138765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 139425000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 140115000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 140775000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 142300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 142300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 142300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 142300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 142900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 144300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 144300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 144300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 144300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 144900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 147900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 147900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 147900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 147900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 148600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 149235000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 149820000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 150420000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 151425000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 152020000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 153400000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 153500000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 153700000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 154580000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 154680000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 154780000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 154880000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 155240000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 155360000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 155480000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 155600000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 158145000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 158460000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 158540000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 158820000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 159945000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 161080000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 161800000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 162060000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 166180000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 166440000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 167880000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 168160000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 169780000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 170040000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 171855000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 172185000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 172700000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 172980000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 173260000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 173520000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 174435000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 174720000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 175260000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 175540000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 177645000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 177940000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 178480000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 178560000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 179320000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 180060000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 180940000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 181200000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 181480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 181960000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 182800000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 183060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 184320000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 185540000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 185820000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 187080000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 187725000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 188020000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 188560000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 188820000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 189480000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 192945000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 193300000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 193995000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 194340000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 194955000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 195400000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 196360000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 196520000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 196800000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 197280000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 197660000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 198240000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 198420000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 198700000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 199180000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 200140000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 200400000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 200680000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 201375000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 201660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 202275000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 202605000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 202900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 203385000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 203580000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 203860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 204340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 204887000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 205080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 205360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 205840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 206445000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 206640000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 206920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 207400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 207885000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 208080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 208360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 208840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 209325000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 209520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 209800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 210280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 210975000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 211160000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 211440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 211920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 212535000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 212865000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 213160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 213645000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 213840000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 214120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 214635000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 214820000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 215100000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 215580000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 217065000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 217260000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 217540000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 218020000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 218925000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 219120000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 219400000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 219880000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 222945000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 223185000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 223425000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 223935000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 224205000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 224445000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 225075000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 225315000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 225945000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 226515000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 226905000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 227625000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 227865000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 228705000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 231615000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 231885000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 232305000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 232725000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 241515000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 260520000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 261420000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 266020000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 266820000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 267520000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 268660000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 270060000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 270660000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 277840000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 278620000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 279400000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 280395000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 284080000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 284920000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 285820000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 286600000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 287200000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 318495000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 319040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 319515000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 320040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 321465000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 322095000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 322725000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 323415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 324105000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 325680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 325680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 325680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 325680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 326380000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 327780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 327780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 327780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 327780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 328480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 331480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 331480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 331480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 331480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 332180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 332805000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 333400000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 334000000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 334995000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 335580000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 337305000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 337840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 338295000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 338840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 340275000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 340875000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 341535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 342225000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 342885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 344480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 344480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 344480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 344480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 345180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 346580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 346580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 346580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 346580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 347280000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 350280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 350280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 350280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 350280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 350980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 351615000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 352200000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 352800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 353805000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 354400000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 356115000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 356660000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 357135000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 357660000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 359085000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 359715000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 360345000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 361035000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 361725000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 363300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 363300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 363300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 363300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 364000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 365400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 365400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 365400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 365400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 366100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 369100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 369100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 369100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 369100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 369800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 370425000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 371020000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 371620000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 372615000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 373200000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 374580000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 374680000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 374880000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 375760000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 375860000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 375960000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 376060000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 376420000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 376540000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 376660000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 376780000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 379335000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 379680000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 379760000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 380040000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 381165000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 382300000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 383020000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 383280000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 387500000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 387780000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 389320000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 389580000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 391200000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 391480000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 393315000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 393675000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 394140000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 394420000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 394680000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 394960000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 395925000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 396220000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 396760000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 397020000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 399195000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 399480000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 400020000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 400100000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 400860000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 401640000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 402520000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 402780000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 403060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 403540000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 404380000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 404640000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 406000000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 407320000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 407580000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 408940000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 409575000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 409860000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 410400000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 410680000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 411340000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 414825000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 415180000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 415905000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 416260000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 416895000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 417340000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 418300000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 418460000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!*****************************************************************************************...*****************************************************************************************At time 1960240000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1961700000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1961820000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1962020000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1963060000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1963180000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1963280000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1963380000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1963800000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1963940000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1964060000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1964180000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1966935000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1967300000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1967380000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1967660000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1968885000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1970120000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1970900000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1971180000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1975460000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1975760000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1977320000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1977620000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1979240000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1979540000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1981455000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1981845000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1982360000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1982660000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1982960000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1983260000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1984335000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1984640000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1985240000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1985540000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1987755000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1988060000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1988660000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1988740000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1989540000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1990340000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1991360000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1991660000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1991960000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1992480000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1993360000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1993640000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1995020000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1996260000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1996560000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1997920000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1998585000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1998900000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1999500000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1999800000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2000480000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!*****************************************************************************************...*****************************************************************************************At time 5175780000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5176900000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5177220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5177640000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5179380000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5179720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5180040000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5180380000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5180780000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5181255000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5181320000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5184680000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5187690000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5190200000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5193210000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5195160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5195500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5195580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5196360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!*****************************************************************************************...*****************************************************************************************At time 35435595000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35435805000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35436615000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35437060000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35442465000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35445045000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35446240000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35450840000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35453520000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!************************************************************************************************************************ PCI Testcase summary *******************************Tests performed: 36000Failed tests : 0Successfull tests: 36000******************************* PCI Testcase summary *******************************