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[/] [pci/] [tags/] [working_demo/] [rtl/] [verilog/] [io_mux_load_mux.v] - Rev 154
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////////////////////////////////////////////////////////////////////// //// //// //// File name "io_mux_load_mux.v" //// //// //// //// This file is part of the "PCI bridge" project //// //// http://www.opencores.org/cores/pci/ //// //// //// //// Author(s): //// //// - Miha Dolenc (mihad@opencores.org) //// //// //// //// All additional information is avaliable in the README //// //// file. //// //// //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.1.1.1 2001/10/02 15:33:46 mihad // New project directory structure // // // this module is provided for downsizing fanout of critical logic cells, which use heavily constrained // pci inputs - if target is driving ad lines it is also responsible for clock enables of output // flip flops - otherwise master controls clock enable of output flip flops. `include "timescale.v" module IO_MUX_LOAD_MUX ( tar_ad_en_reg_in, mas_ad_load_in, tar_ad_load_in, ad_load_out ); input tar_ad_en_reg_in ; input mas_ad_load_in ; input tar_ad_load_in ; output ad_load_out ; assign ad_load_out = tar_ad_en_reg_in ? tar_ad_load_in : mas_ad_load_in ; endmodule