Subversion Repositories pci

ncvlog: v03.30.(p001): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc.
ncvlog: v03.30.(p001): Started on Jul 08, 2001 at 11:28:41
ncvlog
    -f ./ncvlog.args
        -cdslib ../bin/cds.lib
        -hdlvar ../bin/hdl.var
        -logfile ../log/ncvlog.log
        -update
        -messages
        -INCDIR ../../../bench/verilog
        -INCDIR ../../../rtl/verilog
        ../../../rtl/verilog/pci_parity_check.v
        ../../../rtl/verilog/pci_target_unit.v
        ../../../rtl/verilog/wb_addr_mux.v
        ../../../rtl/verilog/cbe_en_crit.v
        ../../../rtl/verilog/fifo_control.v
        ../../../rtl/verilog/out_reg.v
        ../../../rtl/verilog/pci_tpram.v
        ../../../rtl/verilog/wb_master.v
        ../../../rtl/verilog/conf_cyc_addr_dec.v
        ../../../rtl/verilog/frame_crit.v
        ../../../rtl/verilog/pci_target32_clk_en.v
        ../../../rtl/verilog/pciw_fifo_control.v
        ../../../rtl/verilog/wb_slave.v
        ../../../rtl/verilog/conf_space.v
        ../../../rtl/verilog/frame_en_crit.v
        ../../../rtl/verilog/par_crit.v
        ../../../rtl/verilog/pciw_pcir_fifos.v
        ../../../rtl/verilog/wb_slave_unit.v
        ../../../rtl/verilog/frame_load_crit.v
        ../../../rtl/verilog/pci_bridge32.v
        ../../../rtl/verilog/pci_target32_devs_crit.v
        ../../../rtl/verilog/perr_crit.v
        ../../../rtl/verilog/wbr_fifo_control.v
        ../../../rtl/verilog/cur_out_reg.v
        ../../../rtl/verilog/pci_decoder.v
        ../../../rtl/verilog/pci_target32_interface.v
        ../../../rtl/verilog/perr_en_crit.v
        ../../../rtl/verilog/wbw_fifo_control.v
        ../../../rtl/verilog/decoder.v
        ../../../rtl/verilog/pci_in_reg.v
        ../../../rtl/verilog/serr_crit.v
        ../../../rtl/verilog/wbw_wbr_fifos.v
        ../../../rtl/verilog/delayed_sync.v
        ../../../rtl/verilog/irdy_out_crit.v
        ../../../rtl/verilog/pci_io_mux.v
        ../../../rtl/verilog/pci_io_mux_ad_en_crit.v
        ../../../rtl/verilog/pci_io_mux_ad_load_crit.v
        ../../../rtl/verilog/pci_target32_sm.v
        ../../../rtl/verilog/serr_en_crit.v
        ../../../rtl/verilog/delayed_write_reg.v
        ../../../rtl/verilog/mas_ad_en_crit.v
        ../../../rtl/verilog/mas_ad_load_crit.v
        ../../../rtl/verilog/pci_master32_sm.v
        ../../../rtl/verilog/pci_target32_stop_crit.v
        ../../../rtl/verilog/synchronizer_flop.v
        ../../../rtl/verilog/async_reset_flop.v
        ../../../rtl/verilog/mas_ch_state_crit.v
        ../../../rtl/verilog/pci_master32_sm_if.v
        ../../../rtl/verilog/pci_target32_trdy_crit.v
        ../../../rtl/verilog/top.v
        ../../../rtl/verilog/pci_rst_int.v
        ../../../rtl/verilog/sync_module.v
        ../../../rtl/verilog/wb_tpram.v
        ../../../bench/verilog/wb_master32.v
        ../../../bench/verilog/wb_master_behavioral.v
        ../../../bench/verilog/system.v
        ../../../bench/verilog/pci_blue_arbiter.v
        ../../../bench/verilog/pci_bus_monitor.v
        ../../../bench/verilog/pci_behaviorial_device.v
        ../../../bench/verilog/pci_behaviorial_master.v
        ../../../bench/verilog/pci_behaviorial_target.v
        ../../../bench/verilog/wb_slave_behavioral.v
        ../../../bench/verilog/wb_bus_mon.v
        ../../../bench/verilog/pci_behavioral_iack_target.v
        ../../../bench/verilog/pci_unsupported_commands_master.v
        ../../../../../../lib/xilinx/lib/glbl/glbl.v
        ../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
        ../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v

file: ../../../rtl/verilog/pci_parity_check.v
        module worklib.PCI_PARITY_CHECK:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_target_unit.v
        module worklib.PCI_TARGET_UNIT:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/wb_addr_mux.v
        module worklib.WB_ADDR_MUX:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/cbe_en_crit.v
        module worklib.CBE_EN_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/fifo_control.v
        module worklib.FIFO_CONTROL:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/out_reg.v
        module worklib.OUT_REG:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_tpram.v
        module worklib.PCI_TPRAM:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/wb_master.v
        module worklib.WB_MASTER:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/conf_cyc_addr_dec.v
        module worklib.CONF_CYC_ADDR_DEC:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/frame_crit.v
        module worklib.FRAME_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_target32_clk_en.v
        module worklib.PCI_TARGET32_CLK_EN:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pciw_fifo_control.v
        module worklib.PCIW_FIFO_CONTROL:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/wb_slave.v
        module worklib.WB_SLAVE:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/conf_space.v
        module worklib.CONF_SPACE:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/frame_en_crit.v
        module worklib.FRAME_EN_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/par_crit.v
        module worklib.PAR_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pciw_pcir_fifos.v
        module worklib.PCIW_PCIR_FIFOS:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/wb_slave_unit.v
        module worklib.WB_SLAVE_UNIT:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/frame_load_crit.v
        module worklib.FRAME_LOAD_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_bridge32.v
        module worklib.PCI_BRIDGE32:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_target32_devs_crit.v
        module worklib.PCI_TARGET32_DEVS_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/perr_crit.v
        module worklib.PERR_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/wbr_fifo_control.v
        module worklib.WBR_FIFO_CONTROL:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/cur_out_reg.v
        module worklib.CUR_OUT_REG:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_decoder.v
        module worklib.PCI_DECODER:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_target32_interface.v
        module worklib.PCI_TARGET32_INTERFACE:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/perr_en_crit.v
        module worklib.PERR_EN_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/wbw_fifo_control.v
        module worklib.WBW_FIFO_CONTROL:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/decoder.v
        module worklib.DECODER:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_in_reg.v
        module worklib.PCI_IN_REG:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/serr_crit.v
        module worklib.SERR_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/wbw_wbr_fifos.v
        module worklib.WBW_WBR_FIFOS:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/delayed_sync.v
        module worklib.DELAYED_SYNC:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/irdy_out_crit.v
        module worklib.IRDY_OUT_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_io_mux.v
        module worklib.PCI_IO_MUX:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_io_mux_ad_en_crit.v
        module worklib.PCI_IO_MUX_AD_EN_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_io_mux_ad_load_crit.v
        module worklib.PCI_IO_MUX_AD_LOAD_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_target32_sm.v
        module worklib.PCI_TARGET32_SM:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/serr_en_crit.v
        module worklib.SERR_EN_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/delayed_write_reg.v
        module worklib.DELAYED_WRITE_REG:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/mas_ad_en_crit.v
        module worklib.MAS_AD_EN_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/mas_ad_load_crit.v
        module worklib.MAS_AD_LOAD_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_master32_sm.v
        module worklib.PCI_MASTER32_SM:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_target32_stop_crit.v
        module worklib.PCI_TARGET32_STOP_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/synchronizer_flop.v
        module worklib.synchronizer_flop:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/async_reset_flop.v
        module worklib.async_reset_flop:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/mas_ch_state_crit.v
        module worklib.MAS_CH_STATE_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_master32_sm_if.v
        module worklib.PCI_MASTER32_SM_IF:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_target32_trdy_crit.v
        module worklib.PCI_TARGET32_TRDY_CRIT:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/top.v
        module worklib.TOP:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/pci_rst_int.v
        module worklib.PCI_RST_INT:v
                errors: 0, warnings: 0
file: ../../../rtl/verilog/sync_module.v
        module worklib.SYNC_MODULE:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../rtl/verilog/wb_tpram.v
        module worklib.WB_TPRAM:v
                errors: 0, warnings: 0
file: ../../../bench/verilog/wb_master32.v
        module worklib.WB_MASTER32:v
                errors: 0, warnings: 0
file: ../../../bench/verilog/wb_master_behavioral.v
        module worklib.WB_MASTER_BEHAVIORAL:v
                errors: 0, warnings: 0
file: ../../../bench/verilog/system.v
        module worklib.SYSTEM:v
                errors: 0, warnings: 0
file: ../../../bench/verilog/pci_blue_arbiter.v
        module worklib.pci_blue_arbiter:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../bench/verilog/pci_bus_monitor.v
        module worklib.pci_bus_monitor:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../bench/verilog/pci_behaviorial_device.v
        module worklib.pci_behaviorial_device:v (up-to-date)
                errors: 0, warnings: 0
        module worklib.delayed_test_pad:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../bench/verilog/pci_behaviorial_master.v
        module worklib.pci_behaviorial_master:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../bench/verilog/pci_behaviorial_target.v
        module worklib.pci_behaviorial_target:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../bench/verilog/wb_slave_behavioral.v
        module worklib.WB_SLAVE_BEHAVIORAL:v
                errors: 0, warnings: 0
file: ../../../bench/verilog/wb_bus_mon.v
        module worklib.WB_BUS_MON:v
                errors: 0, warnings: 0
file: ../../../bench/verilog/pci_behavioral_iack_target.v
        module worklib.PCI_BEHAVIORAL_IACK_TARGET:v
                errors: 0, warnings: 0
file: ../../../bench/verilog/pci_unsupported_commands_master.v
        module worklib.pci_unsupported_commands_master:v
                errors: 0, warnings: 0
file: ../../../../../../lib/xilinx/lib/glbl/glbl.v
        module worklib.glbl:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
        module worklib.RAMB4_S16_S16:v (up-to-date)
                errors: 0, warnings: 0
file: ../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v
        module worklib.RAM16X1D:v (up-to-date)
                errors: 0, warnings: 0
ncvlog: v03.30.(p001): Exiting on Jul 08, 2001 at 11:28:46  (total: 00:00:05)