Subversion Repositories pci

/* Enable Verilog HDL preprocessor */
hdlin_enable_vpp = true

/* Set log path */
LOG_PATH = "../logs/"

/* Set gate-level netlist path */
GATE_PATH = "../gate/"

/* Set RAMS_PATH */
RAMS_PATH = "../../lib/"

/* Set RTL source path */
RTL_PATH = "../../rtl/verilog/"

/* Optimize adders */
synlib_model_map_effort = high
hlo_share_effort = medium