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URL https://opencores.org/ocsvn/pci/pci/trunk

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[/] [pci/] [trunk/] [syn/] [scr/] [set_env.inc] - Rev 154

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/* Enable Verilog HDL preprocessor */
hdlin_enable_vpp = true

/* Set log path */
LOG_PATH = "../logs/"

/* Set gate-level netlist path */
GATE_PATH = "../gate/"

/* Set RAMS_PATH */
RAMS_PATH = "../../lib/"

/* Set RTL source path */
RTL_PATH = "../../rtl/verilog/"

/* Optimize adders */
synlib_model_map_effort = high
hlo_share_effort = medium

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