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<b><font size=+2 face="Helvetica, Arial"color=#bf0000>Project Name: PCI bridge</font></b>
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<a href="http://www.opencores.org/cores/pci/index.shtml">Introduction</a>               |
<a href="http://www.opencores.org/cores/pci/documentation.shtml">Documentation</a>               |
<a href="http://www.opencores.org/cores/pci/charact.shtml">Characteristics</a>               |
<a href="http://www.opencores.org/cores/pci/current_stat.shtml">Current Status</a>               |
<a href="http://www.opencores.org/cores/pci/todo_list.shtml">To Do list</a>               |
<a href="http://www.opencores.org/cores/pci/test_app.shtml">Test Application</a>               |
<a href="http://www.opencores.org/cores/pci/download.shtml">Download</a>               |
<a href="http://www.opencores.org/cores/pci/testbench.shtml">Testbench</a>               |
<a href="http://www.opencores.org/cores/pci/references.shtml">References</a>               |
<a href="http://www.opencores.org/cores/pci/links.shtml">Links</a>               |
<a href="mailto:pci@opencores.org">Mailing list</a>               |
<a href="http://www.opencores.org/cores/pci/contacts.shtml">Contacts</a>    
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<p><center><font color="#bf0000" size=+3><b>Current Status</b></font></center>
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<b>Current Status:<br>
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<ul>
<li>Most of RTL design for 32-bit PCI bridge done. Sources available via CVS.</li>
<li>Design synthesized and tested with Insight's PCI development kit (Spartan II 150k gates, speed grade -5).</li>
<li>Sample application, bit-stream for Insight's kit etc. also available via CVS.</li>
<li>Specification is updated (there have been some minor changes).</li>
<li>Working on verification suite (PCI BFMs).</li>
<li>Design document will be done after verification suite is finished.</li>
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<b>Available Blocks on the opencores CVS:<br>
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<li>Verilog RTL sources for 32-bit PCI to WISHBONE bridge.</li>
<li>Verilog RTL sources for sample application.</li>
<li>Bit-stream and timing simulation models for sample application (Can be tested with Insight's PCI development kit).</li>
<li>Also look at PCI blue interface project - its simulation models will probably be used in this project too (thanks to Blue Beaver).</li>
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