Subversion Repositories pci

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<b><font size=+2 face="Helvetica, Arial"color=#bf0000>Project Name: PCI bridge</font></b>
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<a href="http://www.opencores.org/cores/pci/index.shtml">Introduction</a>               |
<a href="http://www.opencores.org/cores/pci/documentation.shtml">Documentation</a>               |
<a href="http://www.opencores.org/cores/pci/charact.shtml">Characteristics</a>               |
<a href="http://www.opencores.org/cores/pci/current_stat.shtml">Current Status</a>               |
<a href="http://www.opencores.org/cores/pci/todo_list.shtml">To Do list</a>               |
<a href="http://www.opencores.org/cores/pci/test_app.shtml">Test Application</a>               |
<a href="http://www.opencores.org/cores/pci/download.shtml">Download</a>               |
<a href="http://www.opencores.org/cores/pci/testbench.shtml">Testbench</a>               |
<a href="http://www.opencores.org/cores/pci/references.shtml">References</a>               |
<a href="http://www.opencores.org/cores/pci/links.shtml">Links</a>               |
<a href="mailto:pci@opencores.org">Mailing list</a>               |
<a href="http://www.opencores.org/cores/pci/contacts.shtml">Contacts</a>    
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<p><center><font color="#bf0000" size=+3><b>Documentation</b></font></center>
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<b>Summary<br>
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<br>
The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI 
local bus. It consists of two independent units, one handling transactions originating on the 
PCI bus, the other one handling transactions originating on the WISHBONE bus.  
<br><br>  
The core has been designed to offer as much flexibility as possible to all kinds of applications.
The following lists the main features of the PCI IP core:
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<li type=circle>32-bit PCI interface
<li type=circle>Fully PCI 2.2 compliant (with 66 MHz PCI specification)
<li type=circle>Separated initiator and target functional blocks 
<li type=circle>Supported initiator commands and functions:
<li type=disc>   Memory Read, Memory Write
<li type=disc>   Memory Read Multiple (MRM)
<li type=disc>   Memory Read Line (MRL)
<li type=disc>   I/O Read, I/O Write
<li type=disc>   Configuration Read, Configuration Write
<li type=disc>   Bus Parking
<li type=disc>   Interrupt Acknowledge
<li type=disc>   Host Bridging
<li type=circle>Supported target commands and functions:
<li type=disc>   Type 0 Configuration Space Header<br> 
	(Type 0 is used to configure agents on the same bus segment)<br>
	(Type 1 is used to configure across PCI-to-PCI bridges) 
<li type=disc>   Parity Generation (PAR), Parity Error Detection (PERR# and SERR#)
<li type=disc>   Memory Read, Memory Write
<li type=disc>   Memory Read Multiple (MRM)
<li type=disc>   Memory Read Line (MRL)
<li type=disc>   Memory Write and Invalidate (MWI)
<li type=disc>   I/O Read, I/O Write
<li type=disc>   Configuration Read, Configuration Write
<li type=disc>   Target Abort, Target Retry, Target Disconnect
<li type=disc>   Full Command/Status registers
<li type=circle>WISHBONE SoC Interconnection Rev. B compliant interface on processor side (master with Target PCI and slave with Initiator PCI interface)
<li type=circle>Configurable on-chip FIFOs 
</ul>
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A detailed PCI IP Core Spcification is available on the following link:<br>
<h3><a href="http://www.opencores.org/cgi-bin/cvsget.cgi/pci/doc/pci_specification.pdf">PCI
Bridge IP Core Specification, Rev 0.5</a> (616 kB) PDF document</h3>
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