Subversion Repositories pci

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<b><font size=+2 face="Helvetica, Arial"color=#bf0000>Project Name: PCI bridge</font></b>
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<a href="http://www.opencores.org/cores/pci/index.shtml">Introduction</a>               |
<a href="http://www.opencores.org/cores/pci/documentation.shtml">Documentation</a>               |
<a href="http://www.opencores.org/cores/pci/charact.shtml">Characteristics</a>               |
<a href="http://www.opencores.org/cores/pci/current_stat.shtml">Current Status</a>               |
<a href="http://www.opencores.org/cores/pci/todo_list.shtml">To Do list</a>               |
<a href="http://www.opencores.org/cores/pci/test_app.shtml">Test Application</a>               |
<a href="http://www.opencores.org/cores/pci/download.shtml">Download</a>               |
<a href="http://www.opencores.org/cores/pci/testbench.shtml">Testbench</a>               |
<a href="http://www.opencores.org/cores/pci/references.shtml">References</a>               |
<a href="http://www.opencores.org/cores/pci/links.shtml">Links</a>               |
<a href="mailto:pci@opencores.org">Mailing list</a>               |
<a href="http://www.opencores.org/cores/pci/contacts.shtml">Contacts</a>    
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<p><center><font color="#bf0000" size=+3><b>To Do list</b></font></center>
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<b>PCI Behavioral Models and PCI bus Monitor<br>
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<br>We start using the PCI BFMs written by Blue Beaver. This BFMs support only MEMORY READ/WRITE
and CONFIG READ/WRITE commands.
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<b>Synchronous clock operation<br>
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<br>There should be added one more DEFINE for synchronous clock operation between PCI and WISHBONE
buses. This is usefull in FPGAs to use less slices when an application does not require different 
bus clock domains.
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<b>Design document<br>
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<br>After finishing the testbench, we will write the design document describing the PCI core structure
and all defines that can be (an why) changed by an user.
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