Subversion Repositories pcie_ds_dma

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2006 12 26 11 0 53)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.2.03i; Cores Update # 2"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2006 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_rd_freq = 100 ")
       (comment "c_wr_response_latency = 1 ")
       (comment "c_has_srst = 0 ")
       (comment "c_has_rd_data_count = 1 ")
       (comment "c_din_width = 65 ")
       (comment "c_has_wr_data_count = 1 ")
       (comment "InstanceName = ctrl_fifo1024x65_v5 ")
       (comment "c_implementation_type = 2 ")
       (comment "c_family = spartan3 ")
       (comment "c_has_wr_rst = 0 ")
       (comment "c_wr_freq = 100 ")
       (comment "c_underflow_low = 0 ")
       (comment "c_has_meminit_file = 0 ")
       (comment "c_has_overflow = 0 ")
       (comment "c_preload_latency = 1 ")
       (comment "c_dout_width = 65 ")
       (comment "c_rd_depth = 1024 ")
       (comment "c_default_value = BlankString ")
       (comment "c_mif_file_name = BlankString ")
       (comment "c_has_underflow = 0 ")
       (comment "c_has_rd_rst = 0 ")
       (comment "c_has_almost_full = 0 ")
       (comment "c_has_rst = 1 ")
       (comment "c_data_count_width = 10 ")
       (comment "c_has_wr_ack = 0 ")
       (comment "c_wr_ack_low = 0 ")
       (comment "c_common_clock = 0 ")
       (comment "c_rd_pntr_width = 10 ")
       (comment "c_has_almost_empty = 0 ")
       (comment "c_rd_data_count_width = 1 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_wr_pntr_width = 10 ")
       (comment "c_overflow_low = 0 ")
       (comment "c_prog_empty_type = 1 ")
       (comment "c_optimization_mode = 0 ")
       (comment "c_wr_data_count_width = 1 ")
       (comment "c_preload_regs = 0 ")
       (comment "c_dout_rst_val = 0 ")
       (comment "c_has_data_count = 0 ")
       (comment "c_prog_full_thresh_negate_val = 991 ")
       (comment "c_wr_depth = 1024 ")
       (comment "c_prog_empty_thresh_negate_val = 33 ")
       (comment "c_prog_empty_thresh_assert_val = 32 ")
       (comment "c_has_valid = 0 ")
       (comment "c_init_wr_pntr_val = 0 ")
       (comment "c_prog_full_thresh_assert_val = 992 ")
       (comment "c_use_fifo16_flags = 0 ")
       (comment "c_has_backup = 0 ")
       (comment "c_valid_low = 0 ")
       (comment "c_prim_fifo_type = 1kx36 ")
       (comment "c_count_type = 0 ")
       (comment "c_prog_full_type = 1 ")
       (comment "c_memory_type = 1 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
   )
   (external ctrl_fifo1024x65_v5_fifo_generator_v3_2_xst_1_lib (edifLevel 0)
       (technology (numberDefinition))
       (cell ctrl_fifo1024x65_v5_fifo_generator_v3_2_xst_1 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port clk (direction INPUT))
                   (port backup (direction INPUT))
                   (port backup_marker (direction INPUT))
                   (port ( array ( rename din "din<64:0>") 65 ) (direction INPUT))
                   (port ( array ( rename prog_empty_thresh "prog_empty_thresh<9:0>") 10 ) (direction INPUT))
                   (port ( array ( rename prog_empty_thresh_assert "prog_empty_thresh_assert<9:0>") 10 ) (direction INPUT))
                   (port ( array ( rename prog_empty_thresh_negate "prog_empty_thresh_negate<9:0>") 10 ) (direction INPUT))
                   (port ( array ( rename prog_full_thresh "prog_full_thresh<9:0>") 10 ) (direction INPUT))
                   (port ( array ( rename prog_full_thresh_assert "prog_full_thresh_assert<9:0>") 10 ) (direction INPUT))
                   (port ( array ( rename prog_full_thresh_negate "prog_full_thresh_negate<9:0>") 10 ) (direction INPUT))
                   (port rd_clk (direction INPUT))
                   (port rd_en (direction INPUT))
                   (port rd_rst (direction INPUT))
                   (port rst (direction INPUT))
                   (port srst (direction INPUT))
                   (port wr_clk (direction INPUT))
                   (port wr_en (direction INPUT))
                   (port wr_rst (direction INPUT))
                   (port almost_empty (direction OUTPUT))
                   (port almost_full (direction OUTPUT))
                   (port ( array ( rename data_count "data_count<9:0>") 10 ) (direction OUTPUT))
                   (port ( array ( rename dout "dout<64:0>") 65 ) (direction OUTPUT))
                   (port empty (direction OUTPUT))
                   (port full (direction OUTPUT))
                   (port overflow (direction OUTPUT))
                   (port prog_empty (direction OUTPUT))
                   (port prog_full (direction OUTPUT))
                   (port valid (direction OUTPUT))
                   (port ( array ( rename rd_data_count "rd_data_count<0:0>") 1 ) (direction OUTPUT))
                   (port underflow (direction OUTPUT))
                   (port wr_ack (direction OUTPUT))
                   (port ( array ( rename wr_data_count "wr_data_count<0:0>") 1 ) (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell ctrl_fifo1024x65_v5
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( array ( rename din "din<64:0>") 65 ) (direction INPUT))
   (port ( rename rd_clk "rd_clk") (direction INPUT))
   (port ( rename rd_en "rd_en") (direction INPUT))
   (port ( rename rst "rst") (direction INPUT))
   (port ( rename wr_clk "wr_clk") (direction INPUT))
   (port ( rename wr_en "wr_en") (direction INPUT))
   (port ( array ( rename dout "dout<64:0>") 65 ) (direction OUTPUT))
   (port ( rename empty "empty") (direction OUTPUT))
   (port ( rename full "full") (direction OUTPUT))
   (port ( rename prog_empty "prog_empty") (direction OUTPUT))
   (port ( rename prog_full "prog_full") (direction OUTPUT))
   (port ( array ( rename rd_data_count "rd_data_count<0:0>") 1 ) (direction OUTPUT))
   (port ( array ( rename wr_data_count "wr_data_count<0:0>") 1 ) (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU2
      (viewRef view_1 (cellRef ctrl_fifo1024x65_v5_fifo_generator_v3_2_xst_1 (libraryRef ctrl_fifo1024x65_v5_fifo_generator_v3_2_xst_1_lib)))
   )
   (net (rename N5 "din<64>")
    (joined
      (portRef (member din 0))
      (portRef (member din 0) (instanceRef BU2))
    )
   )
   (net (rename N6 "din<63>")
    (joined
      (portRef (member din 1))
      (portRef (member din 1) (instanceRef BU2))
    )
   )
   (net (rename N7 "din<62>")
    (joined
      (portRef (member din 2))
      (portRef (member din 2) (instanceRef BU2))
    )
   )
   (net (rename N8 "din<61>")
    (joined
      (portRef (member din 3))
      (portRef (member din 3) (instanceRef BU2))
    )
   )
   (net (rename N9 "din<60>")
    (joined
      (portRef (member din 4))
      (portRef (member din 4) (instanceRef BU2))
    )
   )
   (net (rename N10 "din<59>")
    (joined
      (portRef (member din 5))
      (portRef (member din 5) (instanceRef BU2))
    )
   )
   (net (rename N11 "din<58>")
    (joined
      (portRef (member din 6))
      (portRef (member din 6) (instanceRef BU2))
    )
   )
   (net (rename N12 "din<57>")
    (joined
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      (portRef (member din 7) (instanceRef BU2))
    )
   )
   (net (rename N13 "din<56>")
    (joined
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    )
   )
   (net (rename N14 "din<55>")
    (joined
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    )
   )
   (net (rename N15 "din<54>")
    (joined
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    )
   )
   (net (rename N16 "din<53>")
    (joined
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      (portRef (member din 11) (instanceRef BU2))
    )
   )
   (net (rename N17 "din<52>")
    (joined
      (portRef (member din 12))
      (portRef (member din 12) (instanceRef BU2))
    )
   )
   (net (rename N18 "din<51>")
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    )
   )
   (net (rename N19 "din<50>")
    (joined
      (portRef (member din 14))
      (portRef (member din 14) (instanceRef BU2))
    )
   )
   (net (rename N20 "din<49>")
    (joined
      (portRef (member din 15))
      (portRef (member din 15) (instanceRef BU2))
    )
   )
   (net (rename N21 "din<48>")
    (joined
      (portRef (member din 16))
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    )
   )
   (net (rename N22 "din<47>")
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    )
   )
   (net (rename N23 "din<46>")
    (joined
      (portRef (member din 18))
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    )
   )
   (net (rename N24 "din<45>")
    (joined
      (portRef (member din 19))
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    )
   )
   (net (rename N25 "din<44>")
    (joined
      (portRef (member din 20))
      (portRef (member din 20) (instanceRef BU2))
    )
   )
   (net (rename N26 "din<43>")
    (joined
      (portRef (member din 21))
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    )
   )
   (net (rename N27 "din<42>")
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      (portRef (member din 22))
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    )
   )
   (net (rename N28 "din<41>")
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    )
   )
   (net (rename N29 "din<40>")
    (joined
      (portRef (member din 24))
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    )
   )
   (net (rename N30 "din<39>")
    (joined
      (portRef (member din 25))
      (portRef (member din 25) (instanceRef BU2))
    )
   )
   (net (rename N31 "din<38>")
    (joined
      (portRef (member din 26))
      (portRef (member din 26) (instanceRef BU2))
    )
   )
   (net (rename N32 "din<37>")
    (joined
      (portRef (member din 27))
      (portRef (member din 27) (instanceRef BU2))
    )
   )
   (net (rename N33 "din<36>")
    (joined
      (portRef (member din 28))
      (portRef (member din 28) (instanceRef BU2))
    )
   )
   (net (rename N34 "din<35>")
    (joined
      (portRef (member din 29))
      (portRef (member din 29) (instanceRef BU2))
    )
   )
   (net (rename N35 "din<34>")
    (joined
      (portRef (member din 30))
      (portRef (member din 30) (instanceRef BU2))
    )
   )
   (net (rename N36 "din<33>")
    (joined
      (portRef (member din 31))
      (portRef (member din 31) (instanceRef BU2))
    )
   )
   (net (rename N37 "din<32>")
    (joined
      (portRef (member din 32))
      (portRef (member din 32) (instanceRef BU2))
    )
   )
   (net (rename N38 "din<31>")
    (joined
      (portRef (member din 33))
      (portRef (member din 33) (instanceRef BU2))
    )
   )
   (net (rename N39 "din<30>")
    (joined
      (portRef (member din 34))
      (portRef (member din 34) (instanceRef BU2))
    )
   )
   (net (rename N40 "din<29>")
    (joined
      (portRef (member din 35))
      (portRef (member din 35) (instanceRef BU2))
    )
   )
   (net (rename N41 "din<28>")
    (joined
      (portRef (member din 36))
      (portRef (member din 36) (instanceRef BU2))
    )
   )
   (net (rename N42 "din<27>")
    (joined
      (portRef (member din 37))
      (portRef (member din 37) (instanceRef BU2))
    )
   )
   (net (rename N43 "din<26>")
    (joined
      (portRef (member din 38))
      (portRef (member din 38) (instanceRef BU2))
    )
   )
   (net (rename N44 "din<25>")
    (joined
      (portRef (member din 39))
      (portRef (member din 39) (instanceRef BU2))
    )
   )
   (net (rename N45 "din<24>")
    (joined
      (portRef (member din 40))
      (portRef (member din 40) (instanceRef BU2))
    )
   )
   (net (rename N46 "din<23>")
    (joined
      (portRef (member din 41))
      (portRef (member din 41) (instanceRef BU2))
    )
   )
   (net (rename N47 "din<22>")
    (joined
      (portRef (member din 42))
      (portRef (member din 42) (instanceRef BU2))
    )
   )
   (net (rename N48 "din<21>")
    (joined
      (portRef (member din 43))
      (portRef (member din 43) (instanceRef BU2))
    )
   )
   (net (rename N49 "din<20>")
    (joined
      (portRef (member din 44))
      (portRef (member din 44) (instanceRef BU2))
    )
   )
   (net (rename N50 "din<19>")
    (joined
      (portRef (member din 45))
      (portRef (member din 45) (instanceRef BU2))
    )
   )
   (net (rename N51 "din<18>")
    (joined
      (portRef (member din 46))
      (portRef (member din 46) (instanceRef BU2))
    )
   )
   (net (rename N52 "din<17>")
    (joined
      (portRef (member din 47))
      (portRef (member din 47) (instanceRef BU2))
    )
   )
   (net (rename N53 "din<16>")
    (joined
      (portRef (member din 48))
      (portRef (member din 48) (instanceRef BU2))
    )
   )
   (net (rename N54 "din<15>")
    (joined
      (portRef (member din 49))
      (portRef (member din 49) (instanceRef BU2))
    )
   )
   (net (rename N55 "din<14>")
    (joined
      (portRef (member din 50))
      (portRef (member din 50) (instanceRef BU2))
    )
   )
   (net (rename N56 "din<13>")
    (joined
      (portRef (member din 51))
      (portRef (member din 51) (instanceRef BU2))
    )
   )
   (net (rename N57 "din<12>")
    (joined
      (portRef (member din 52))
      (portRef (member din 52) (instanceRef BU2))
    )
   )
   (net (rename N58 "din<11>")
    (joined
      (portRef (member din 53))
      (portRef (member din 53) (instanceRef BU2))
    )
   )
   (net (rename N59 "din<10>")
    (joined
      (portRef (member din 54))
      (portRef (member din 54) (instanceRef BU2))
    )
   )
   (net (rename N60 "din<9>")
    (joined
      (portRef (member din 55))
      (portRef (member din 55) (instanceRef BU2))
    )
   )
   (net (rename N61 "din<8>")
    (joined
      (portRef (member din 56))
      (portRef (member din 56) (instanceRef BU2))
    )
   )
   (net (rename N62 "din<7>")
    (joined
      (portRef (member din 57))
      (portRef (member din 57) (instanceRef BU2))
    )
   )
   (net (rename N63 "din<6>")
    (joined
      (portRef (member din 58))
      (portRef (member din 58) (instanceRef BU2))
    )
   )
   (net (rename N64 "din<5>")
    (joined
      (portRef (member din 59))
      (portRef (member din 59) (instanceRef BU2))
    )
   )
   (net (rename N65 "din<4>")
    (joined
      (portRef (member din 60))
      (portRef (member din 60) (instanceRef BU2))
    )
   )
   (net (rename N66 "din<3>")
    (joined
      (portRef (member din 61))
      (portRef (member din 61) (instanceRef BU2))
    )
   )
   (net (rename N67 "din<2>")
    (joined
      (portRef (member din 62))
      (portRef (member din 62) (instanceRef BU2))
    )
   )
   (net (rename N68 "din<1>")
    (joined
      (portRef (member din 63))
      (portRef (member din 63) (instanceRef BU2))
    )
   )
   (net (rename N69 "din<0>")
    (joined
      (portRef (member din 64))
      (portRef (member din 64) (instanceRef BU2))
    )
   )
   (net (rename N130 "rd_clk")
    (joined
      (portRef rd_clk)
      (portRef rd_clk (instanceRef BU2))
    )
   )
   (net (rename N131 "rd_en")
    (joined
      (portRef rd_en)
      (portRef rd_en (instanceRef BU2))
    )
   )
   (net (rename N133 "rst")
    (joined
      (portRef rst)
      (portRef rst (instanceRef BU2))
    )
   )
   (net (rename N135 "wr_clk")
    (joined
      (portRef wr_clk)
      (portRef wr_clk (instanceRef BU2))
    )
   )
   (net (rename N136 "wr_en")
    (joined
      (portRef wr_en)
      (portRef wr_en (instanceRef BU2))
    )
   )
   (net (rename N150 "dout<64>")
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      (portRef (member dout 0))
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    )
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   (net (rename N151 "dout<63>")
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   (net (rename N152 "dout<62>")
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      (portRef (member rd_data_count 0))
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   )
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    (joined
      (portRef (member wr_data_count 0))
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    )
   )
))))
(design ctrl_fifo1024x65_v5 (cellRef ctrl_fifo1024x65_v5 (libraryRef test_lib))
  (property X_CORE_INFO (string "fifo_generator_v3_2, Coregen 8.2.03i_ip2"))
  (property PART (string "xc3s1000-fg456-5") (owner "Xilinx")))
)