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https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk
Subversion Repositories pcie_ds_dma
[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source/] [extend_clk.v] - Rev 32
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//----------------------------------------------------------------------------- // // (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // Project : V5-Block Plus for PCI Express // File : extend_clk.v //-------------------------------------------------------------------------------- //-------------------------------------------------------------------------------- // // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 1.1 // \ \ Application : Generated by Xilinx PCI Express Wizard // / / Filename : extend_clk.v // /___/ /\ Module : Extend Clk period of certain signals // \ \ / \ // \___\/\___\ // //------------------------------------------------------------------------------ // Purpose: Extend signals coming out of Block that are clocked with core_clk // by 0, 2 or 4 signals depending on frequency so BlkPlus(clocked using // user_clk) logic does not miss them. `ifndef Tcq `define Tcq 1 `endif module extend_clk #( // use 1 for 250Mhz use 2 for 125Mhz and 4 for 62.5Mhz parameter CLKRATIO=1 ) ( input clk, input rst_n, input [6:0] l0_dll_error_vector, input [1:0] l0_rx_mac_link_error, output [6:0] l0_dll_error_vector_retime, output [1:0] l0_rx_mac_link_error_retime ); reg [6:0] l0_dll_error_vector_d; reg [6:0] l0_dll_error_vector_dd; reg [6:0] l0_dll_error_vector_ddd; reg [1:0] l0_rx_mac_link_error_d; reg [1:0] l0_rx_mac_link_error_dd; reg [1:0] l0_rx_mac_link_error_ddd; always @(posedge clk) begin if (CLKRATIO == 2) begin // 125Mhz if (!rst_n) begin l0_dll_error_vector_d <= #`Tcq 6'h00; l0_rx_mac_link_error_d <= #`Tcq 2'h0; end else begin l0_dll_error_vector_d <= #`Tcq l0_dll_error_vector; l0_rx_mac_link_error_d <= #`Tcq l0_rx_mac_link_error; end end else if (CLKRATIO == 4) begin // 62.5Mhz if (!rst_n) begin l0_dll_error_vector_d <= #`Tcq 6'h00; l0_dll_error_vector_dd <= #`Tcq 6'h00; l0_dll_error_vector_ddd <= #`Tcq 6'h00; l0_rx_mac_link_error_d <= #`Tcq 2'h0; l0_rx_mac_link_error_dd <= #`Tcq 2'h0; l0_rx_mac_link_error_ddd <= #`Tcq 2'h0; end else begin l0_dll_error_vector_d <= #`Tcq l0_dll_error_vector; l0_dll_error_vector_dd <= #`Tcq l0_dll_error_vector_d; l0_dll_error_vector_ddd <= #`Tcq l0_dll_error_vector_dd; l0_rx_mac_link_error_d <= #`Tcq l0_rx_mac_link_error; l0_rx_mac_link_error_dd <= #`Tcq l0_rx_mac_link_error_d; l0_rx_mac_link_error_ddd <= #`Tcq l0_rx_mac_link_error_dd; end end end assign l0_dll_error_vector_retime[6] = (CLKRATIO==2) ? (l0_dll_error_vector[6] | l0_dll_error_vector_d[6]) : (CLKRATIO==4) ? (l0_dll_error_vector[6] | l0_dll_error_vector_d[6] | l0_dll_error_vector_dd[6] | l0_dll_error_vector_ddd[6]) : l0_dll_error_vector[6]; assign l0_dll_error_vector_retime[5] = (CLKRATIO==2) ? (l0_dll_error_vector[5] | l0_dll_error_vector_d[5]) : (CLKRATIO==4) ? (l0_dll_error_vector[5] | l0_dll_error_vector_d[5] | l0_dll_error_vector_dd[5] | l0_dll_error_vector_ddd[5]) : l0_dll_error_vector[5]; assign l0_dll_error_vector_retime[4] = (CLKRATIO==2) ? (l0_dll_error_vector[4] | l0_dll_error_vector_d[4]) : (CLKRATIO==4) ? (l0_dll_error_vector[4] | l0_dll_error_vector_d[4] | l0_dll_error_vector_dd[4] | l0_dll_error_vector_ddd[4]) : l0_dll_error_vector[4]; assign l0_dll_error_vector_retime[3] = (CLKRATIO==2) ? (l0_dll_error_vector[3] | l0_dll_error_vector_d[3]) : (CLKRATIO==4) ? (l0_dll_error_vector[3] | l0_dll_error_vector_d[3] | l0_dll_error_vector_dd[3] | l0_dll_error_vector_ddd[3]) : l0_dll_error_vector[3]; assign l0_dll_error_vector_retime[2] = (CLKRATIO==2) ? (l0_dll_error_vector[2] | l0_dll_error_vector_d[2]) : (CLKRATIO==4) ? (l0_dll_error_vector[2] | l0_dll_error_vector_d[2] | l0_dll_error_vector_dd[2] | l0_dll_error_vector_ddd[2]) : l0_dll_error_vector[2]; assign l0_dll_error_vector_retime[1] = (CLKRATIO==2) ? (l0_dll_error_vector[1] | l0_dll_error_vector_d[1]) : (CLKRATIO==4) ? (l0_dll_error_vector[1] | l0_dll_error_vector_d[1] | l0_dll_error_vector_dd[1] | l0_dll_error_vector_ddd[1]) : l0_dll_error_vector[1]; assign l0_dll_error_vector_retime[0] = (CLKRATIO==2) ? (l0_dll_error_vector[0] | l0_dll_error_vector_d[0]) : (CLKRATIO==4) ? (l0_dll_error_vector[0] | l0_dll_error_vector_d[0] | l0_dll_error_vector_dd[0] | l0_dll_error_vector_ddd[0]) : l0_dll_error_vector[0]; assign l0_rx_mac_link_error_retime[1] = (CLKRATIO==2) ? (l0_rx_mac_link_error[1] | l0_rx_mac_link_error_d[1]) : (CLKRATIO==4) ? (l0_rx_mac_link_error_d[1] | l0_rx_mac_link_error_dd[1] | l0_rx_mac_link_error_dd[1] | l0_rx_mac_link_error_ddd[1]) : l0_rx_mac_link_error; assign l0_rx_mac_link_error_retime[0] = (CLKRATIO==2) ? (l0_rx_mac_link_error[0] | l0_rx_mac_link_error_d[0]) : (CLKRATIO==4) ? (l0_rx_mac_link_error_d[0] | l0_rx_mac_link_error_dd[0] | l0_rx_mac_link_error_dd[0] | l0_rx_mac_link_error_ddd[0]) : l0_rx_mac_link_error; endmodule
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