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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source/] [pcie_top.v] - Rev 2
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//----------------------------------------------------------------------------- // // (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // Project : V5-Block Plus for PCI Express // File : pcie_top.v //-------------------------------------------------------------------------------- //-------------------------------------------------------------------------------- // // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 1.1 // \ \ Application : Generated by Xilinx PCI Express Wizard // / / Filename : pcie_top.v // /___/ /\ Module : pcie_top_wrapper // \ \ / \ // \___\/\___\ // //------------------------------------------------------------------------------ `define PRODFIX 1 `define MINF(A,B) (A)>(B)?(B):(A) `define MAXF(A,B) (A)>(B)?(A):(B) module pcie_top_wrapper # ( parameter G_SIM = 1, parameter G_USER_RESETS = 0, // integer: 0 for 100MHz, 1 for 250 MHz // ------------------------------------------------------ parameter REF_CLK_FREQ = 1, // integer: 0 for PCI Express Endpoint, 1 for Legacy PCI Express Endpoint // ------------------------------------------------------ parameter COMPONENTTYPE = 0, // integer: 1 for x1 lane, 2 for x2 lanes, 4 for x4 lanes, 8 for x8 lanes // ------------------------------------------------------ parameter NO_OF_LANES = 1, // integer: 1 for 1/1 ratio, 2 for 1/2 ratio, 4 for 1/4 ratio // ------------------------------------------------------ parameter CLKRATIO = 1, // 1: USERCLK = 250 MHz; 2: USERCLK = 125 MHz; 4: USERCLK = 62.5 MHz // (CLKRATIO > 1) ? "TRUE" : "FALSE"; // ------------------------------------------------------ parameter CLKDIVIDED = "FALSE", // V5FXT Product parameter USE_V5FXT = 0, // 16 bit hex: 10EE for xilinx // ------------------------------------------------------ parameter VENDORID = 16'h10EE, // 16 bit hex: // ------------------------------------------------------ parameter DEVICEID = 16'h5050, // 8 bit hex: // ------------------------------------------------------ parameter REVISIONID = 8'h00, // 16 bit hex: // ------------------------------------------------------ parameter SUBSYSTEMVENDORID = 16'h10EE, // 16 bit hex: // ------------------------------------------------------ parameter SUBSYSTEMID = 16'h5050, // 24 bit hex: // ------------------------------------------------------ parameter CLASSCODE = 24'h058000, // 32 bit hex: // ------------------------------------------------------ parameter CARDBUSCISPOINTER = 32'h00000000, // integer: 0 for NONE, 1 for INTA, 2 for INTB, 3 for INTC, 4 for INTD // ------------------------------------------------------ parameter [7:0] INTERRUPTPIN = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR0EXIST = "TRUE", // integer: 0 for MEMORY, 1 for I/O // ------------------------------------------------------ parameter BAR0IOMEMN = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR064 = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR0PREFETCHABLE = "FALSE", // integer: // ------------------------------------------------------ parameter [5:0] BAR0MASKWIDTH = 20, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR1EXIST = "FALSE", // integer: 0 for MEMORY, 1 for I/O // ------------------------------------------------------ parameter BAR1IOMEMN = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR1PREFETCHABLE = "FALSE", // integer: // ------------------------------------------------------ parameter [5:0] BAR1MASKWIDTH = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR2EXIST = "FALSE", // integer: 0 for MEMORY, 1 for I/O // ------------------------------------------------------ parameter BAR2IOMEMN = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR264 = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR2PREFETCHABLE = "FALSE", // integer: // ------------------------------------------------------ parameter [5:0] BAR2MASKWIDTH = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR3EXIST = "FALSE", // integer: 0 for MEMORY, 1 for I/O // ------------------------------------------------------ parameter BAR3IOMEMN = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR3PREFETCHABLE = "FALSE", // integer: // ------------------------------------------------------ parameter [5:0] BAR3MASKWIDTH = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR4EXIST = "FALSE", // integer: 0 for MEMORY, 1 for I/O // ------------------------------------------------------ parameter BAR4IOMEMN = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR464 = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR4PREFETCHABLE = "FALSE", // integer: // ------------------------------------------------------ parameter [5:0] BAR4MASKWIDTH = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR5EXIST = "FALSE", // integer: 0 for MEMORY, 1 for I/O // ------------------------------------------------------ parameter BAR5IOMEMN = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter BAR5PREFETCHABLE = "FALSE", // integer: // ------------------------------------------------------ parameter [5:0] BAR5MASKWIDTH = 0, // integer: 0:128, 1:256, 2:512, 3:1024, 4:2048, 5:4096 // ------------------------------------------------------ parameter MAXPAYLOADSIZE = 0, // integer: 0 for max of 64ns, 1 for max of 128ns, 2 for max of 256ns, 3 for max of 512ns, // 4 for max of 1us, 5 for max of 2us, 6 for max of 4us, 7 for no limit // ------------------------------------------------------ parameter [2:0] DEVICECAPABILITYENDPOINTL0SLATENCY = 0, // integer: 0 for max of 1us, 1 for max of 2us, 2 for max of 4us, 3 for max of 8us, // 4 for max of 16us, 5 for max of 32us, 6 for max of 64us, 7 for no limit // ------------------------------------------------------ parameter [2:0] DEVICECAPABILITYENDPOINTL1LATENCY = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter LINKCAPABILITYASPMSUPPORTEN = 0, // integer: 0 for less than 64ns, 1 for 64ns to 128ns, 2 for 128ns to 256ns, 3 for 256ns to 512ns, // 4 for 512ns to 1us, 5 for 1us to 2us, 6 for 2us to 4us, 7 for more than 4us // ------------------------------------------------------ parameter L0SEXITLATENCY = 7, // integer: 0 for less than 64ns, 1 for 64ns to 128ns, 2 for 128ns to 256ns, 3 for 256ns to 512ns, // 4 for 512ns to 1us, 5 for 1us to 2us, 6 for 2us to 4us, 7 for more than 4us // ------------------------------------------------------ parameter L0SEXITLATENCYCOMCLK = 7, // integer: 0 for less than 1us, 1 for 1us to 2us, 2 for 2us to 4us, 3 for 4us to 8us, // 4 for 8us to 16us, 5 for 16us to 32us, 6 for 32us to 64us, 7 for more than 64us // ------------------------------------------------------ parameter L1EXITLATENCY = 7, // integer: 0 for less than 1us, 1 for 1us to 2us, 2 for 2us to 4us, 3 for 4us to 8us, // 4 for 8us to 16us, 5 for 16us to 32us, 6 for 32us to 64us, 7 for more than 64us // ------------------------------------------------------ parameter L1EXITLATENCYCOMCLK = 7, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter MSIENABLE = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter DSNENABLE = 0, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter VCENABLE = 0, // integer: 0 for 1 message, 1 for 2 messages, 2 for 4 messages // ------------------------------------------------------ parameter [2:0] MSICAPABILITYMULTIMSGCAP = 0, //boolean // ------------------------------------------------------ parameter PMCAPABILITYDSI = "TRUE", // PME Support // 5bit: {D3cold, D3hot, D2, D1, D0} // ------------------------------------------------------ parameter PMCAPABILITYPMESUPPORT = 5'b00000, // integer: 0, 1 // ------------------------------------------------------ parameter [2:0] PORTVCCAPABILITYEXTENDEDVCCOUNT = 0, // integer: 0 for none, 1 for round robin, 2 for weighted round robin // ------------------------------------------------------ parameter [7:0] PORTVCCAPABILITYVCARBCAP = 0, // integer: 0, 1 // ------------------------------------------------------ parameter LOWPRIORITYVCCOUNT = 0, // 64 bit hex: // ------------------------------------------------------ parameter DEVICESERIALNUMBER = 64'hE000000001000A35, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter FORCENOSCRAMBLING = 1'b0, // boolean // ------------------------------------------------------ parameter INFINITECOMPLETIONS = "TRUE", // integer: 0 - 255 // ------------------------------------------------------ parameter VC0_CREDITS_PH = 8, parameter VC0_CREDITS_NPH = 8, // integer: 0 for false, 1 for true // ------------------------------------------------------ parameter LINKSTATUSSLOTCLOCKCONFIG = "FALSE", // integer: 0..255 // ------------------------------------------------------ parameter TXTSNFTS = 255, // integer: 0..255 // ------------------------------------------------------ parameter TXTSNFTSCOMCLK = 255, // boolean // ------------------------------------------------------ parameter RESETMODE = "TRUE", // integer: 4096, 8192, 16384, 32768 // GUI encoding: 4096bytes: 9, 8192: 10, 16384: 11, 32768: 12 // ------------------------------------------------------ parameter RETRYRAMSIZE = 9, // integer: // ------------------------------------------------------ parameter VC0RXFIFOSIZEP = 1024, // integer: // ------------------------------------------------------ parameter VC0RXFIFOSIZENP = 192, // integer: // ------------------------------------------------------ parameter VC0RXFIFOSIZEC = 1024, // integer: // ------------------------------------------------------ parameter VC1RXFIFOSIZEP = 0, // integer: // ------------------------------------------------------ parameter VC1RXFIFOSIZENP = 0, // integer: // ------------------------------------------------------ parameter VC1RXFIFOSIZEC = 0, // integer: // ------------------------------------------------------ parameter VC0TXFIFOSIZEP = 1024, // integer: // ------------------------------------------------------ parameter VC0TXFIFOSIZENP = 192, // integer: // ------------------------------------------------------ parameter VC0TXFIFOSIZEC = 1024, // integer: // ------------------------------------------------------ parameter VC1TXFIFOSIZEP = 0, // integer: // ------------------------------------------------------ parameter VC1TXFIFOSIZENP = 0, // integer: // ------------------------------------------------------ parameter VC1TXFIFOSIZEC = 0, // integer: // ------------------------------------------------------ parameter TXDIFFBOOST = "FALSE", // integer: // ------------------------------------------------------ parameter GTDEBUGPORTS = 0 ) ( input wire user_reset_n, output wire core_clk, output wire user_clk, output wire clock_lock, input wire gsr, input wire crm_urst_n, input wire crm_nvrst_n, input wire crm_mgmt_rst_n, input wire crm_user_cfg_rst_n, input wire crm_mac_rst_n, input wire crm_link_rst_n, input wire compliance_avoid, input wire l0_cfg_loopback_master, input wire l0_transactions_pending, input wire l0_set_completer_abort_error, input wire l0_set_detected_corr_error, input wire l0_set_detected_fatal_error, input wire l0_set_detected_nonfatal_error, input wire l0_set_user_detected_parity_error, input wire l0_set_user_master_data_parity, input wire l0_set_user_received_master_abort, input wire l0_set_user_received_target_abort, input wire l0_set_user_system_error, input wire l0_set_user_signalled_target_abort, input wire l0_set_completion_timeout_uncorr_error, input wire l0_set_completion_timeout_corr_error, input wire l0_set_unexpected_completion_uncorr_error, input wire l0_set_unexpected_completion_corr_error, input wire l0_set_unsupported_request_nonposted_error, input wire l0_set_unsupported_request_other_error, input wire l0_legacy_int_funct0, input wire [3:0] l0_msi_request0, input wire [31:0] mgmt_wdata, input wire [3:0] mgmt_bwren, input wire mgmt_wren, input wire [10:0] mgmt_addr, input wire mgmt_rden, input wire [6:0] mgmt_stats_credit_sel, output crm_do_hot_reset_n, output crm_pwr_soft_reset_n, output [31:0] mgmt_rdata, output [16:0] mgmt_pso, output [11:0] mgmt_stats_credit, output l0_first_cfg_write_occurred, output l0_cfg_loopback_ack, output [1:0] l0_rx_mac_link_error, output l0_mac_link_up, output wire [3:0] l0_mac_negotiated_link_width, output l0_mac_link_training, output [3:0] l0_ltssm_state, output l0_mac_new_state_ack, output l0_mac_rx_l0s_state, output l0_mac_entered_l0, output [7:0] l0_dl_up_down, output [6:0] l0_dll_error_vector, output [12:0] l0_completer_id, output l0_msi_enable0, output [2:0] l0_multi_msg_en0, output l0_stats_dllp_received, output l0_stats_dllp_transmitted, output l0_stats_os_received, output l0_stats_os_transmitted, output l0_stats_tlp_received, output l0_stats_tlp_transmitted, output l0_stats_cfg_received, output l0_stats_cfg_transmitted, output l0_stats_cfg_other_received, output l0_stats_cfg_other_transmitted, output [1:0] l0_pwr_state0, output l0_pwr_l23_ready_state, output l0_pwr_tx_l0s_state, output l0_pwr_turn_off_req, input l0_pme_req_in, //JBG output l0_pme_ack, //JBG output io_space_enable, output mem_space_enable, output bus_master_enable, output parity_error_response, output serr_enable, output interrupt_disable, output ur_reporting_enable, //Local Link Interface ports // TX ports input wire [63:0] llk_tx_data, input wire llk_tx_src_rdy_n, input wire llk_tx_sof_n, input wire llk_tx_eof_n, input wire llk_tx_sop_n, input wire llk_tx_eop_n, input wire [1:0] llk_tx_enable_n, input wire [2:0] llk_tx_ch_tc, input wire [1:0] llk_tx_ch_fifo, input wire llk_tx_src_dsc_n, output llk_tx_dst_rdy_n, output [9:0] llk_tx_chan_space, output [7:0] llk_tx_ch_posted_ready_n, output [7:0] llk_tx_ch_non_posted_ready_n, output [7:0] llk_tx_ch_completion_ready_n, // RX Ports input wire llk_rx_dst_req_n, input wire llk_rx_dst_cont_req_n, input wire [2:0] llk_rx_ch_tc, input wire [1:0] llk_rx_ch_fifo, output [7:0] llk_tc_status, output [63:0] llk_rx_data, output llk_rx_src_rdy_n, output llk_rx_src_last_req_n, output llk_rx_sof_n, output llk_rx_eof_n, output llk_rx_sop_n, output llk_rx_eop_n, output [1:0] llk_rx_valid_n, output [7:0] llk_rx_ch_posted_available_n, output [7:0] llk_rx_ch_non_posted_available_n, output [7:0] llk_rx_ch_completion_available_n, output [15:0] llk_rx_preferred_type, input wire [NO_OF_LANES - 1: 0] RXN, input wire [NO_OF_LANES - 1: 0] RXP, output wire [NO_OF_LANES - 1: 0] TXN, output wire [NO_OF_LANES - 1: 0] TXP, output wire GTPCLK_bufg, output wire REFCLKOUT_bufg, output wire [3: 0] PLLLKDET_OUT, output wire [7: 0] RESETDONE, output wire [338:0] DEBUG, input wire GTPRESET, input wire REFCLK, input wire [7:0] gt_rx_present, input gt_dclk, input wire [NO_OF_LANES*7-1:0] gt_daddr, input wire [NO_OF_LANES-1:0] gt_den, input wire [NO_OF_LANES-1:0] gt_dwen, input wire [NO_OF_LANES*16-1:0] gt_di, output wire [NO_OF_LANES*16-1:0] gt_do, output wire [NO_OF_LANES-1:0] gt_drdy, input wire [2:0] gt_txdiffctrl_0, input wire [2:0] gt_txdiffctrl_1, input wire [2:0] gt_txbuffctrl_0, input wire [2:0] gt_txbuffctrl_1, input wire [2:0] gt_txpreemphesis_0, input wire [2:0] gt_txpreemphesis_1, input trn_lnk_up_n, output wire [2:0] max_payload_size, output wire [2:0] max_read_request_size, `ifdef MANAGEMENT_WRITE input wire mgmt_reset_delay_n, output wire mgmt_rdy, `endif input fast_train_simulation_only ); ////////////////////////////////// // PARAMETER DECLARATIONS WHICH MATCH GUI SOFTWARE ATTRIBUTES // COREGEN WILL INSTANTIATE THE TOP LEVEL MODULE AND MAP THE PARAMETERS // BASED ON GUI ENTRIES // // generic parameter definitions parameter DUALROLECFGCNTRLROOTEPN = 1'b0; parameter ISSWITCH = "FALSE"; parameter UPSTREAMFACING = "TRUE"; parameter HEADERTYPE = 8'h00; parameter XPDEVICEPORTTYPE = (COMPONENTTYPE==0)? 4'b0000:4'b0001; // NO_OF_LANES is defined at the module port list level as it is used to decide // the width of the cumulative serial rx and tx ports parameter [7:0] ACTIVELANESIN = 2**(NO_OF_LANES) - 1; //SCREEN 2 // GUI Note //SCREEN 3 :BASE ADDRESS REGISTERS // GUI Note // override settings if IO, else pass through after converting boolean to binary localparam [0:0] BAR0ADDRWIDTH_CALC = (BAR0IOMEMN == 0) ? BAR064 :0; //localparam BAR0PREFETCHABLE_CALC = (BAR0IOMEMN == 0) ? BAR0PREFETCHABLE :"FALSE"; `define BAR0PREFETCHABLE_CALC ((BAR0IOMEMN == 0) ? (BAR0PREFETCHABLE) :("FALSE")) // override settings if IO, else pass through after converting boolean to binary // Note that BAR1 cannot have 64 bit checked. BAR364 will always be FALSE localparam [0:0] BAR1ADDRWIDTH_CALC = 0; //localparam BAR1PREFETCHABLE_CALC = (BAR1IOMEMN == 0) ? BAR1PREFETCHABLE:"FALSE"; `define BAR1PREFETCHABLE_CALC ((BAR1IOMEMN == 0) ? (BAR1PREFETCHABLE):("FALSE")) localparam [0:0] BAR2ADDRWIDTH_CALC = (BAR2IOMEMN == 0) ? BAR264:0; //localparam BAR2PREFETCHABLE_CALC = (BAR2IOMEMN == 0) ? BAR2PREFETCHABLE:"FALSE"; `define BAR2PREFETCHABLE_CALC ((BAR2IOMEMN == 0) ? (BAR2PREFETCHABLE):("FALSE")) // override settings if IO, else pass through after converting boolean to binary // Note that BAR3 cannot have 64 bit checked. BAR364 will always be FALSE localparam [0:0] BAR3ADDRWIDTH_CALC = 0; //localparam BAR3PREFETCHABLE_CALC = (BAR3IOMEMN == 0) ? BAR3PREFETCHABLE:"FALSE"; `define BAR3PREFETCHABLE_CALC ((BAR3IOMEMN == 0) ? (BAR3PREFETCHABLE):("FALSE")) localparam [0:0] BAR4ADDRWIDTH_CALC = (BAR4IOMEMN == 0) ? BAR464:0; //localparam BAR4PREFETCHABLE_CALC = (BAR4IOMEMN == 0) ? BAR4PREFETCHABLE :"FALSE"; `define BAR4PREFETCHABLE_CALC ((BAR4IOMEMN == 0) ? (BAR4PREFETCHABLE):("FALSE")) // override settings if IO, else pass through after converting boolean to binary // Note that BAR5 cannot have 64 bit checked. BAR564 will always be FALSE //localparam [0:0] BAR5ADDRWIDTH_CALC = 0; //localparam BAR5PREFETCHABLE_CALC = (BAR5IOMEMN == 0) ? BAR5PREFETCHABLE :"FALSE"; `define BAR5PREFETCHABLE_CALC ((BAR5IOMEMN == 0) ? (BAR5PREFETCHABLE):("FALSE")) //SCREEN 4 :CONFIGURATION REGISTERS // GUI Note // DEVICE CAPABILITY REGISTER VALUES // GUI Note // NOTE THAT THIS IS BROKEN DOWN INTO INDIVIDUAL ATTRIBUTES // GUI Note localparam XPMAXPAYLOAD = MAXPAYLOADSIZE;//encoded value is passed by GUI localparam MAXPAYLOADBYTES = 2**(MAXPAYLOADSIZE+7);//encoded value is passed by GUI // LINK CAPABILITY REGISTER VALUES // GUI Note // NOTE THAT THIS IS BROKEN DOWN INTO INDIVIDUAL ATTRIBUTES // GUI Note // NOTE_X: Maximum link speed has no corresponding attribute // GUI Note parameter [5:0] LINKCAPABILITYMAXLINKWIDTH = NO_OF_LANES; localparam [1:0] LINKCAPABILITYASPMSUPPORT_CALC = LINKCAPABILITYASPMSUPPORTEN ? 2'b11:2'b01; // EXTENDED CAPABILITIES REGISTERS // GUI Note // REPRESENTED AS A LINK LIST // GUI Note parameter PMENABLE = 1; //GUI parameter: Power management capability checked = 1, unchecked = 0 parameter XPENABLE = 1; // GUI parameter : PCI Express checked = 1, unchecked = 0 localparam [11:0] PMBASEPTR = 64;// 40h localparam [11:0] MSIBASEPTR = 72;//48h localparam [7:0] XPBASEPTR = 96;//60h parameter [7:0] CAPABILITIESPTR_CALC = (PMENABLE==1) ? 64 : (MSIENABLE==1) ? 72: (XPENABLE==1) ? 96:0; parameter [7:0] PMCAPABILITYNEXTPTR_CALC = (PMENABLE==1)? (MSIENABLE==1)?72:(XPENABLE==1)?96:0 : 72; parameter [7:0] MSICAPABILITYNEXTPTR_CALC = (MSIENABLE==1)?(XPENABLE==1)?96:0 :96; parameter [7:0] PCIECAPABILITYNEXTPTR_CALC = 0; // SECOND LINK LIST // GUI Note // Only 4 possibilities can alter the base pointer values // GUI Note parameter AERENABLE = 0; // GUI parameter : Advanced Error Reporting checked = 1, unchecked = 0 parameter PBENABLE = 0; // GUI parameter : Power Budgeting checked = 1, unchecked = 0 localparam FIRSTENABLEDPTR = 256;//100h localparam AERREGSIZE = 56; localparam PBREGSIZE = 16; localparam DSNREGSIZE = 12; localparam VCREGSIZE = 48; parameter [11:0] AERBASEPTR = AERENABLE ? 256 : //100h PBENABLE ? 272 : //110h DSNENABLE ? 268 : //10Ch VCENABLE ? 300 : 272; //12Ch : 110h parameter [11:0] PBBASEPTR = AERENABLE ? 312 : //138h PBENABLE ? 256 : //100h DSNENABLE ? 324 : //144h VCENABLE ? 356 : 312;//164h : 138h parameter [11:0] DSNBASEPTR = AERENABLE ? 328 : //148h PBENABLE ? 328 : //148h DSNENABLE ? 256 : // 100h VCENABLE ? 372 : 328; //174h : 148h parameter [11:0] VCBASEPTR = AERENABLE ? 340 : //154h PBENABLE ? 340 : // 154h DSNENABLE ? 340 : //154h VCENABLE ? 256 : 340; //100h : 154h // parameter [11:0] AERCAPABILITYNEXTPTR = AERENABLE ? PBENABLE ? PBBASEPTR:(DSNENABLE ? DSNBASEPTR : VCENABLE ? VCBASEPTR : 0):PBBASEPTR; parameter [11:0] PBCAPABILITYNEXTPTR = PBENABLE ? (DSNENABLE ? DSNBASEPTR : VCENABLE ? VCBASEPTR : 0 ):DSNBASEPTR ; parameter [11:0] DSNCAPABILITYNEXTPTR = DSNENABLE ? (VCENABLE ? VCBASEPTR : 0):VCBASEPTR; parameter [11:0] VCCAPABILITYNEXTPTR = 0; //PCIe Extended Capabilities Register Components // GUI Note parameter PCIECAPABILITYSLOTIMPL = "FALSE"; // GUI parameter : checked = 1, unchecked = 0 parameter PCIECAPABILITYINTMSGNUM = 5'b00000; // GUI parameter : integer // POWER Management extended capabilities register components // GUI Note parameter PMCAPABILITYAUXCURRENT = 3'b000; // GUI parameter: integer parameter PMCAPABILITYD1SUPPORT = "FALSE"; // GUI parameter: checked = 1, unchecked = 0 parameter PMCAPABILITYD2SUPPORT = "FALSE"; // GUI parameter: checked = 1, unchecked = 0 // parameter PMCAPABILITYPMESUPPORT = 5'b00000; // GUI parameter: 5 bit binary value based on checked boxes parameter PMDATA0 = 8'h00; parameter PMDATA1 = 8'h00; parameter PMDATA2 = 8'h00; parameter PMDATA3 = 8'h00; parameter PMDATA4 = 8'h00; parameter PMDATA5 = 8'h00; parameter PMDATA6 = 8'h00; parameter PMDATA7 = 8'h00; parameter PMDATA8 = 8'h00; parameter PMDATASCALE0 = 2'h0; parameter PMDATASCALE1 = 2'h0; parameter PMDATASCALE2 = 2'h0; parameter PMDATASCALE3 = 2'h0; parameter PMDATASCALE4 = 2'h0; parameter PMDATASCALE5 = 2'h0; parameter PMDATASCALE6 = 2'h0; parameter PMDATASCALE7 = 2'h0; parameter PMDATASCALE8 = 2'h0; //AER Register Components // GUI Note parameter AERCAPABILITYECRCGENCAPABLE = "FALSE"; // GUI Parameter : checked = 1, unchecked = 0 parameter AERCAPABILITYECRCCHECKCAPABLE = "FALSE"; // GUI Parameter: checked = 1, unchecked = 0 // VC Register Components // GUI Note localparam L0VC0PREVIEWEXPAND = 1'b0; localparam [7:0] PORTVCCAPABILITYVCARBTABLEOFFSET_CALC = (LOWPRIORITYVCCOUNT==1) ? 8: 0 ; // Power capabilities parameter [7:0] PBCAPABILITYDW0BASEPOWER = 0; parameter [1:0] PBCAPABILITYDW0DATASCALE = 0; parameter [2:0] PBCAPABILITYDW0PMSUBSTATE = 0; parameter [1:0] PBCAPABILITYDW0PMSTATE = 0; parameter [2:0] PBCAPABILITYDW0TYPE = 0; parameter [2:0] PBCAPABILITYDW0POWERRAIL = 0; parameter [7:0] PBCAPABILITYDW1BASEPOWER = 0; parameter [1:0] PBCAPABILITYDW1DATASCALE = 0; parameter [2:0] PBCAPABILITYDW1PMSUBSTATE = 0; parameter [1:0] PBCAPABILITYDW1PMSTATE = 0; parameter [2:0] PBCAPABILITYDW1TYPE = 0; parameter [2:0] PBCAPABILITYDW1POWERRAIL = 0; parameter [7:0] PBCAPABILITYDW2BASEPOWER = 0; parameter [1:0] PBCAPABILITYDW2DATASCALE = 0; parameter [2:0] PBCAPABILITYDW2PMSUBSTATE = 0; parameter [1:0] PBCAPABILITYDW2PMSTATE = 0; parameter [2:0] PBCAPABILITYDW2TYPE = 0; parameter [2:0] PBCAPABILITYDW2POWERRAIL = 0; parameter [7:0] PBCAPABILITYDW3BASEPOWER = 0; parameter [1:0] PBCAPABILITYDW3DATASCALE = 0; parameter [2:0] PBCAPABILITYDW3PMSUBSTATE = 0; parameter [1:0] PBCAPABILITYDW3PMSTATE = 0; parameter [2:0] PBCAPABILITYDW3TYPE = 0; parameter [2:0] PBCAPABILITYDW3POWERRAIL = 0; parameter PBCAPABILITYSYSTEMALLOCATED = "FALSE"; parameter AUXPOWER = 1'b0; parameter MAINPOWER = 1'b1; //SCREEN 5 : BUFFERING //calculate rety ram size based on payload size localparam [11:0] RETRYRAMSIZE_CALC = (MAXPAYLOADBYTES == 2048) ? `MAXF(10,RETRYRAMSIZE) : (MAXPAYLOADBYTES == 4096) ? `MAXF(11,RETRYRAMSIZE) : RETRYRAMSIZE; parameter RETRYRAMWIDTH = 1'b0; parameter [2:0] RETRYRAMREADLATENCY = 3;//GUI parameter parameter [2:0] RETRYRAMWRITELATENCY = 1;//GUI parameter // calculate minimum values of RX Posted FIFO Sizes localparam VC0RXFIFOSIZEP_MIN = 192 + MAXPAYLOADBYTES; localparam VC0RXFIFOSIZEP_MAX = `MINF(192 + (8*MAXPAYLOADBYTES), 32768); localparam VC1RXFIFOSIZEP_MIN = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 192 + MAXPAYLOADBYTES; localparam VC1RXFIFOSIZEP_MAX = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : `MINF(192 + (8*MAXPAYLOADBYTES), 32768); localparam VC0RXFIFOSIZENP_CALC = 192; localparam VC1RXFIFOSIZENP_CALC = (PORTVCCAPABILITYEXTENDEDVCCOUNT==0) ? 0 : 192; // calculate minimum/max values of RX Posted Completion FIFO Sizes localparam VC0RXFIFOSIZEC_MIN = 128 + MAXPAYLOADBYTES; localparam VC0RXFIFOSIZEC_MAX = `MINF(128 + (8*MAXPAYLOADBYTES), 32768); localparam VC1RXFIFOSIZEC_MIN = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 128 + MAXPAYLOADBYTES; localparam VC1RXFIFOSIZEC_MAX = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : `MINF(128 + (8*MAXPAYLOADBYTES), 32768); // calculate minimum/max values of TX Posted FIFO Sizes localparam VC0TXFIFOSIZEP_MIN = 192 + MAXPAYLOADBYTES; localparam VC0TXFIFOSIZEP_MAX = `MINF(192 + (8*MAXPAYLOADBYTES), 32768); localparam VC1TXFIFOSIZEP_MIN = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 192 + MAXPAYLOADBYTES; localparam VC1TXFIFOSIZEP_MAX = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : `MINF(192 + (8*MAXPAYLOADBYTES), 32768); localparam VC0TXFIFOSIZENP_CALC = 192; localparam VC1TXFIFOSIZENP_CALC = (PORTVCCAPABILITYEXTENDEDVCCOUNT==0) ? 0 : 192; localparam VC0TXFIFOSIZEC_MIN = 128 + MAXPAYLOADBYTES; localparam VC0TXFIFOSIZEC_MAX = `MINF(128 + (8*MAXPAYLOADBYTES), 32768); localparam VC1TXFIFOSIZEC_MIN = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 128 + MAXPAYLOADBYTES; localparam VC1TXFIFOSIZEC_MAX = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : `MINF(128 + (8*MAXPAYLOADBYTES), 32768); // calculate base and limit values for the FIFOs // The calculated min,max values for fifos based on XPMAXPAYLOAD will override // GUI NOTE // user entries in case the value goes out of band // GUI NOTE // algorithm: final size = min(max(lowerlimit,userinput),upperlimit) // GUI NOTE localparam VC0RXFIFOSIZEP_CALC = `MINF(`MAXF(VC0RXFIFOSIZEP_MIN,VC0RXFIFOSIZEP),VC0RXFIFOSIZEP_MAX); localparam VC0RXFIFOSIZEC_CALC = 5752+8; //`MINF(`MAXF(VC0RXFIFOSIZEC_MIN,VC0RXFIFOSIZEC),VC0RXFIFOSIZEC_MAX); localparam VC0TXFIFOSIZEP_CALC = `MINF(`MAXF(VC0TXFIFOSIZEP_MIN,VC0TXFIFOSIZEP),VC0TXFIFOSIZEP_MAX); localparam VC0TXFIFOSIZEC_CALC = `MINF(`MAXF(VC0TXFIFOSIZEC_MIN,VC0TXFIFOSIZEC),VC0TXFIFOSIZEC_MAX); localparam VC1RXFIFOSIZEP_CALC = `MINF(`MAXF(VC1RXFIFOSIZEP_MIN,VC1RXFIFOSIZEP),VC1RXFIFOSIZEP_MAX); localparam VC1RXFIFOSIZEC_CALC = `MINF(`MAXF(VC1RXFIFOSIZEC_MIN,VC1RXFIFOSIZEC),VC1RXFIFOSIZEC_MAX); localparam VC1TXFIFOSIZEP_CALC = `MINF(`MAXF(VC1TXFIFOSIZEP_MIN,VC1TXFIFOSIZEP),VC1TXFIFOSIZEP_MAX); localparam VC1TXFIFOSIZEC_CALC = `MINF(`MAXF(VC1TXFIFOSIZEC_MIN,VC1TXFIFOSIZEC),VC1TXFIFOSIZEC_MAX); // calculate base pointers and limits for FIFOs localparam [12:0] VC0RXFIFOBASEP_CALC = 0; localparam [12:0] VC0RXFIFOLIMITP_CALC = VC0RXFIFOBASEP_CALC + VC0RXFIFOSIZEP_CALC/8 - 1; localparam [12:0] VC0RXFIFOBASENP_CALC = VC0RXFIFOLIMITP_CALC + 1; localparam [12:0] VC0RXFIFOLIMITNP_CALC = VC0RXFIFOBASENP_CALC + VC0RXFIFOSIZENP_CALC/8 - 1; localparam [12:0] VC0RXFIFOBASEC_CALC = VC0RXFIFOLIMITNP_CALC + 1; localparam [12:0] VC0RXFIFOLIMITC_CALC = VC0RXFIFOBASEC_CALC + VC0RXFIFOSIZEC_CALC/8 - 1; localparam [12:0] VC1RXFIFOBASEP_CALC = VC0RXFIFOLIMITC_CALC + 1; localparam [12:0] VC1RXFIFOLIMITP_CALC = VC1RXFIFOBASEP_CALC + VC1RXFIFOSIZEP_CALC/8 - 1; localparam [12:0] VC1RXFIFOBASENP_CALC = VC1RXFIFOLIMITP_CALC + 1; localparam [12:0] VC1RXFIFOLIMITNP_CALC = VC1RXFIFOBASENP_CALC + VC1RXFIFOSIZENP_CALC/8 - 1; localparam [12:0] VC1RXFIFOBASEC_CALC = VC1RXFIFOLIMITNP_CALC + 1; localparam [12:0] VC1RXFIFOLIMITC_CALC = VC1RXFIFOBASEC_CALC + VC1RXFIFOSIZEC_CALC/8 - 1; localparam [12:0] VC0TXFIFOBASEP_CALC = 0; localparam [12:0] VC0TXFIFOLIMITP_CALC = VC0TXFIFOBASEP_CALC + VC0TXFIFOSIZEP_CALC/8 - 1; localparam [12:0] VC0TXFIFOBASENP_CALC = VC0TXFIFOLIMITP_CALC + 1; localparam [12:0] VC0TXFIFOLIMITNP_CALC = VC0TXFIFOBASENP_CALC + VC0TXFIFOSIZENP_CALC/8 - 1; localparam [12:0] VC0TXFIFOBASEC_CALC = VC0TXFIFOLIMITNP_CALC + 1; localparam [12:0] VC0TXFIFOLIMITC_CALC = VC0TXFIFOBASEC_CALC + VC0TXFIFOSIZEC_CALC/8 - 1; localparam [12:0] VC1TXFIFOBASEP_CALC = VC0TXFIFOLIMITC_CALC + 1; localparam [12:0] VC1TXFIFOLIMITP_CALC = VC1TXFIFOBASEP_CALC + VC1TXFIFOSIZEP_CALC/8 - 1; localparam [12:0] VC1TXFIFOBASENP_CALC = VC1TXFIFOLIMITP_CALC + 1; localparam [12:0] VC1TXFIFOLIMITNP_CALC = VC1TXFIFOBASENP_CALC + VC1TXFIFOSIZENP_CALC/8 - 1; localparam [12:0] VC1TXFIFOBASEC_CALC = VC1TXFIFOLIMITNP_CALC + 1; localparam [12:0] VC1TXFIFOLIMITC_CALC = VC1TXFIFOBASEC_CALC + VC1TXFIFOSIZEC_CALC/8 - 1; ////////////////////////////////////////////////////// // calculations for total BRAM size for each of the buffers TL_TX, TL_RX, DLL_RETRY localparam TL_TX_SIZE = VC0TXFIFOSIZEP_CALC + VC0TXFIFOSIZENP_CALC + VC0TXFIFOSIZEC_CALC + VC1TXFIFOSIZEP_CALC + VC1TXFIFOSIZENP_CALC + VC1TXFIFOSIZEC_CALC; localparam TL_RX_SIZE = VC0RXFIFOSIZEP_CALC + VC0RXFIFOSIZENP_CALC + VC0RXFIFOSIZEC_CALC + VC1RXFIFOSIZEP_CALC + VC1RXFIFOSIZENP_CALC + VC1RXFIFOSIZEC_CALC; // RAM Latencies parameter [2:0] TLRAMREADLATENCY = 3; //GUI parameter parameter [2:0] TLRAMWRITELATENCY = 1; //GUI parameter parameter TLRAMWIDTH = 1'b0; //GUI parameter parameter RAMSHARETXRX = "FALSE"; //GUI parameter. GUI should convert Boolean to Binary // FIFO CREDIT VAlUES localparam [6:0] VC0TOTALCREDITSPH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? VC0_CREDITS_PH : VC0_CREDITS_PH; localparam [6:0] VC0TOTALCREDITSNPH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? VC0_CREDITS_NPH : VC0_CREDITS_NPH; localparam [6:0] VC0TOTALCREDITSCH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? (INFINITECOMPLETIONS ? 0 : 8) : (INFINITECOMPLETIONS ? 0 : 8); // gui //localparam [6:0] VC0TOTALCREDITSCH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 0 ; localparam [10:0] VC0TOTALCREDITSPD = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? ((VC0RXFIFOSIZEP_CALC - 192)/16) : ((VC0RXFIFOSIZEP_CALC - 192)/16); localparam [10:0] VC0TOTALCREDITSCD = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? (INFINITECOMPLETIONS ? 0 : 11'h080) : (INFINITECOMPLETIONS ? 0 : 11'h080); // gui //localparam [10:0] VC0TOTALCREDITSCD = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 0 ; localparam [6:0] VC1TOTALCREDITSPH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 8 ; localparam [6:0] VC1TOTALCREDITSNPH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 8 ; localparam [6:0] VC1TOTALCREDITSCH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 0 ; localparam [10:0] VC1TOTALCREDITSPD = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : ((VC1RXFIFOSIZEP_CALC - 192)/16); localparam [10:0] VC1TOTALCREDITSCD = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? 0 : 0 ; //localparam INFINITECOMPLETIONS = "TRUE"; // Set to True // ADDITIONAL ATTRIBUTES // EITHER NOT SUPPORTED IN RELEASE OR TEST FEATURES localparam SELECTDLLIF = "FALSE"; localparam SELECTASMODE = "FALSE"; localparam LLKBYPASS = "FALSE"; localparam XPRCBCONTROL = 1'b0; localparam CONFIGROUTING = 3'h1; localparam EXTCFGCAPPTR = 8'b0; localparam EXTCFGXPCAPPTR = 12'b0; localparam XLINKSUPPORTED = "FALSE"; localparam PCIEREVISION = 1'b1; localparam RETRYWRITEPIPE = "FALSE"; localparam RETRYREADADDRPIPE = "FALSE"; localparam RETRYREADDATAPIPE = "FALSE"; localparam DUALCORESLAVE = "FALSE"; localparam DUALCOREENABLE = "FALSE"; localparam RXWRITEPIPE = "FALSE"; localparam RXREADADDRPIPE = "FALSE"; localparam RXREADDATAPIPE = "FALSE"; localparam TXWRITEPIPE = "FALSE"; localparam TXREADADDRPIPE = "FALSE"; localparam TXREADDATAPIPE = "FALSE"; localparam SLOTIMPLEMENTED = "FALSE"; localparam PMSTATUSCONTROLDATASCALE = 2'b00; ////////////////////////////////////////////////////// // Tie off declarations: localparam TIEOFFTOHIGH1 = 1'b1;//1 bit localparam TIEOFFTOLOW1 = 1'b0;//1 bit localparam TIEOFFTOHIGH2 = 2'b11;//2 bit localparam TIEOFFTOLOW2 = 2'b00;//2 bit localparam TIEOFFTOLOW3 = 3'b000;//2 bit ////////////////////////////////////////////// //Parameters parameter L0_TL_LINK_RETRAIN = 1'b0; parameter [5:0] CFG_NEGOTIATED_LINK_WIDTH = 6'b000000; parameter CROSSLINKSEED = 1'b1; parameter [23:0] L0_CFG_VC_ID = 24'h000000; parameter [11:0] L0_REPLAY_TIMER_ADJUSTMENT = 12'h000; parameter L0_ACKNAK_TIMER_ADJUSTMENT = 12'h000; parameter L0_DLL_HOLD_LINK_UP = 1'b0; parameter [3:0] L0_CFG_AS_STATE_CHANGE_CMD = 4'h0; parameter L0_CFG_AS_SPAN_TREE_OWNED_STATE = 1'b0; parameter L0_AS_E = 1'b0; parameter [2:0] L0_AS_TURN_POOL_BITS_CONSUMED = 3'b0; parameter [7:0] L0_AS_PORT_COUNT = 8'h00; parameter [7:0] L0_CFG_VC_ENABLE = 8'h00; parameter [2:0] L0_CFG_NEGOTIATED_MAXP = 3'h0; parameter L0_CFG_EXTENDED_SYNC = 1'b0; parameter L0_CFG_LINK_DISABLE = 1'b0; parameter L0_ALL_DOWN_PORTS_IN_L1 = 1'b0; parameter L0_ATTENTION_BUTTON_PRESSED = 1'b0; parameter L0_TX_BEACON = 1'b0; parameter L0_WAKE_N = 1'b1; //parameter L0_PME_REQ_IN = 1'b0; //JBG parameter L0_ROOT_TURN_OFF_REQ = 1'b0; parameter L0_TX_CFG_PM = 1'b0; parameter [2:0] L0_TX_CFG_PM_TYPE = 3'b000; parameter L0_PWR_NEW_STATE_REQ = 1'b0; parameter [1:0] L0_PWR_NEXT_LINK_STATE = 2'b00; parameter L0_CFG_L0S_ENTRY_SUP = 1'b0; parameter L0_CFG_L0S_ENTRY_ENABLE = 1'b0; parameter [2:0] L0_CFG_L0S_EXIT_LAT = 3'b000; //check gui spec parameter [63:0] L0_TX_TL_TLP_DATA = 64'h0000_0000_0000_0000; parameter [1:0] L0_TX_TL_TLP_END = 2'b00; parameter [1:0] L0_TX_TL_TLP_ENABLE = 2'b00; parameter L0_TX_TL_TLP_EDB = 1'b0; parameter L0_TX_TL_TLP_REQ = 1'b0; parameter L0_TX_TL_TLP_REQ_END = 1'b0; parameter L0_TX_TL_TLP_WIDTH = 1'b0; parameter [3:0] L0_TX_TL_TLP_LATENCY = 4'h0; parameter L0_TL_AS_FC_CRED_STARVATION = 1'b0; parameter [18:0] L0_TX_TL_SBFC_DATA = 19'h0; parameter L0_TX_TL_SBFC_UPDATE = 1'b0; parameter [191:0] L0_TX_TL_FC_NPOST_BYP_CRED = 192'h0; parameter [15:0] L0_TX_TL_FC_NPOST_BYP_UPDATE = 16'h0000; parameter [159:0] L0_TX_TL_FC_POST_ORD_CRED = 160'h0; parameter [15:0] L0_TX_TL_FC_POST_ORD_UPDATE = 16'h0000; parameter [159:0] L0_TX_TL_FC_CMPL_MC_CRED = 160'h0; parameter [15:0] L0_TX_TL_FC_CMPL_MC_UPDATE = 16'h0000; parameter [7:0] L0_RX_TL_TLP_NON_INITIALIZED_VC = 8'h00; parameter SLOTCAPABILITYATTBUTTONPRESENT = "FALSE"; parameter SLOTCAPABILITYPOWERCONTROLLERPRESENT = "FALSE"; parameter SLOTCAPABILITYMSLSENSORPRESENT = "FALSE"; parameter SLOTCAPABILITYATTINDICATORPRESENT = "FALSE"; parameter SLOTCAPABILITYPOWERINDICATORPRESENT = "FALSE"; parameter SLOTCAPABILITYHOTPLUGSURPRISE = "FALSE"; parameter SLOTCAPABILITYHOTPLUGCAPABLE = "FALSE"; parameter SLOTCAPABILITYSLOTPOWERLIMITVALUE = 8'h00; parameter SLOTCAPABILITYSLOTPOWERLIMITSCALE = 2'b00; parameter SLOTCAPABILITYPHYSICALSLOTNUM = 13'h0000; //signals for module pcie_mim wire mim_rx_bwclk; wire mim_rx_brclk; wire mim_tx_bwclk; wire mim_tx_brclk; wire mim_dll_bclk; wire [63:0] mim_rx_brdata; wire [12:0] mim_rx_bradd; wire mim_rx_bren; wire [63:0] mim_rx_bwdata; wire [12:0] mim_rx_bwadd; wire mim_rx_bwen; wire [63:0] mim_tx_brdata; wire [12:0] mim_tx_bradd; wire mim_tx_bren; wire [63:0] mim_tx_bwdata; wire [12:0] mim_tx_bwadd; wire mim_tx_bwen; wire [63:0] mim_dll_brdata; wire [11:0] mim_dll_bradd; wire mim_dll_bren; wire [63:0] mim_dll_bwdata; wire [11:0] mim_dll_bwadd; wire mim_dll_bwen; wire [63:0] mim_rx_brdata_out; wire pipe_rx_elec_idle_l0; wire [2:0] pipe_rx_status_l0; wire [7:0] pipe_rx_data_l0; wire pipe_rx_phy_status_l0; wire pipe_rx_data_k_l0; wire pipe_rx_valid_l0; wire pipe_rxchanisaligned_l0; wire [7:0] pipe_tx_data_l0; wire pipe_tx_data_k_l0; wire pipe_tx_elec_idle_l0; wire pipe_tx_detect_rx_loopback_l0; wire pipe_tx_compliance_l0; wire pipe_rx_polarity_l0; wire [1:0] pipe_power_down_l0; wire pipe_deskew_lanes_l0; wire pipe_reset_l0; wire pipe_rx_elec_idle_l1; wire [2:0] pipe_rx_status_l1; wire [7:0] pipe_rx_data_l1; wire pipe_rx_phy_status_l1; wire pipe_rx_data_k_l1; wire pipe_rx_valid_l1; wire pipe_rxchanisaligned_l1; wire [7:0] pipe_tx_data_l1; wire pipe_tx_data_k_l1; wire pipe_tx_elec_idle_l1; wire pipe_tx_detect_rx_loopback_l1; wire pipe_tx_compliance_l1; wire pipe_rx_polarity_l1; wire [1:0] pipe_power_down_l1; wire pipe_deskew_lanes_l1; wire pipe_reset_l1; wire pipe_rx_elec_idle_l2; wire [2:0] pipe_rx_status_l2; wire [7:0] pipe_rx_data_l2; wire pipe_rx_phy_status_l2; wire pipe_rx_data_k_l2; wire pipe_rx_valid_l2; wire pipe_rxchanisaligned_l2; wire [7:0] pipe_tx_data_l2; wire pipe_tx_data_k_l2; wire pipe_tx_elec_idle_l2; wire pipe_tx_detect_rx_loopback_l2; wire pipe_tx_compliance_l2; wire pipe_rx_polarity_l2; wire [1:0] pipe_power_down_l2; wire pipe_deskew_lanes_l2; wire pipe_reset_l2; wire pipe_rx_elec_idle_l3; wire [2:0] pipe_rx_status_l3; wire [7:0] pipe_rx_data_l3; wire pipe_rx_phy_status_l3; wire pipe_rx_data_k_l3; wire pipe_rx_valid_l3; wire pipe_rxchanisaligned_l3; wire [7:0] pipe_tx_data_l3; wire pipe_tx_data_k_l3; wire pipe_tx_elec_idle_l3; wire pipe_tx_detect_rx_loopback_l3; wire pipe_tx_compliance_l3; wire pipe_rx_polarity_l3; wire [1:0] pipe_power_down_l3; wire pipe_deskew_lanes_l3; wire pipe_reset_l3; wire pipe_rx_elec_idle_l4; wire [2:0] pipe_rx_status_l4; wire [7:0] pipe_rx_data_l4; wire pipe_rx_phy_status_l4; wire pipe_rx_data_k_l4; wire pipe_rx_valid_l4; wire pipe_rxchanisaligned_l4; wire [7:0] pipe_tx_data_l4; wire pipe_tx_data_k_l4; wire pipe_tx_elec_idle_l4; wire pipe_tx_detect_rx_loopback_l4; wire pipe_tx_compliance_l4; wire pipe_rx_polarity_l4; wire [1:0] pipe_power_down_l4; wire pipe_deskew_lanes_l4; wire pipe_reset_l4; wire pipe_rx_elec_idle_l5; wire [2:0] pipe_rx_status_l5; wire [7:0] pipe_rx_data_l5; wire pipe_rx_phy_status_l5; wire pipe_rx_data_k_l5; wire pipe_rx_valid_l5; wire pipe_rxchanisaligned_l5; wire [7:0] pipe_tx_data_l5; wire pipe_tx_data_k_l5; wire pipe_tx_elec_idle_l5; wire pipe_tx_detect_rx_loopback_l5; wire pipe_tx_compliance_l5; wire pipe_rx_polarity_l5; wire [1:0] pipe_power_down_l5; wire pipe_deskew_lanes_l5; wire pipe_reset_l5; wire pipe_rx_elec_idle_l6; wire [2:0] pipe_rx_status_l6; wire [7:0] pipe_rx_data_l6; wire pipe_rx_phy_status_l6; wire pipe_rx_data_k_l6; wire pipe_rx_valid_l6; wire pipe_rxchanisaligned_l6; wire [7:0] pipe_tx_data_l6; wire pipe_tx_data_k_l6; wire pipe_tx_elec_idle_l6; wire pipe_tx_detect_rx_loopback_l6; wire pipe_tx_compliance_l6; wire pipe_rx_polarity_l6; wire [1:0] pipe_power_down_l6; wire pipe_deskew_lanes_l6; wire pipe_reset_l6; wire pipe_rx_elec_idle_l7; wire [2:0] pipe_rx_status_l7; wire [7:0] pipe_rx_data_l7; wire pipe_rx_phy_status_l7; wire pipe_rx_data_k_l7; wire pipe_rx_valid_l7; wire pipe_rxchanisaligned_l7; wire [7:0] pipe_tx_data_l7; wire pipe_tx_data_k_l7; wire pipe_tx_elec_idle_l7; wire pipe_tx_detect_rx_loopback_l7; wire pipe_tx_compliance_l7; wire pipe_rx_polarity_l7; wire [1:0] pipe_power_down_l7; wire pipe_deskew_lanes_l7; wire pipe_reset_l7; wire [63:0] pipe_rx_data; wire [7:0] pipe_rx_data_k; wire [7:0] pipe_rx_valid; wire [7:0] pipe_rx_elec_idle; wire [23:0] pipe_rx_status; wire [7:0] pipe_rx_phy_status; wire [7:0] pipe_rxchanisaligned; wire [7:0] pipe_rx_polarity; wire [63:0] pipe_tx_data; wire [7:0] pipe_tx_data_k; wire [7:0] pipe_tx_elec_idle; wire [7:0] pipe_tx_compliance; wire [15:0] pipe_power_down; wire [7:0] pipe_tx_detect_rx_loopback; wire [7:0] pipe_deskew_lanes; wire [7:0] pipe_reset; wire [2:0] maxpayloadsize_i; wire [2:0] maxreadrequestsize_i; wire [3:0] negotiated_link_width; /* wire gt_dclk = 0; wire [NO_OF_LANES*7-1:0] gt_daddr = 0; wire [NO_OF_LANES-1:0] gt_den = 0; wire [NO_OF_LANES-1:0] gt_dwen = 0; wire [NO_OF_LANES*16-1:0] gt_di = 0; wire [NO_OF_LANES*16-1:0] gt_do = 0; wire [NO_OF_LANES-1:0] gt_drdy = 0; */ wire [7:0] RXBYTEISALIGNED; wire [7:0] RXCHANBONDSEQ; wire gt_usrclk; wire core_clkb; wire mem_user_clk; // Selecting which resets to use wire mux_crm_urst_n; wire mux_crm_nvrst_n; wire mux_crm_mgmt_rst_n; wire mux_crm_user_cfg_rst_n; wire mux_crm_mac_rst_n; wire mux_crm_link_rst_n; wire rb_crm_urst_n; wire rb_crm_nvrst_n; wire rb_crm_mgmt_rst_n; wire rb_crm_user_cfg_rst_n; wire rb_crm_mac_rst_n; wire rb_crm_link_rst_n; wire usrclk; wire crm_core_clk_rx_o; wire crm_user_clk_rx_o; wire crm_core_clk_tx_o; wire crm_user_clk_tx_o; wire crm_core_clk_dl_o; wire crm_core_clk; wire crm_core_clkb; wire crm_user_clk; reg reg_enable_ltssm_reset; wire enable_ltssm_reset; reg [3:0] reg_ltssm_reset; wire [3:0] ltssm_reset; reg [3:0] reg_l0_ltssm_state_internal; wire [3:0] l0_ltssm_state_internal; `ifdef PRODFIX wire trn_reset_n; wire upcfgcap_cycle; wire masking_ack; wire [7:0] pipe_rx_data_l0_out; wire [7:0] pipe_rx_data_l1_out; wire [7:0] pipe_rx_data_l2_out; wire [7:0] pipe_rx_data_l3_out; wire [7:0] pipe_rx_data_l4_out; wire [7:0] pipe_rx_data_l5_out; wire [7:0] pipe_rx_data_l6_out; wire [7:0] pipe_rx_data_l7_out; reg [7:0] pipe_lane_present_aligned; wire [7:0] pipe_rx_data_k_out; wire [7:0] pipe_rx_valid_out; wire chan_bond_done; `endif reg [4:0] cmt_rst_cnt = 5'b0; reg cmt_rst; // New Delayed User Reset, per Email from Sweatha 11/17/07 part of fix for Matrox training issue wire pcie_reset; // from gt wrapper wire d_user_reset_n = user_reset_n & (~pcie_reset); // register ltssm state for timing purposes always @(posedge crm_core_clk or negedge d_user_reset_n) begin if (!d_user_reset_n) reg_l0_ltssm_state_internal <= 4'h0; else reg_l0_ltssm_state_internal <= l0_ltssm_state; end assign l0_ltssm_state_internal = reg_l0_ltssm_state_internal; // enable ltssm reset only under the condition elec idle is broken // after ltssm is in polling. Disable it after reset is done. always @(posedge crm_core_clk or negedge d_user_reset_n) begin if (!d_user_reset_n) reg_enable_ltssm_reset <= 0; else if (ltssm_reset[3]) reg_enable_ltssm_reset <= 0; else if (pipe_rx_elec_idle_l0 & (l0_ltssm_state_internal == 4'b0010)) reg_enable_ltssm_reset <= 1; end assign enable_ltssm_reset = reg_enable_ltssm_reset; // count up to 8 clock cycles when enable is asserted and elec idle is broken. // Stop counting after 8 clock cycles. always @(posedge crm_core_clk or negedge d_user_reset_n) begin if (!d_user_reset_n) reg_ltssm_reset <= 4'h0; else if (enable_ltssm_reset & !ltssm_reset[3] & !pipe_rx_elec_idle_l0) reg_ltssm_reset <= reg_ltssm_reset + 4'h1; end assign ltssm_reset = reg_ltssm_reset; // assert and hold ltssm reset for 8 clock cycles when enable_ltssm_reset is asserted and elec idle is broken wire user_reset_workaround_n = d_user_reset_n & !(enable_ltssm_reset & !pipe_rx_elec_idle_l0 & !ltssm_reset[3]); //wire ignore_this_rst = (enable_ltssm_reset & !pipe_rx_elec_idle_l0 & !ltssm_reset[3]); generate if (G_USER_RESETS == 1) begin : no_reset_logic assign rb_crm_urst_n = 1'b1; assign rb_crm_nvrst_n = 1'b1; assign rb_crm_mgmt_rst_n = 1'b1; assign rb_crm_user_cfg_rst_n = 1'b1; assign rb_crm_mac_rst_n = 1'b1; assign rb_crm_link_rst_n = 1'b1; end else begin : use_reset_logic reset_logic #( .G_RESETMODE (RESETMODE), .G_RESETSUBMODE (0) ) reset_i ( .L0DLUPDOWN (l0_dl_up_down[0]), .GSR (gsr), .CRMCORECLK (crm_core_clk), .USERCLK (user_clk), .L0LTSSMSTATE (l0_ltssm_state), .CRMDOHOTRESETN (crm_do_hot_reset_n), .CRMPWRSOFTRESETN (crm_pwr_soft_reset_n), .L0STATSCFGTRANSMITTED (l0_stats_cfg_transmitted), .CRMMGMTRSTN (rb_crm_mgmt_rst_n), .CRMNVRSTN (rb_crm_nvrst_n), .CRMMACRSTN (rb_crm_mac_rst_n), .CRMLINKRSTN (rb_crm_link_rst_n), .CRMURSTN (rb_crm_urst_n), .CRMUSERCFGRSTN (rb_crm_user_cfg_rst_n), .user_master_reset_n (user_reset_workaround_n), .clock_ready (clock_lock) ); end endgenerate assign mux_crm_mgmt_rst_n = (G_USER_RESETS == 1) ? crm_mgmt_rst_n : rb_crm_mgmt_rst_n; `ifdef MANAGEMENT_WRITE assign mux_crm_nvrst_n = (G_USER_RESETS == 1) ? crm_nvrst_n : (rb_crm_nvrst_n && mgmt_reset_delay_n); assign mux_crm_mac_rst_n = (G_USER_RESETS == 1) ? crm_mac_rst_n : (rb_crm_mac_rst_n && mgmt_reset_delay_n); assign mux_crm_link_rst_n = (G_USER_RESETS == 1) ? crm_link_rst_n : (rb_crm_link_rst_n && mgmt_reset_delay_n); assign mux_crm_urst_n = (G_USER_RESETS == 1) ? crm_urst_n : (rb_crm_urst_n && mgmt_reset_delay_n); assign mux_crm_user_cfg_rst_n = (G_USER_RESETS == 1) ? crm_user_cfg_rst_n : (rb_crm_user_cfg_rst_n && mgmt_reset_delay_n); assign mgmt_rdy = rb_crm_mgmt_rst_n; `else assign mux_crm_nvrst_n = (G_USER_RESETS == 1) ? crm_nvrst_n : rb_crm_nvrst_n; assign mux_crm_mac_rst_n = (G_USER_RESETS == 1) ? crm_mac_rst_n : rb_crm_mac_rst_n; assign mux_crm_link_rst_n = (G_USER_RESETS == 1) ? crm_link_rst_n : rb_crm_link_rst_n; assign mux_crm_urst_n = (G_USER_RESETS == 1) ? crm_urst_n : rb_crm_urst_n; assign mux_crm_user_cfg_rst_n = (G_USER_RESETS == 1) ? crm_user_cfg_rst_n : rb_crm_user_cfg_rst_n; `endif always @(posedge REFCLKOUT_bufg) begin if (user_reset_n == 1'b1) begin cmt_rst_cnt <= 0; end else if (cmt_rst_cnt == 16) begin cmt_rst_cnt <= 16; end else if (user_reset_n == 1'b0) begin cmt_rst_cnt <= cmt_rst_cnt + 1'b1; end if (cmt_rst_cnt > 0 && cmt_rst_cnt < 16) begin cmt_rst <= 1'b1; end else begin cmt_rst <= 1'b0; end end pcie_clocking #( .G_DIVIDE_VAL (CLKRATIO), // use 1 for 250MHz use 2 for 125MHz and 4 for 62.5MHz .REF_CLK_FREQ (REF_CLK_FREQ) // use 0 for 100 MHz, 1 for 250 MHz ) clocking_i ( .clkin_pll (REFCLKOUT_bufg), .clkin_dcm (GTPCLK_bufg), //.rst (cmt_rst), .rst (~PLLLKDET_OUT[0]), .coreclk (core_clk), .userclk (user_clk), .gtx_usrclk (gt_usrclk), .txsync_clk (txsync_clk), .locked (clock_lock), .fast_train_simulation_only(fast_train_simulation_only) ); assign usrclk = (CLKDIVIDED == "FALSE") ? 1'b1 : user_clk; assign crm_core_clk_rx_o = core_clk; assign crm_user_clk_rx_o = usrclk; assign crm_core_clk_tx_o = core_clk; assign crm_user_clk_tx_o = usrclk; assign crm_core_clk_dl_o = core_clk; assign crm_core_clk = core_clk; assign crm_core_clkb = core_clkb; assign crm_user_clk = usrclk; //synthesis translate_off `ifdef PCIEBLKRTL initial begin force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.cfg_reset = glbl.GSR; force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.grestore = glbl.GSR; force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.gwe = 1'b1; force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.ghigh_b = 1'b1; force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.scanenable_n = 1'b1; force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.scanmode_n = 1'b1; force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.scanin = 8'b0; force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.mc_core_clk_dl_o_inv = 1'b0; force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.mc_core_clk_rx_o_inv = 1'b0; force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.mc_user_clk_rx_o_inv = 1'b0; force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.mc_core_clk_tx_o_inv = 1'b0; force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.mc_user_clk_tx_o_inv = 1'b0; force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.mc_core_clk_inv = 1'b0; force pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.ipcie.mc_user_clk_inv = 1'b0; end defparam pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.G_TEST_MODE = 1; //`else //defparam pcie_ep.pcie_internal_1_1_1.pcie_internal_1_1_swift_1.TEST_MODE = "1"; `endif //synthesis translate_on PCIE_EP # ( .CLKDIVIDED (CLKDIVIDED ), .RESETMODE (RESETMODE ), .VENDORID (VENDORID ), .DEVICEID (DEVICEID ), .REVISIONID (REVISIONID ), .CLASSCODE (CLASSCODE ), .CARDBUSCISPOINTER (CARDBUSCISPOINTER ), .SUBSYSTEMVENDORID (SUBSYSTEMVENDORID ), .SUBSYSTEMID (SUBSYSTEMID ), .CAPABILITIESPOINTER (CAPABILITIESPTR_CALC ), .INTERRUPTPIN (INTERRUPTPIN ), .AERBASEPTR (AERBASEPTR ), .DSNBASEPTR (DSNBASEPTR ), .MSIBASEPTR (MSIBASEPTR ), .PBBASEPTR (PBBASEPTR ), .PMBASEPTR (PMBASEPTR ), .VCBASEPTR (VCBASEPTR ), .XPBASEPTR (XPBASEPTR ), .PMDATASCALE0 (PMDATASCALE0 ), .PMDATASCALE1 (PMDATASCALE1 ), .PMDATASCALE2 (PMDATASCALE2 ), .PMDATASCALE3 (PMDATASCALE3 ), .PMDATASCALE4 (PMDATASCALE4 ), .PMDATASCALE5 (PMDATASCALE5 ), .PMDATASCALE6 (PMDATASCALE6 ), .PMDATASCALE7 (PMDATASCALE7 ), .PMCAPABILITYNEXTPTR (PMCAPABILITYNEXTPTR_CALC ), .PMCAPABILITYDSI (PMCAPABILITYDSI ), .PMCAPABILITYAUXCURRENT (PMCAPABILITYAUXCURRENT ), .PMCAPABILITYD1SUPPORT (PMCAPABILITYD1SUPPORT ), .PMCAPABILITYD2SUPPORT (PMCAPABILITYD2SUPPORT ), .PMCAPABILITYPMESUPPORT (PMCAPABILITYPMESUPPORT ), .PMDATA0 (PMDATA0 ), .PMDATA1 (PMDATA1 ), .PMDATA2 (PMDATA2 ), .PMDATA3 (PMDATA3 ), .PMDATA4 (PMDATA4 ), .PMDATA5 (PMDATA5 ), .PMDATA6 (PMDATA6 ), .PMDATA7 (PMDATA7 ), .MSICAPABILITYNEXTPTR (MSICAPABILITYNEXTPTR_CALC ), .MSICAPABILITYMULTIMSGCAP (MSICAPABILITYMULTIMSGCAP ), .PCIECAPABILITYNEXTPTR (PCIECAPABILITYNEXTPTR_CALC ), .DEVICECAPABILITYENDPOINTL0SLATENCY (DEVICECAPABILITYENDPOINTL0SLATENCY ), .DEVICECAPABILITYENDPOINTL1LATENCY (DEVICECAPABILITYENDPOINTL1LATENCY ), .LINKCAPABILITYMAXLINKWIDTH (LINKCAPABILITYMAXLINKWIDTH ), .LINKCAPABILITYASPMSUPPORT (LINKCAPABILITYASPMSUPPORT_CALC ), .LINKSTATUSSLOTCLOCKCONFIG (LINKSTATUSSLOTCLOCKCONFIG ), .AERCAPABILITYNEXTPTR (AERCAPABILITYNEXTPTR ), .VCCAPABILITYNEXTPTR (VCCAPABILITYNEXTPTR ), .PORTVCCAPABILITYEXTENDEDVCCOUNT (PORTVCCAPABILITYEXTENDEDVCCOUNT ), .PORTVCCAPABILITYVCARBCAP (PORTVCCAPABILITYVCARBCAP ), .PORTVCCAPABILITYVCARBTABLEOFFSET (PORTVCCAPABILITYVCARBTABLEOFFSET_CALC), .DSNCAPABILITYNEXTPTR (DSNCAPABILITYNEXTPTR ), .DEVICESERIALNUMBER (DEVICESERIALNUMBER ), .PBCAPABILITYNEXTPTR (PBCAPABILITYNEXTPTR ), .PBCAPABILITYDW0BASEPOWER (PBCAPABILITYDW0BASEPOWER ), .PBCAPABILITYDW0DATASCALE (PBCAPABILITYDW0DATASCALE ), .PBCAPABILITYDW0PMSUBSTATE (PBCAPABILITYDW0PMSUBSTATE ), .PBCAPABILITYDW0PMSTATE (PBCAPABILITYDW0PMSTATE ), .PBCAPABILITYDW0TYPE (PBCAPABILITYDW0TYPE ), .PBCAPABILITYDW0POWERRAIL (PBCAPABILITYDW0POWERRAIL ), .PBCAPABILITYDW1BASEPOWER (PBCAPABILITYDW1BASEPOWER ), .PBCAPABILITYDW1DATASCALE (PBCAPABILITYDW1DATASCALE ), .PBCAPABILITYDW1PMSUBSTATE (PBCAPABILITYDW1PMSUBSTATE ), .PBCAPABILITYDW1PMSTATE (PBCAPABILITYDW1PMSTATE ), .PBCAPABILITYDW1TYPE (PBCAPABILITYDW1TYPE ), .PBCAPABILITYDW1POWERRAIL (PBCAPABILITYDW1POWERRAIL ), .PBCAPABILITYDW2BASEPOWER (PBCAPABILITYDW2BASEPOWER ), .PBCAPABILITYDW2DATASCALE (PBCAPABILITYDW2DATASCALE ), .PBCAPABILITYDW2PMSUBSTATE (PBCAPABILITYDW2PMSUBSTATE ), .PBCAPABILITYDW2PMSTATE (PBCAPABILITYDW2PMSTATE ), .PBCAPABILITYDW2TYPE (PBCAPABILITYDW2TYPE ), .PBCAPABILITYDW2POWERRAIL (PBCAPABILITYDW2POWERRAIL ), .PBCAPABILITYDW3BASEPOWER (PBCAPABILITYDW3BASEPOWER ), .PBCAPABILITYDW3DATASCALE (PBCAPABILITYDW3DATASCALE ), .PBCAPABILITYDW3PMSUBSTATE (PBCAPABILITYDW3PMSUBSTATE ), .PBCAPABILITYDW3PMSTATE (PBCAPABILITYDW3PMSTATE ), .PBCAPABILITYDW3TYPE (PBCAPABILITYDW3TYPE ), .PBCAPABILITYDW3POWERRAIL (PBCAPABILITYDW3POWERRAIL ), .PBCAPABILITYSYSTEMALLOCATED (PBCAPABILITYSYSTEMALLOCATED ), .VC0TXFIFOBASEP (VC0TXFIFOBASEP_CALC ), .VC0TXFIFOBASENP (VC0TXFIFOBASENP_CALC ), .VC0TXFIFOBASEC (VC0TXFIFOBASEC_CALC ), .VC0TXFIFOLIMITP (VC0TXFIFOLIMITP_CALC ), .VC0TXFIFOLIMITNP (VC0TXFIFOLIMITNP_CALC ), .VC0TXFIFOLIMITC (VC0TXFIFOLIMITC_CALC ), .VC0TOTALCREDITSPH (VC0TOTALCREDITSPH ), .VC0TOTALCREDITSNPH (VC0TOTALCREDITSNPH ), .VC0TOTALCREDITSCH (VC0TOTALCREDITSCH ), .VC0TOTALCREDITSPD (VC0TOTALCREDITSPD ), .VC0TOTALCREDITSCD (VC0TOTALCREDITSCD ), .VC0RXFIFOBASEP (VC0RXFIFOBASEP_CALC ), .VC0RXFIFOBASENP (VC0RXFIFOBASENP_CALC ), .VC0RXFIFOBASEC (VC0RXFIFOBASEC_CALC ), .VC0RXFIFOLIMITP (VC0RXFIFOLIMITP_CALC ), .VC0RXFIFOLIMITNP (VC0RXFIFOLIMITNP_CALC ), .VC0RXFIFOLIMITC (VC0RXFIFOLIMITC_CALC ), .VC1TXFIFOBASEP (VC1TXFIFOBASEP_CALC ), .VC1TXFIFOBASENP (VC1TXFIFOBASENP_CALC ), .VC1TXFIFOBASEC (VC1TXFIFOBASEC_CALC ), .VC1TXFIFOLIMITP (VC1TXFIFOLIMITP_CALC ), .VC1TXFIFOLIMITNP (VC1TXFIFOLIMITNP_CALC ), .VC1TXFIFOLIMITC (VC1TXFIFOLIMITC_CALC ), .VC1TOTALCREDITSPH (VC1TOTALCREDITSPH ), .VC1TOTALCREDITSNPH (VC1TOTALCREDITSNPH ), .VC1TOTALCREDITSCH (VC1TOTALCREDITSCH ), .VC1TOTALCREDITSPD (VC1TOTALCREDITSPD ), .VC1TOTALCREDITSCD (VC1TOTALCREDITSCD ), .VC1RXFIFOBASEP (VC1RXFIFOBASEP_CALC ), .VC1RXFIFOBASENP (VC1RXFIFOBASENP_CALC ), .VC1RXFIFOBASEC (VC1RXFIFOBASEC_CALC ), .VC1RXFIFOLIMITP (VC1RXFIFOLIMITP_CALC ), .VC1RXFIFOLIMITNP (VC1RXFIFOLIMITNP_CALC ), .VC1RXFIFOLIMITC (VC1RXFIFOLIMITC_CALC ), .BAR0EXIST (BAR0EXIST ), .BAR1EXIST (BAR1EXIST ), .BAR2EXIST (BAR2EXIST ), .BAR3EXIST (BAR3EXIST ), .BAR4EXIST (BAR4EXIST ), .BAR5EXIST (BAR5EXIST ), .BAR0ADDRWIDTH (BAR0ADDRWIDTH_CALC ), .BAR1ADDRWIDTH (BAR1ADDRWIDTH_CALC ), .BAR2ADDRWIDTH (BAR2ADDRWIDTH_CALC ), .BAR3ADDRWIDTH (BAR3ADDRWIDTH_CALC ), .BAR4ADDRWIDTH (BAR4ADDRWIDTH_CALC ), .BAR0PREFETCHABLE (`BAR0PREFETCHABLE_CALC ), .BAR1PREFETCHABLE (`BAR1PREFETCHABLE_CALC ), .BAR2PREFETCHABLE (`BAR2PREFETCHABLE_CALC ), .BAR3PREFETCHABLE (`BAR3PREFETCHABLE_CALC ), .BAR4PREFETCHABLE (`BAR4PREFETCHABLE_CALC ), .BAR5PREFETCHABLE (`BAR5PREFETCHABLE_CALC ), .BAR0IOMEMN (BAR0IOMEMN ), .BAR1IOMEMN (BAR1IOMEMN ), .BAR2IOMEMN (BAR2IOMEMN ), .BAR3IOMEMN (BAR3IOMEMN ), .BAR4IOMEMN (BAR4IOMEMN ), .BAR5IOMEMN (BAR5IOMEMN ), .BAR0MASKWIDTH (BAR0MASKWIDTH ), .BAR1MASKWIDTH (BAR1MASKWIDTH ), .BAR2MASKWIDTH (BAR2MASKWIDTH ), .BAR3MASKWIDTH (BAR3MASKWIDTH ), .BAR4MASKWIDTH (BAR4MASKWIDTH ), .BAR5MASKWIDTH (BAR5MASKWIDTH ), .XPDEVICEPORTTYPE (XPDEVICEPORTTYPE ), .XPMAXPAYLOAD (XPMAXPAYLOAD ), .INFINITECOMPLETIONS (INFINITECOMPLETIONS ), .ACTIVELANESIN (ACTIVELANESIN ), .LOWPRIORITYVCCOUNT (LOWPRIORITYVCCOUNT ), .L0SEXITLATENCY (L0SEXITLATENCY ), .L0SEXITLATENCYCOMCLK (L0SEXITLATENCYCOMCLK ), .L1EXITLATENCY (L1EXITLATENCY ), .L1EXITLATENCYCOMCLK (L1EXITLATENCYCOMCLK ), .TXTSNFTS (TXTSNFTS ), .TXTSNFTSCOMCLK (TXTSNFTSCOMCLK ), .TLRAMREADLATENCY (TLRAMREADLATENCY ), .TLRAMWRITELATENCY (TLRAMWRITELATENCY ), .RETRYRAMSIZE (RETRYRAMSIZE_CALC ), .RETRYRAMREADLATENCY (RETRYRAMREADLATENCY ), .RETRYRAMWRITELATENCY (RETRYRAMWRITELATENCY ) ) pcie_ep ( .PIPERXELECIDLEL0 ( pipe_rx_elec_idle_l0 ), .PIPERXSTATUSL0 ( pipe_rx_status_l0 ), `ifdef PRODFIX .PIPERXDATAL0 ( pipe_rx_data_l0_out ), `else .PIPERXDATAL0 ( pipe_rx_data_l0 ), `endif .PIPEPHYSTATUSL0 ( pipe_rx_phy_status_l0 ), `ifdef PRODFIX .PIPERXDATAKL0 ( pipe_rx_data_k_l0 ), .PIPERXVALIDL0 ( pipe_rx_valid_l0 ), `else .PIPERXDATAKL0 ( pipe_rx_data_k[0] ), .PIPERXVALIDL0 ( pipe_rx_valid[0] ), `endif .PIPERXCHANISALIGNEDL0 ( pipe_rxchanisaligned_l0 ), .PIPERXELECIDLEL1 ( pipe_rx_elec_idle_l1 ), .PIPERXSTATUSL1 ( pipe_rx_status_l1 ), `ifdef PRODFIX .PIPERXDATAL1 ( pipe_rx_data_l1_out ), `else .PIPERXDATAL1 ( pipe_rx_data_l1 ), `endif .PIPEPHYSTATUSL1 ( pipe_rx_phy_status_l1 ), `ifdef PRODFIX .PIPERXDATAKL1 ( pipe_rx_data_k_l1 ), .PIPERXVALIDL1 ( pipe_rx_valid_l1 ), `else .PIPERXDATAKL1 ( pipe_rx_data_k[1] ), .PIPERXVALIDL1 ( pipe_rx_valid[1] ), `endif .PIPERXCHANISALIGNEDL1 ( pipe_rxchanisaligned_l1 ), .PIPERXELECIDLEL2 ( pipe_rx_elec_idle_l2 ), .PIPERXSTATUSL2 ( pipe_rx_status_l2 ), `ifdef PRODFIX .PIPERXDATAL2 ( pipe_rx_data_l2_out ), `else .PIPERXDATAL2 ( pipe_rx_data_l2 ), `endif .PIPEPHYSTATUSL2 ( pipe_rx_phy_status_l2 ), `ifdef PRODFIX .PIPERXDATAKL2 ( pipe_rx_data_k_l2 ), .PIPERXVALIDL2 ( pipe_rx_valid_l2 ), `else .PIPERXDATAKL2 ( pipe_rx_data_k[2] ), .PIPERXVALIDL2 ( pipe_rx_valid[2] ), `endif .PIPERXCHANISALIGNEDL2 ( pipe_rxchanisaligned_l2 ), .PIPERXELECIDLEL3 ( pipe_rx_elec_idle_l3 ), .PIPERXSTATUSL3 ( pipe_rx_status_l3 ), `ifdef PRODFIX .PIPERXDATAL3 ( pipe_rx_data_l3_out ), `else .PIPERXDATAL3 ( pipe_rx_data_l3 ), `endif .PIPEPHYSTATUSL3 ( pipe_rx_phy_status_l3 ), `ifdef PRODFIX .PIPERXDATAKL3 ( pipe_rx_data_k_l3 ), .PIPERXVALIDL3 ( pipe_rx_valid_l3 ), `else .PIPERXDATAKL3 ( pipe_rx_data_k[3] ), .PIPERXVALIDL3 ( pipe_rx_valid[3] ), `endif .PIPERXCHANISALIGNEDL3 ( pipe_rxchanisaligned_l3 ), .PIPERXELECIDLEL4 ( pipe_rx_elec_idle_l4 ), .PIPERXSTATUSL4 ( pipe_rx_status_l4 ), `ifdef PRODFIX .PIPERXDATAL4 ( pipe_rx_data_l4_out ), `else .PIPERXDATAL4 ( pipe_rx_data_l4 ), `endif .PIPEPHYSTATUSL4 ( pipe_rx_phy_status_l4 ), `ifdef PRODFIX .PIPERXDATAKL4 ( pipe_rx_data_k_l4 ), .PIPERXVALIDL4 ( pipe_rx_valid_l4 ), `else .PIPERXDATAKL4 ( pipe_rx_data_k[4] ), .PIPERXVALIDL4 ( pipe_rx_valid[4] ), `endif .PIPERXCHANISALIGNEDL4 ( pipe_rxchanisaligned_l4 ), .PIPERXELECIDLEL5 ( pipe_rx_elec_idle_l5 ), .PIPERXSTATUSL5 ( pipe_rx_status_l5 ), `ifdef PRODFIX .PIPERXDATAL5 ( pipe_rx_data_l5_out ), `else .PIPERXDATAL5 ( pipe_rx_data_l5 ), `endif .PIPEPHYSTATUSL5 ( pipe_rx_phy_status_l5 ), `ifdef PRODFIX .PIPERXDATAKL5 ( pipe_rx_data_k_l5 ), .PIPERXVALIDL5 ( pipe_rx_valid_l5 ), `else .PIPERXDATAKL5 ( pipe_rx_data_k[5] ), .PIPERXVALIDL5 ( pipe_rx_valid[5] ), `endif .PIPERXCHANISALIGNEDL5 ( pipe_rxchanisaligned_l5 ), .PIPERXELECIDLEL6 ( pipe_rx_elec_idle_l6 ), .PIPERXSTATUSL6 ( pipe_rx_status_l6 ), `ifdef PRODFIX .PIPERXDATAL6 ( pipe_rx_data_l6_out ), `else .PIPERXDATAL6 ( pipe_rx_data_l6 ), `endif .PIPEPHYSTATUSL6 ( pipe_rx_phy_status_l6 ), `ifdef PRODFIX .PIPERXDATAKL6 ( pipe_rx_data_k_l6 ), .PIPERXVALIDL6 ( pipe_rx_valid_l6 ), `else .PIPERXDATAKL6 ( pipe_rx_data_k[6] ), .PIPERXVALIDL6 ( pipe_rx_valid[6] ), `endif .PIPERXCHANISALIGNEDL6 ( pipe_rxchanisaligned_l6 ), .PIPERXELECIDLEL7 ( pipe_rx_elec_idle_l7 ), .PIPERXSTATUSL7 ( pipe_rx_status_l7 ), `ifdef PRODFIX .PIPERXDATAL7 ( pipe_rx_data_l7_out ), `else .PIPERXDATAL7 ( pipe_rx_data_l7 ), `endif .PIPEPHYSTATUSL7 ( pipe_rx_phy_status_l7 ), `ifdef PRODFIX .PIPERXDATAKL7 ( pipe_rx_data_k_l7 ), .PIPERXVALIDL7 ( pipe_rx_valid_l7 ), `else .PIPERXDATAKL7 ( pipe_rx_data_k[7] ), .PIPERXVALIDL7 ( pipe_rx_valid[7] ), `endif .PIPERXCHANISALIGNEDL7 ( pipe_rxchanisaligned_l7 ), .MIMRXBRDATA ( mim_rx_brdata ), .CRMCORECLKRXO ( crm_core_clk_rx_o ), .CRMUSERCLKRXO ( crm_user_clk_rx_o ), .MIMTXBRDATA ( mim_tx_brdata ), .CRMCORECLKTXO ( crm_core_clk_tx_o ), .CRMUSERCLKTXO ( crm_user_clk_tx_o ), .MIMDLLBRDATA ( mim_dll_brdata ), .CRMCORECLKDLO ( crm_core_clk_dl_o ), .CRMCORECLK ( crm_core_clk ), .CRMUSERCLK ( crm_user_clk ), .CRMURSTN (mux_crm_urst_n ), .CRMNVRSTN (mux_crm_nvrst_n ), .CRMMGMTRSTN (mux_crm_mgmt_rst_n ), .CRMLINKRSTN (mux_crm_link_rst_n ), .CRMMACRSTN (mux_crm_mac_rst_n ), .CRMUSERCFGRSTN (mux_crm_user_cfg_rst_n ), .LLKTXDATA (llk_tx_data ), .LLKTXSRCRDYN (llk_tx_src_rdy_n ), .LLKTXSRCDSCN (llk_tx_src_dsc_n ), .LLKTXSOFN (llk_tx_sof_n ), .LLKTXEOFN (llk_tx_eof_n ), .LLKTXSOPN (llk_tx_sop_n ), .LLKTXEOPN (llk_tx_eop_n ), .LLKTXENABLEN (llk_tx_enable_n ), .LLKTXCHTC (llk_tx_ch_tc ), .LLKTXCHFIFO (llk_tx_ch_fifo ), .LLKRXDSTREQN (llk_rx_dst_req_n ), .LLKRXDSTCONTREQN (llk_rx_dst_cont_req_n ), .LLKRXCHTC (llk_rx_ch_tc ), .LLKRXCHFIFO (llk_rx_ch_fifo ), .MGMTWDATA (mgmt_wdata ), .MGMTBWREN (mgmt_bwren ), .MGMTWREN (mgmt_wren ), .MGMTADDR (mgmt_addr ), .MGMTRDEN (mgmt_rden ), .MGMTSTATSCREDITSEL (mgmt_stats_credit_sel ), .AUXPOWER (AUXPOWER ), .COMPLIANCEAVOID (compliance_avoid ), .L0CFGLOOPBACKMASTER (l0_cfg_loopback_master ), .L0CFGDISABLESCRAMBLE (FORCENOSCRAMBLING ), .L0TRANSACTIONSPENDING (l0_transactions_pending ), .L0SETCOMPLETERABORTERROR (l0_set_completer_abort_error ), .L0SETDETECTEDCORRERROR (l0_set_detected_corr_error ), .L0SETDETECTEDFATALERROR (l0_set_detected_fatal_error ), .L0SETDETECTEDNONFATALERROR (l0_set_detected_nonfatal_error ), .L0SETUSERDETECTEDPARITYERROR (l0_set_user_detected_parity_error), .L0SETUSERMASTERDATAPARITY (l0_set_user_master_data_parity ), .L0SETUSERRECEIVEDMASTERABORT (l0_set_user_received_master_abort), .L0SETUSERRECEIVEDTARGETABORT (l0_set_user_received_target_abort), .L0SETUSERSYSTEMERROR (l0_set_user_system_error ), .L0SETUSERSIGNALLEDTARGETABORT (l0_set_user_signalled_target_abort), .L0SETCOMPLETIONTIMEOUTUNCORRERROR(l0_set_completion_timeout_uncorr_error), .L0SETCOMPLETIONTIMEOUTCORRERROR (l0_set_completion_timeout_corr_error), .L0SETUNEXPECTEDCOMPLETIONUNCORRERROR(l0_set_unexpected_completion_uncorr_error), .L0SETUNEXPECTEDCOMPLETIONCORRERROR(l0_set_unexpected_completion_corr_error), .L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR(l0_set_unsupported_request_nonposted_error), .L0SETUNSUPPORTEDREQUESTOTHERERROR(l0_set_unsupported_request_other_error), .L0PACKETHEADERFROMUSER (128'h00000000000000000000000000000000), .L0LEGACYINTFUNCT0 (l0_legacy_int_funct0 ), .L0MSIREQUEST0 (l0_msi_request0 ), .L0PMEREQIN (l0_pme_req_in ), .PIPETXDATAL0 (pipe_tx_data_l0 ), .PIPETXDATAKL0 (pipe_tx_data_k_l0 ), .PIPETXELECIDLEL0 (pipe_tx_elec_idle_l0 ), .PIPETXDETECTRXLOOPBACKL0 (pipe_tx_detect_rx_loopback_l0 ), .PIPETXCOMPLIANCEL0 (pipe_tx_compliance_l0 ), .PIPERXPOLARITYL0 (pipe_rx_polarity_l0 ), .PIPEPOWERDOWNL0 (pipe_power_down_l0 ), .PIPEDESKEWLANESL0 (pipe_deskew_lanes_l0 ), .PIPERESETL0 (pipe_reset_l0 ), .PIPETXDATAL1 (pipe_tx_data_l1 ), .PIPETXDATAKL1 (pipe_tx_data_k_l1 ), .PIPETXELECIDLEL1 (pipe_tx_elec_idle_l1 ), .PIPETXDETECTRXLOOPBACKL1 (pipe_tx_detect_rx_loopback_l1 ), .PIPETXCOMPLIANCEL1 (pipe_tx_compliance_l1 ), .PIPERXPOLARITYL1 (pipe_rx_polarity_l1 ), .PIPEPOWERDOWNL1 (pipe_power_down_l1 ), .PIPEDESKEWLANESL1 (pipe_deskew_lanes_l1 ), .PIPERESETL1 (pipe_reset_l1 ), .PIPETXDATAL2 (pipe_tx_data_l2 ), .PIPETXDATAKL2 (pipe_tx_data_k_l2 ), .PIPETXELECIDLEL2 (pipe_tx_elec_idle_l2 ), .PIPETXDETECTRXLOOPBACKL2 (pipe_tx_detect_rx_loopback_l2 ), .PIPETXCOMPLIANCEL2 (pipe_tx_compliance_l2 ), .PIPERXPOLARITYL2 (pipe_rx_polarity_l2 ), .PIPEPOWERDOWNL2 (pipe_power_down_l2 ), .PIPEDESKEWLANESL2 (pipe_deskew_lanes_l2 ), .PIPERESETL2 (pipe_reset_l2 ), .PIPETXDATAL3 (pipe_tx_data_l3 ), .PIPETXDATAKL3 (pipe_tx_data_k_l3 ), .PIPETXELECIDLEL3 (pipe_tx_elec_idle_l3 ), .PIPETXDETECTRXLOOPBACKL3 (pipe_tx_detect_rx_loopback_l3 ), .PIPETXCOMPLIANCEL3 (pipe_tx_compliance_l3 ), .PIPERXPOLARITYL3 (pipe_rx_polarity_l3 ), .PIPEPOWERDOWNL3 (pipe_power_down_l3 ), .PIPEDESKEWLANESL3 (pipe_deskew_lanes_l3 ), .PIPERESETL3 (pipe_reset_l3 ), .PIPETXDATAL4 (pipe_tx_data_l4 ), .PIPETXDATAKL4 (pipe_tx_data_k_l4 ), .PIPETXELECIDLEL4 (pipe_tx_elec_idle_l4 ), .PIPETXDETECTRXLOOPBACKL4 (pipe_tx_detect_rx_loopback_l4 ), .PIPETXCOMPLIANCEL4 (pipe_tx_compliance_l4 ), .PIPERXPOLARITYL4 (pipe_rx_polarity_l4 ), .PIPEPOWERDOWNL4 (pipe_power_down_l4 ), .PIPEDESKEWLANESL4 (pipe_deskew_lanes_l4 ), .PIPERESETL4 (pipe_reset_l4 ), .PIPETXDATAL5 (pipe_tx_data_l5 ), .PIPETXDATAKL5 (pipe_tx_data_k_l5 ), .PIPETXELECIDLEL5 (pipe_tx_elec_idle_l5 ), .PIPETXDETECTRXLOOPBACKL5 (pipe_tx_detect_rx_loopback_l5 ), .PIPETXCOMPLIANCEL5 (pipe_tx_compliance_l5 ), .PIPERXPOLARITYL5 (pipe_rx_polarity_l5 ), .PIPEPOWERDOWNL5 (pipe_power_down_l5 ), .PIPEDESKEWLANESL5 (pipe_deskew_lanes_l5 ), .PIPERESETL5 (pipe_reset_l5 ), .PIPETXDATAL6 (pipe_tx_data_l6 ), .PIPETXDATAKL6 (pipe_tx_data_k_l6 ), .PIPETXELECIDLEL6 (pipe_tx_elec_idle_l6 ), .PIPETXDETECTRXLOOPBACKL6 (pipe_tx_detect_rx_loopback_l6 ), .PIPETXCOMPLIANCEL6 (pipe_tx_compliance_l6 ), .PIPERXPOLARITYL6 (pipe_rx_polarity_l6 ), .PIPEPOWERDOWNL6 (pipe_power_down_l6 ), .PIPEDESKEWLANESL6 (pipe_deskew_lanes_l6 ), .PIPERESETL6 (pipe_reset_l6 ), .PIPETXDATAL7 (pipe_tx_data_l7 ), .PIPETXDATAKL7 (pipe_tx_data_k_l7 ), .PIPETXELECIDLEL7 (pipe_tx_elec_idle_l7 ), .PIPETXDETECTRXLOOPBACKL7 (pipe_tx_detect_rx_loopback_l7 ), .PIPETXCOMPLIANCEL7 (pipe_tx_compliance_l7 ), .PIPERXPOLARITYL7 (pipe_rx_polarity_l7 ), .PIPEPOWERDOWNL7 (pipe_power_down_l7 ), .PIPEDESKEWLANESL7 (pipe_deskew_lanes_l7 ), .PIPERESETL7 (pipe_reset_l7 ), .MIMRXBWDATA (mim_rx_bwdata ), .MIMRXBWADD (mim_rx_bwadd ), .MIMRXBRADD (mim_rx_bradd ), .MIMRXBWEN (mim_rx_bwen ), .MIMRXBREN (mim_rx_bren ), .MIMTXBWDATA (mim_tx_bwdata ), .MIMTXBWADD (mim_tx_bwadd ), .MIMTXBRADD (mim_tx_bradd ), .MIMTXBWEN (mim_tx_bwen ), .MIMTXBREN (mim_tx_bren ), .MIMDLLBWDATA (mim_dll_bwdata ), .MIMDLLBWADD (mim_dll_bwadd ), .MIMDLLBRADD (mim_dll_bradd ), .MIMDLLBWEN (mim_dll_bwen ), .MIMDLLBREN (mim_dll_bren ), .CRMDOHOTRESETN (crm_do_hot_reset_n ), .CRMPWRSOFTRESETN (crm_pwr_soft_reset_n ), .LLKTCSTATUS (llk_tc_status ), .LLKTXDSTRDYN (llk_tx_dst_rdy_n ), .LLKTXCHANSPACE (llk_tx_chan_space ), .LLKTXCHPOSTEDREADYN (llk_tx_ch_posted_ready_n ), .LLKTXCHNONPOSTEDREADYN (llk_tx_ch_non_posted_ready_n ), .LLKTXCHCOMPLETIONREADYN (llk_tx_ch_completion_ready_n ), .LLKRXDATA (llk_rx_data ), .LLKRXSRCRDYN (llk_rx_src_rdy_n ), .LLKRXSRCLASTREQN (llk_rx_src_last_req_n ), .LLKRXSOFN (llk_rx_sof_n ), .LLKRXEOFN (llk_rx_eof_n ), .LLKRXSOPN (llk_rx_sop_n ), .LLKRXEOPN (llk_rx_eop_n ), .LLKRXVALIDN (llk_rx_valid_n ), .LLKRXPREFERREDTYPE (llk_rx_preferred_type ), .LLKRXCHPOSTEDAVAILABLEN (llk_rx_ch_posted_available_n ), .LLKRXCHNONPOSTEDAVAILABLEN (llk_rx_ch_non_posted_available_n), .LLKRXCHCOMPLETIONAVAILABLEN (llk_rx_ch_completion_available_n), .MGMTRDATA (mgmt_rdata ), .MGMTPSO (mgmt_pso ), .MGMTSTATSCREDIT (mgmt_stats_credit ), .DLLTXPMDLLPOUTSTANDING (), .L0FIRSTCFGWRITEOCCURRED (l0_first_cfg_write_occurred ), .L0CFGLOOPBACKACK (l0_cfg_loopback_ack ), .L0RXMACLINKERROR (l0_rx_mac_link_error ), .L0MACLINKUP (l0_mac_link_up ), .L0MACNEGOTIATEDLINKWIDTH (negotiated_link_width ), .L0MACLINKTRAINING (l0_mac_link_training ), .L0LTSSMSTATE (l0_ltssm_state ), .L0DLLVCSTATUS (), .L0DLUPDOWN (l0_dl_up_down ), .L0DLLERRORVECTOR (l0_dll_error_vector ), .L0COMPLETERID (l0_completer_id ), .L0UNLOCKRECEIVED (), .L0MSIENABLE0 (l0_msi_enable0 ), .L0MULTIMSGEN0 (l0_multi_msg_en0 ), .L0STATSDLLPRECEIVED (l0_stats_dllp_received ), .L0STATSDLLPTRANSMITTED (l0_stats_dllp_transmitted ), .L0STATSOSRECEIVED (l0_stats_os_received ), .L0STATSOSTRANSMITTED (l0_stats_os_transmitted ), .L0STATSTLPRECEIVED (l0_stats_tlp_received ), .L0STATSTLPTRANSMITTED (l0_stats_tlp_transmitted ), .L0STATSCFGRECEIVED (l0_stats_cfg_received ), .L0STATSCFGTRANSMITTED (l0_stats_cfg_transmitted ), .L0STATSCFGOTHERRECEIVED (l0_stats_cfg_other_received ), .L0STATSCFGOTHERTRANSMITTED (l0_stats_cfg_other_transmitted ), .MAXPAYLOADSIZE (maxpayloadsize_i ), .MAXREADREQUESTSIZE (maxreadrequestsize_i ), .IOSPACEENABLE (io_space_enable ), .MEMSPACEENABLE (mem_space_enable ), .L0PWRSTATE0 (l0_pwr_state0 ), .L0PMEACK (l0_pme_ack ), //JBG .L0PMEREQOUT (), .L0PMEEN (), .L0PWRL1STATE (), .L0PWRL23READYSTATE (l0_pwr_l23_ready_state ), .L0PWRTXL0SSTATE (l0_pwr_tx_l0s_state ), .L0PWRTURNOFFREQ (l0_pwr_turn_off_req), .L0RXDLLPM (), .L0RXDLLPMTYPE (), .L0MACNEWSTATEACK (l0_mac_new_state_ack ), .L0MACRXL0SSTATE (l0_mac_rx_l0s_state ), .L0MACENTEREDL0 (l0_mac_entered_l0 ), .L0DLLRXACKOUTSTANDING (), .L0DLLTXOUTSTANDING (), .L0DLLTXNONFCOUTSTANDING (), .BUSMASTERENABLE (bus_master_enable ), .PARITYERRORRESPONSE (parity_error_response ), .SERRENABLE (serr_enable ), .INTERRUPTDISABLE (interrupt_disable ), .URREPORTINGENABLE (ur_reporting_enable ) ); assign l0_mac_negotiated_link_width = negotiated_link_width; `ifdef PRODFIX assign trn_reset_n = PLLLKDET_OUT[0] && clock_lock && user_reset_workaround_n; //d_user_reset_n; assign chan_bond_done = &pipe_lane_present_aligned[7:0] && pipe_rxchanisaligned[0]; always@(posedge core_clk) begin pipe_lane_present_aligned[0] <= pipe_rxchanisaligned[0] ^ pipe_rx_elec_idle[0]; pipe_lane_present_aligned[1] <= pipe_rxchanisaligned[1] ^ pipe_rx_elec_idle[1]; pipe_lane_present_aligned[2] <= pipe_rxchanisaligned[2] ^ pipe_rx_elec_idle[2]; pipe_lane_present_aligned[3] <= pipe_rxchanisaligned[3] ^ pipe_rx_elec_idle[3]; pipe_lane_present_aligned[4] <= pipe_rxchanisaligned[4] ^ pipe_rx_elec_idle[4]; pipe_lane_present_aligned[5] <= pipe_rxchanisaligned[5] ^ pipe_rx_elec_idle[5]; pipe_lane_present_aligned[6] <= pipe_rxchanisaligned[6] ^ pipe_rx_elec_idle[6]; pipe_lane_present_aligned[7] <= pipe_rxchanisaligned[7] ^ pipe_rx_elec_idle[7]; end prod_fixes prod_fixes_I ( .clk(core_clk), .bit_reset_n(trn_reset_n), .l0_ltssm_state(l0_ltssm_state), //.char_is_k_l0(pipe_rx_data_k_l0), .pipe_rx_data_k(pipe_rx_data_k), .pipe_rx_valid(pipe_rx_valid), //.l0_stats_os_received(l0_stats_os_received), .negotiated_link_width(negotiated_link_width), .trn_lnk_up_n(trn_lnk_up_n), .chan_bond_done(chan_bond_done), .pipe_rx_data_l0(pipe_rx_data_l0), .pipe_rx_data_l1(pipe_rx_data_l1), .pipe_rx_data_l2(pipe_rx_data_l2), .pipe_rx_data_l3(pipe_rx_data_l3), .pipe_rx_data_l4(pipe_rx_data_l4), .pipe_rx_data_l5(pipe_rx_data_l5), .pipe_rx_data_l6(pipe_rx_data_l6), .pipe_rx_data_l7(pipe_rx_data_l7), .pipe_rx_data_l0_out(pipe_rx_data_l0_out), .pipe_rx_data_l1_out(pipe_rx_data_l1_out), .pipe_rx_data_l2_out(pipe_rx_data_l2_out), .pipe_rx_data_l3_out(pipe_rx_data_l3_out), .pipe_rx_data_l4_out(pipe_rx_data_l4_out), .pipe_rx_data_l5_out(pipe_rx_data_l5_out), .pipe_rx_data_l6_out(pipe_rx_data_l6_out), .pipe_rx_data_l7_out(pipe_rx_data_l7_out), .upcfgcap_cycle(upcfgcap_cycle), .masking_ack(masking_ack), .pipe_rx_data_k_out(pipe_rx_data_k_out), .pipe_rx_valid_out(pipe_rx_valid_out) ); `endif assign mem_user_clk = (CLKDIVIDED == "FALSE") ? crm_core_clk : crm_user_clk; assign max_payload_size = maxpayloadsize_i; assign max_read_request_size = maxreadrequestsize_i; pcie_mim_wrapper # ( .RETRYRAMWRITELATENCY (RETRYRAMWRITELATENCY ), .RETRYRAMREADLATENCY (RETRYRAMREADLATENCY ), .RETRYRAMSIZE (RETRYRAMSIZE_CALC), .RETRYREADDATAPIPE (0 ), .TLRAMWRITELATENCY (TLRAMWRITELATENCY ), .TLRAMREADLATENCY (TLRAMREADLATENCY ), .TL_TX_SIZE (TL_TX_SIZE), .TXREADDATAPIPE (0 ), .RXREADDATAPIPE (0 ), .TL_RX_SIZE (TL_RX_SIZE) ) pcie_mim_wrapper_i ( .mim_dll_bwadd (mim_dll_bwadd), .mim_dll_bwen (mim_dll_bwen), .mim_dll_bren (mim_dll_bren), .mim_dll_bwdata (mim_dll_bwdata), .mim_dll_bradd (mim_dll_bradd), .mim_dll_brdata (mim_dll_brdata), .mim_dll_bclk (crm_core_clk), .mim_tx_bwadd (mim_tx_bwadd), .mim_tx_bwen (mim_tx_bwen), .mim_tx_bren (mim_tx_bren), .mim_tx_bwdata (mim_tx_bwdata), .mim_tx_bradd (mim_tx_bradd), .mim_tx_brdata (mim_tx_brdata), .mim_tx_brclk (crm_core_clk), .mim_tx_bwclk (mem_user_clk), .mim_rx_bwadd (mim_rx_bwadd), .mim_rx_bwen (mim_rx_bwen), .mim_rx_bren (mim_rx_bren), .mim_rx_bwdata (mim_rx_bwdata), .mim_rx_bradd (mim_rx_bradd), .mim_rx_brdata (mim_rx_brdata), .mim_rx_bwclk (crm_core_clk), .mim_rx_brclk (mem_user_clk) ); assign {pipe_rx_elec_idle_l7, pipe_rx_elec_idle_l6, pipe_rx_elec_idle_l5, pipe_rx_elec_idle_l4, pipe_rx_elec_idle_l3, pipe_rx_elec_idle_l2, pipe_rx_elec_idle_l1, pipe_rx_elec_idle_l0} = pipe_rx_elec_idle; assign {pipe_rx_status_l7, pipe_rx_status_l6, pipe_rx_status_l5, pipe_rx_status_l4, pipe_rx_status_l3, pipe_rx_status_l2, pipe_rx_status_l1, pipe_rx_status_l0} = pipe_rx_status; assign {pipe_rx_data_k_l7, pipe_rx_data_k_l6, pipe_rx_data_k_l5, pipe_rx_data_k_l4, pipe_rx_data_k_l3, pipe_rx_data_k_l2, pipe_rx_data_k_l1, pipe_rx_data_k_l0} = pipe_rx_data_k_out; assign {pipe_rx_phy_status_l7, pipe_rx_phy_status_l6, pipe_rx_phy_status_l5, pipe_rx_phy_status_l4, pipe_rx_phy_status_l3, pipe_rx_phy_status_l2, pipe_rx_phy_status_l1, pipe_rx_phy_status_l0} = pipe_rx_phy_status; assign {pipe_rx_data_l7, pipe_rx_data_l6, pipe_rx_data_l5, pipe_rx_data_l4, pipe_rx_data_l3, pipe_rx_data_l2, pipe_rx_data_l1, pipe_rx_data_l0} = pipe_rx_data; assign {pipe_rx_valid_l7, pipe_rx_valid_l6, pipe_rx_valid_l5, pipe_rx_valid_l4, pipe_rx_valid_l3, pipe_rx_valid_l2, pipe_rx_valid_l1, pipe_rx_valid_l0} = pipe_rx_valid_out; assign {pipe_rxchanisaligned_l7, pipe_rxchanisaligned_l6, pipe_rxchanisaligned_l5, pipe_rxchanisaligned_l4, pipe_rxchanisaligned_l3, pipe_rxchanisaligned_l2, pipe_rxchanisaligned_l1, pipe_rxchanisaligned_l0} = pipe_rxchanisaligned; assign pipe_tx_data = {pipe_tx_data_l7, pipe_tx_data_l6, pipe_tx_data_l5, pipe_tx_data_l4, pipe_tx_data_l3, pipe_tx_data_l2, pipe_tx_data_l1, pipe_tx_data_l0}; assign pipe_tx_data_k = {pipe_tx_data_k_l7, pipe_tx_data_k_l6, pipe_tx_data_k_l5, pipe_tx_data_k_l4, pipe_tx_data_k_l3, pipe_tx_data_k_l2, pipe_tx_data_k_l1, pipe_tx_data_k_l0}; assign pipe_tx_elec_idle = {pipe_tx_elec_idle_l7, pipe_tx_elec_idle_l6, pipe_tx_elec_idle_l5, pipe_tx_elec_idle_l4, pipe_tx_elec_idle_l3, pipe_tx_elec_idle_l2, pipe_tx_elec_idle_l1, pipe_tx_elec_idle_l0}; assign pipe_tx_detect_rx_loopback = {pipe_tx_detect_rx_loopback_l7, pipe_tx_detect_rx_loopback_l6, pipe_tx_detect_rx_loopback_l5, pipe_tx_detect_rx_loopback_l4, pipe_tx_detect_rx_loopback_l3, pipe_tx_detect_rx_loopback_l2, pipe_tx_detect_rx_loopback_l1, pipe_tx_detect_rx_loopback_l0}; assign pipe_tx_compliance = {pipe_tx_compliance_l7, pipe_tx_compliance_l6, pipe_tx_compliance_l5, pipe_tx_compliance_l4, pipe_tx_compliance_l3, pipe_tx_compliance_l2, pipe_tx_compliance_l1, pipe_tx_compliance_l0}; assign pipe_rx_polarity = {pipe_rx_polarity_l7, pipe_rx_polarity_l6, pipe_rx_polarity_l5, pipe_rx_polarity_l4, pipe_rx_polarity_l3, pipe_rx_polarity_l2, pipe_rx_polarity_l1, pipe_rx_polarity_l0}; assign pipe_power_down = {pipe_power_down_l7, pipe_power_down_l6, pipe_power_down_l5, pipe_power_down_l4, pipe_power_down_l3, pipe_power_down_l2, pipe_power_down_l1, pipe_power_down_l0}; assign pipe_deskew_lanes = {pipe_deskew_lanes_l7, pipe_deskew_lanes_l6, pipe_deskew_lanes_l5, pipe_deskew_lanes_l4, pipe_deskew_lanes_l3, pipe_deskew_lanes_l2, pipe_deskew_lanes_l1, pipe_deskew_lanes_l0}; assign pipe_reset = {pipe_reset_l7, pipe_reset_l6, pipe_reset_l5, pipe_reset_l4, pipe_reset_l3, pipe_reset_l2, pipe_reset_l1, pipe_reset_l0}; pcie_gt_wrapper_top# ( .NO_OF_LANES(NO_OF_LANES), .SIM(G_SIM), .USE_V5FXT(USE_V5FXT), .REF_CLK_FREQ (REF_CLK_FREQ), // use 0 for 100 MHz, 1 for 250 MHz .TXDIFFBOOST(TXDIFFBOOST), .GTDEBUGPORTS(GTDEBUGPORTS) ) SIO ( .gt_rx_elec_idle (pipe_rx_elec_idle), .gt_rx_status (pipe_rx_status), .gt_rx_data (pipe_rx_data), .gt_rx_phy_status (pipe_rx_phy_status), .gt_rx_data_k (pipe_rx_data_k), .gt_rx_valid (pipe_rx_valid), .gt_rx_chanisaligned (pipe_rxchanisaligned), .gt_rx_n (RXN), .gt_rx_p (RXP), .gt_tx_n (TXN), .gt_tx_p (TXP), .gt_tx_data (pipe_tx_data), .gt_tx_data_k (pipe_tx_data_k), .gt_tx_elec_idle (pipe_tx_elec_idle), .gt_tx_detect_rx_loopback(pipe_tx_detect_rx_loopback), .gt_tx_compliance (pipe_tx_compliance), .gt_rx_polarity (pipe_rx_polarity), .gt_power_down (pipe_power_down), .gt_deskew_lanes (pipe_deskew_lanes), .gt_pipe_reset (pipe_reset), .gt_rx_present (gt_rx_present), .gsr (gsr), .gtreset (GTPRESET), .refclk (REFCLK), .refclkout_bufg (REFCLKOUT_bufg), .gtclk_bufg (GTPCLK_bufg), .plllkdet_out (PLLLKDET_OUT), .resetdone (RESETDONE), .gt_usrclk (gt_usrclk), .gt_usrclk2 (crm_core_clk), .txsync_clk (txsync_clk), .rxbyteisaligned (RXBYTEISALIGNED), .rxchanbondseq (RXCHANBONDSEQ), .pcie_reset (pcie_reset), .clock_lock (clock_lock), .trn_lnk_up_n (trn_lnk_up_n), // GTP register ports .gt_dclk (gt_dclk), .gt_daddr (gt_daddr), .gt_den (gt_den), .gt_dwen (gt_dwen), .gt_di (gt_di), .gt_do (gt_do), .gt_drdy (gt_drdy), .gt_txdiffctrl_0 (gt_txdiffctrl_0), .gt_txdiffctrl_1 (gt_txdiffctrl_1), .gt_txbuffctrl_0 (gt_txbuffctrl_0), .gt_txbuffctrl_1 (gt_txbuffctrl_1), .gt_txpreemphesis_0 (gt_txpreemphesis_0), .gt_txpreemphesis_1 (gt_txpreemphesis_1) ); assign DEBUG[12:0] = mim_tx_bwadd; assign DEBUG[13] = mim_tx_bwen; assign DEBUG[14] = mim_tx_bren; assign DEBUG[78:15] = mim_tx_bwdata; assign DEBUG[91:79] = mim_tx_bradd; assign DEBUG[104:92]= mim_rx_bwadd; assign DEBUG[105] = mim_rx_bwen; assign DEBUG[106] = mim_rx_bren; assign DEBUG[170:107] = mim_rx_bwdata; assign DEBUG[183:171] = mim_rx_bradd; assign DEBUG[247:184] = mim_dll_brdata; assign DEBUG[259:248] = mim_dll_bradd; assign DEBUG[260] = mim_dll_bren; assign DEBUG[324:261] = mim_dll_bwdata; assign DEBUG[336:325] = mim_dll_bwadd; assign DEBUG[337] = mim_dll_bwen; // assign DEBUG[338] = masking_ack; // assign DEBUG[7:0] = pipe_tx_data[7:0]; // assign DEBUG[8] = pipe_tx_detect_rx_loopback[0]; // assign DEBUG[10:9] = pipe_power_down[1:0]; // assign DEBUG[18:11] = pipe_rx_data[7:0]; // assign DEBUG[19] = pipe_tx_elec_idle[0]; // assign DEBUG[20] = pipe_rx_elec_idle[0]; // assign DEBUG[23:21] = pipe_rx_status[2:0]; // assign DEBUG[24] = pipe_rx_phy_status[0]; // assign DEBUG[25] = pipe_rxchanisaligned[0]; // // assign DEBUG[26] = pipe_tx_elec_idle[1]; // assign DEBUG[27] = pipe_rx_elec_idle[1]; // assign DEBUG[30:28] = pipe_rx_status[5:3]; // assign DEBUG[31] = pipe_rx_phy_status[1]; // assign DEBUG[32] = pipe_rxchanisaligned[1]; // // assign DEBUG[33] = pipe_tx_elec_idle[2]; // assign DEBUG[34] = pipe_rx_elec_idle[2]; // assign DEBUG[37:35] = pipe_rx_status[8:6]; // assign DEBUG[38] = pipe_rx_phy_status[2]; // assign DEBUG[39] = pipe_rxchanisaligned[2]; // // assign DEBUG[40] = pipe_tx_elec_idle[3]; // assign DEBUG[41] = pipe_rx_elec_idle[3]; // assign DEBUG[44:42] = pipe_rx_status[11:9]; // assign DEBUG[45] = pipe_rx_phy_status[3]; // assign DEBUG[46] = pipe_rxchanisaligned[3]; // // assign DEBUG[47] = pipe_tx_elec_idle[4]; // assign DEBUG[48] = pipe_rx_elec_idle[4]; // assign DEBUG[51:49] = pipe_rx_status[14:12]; // assign DEBUG[52] = pipe_rx_phy_status[4]; // assign DEBUG[53] = pipe_rxchanisaligned[4]; // // // assign DEBUG[54] = pipe_tx_elec_idle[5]; // assign DEBUG[55] = pipe_rx_elec_idle[5]; // assign DEBUG[58:56] = pipe_rx_status[17:15]; // assign DEBUG[59] = pipe_rx_phy_status[5]; // assign DEBUG[60] = pipe_rxchanisaligned[5]; // // assign DEBUG[61] = pipe_tx_elec_idle[6]; // assign DEBUG[62] = pipe_rx_elec_idle[6]; // assign DEBUG[65:63] = pipe_rx_status[20:18]; // assign DEBUG[66] = pipe_rx_phy_status[6]; // assign DEBUG[67] = pipe_rxchanisaligned[6]; // // assign DEBUG[68] = pipe_tx_elec_idle[7]; // assign DEBUG[69] = pipe_rx_elec_idle[7]; // assign DEBUG[72:70] = pipe_rx_status[23:21]; // assign DEBUG[73] = pipe_rx_phy_status[7]; // assign DEBUG[74] = pipe_rxchanisaligned[7]; // // assign DEBUG[82:75] = pipe_rx_data[15:8]; // assign DEBUG[90:83] = pipe_rx_data[23:16]; // assign DEBUG[98:91] = pipe_rx_data[32:24]; // // assign DEBUG[99] = RXCHANBONDSEQ[0]; // assign DEBUG[100] = RXCHANBONDSEQ[1]; // assign DEBUG[101] = RXCHANBONDSEQ[2]; // assign DEBUG[102] = RXCHANBONDSEQ[3]; // // assign DEBUG[103] = RXBYTEISALIGNED[0]; // assign DEBUG[104] = RXBYTEISALIGNED[1]; // assign DEBUG[105] = RXBYTEISALIGNED[2]; // assign DEBUG[106] = RXBYTEISALIGNED[3]; //`define CHIPSCOPE_LLK_TX_HANG_DEBUG 1 //`define LTSSM_DEBUG 1 //`define LINKTRAIN_DEBUG 1 `ifdef CHIPSCOPE_LLK_TX_HANG_DEBUG reg [1:0] tx_state; reg [4:0] dst_rdy_ctr; reg dst_rdy_trig; wire [35:0] control0; always @(posedge user_clk or negedge clock_lock) begin if (clock_lock == 0) begin tx_state <= 2'b0; dst_rdy_ctr <= 4'b0; dst_rdy_trig <= 0; end else begin dst_rdy_trig <= 0; case (tx_state) 2'b00: begin if ((llk_tx_sof_n == 0) && (llk_tx_src_rdy_n == 0) && (llk_tx_dst_rdy_n == 0)) begin dst_rdy_ctr <= 4'b0; // reset counter tx_state <= 2'b01; end else if ((llk_tx_sof_n == 0) && (llk_tx_src_rdy_n == 0) && (llk_tx_dst_rdy_n != 0)) begin if (dst_rdy_ctr == 5'b11111) begin dst_rdy_trig <= 1'b1; tx_state <= 2'b10; end else begin dst_rdy_ctr <= dst_rdy_ctr + 1'b1; tx_state <= 2'b00; end end else if (llk_tx_dst_rdy_n != 0) begin if (dst_rdy_ctr == 5'b11111) begin dst_rdy_trig <= 1'b1; tx_state <= 2'b10; end else begin dst_rdy_ctr <= dst_rdy_ctr + 1'b1; tx_state <= 2'b00; end end else begin dst_rdy_ctr <= 4'b0; tx_state <= 2'b00; end end 2'b01: begin if ((llk_tx_eof_n == 0) && (llk_tx_src_rdy_n == 0) && (llk_tx_dst_rdy_n == 0)) begin dst_rdy_ctr <= 4'b0; tx_state <= 2'b00; end else if (llk_tx_dst_rdy_n != 0) begin if (dst_rdy_ctr == 5'b11111) begin dst_rdy_trig <= 1'b1; tx_state <= 2'b10; end else begin dst_rdy_ctr <= dst_rdy_ctr + 1'b1; tx_state <= 2'b01; end end end 2'b10: begin dst_rdy_trig <= 1'b1; tx_state <= 2'b10; end endcase end end wire [35:0] control0; ila i_ila ( .control(control0), .clk(user_clk), .data({ `ifdef LTSSM_DEBUG ltssm_reset, // 11 : 8 enable_ltssm_reset, // 7 : 7 user_reset_workaround_n, // 6 : 6 d_user_reset_n, // 5 : 5 pipe_rx_elec_idle_l0, // 4 : 4 l0_ltssm_state // 3 : 0 `else dst_rdy_trig, // 31 llk_tx_ch_posted_ready_n[0], // 30 llk_tx_ch_non_posted_ready_n[0], // 29 llk_tx_ch_completion_ready_n[0], // 28 llk_tx_chan_space, // 27 : 18 llk_tx_ch_fifo, // 17 : 16 llk_tx_ch_tc, // 15 : 13 llk_tx_eof_n, // 12 llk_tx_sof_n, // 11 llk_tx_dst_rdy_n, // 10 llk_tx_src_rdy_n, // 09 llk_tx_enable_n, // 08 : 07 llk_tx_data[62:56] // 06 : 00 `endif }), .trig0({ `ifdef LTSSM_DEBUG ltssm_reset, // 11 : 8 enable_ltssm_reset, // 7 : 7 user_reset_workaround_n, // 6 : 6 d_user_reset_n, // 5 : 5 pipe_rx_elec_idle_l0, // 4 : 4 l0_ltssm_state // 3 : 0 `else dst_rdy_trig, // 11 : 11 llk_tx_data[62:56], // 10 : 4 llk_tx_ch_fifo, // 3 : 2 llk_tx_src_rdy_n, // 1 : 1 llk_tx_sof_n // 0 : 0 `endif }) ); `endif // CHIPSCOPE_LLK_TX_HANG_DEBUG `ifdef LINKTRAIN_DEBUG wire [35:0] control0; wire trig_out; wire [148:0] trig0; wire all_chan_aligned; assign all_chan_aligned = &(pipe_rxchanisaligned); //assign chipscope_trig_out = trig_out; // chipscope can change polarity //assign trig0[3:0] = ltssm_reset[3:0]; //assign trig0[4] = enable_ltssm_reset; //assign trig0[5] = user_reset_workaround_n; //assign trig0[6] = d_user_reset_n; //assign trig0[7] = pipe_rx_elec_idle_l0; //assign trig0[8] = pipe_tx_elec_idle_l0; //assign trig0[12:9] = l0_ltssm_state[3:0]; //assign trig0[16:13] = l0_mac_negotiated_link_width[3:0]; //assign trig0[17] = l0_mac_link_training; //assign trig0[19:18] = l0_rx_mac_link_error[1:0]; //assign trig0[20] = l0_mac_link_up; //assign trig0[21] = PLLLKDET_OUT[0]; //assign trig0[22] = clock_lock; //assign trig0[23] = trn_reset_n; //assign trig0[24] = pipe_power_down_l0; //assign trig0[25] = user_reset_n; //assign trig0[26] = ignore_this_rst; //assign trig0[27] = link_not_x8; //assign trig0[31:28] = 4'b0; // unused assign trig0[7:0] = pipe_rx_data_l0[7:0]; assign trig0[15:8] = pipe_rx_data_l1[7:0]; assign trig0[23:16] = pipe_rx_data_l2[7:0]; assign trig0[31:24] = pipe_rx_data_l3[7:0]; assign trig0[39:32] = pipe_rx_data_l4[7:0]; assign trig0[47:40] = pipe_rx_data_l5[7:0]; assign trig0[55:48] = pipe_rx_data_l6[7:0]; assign trig0[63:56] = pipe_rx_data_l7[7:0]; assign trig0[71:64] = pipe_rx_data_l0_out[7:0]; assign trig0[79:72] = pipe_rx_data_l1_out[7:0]; assign trig0[87:80] = pipe_rx_data_l2_out[7:0]; assign trig0[95:88] = pipe_rx_data_l3_out[7:0]; assign trig0[103:96] = pipe_rx_data_l4_out[7:0]; assign trig0[111:104] = pipe_rx_data_l5_out[7:0]; assign trig0[119:112] = pipe_rx_data_l6_out[7:0]; assign trig0[127:120] = pipe_rx_data_l7_out[7:0]; assign trig0[128] = l0_stats_os_received; assign trig0[132:129] = l0_ltssm_state[3:0]; assign trig0[133] = upcfgcap_cycle; // from inside prod_fix assign trig0[134] = all_chan_aligned; assign trig0[135] = pipe_rx_data_k[0]; assign trig0[136] = l0_mac_link_up; assign trig0[140:137] = l0_mac_negotiated_link_width[3:0]; assign trig0[148:141] = pipe_rxchanisaligned[7:0]; //----------------------------------------------------------------- // // ILA core instance // //----------------------------------------------------------------- ila i_ila ( .control(control0), .clk(core_clk), .trig_out(trig_out), .trig0(trig0) ); icon i_icon ( .control0(control0) ); `endif //LINKTRAIN_DEBUG endmodule `ifdef CHIPSCOPE_LLK_TX_HANG_DEBUG module ila ( control, clk, data, trig0 ) /* synthesis syn_black_box syn_noprune=1 */; input [35:0] control; input clk; input [31:0] data; input [15:0] trig0; endmodule //------------------------------------------------------------------- // // ICON core module declaration // //------------------------------------------------------------------- module icon ( control0 ) /* synthesis syn_black_box syn_noprune=1 */; output [35:0] control0; endmodule `endif // CHIPSCOPE_LLK_TX_HANG_DEBUG `ifdef LINKTRAIN_DEBUG //------------------------------------------------------------------- // // ILA core module declaration // //------------------------------------------------------------------- module ila ( control, clk, trig_out, trig0 ); input [35:0] control; input clk; output trig_out; input [148:0] trig0; endmodule //------------------------------------------------------------------- // // ICON core module declaration // //------------------------------------------------------------------- module icon ( control0 ) /* synthesis syn_black_box syn_noprune=1 */; output [35:0] control0; endmodule `endif // LINKTRAIN_DEBUG