URL
https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk
Subversion Repositories pcie_ds_dma
[/] [pcie_ds_dma/] [trunk/] [projects/] [ambpex5_v20_sx50t_core/] [src/] [top/] [ambpex5_v20_sx50t_core.ucf] - Rev 2
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NET "btp<3>" LOC = "AC9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 16;
NET "btp<2>" LOC = "AC8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 16;
NET "btp<1>" LOC = "AB8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 16;
# PIOX
NET "backwri" LOC = "N10";
NET "backrdi" LOC = "L11";
NET "bpiowri" LOC = "M10";
NET "bpiordi" LOC = "N9";
NET "bpio<9>" LOC = "E12";
NET "bpio<8>" LOC = "G11";
NET "bpio<7>" LOC = "H10";
NET "bpio<6>" LOC = "F13";
NET "bpio<5>" LOC = "G12";
NET "bpio<4>" LOC = "E13";
NET "bpio<3>" LOC = "G13";
NET "bpio<2>" LOC = "J10";
NET "bpio<15>" LOC = "G10";
NET "bpio<14>" LOC = "E11";
NET "bpio<13>" LOC = "D11";
NET "bpio<12>" LOC = "F11";
NET "bpio<11>" LOC = "D12";
NET "bpio<10>" LOC = "C13";
NET "bpio<1>" LOC = "J11";
NET "bpio<0>" LOC = "K11";
NET "bpen1" LOC = "F10";
NET "bpen0" LOC = "L10";
NET "txp<7>" LOC = "AN4";
NET "txn<7>" LOC = "AN3";
NET "txp<6>" LOC = "AK2";
NET "txn<6>" LOC = "AL2";
NET "txp<5>" LOC = "AJ2";
NET "txn<5>" LOC = "AH2";
NET "txp<4>" LOC = "AD2";
NET "txn<4>" LOC = "AE2";
NET "txp<3>" LOC = "AC2";
NET "txn<3>" LOC = "AB2";
NET "txp<2>" LOC = "V2";
NET "txn<2>" LOC = "W2";
NET "txp<1>" LOC = "U2";
NET "txn<1>" LOC = "T2";
NET "txp<0>" LOC = "M2";
NET "txn<0>" LOC = "N2";
NET "bperst" LOC = "AF11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12;
NET "rxp<7>" LOC = "AP3";
NET "rxn<7>" LOC = "AP2";
NET "rxp<6>" LOC = "AL1";
NET "rxn<6>" LOC = "AM1";
NET "rxp<5>" LOC = "AH1";
NET "rxn<5>" LOC = "AG1";
NET "rxp<4>" LOC = "AE1";
NET "rxn<4>" LOC = "AF1";
NET "rxp<3>" LOC = "AB1";
NET "rxn<3>" LOC = "AA1";
NET "rxp<2>" LOC = "W1";
NET "rxn<2>" LOC = "Y1";
NET "rxp<1>" LOC = "T1";
NET "rxn<1>" LOC = "R1";
NET "rxp<0>" LOC = "N1";
NET "rxn<0>" LOC = "P1";
NET "bmgtrefclk_p" LOC = "H4";
NET "bmgtrefclk_n" LOC = "H3";
NET "bmgtavtttx_112_0" LOC = "M3";
NET "bmgtavtttx_112_0" LOC = "U3";
NET "bmgt252_p" LOC = "AG18";
NET "bmgt252_n" LOC = "AF19";
NET "mgt251_p" LOC = "P4";
NET "mgt251_n" LOC = "P3";
NET "bmgt100_p" LOC = "AH20";
NET "bmgt100_n" LOC = "AH19";
NET "bled4" LOC = "AF20";
NET "bled3" LOC = "AF21";
NET "bled2" LOC = "AF23";
NET "bled1" LOC = "AG23";
NET "bclkosc_p" LOC = "J14";
NET "bclkosc_n" LOC = "H13";
#INST "bclkosc*" DIFF_TERM = TRUE;
# PCIe Lanes 0, 1
INST "*/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTP_DUAL_X0Y3;
# PCIe Lanes 2, 3
INST "*/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" LOC = GTP_DUAL_X0Y2;
# PCIe Lanes 4, 5
INST "*/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" LOC = GTP_DUAL_X0Y1;
# PCIe Lanes 6, 7
INST "*/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" LOC = GTP_DUAL_X0Y0;
###############################################################################
# Physical Constraints
###############################################################################
#
# BlockRAM placement
#
INST "*/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst" LOC =RAMB36_X4Y7 ;
INST "*/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst" LOC =RAMB36_X4Y6 ;
INST "*/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst" LOC =RAMB36_X4Y5 ;
INST "*/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst" LOC =RAMB36_X4Y4 ;
INST "*/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst" LOC =RAMB36_X4Y8 ;
###############################################################################
# Timing Constraints
###############################################################################
#
# Timing requirements and related constraints.
#
NET "clk" buffer_type = "none";
#NET "*mgt250*" TNM_NET = "MGTCLK";
NET "amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/clocking_i/clkout0" TNM_NET = "MGTCLK";
TIMESPEC "TS_MGTCLK" = PERIOD "MGTCLK" 250.00 MHz HIGH 50 % ;
INST "core/core/fifo" AREA_GROUP = "pblock_fifo";
INST "amb/gen_syn.pcie/core/fifo" AREA_GROUP = "pblock_fifo";
AREA_GROUP "pblock_fifo" RANGE=SLICE_X24Y0:SLICE_X35Y39;
AREA_GROUP "pblock_fifo" RANGE=DSP48_X3Y0:DSP48_X3Y15;
AREA_GROUP "pblock_fifo" RANGE=RAMB36_X2Y0:RAMB36_X2Y7;
INST "core/core/tx" AREA_GROUP = "pblock_tx";
INST "amb/gen_syn.pcie/core/tx" AREA_GROUP = "pblock_tx";
AREA_GROUP "pblock_tx" RANGE=SLICE_X36Y25:SLICE_X45Y43;
INST "core/core/rx" AREA_GROUP = "pblock_rx";
INST "amb/gen_syn.pcie/core/rx" AREA_GROUP = "pblock_rx";
AREA_GROUP "pblock_rx" RANGE=SLICE_X36Y0:SLICE_X45Y24;
INST "core/core/disp" AREA_GROUP = "pblock_disp";
INST "amb/gen_syn.pcie/core/disp" AREA_GROUP = "pblock_disp";
AREA_GROUP "pblock_disp" RANGE=SLICE_X28Y40:SLICE_X35Y49;
INST "core/core/reg" AREA_GROUP = "pblock_reg";
INST "amb/gen_syn.pcie/core/reg" AREA_GROUP = "pblock_reg";
AREA_GROUP "pblock_reg" RANGE=SLICE_X36Y44:SLICE_X41Y49;
INST "core/tz" AREA_GROUP = "pblock_tz";
INST "amb/gen_syn.pcie/tz" AREA_GROUP = "pblock_tz";
AREA_GROUP "pblock_tz" RANGE=SLICE_X32Y50:SLICE_X45Y53;
INST "core/core/ep" AREA_GROUP = "pblock_ep";
INST "amb/gen_syn.pcie/core/ep" AREA_GROUP = "pblock_ep";
AREA_GROUP "pblock_ep" RANGE=SLICE_X46Y0:SLICE_X67Y49;
AREA_GROUP "pblock_ep" RANGE=RAMB36_X4Y0:RAMB36_X4Y9;
INST "amb/gen_syn.pcie/main" AREA_GROUP = "pblock_main";
AREA_GROUP "pblock_main" RANGE=SLICE_X42Y44:SLICE_X45Y49;
INST "amb/gen_syn.ad" AREA_GROUP = "pblock_gen_syn.ad";
AREA_GROUP "pblock_gen_syn.ad" RANGE=SLICE_X32Y54:SLICE_X51Y69;
AREA_GROUP "pblock_gen_syn.ad" RANGE=RAMB36_X3Y11:RAMB36_X3Y13;
INST "amb/gen_syn.blink" AREA_GROUP = "pblock_gen_syn.blink";
AREA_GROUP "pblock_gen_syn.blink" RANGE=SLICE_X64Y50:SLICE_X67Y56;
INST "dio_out" AREA_GROUP = "pblock_dio_out";
AREA_GROUP "pblock_dio_out" RANGE=SLICE_X22Y70:SLICE_X35Y89;
AREA_GROUP "pblock_dio_out" RANGE=RAMB36_X2Y14:RAMB36_X2Y17;
INST "dio_in" AREA_GROUP = "pblock_dio_in";
AREA_GROUP "pblock_dio_in" RANGE=SLICE_X36Y70:SLICE_X51Y89;
AREA_GROUP "pblock_dio_in" RANGE=RAMB36_X3Y14:RAMB36_X3Y17;
INST "test_ctrl" AREA_GROUP = "pblock_test_ctrl";
AREA_GROUP "pblock_test_ctrl" RANGE=SLICE_X20Y90:SLICE_X59Y119;
AREA_GROUP "pblock_test_ctrl" RANGE=DSP48_X2Y36:DSP48_X5Y47;