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[/] [pcie_ds_dma/] [trunk/] [projects/] [sp605_lx45t_core/] [src/] [top/] [sp605_lx45t_core.ucf] - Rev 35
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##-----------------------------------------------------------------------------
##
## (c) Copyright 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
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## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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##
##-----------------------------------------------------------------------------
## Project : Spartan-6 Integrated Block for PCI Express
## File : xilinx_pcie_1_lane_ep_xc6slx150t-fgg676-2.ucf
## Description: Example User Constraints File
##
## Use this file only with the device listed below. Any other
## combination is invalid. Do not modify this file except in
## regions designated for "User" constraints.
##-----------------------------------------------------------------------------
###############################################################################
# Define Device, Package And Speed Grade
###############################################################################
#CONFIG PART = xc6slx150t-fgg676-2;
###############################################################################
# User Time Names / User Time Groups / Time Specs
###############################################################################
###############################################################################
# User Physical Constraints
###############################################################################
###############################################################################
# Pinout and Related I/O Constraints
###############################################################################
#
# SYS reset (input) signal. The sys_reset_n signal should be
# obtained from the PCI Express interface if possible. For
# slot based form factors, a system reset signal is usually
# present on the connector. For cable based form factors, a
# system reset signal may not be available. In this case, the
# system reset signal must be generated locally by some form of
# supervisory circuit. You may change the IOSTANDARD and LOC
# to suit your requirements and VCCO voltage banking rules.
#
NET sys_reset_n LOC = J7 | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY;
# SYS clock 100 or 125 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Spartan-6 GTP
# Transceiver architecture requires the use of dedicated clock
# resources (FPGA input pins) associated with each GTP Transceiver Tile.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in the example design.
# Please refer to the Spartan-6 GTP Transceiver User Guide
# for guidelines regarding clock resource selection.
#
#NET sys_clk_n LOC = A10;
#NET sys_clk_p LOC = B10;
#
# Transceiver instance placement. This constraint selects the
# transceiver to be used, which also dictates the pinout for the
# transmit and receive differential pairs. Please refer to the
# Spartan-6 GTP Transceiver User Guide for more
# information.
#
# PCIe Lane 0
INST cl_s6pcie_m2_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i LOC = GTPA1_DUAL_X0Y1;
NET pci_exp_txp<0> LOC = B6;
NET pci_exp_txn<0> LOC = A6;
NET pci_exp_rxp<0> LOC = D7;
NET pci_exp_rxn<0> LOC = C7;
NET "gpio_led0" LOC = D17;
NET "gpio_led1" LOC = AB4;
NET "gpio_led2" LOC = D21;
NET "gpio_led3" LOC = W15;
###############################################################################
# Physical Constraints
###############################################################################
###############################################################################
# Timing Constraints
###############################################################################
#
# Ignore timing on asynchronous signals.
#
NET sys_reset_n TIG;
#
# Timing requirements and related constraints.
#
#NET sys_clk_c PERIOD = 8ns;
NET sys_clk_p TNM_NET = GT_REFCLK_OUT;
NET */ep/gt_refclk_out(0) TNM_NET = GT_REFCLK_OUT;
TIMESPEC TS_GT_REFCLK_OUT = PERIOD GT_REFCLK_OUT 8ns HIGH 50 % ;
###############################################################################
# End
###############################################################################
INST "amb/gen_syn.pcie/core/reg" AREA_GROUP = "pblock_reg";
AREA_GROUP "pblock_reg" RANGE=SLICE_X20Y89:SLICE_X25Y95;
INST "amb/gen_syn.pcie/core/int" AREA_GROUP = "pblock_int";
AREA_GROUP "pblock_int" RANGE=SLICE_X26Y88:SLICE_X29Y95;
INST "amb/gen_syn.pcie/core/tx" AREA_GROUP = "pblock_tx";
AREA_GROUP "pblock_tx" RANGE=SLICE_X8Y96:SLICE_X13Y111;
INST "amb/gen_syn.pcie/core/disp" AREA_GROUP = "pblock_disp";
AREA_GROUP "pblock_disp" RANGE=SLICE_X20Y80:SLICE_X25Y87;
INST "amb/gen_syn.pcie/core/fifo" AREA_GROUP = "pblock_fifo";
AREA_GROUP "pblock_fifo" RANGE=SLICE_X8Y80:SLICE_X19Y95, SLICE_X0Y64:SLICE_X7Y95;
AREA_GROUP "pblock_fifo" RANGE=DSP48_X0Y16:DSP48_X0Y23;
AREA_GROUP "pblock_fifo" RANGE=RAMB16_X1Y40:RAMB16_X1Y46, RAMB16_X0Y32:RAMB16_X0Y46;
AREA_GROUP "pblock_fifo" RANGE=RAMB8_X1Y40:RAMB8_X1Y47, RAMB8_X0Y32:RAMB8_X0Y47;
INST "amb/gen_syn.pcie/core/ep" AREA_GROUP = "pblock_ep";
AREA_GROUP "pblock_ep" RANGE=SLICE_X0Y112:SLICE_X3Y125;
AREA_GROUP "pblock_ep" RANGE=RAMB16_X0Y48:RAMB16_X0Y62;
AREA_GROUP "pblock_ep" RANGE=RAMB8_X0Y48:RAMB8_X0Y63;
INST "amb/gen_syn.pcie/main" AREA_GROUP = "pblock_main";
AREA_GROUP "pblock_main" RANGE=SLICE_X26Y80:SLICE_X29Y86;
INST "amb/gen_syn.pcie/tz" AREA_GROUP = "pblock_tz";
AREA_GROUP "pblock_tz" RANGE=SLICE_X20Y75:SLICE_X29Y79;
INST "amb/gen_syn.blink" AREA_GROUP = "pblock_gen_syn.blink";
AREA_GROUP "pblock_gen_syn.blink" RANGE=SLICE_X4Y112:SLICE_X7Y119;
INST "amb/gen_syn.ad" AREA_GROUP = "pblock_gen_syn.ad";
AREA_GROUP "pblock_gen_syn.ad" RANGE=SLICE_X20Y64:SLICE_X29Y74, SLICE_X8Y64:SLICE_X19Y79;
AREA_GROUP "pblock_gen_syn.ad" RANGE=RAMB16_X1Y38:RAMB16_X1Y38, RAMB16_X1Y32:RAMB16_X1Y34;
AREA_GROUP "pblock_gen_syn.ad" RANGE=RAMB8_X1Y38:RAMB8_X1Y39, RAMB8_X1Y32:RAMB8_X1Y35;
INST "test_ctrl" AREA_GROUP = "pblock_test_ctrl";
AREA_GROUP "pblock_test_ctrl" RANGE=SLICE_X0Y16:SLICE_X27Y47;
INST "dio_in" AREA_GROUP = "pblock_dio_in";
AREA_GROUP "pblock_dio_in" RANGE=SLICE_X0Y48:SLICE_X9Y63;
AREA_GROUP "pblock_dio_in" RANGE=DSP48_X0Y12:DSP48_X0Y15;
AREA_GROUP "pblock_dio_in" RANGE=RAMB16_X0Y24:RAMB16_X0Y30;
AREA_GROUP "pblock_dio_in" RANGE=RAMB8_X0Y24:RAMB8_X0Y31;
INST "main" AREA_GROUP = "pblock_main_1";
AREA_GROUP "pblock_main_1" RANGE=SLICE_X24Y48:SLICE_X29Y63;
INST "dio_out" AREA_GROUP = "pblock_dio_out";
AREA_GROUP "pblock_dio_out" RANGE=SLICE_X14Y48:SLICE_X23Y63;
AREA_GROUP "pblock_dio_out" RANGE=RAMB16_X1Y24:RAMB16_X1Y30;
AREA_GROUP "pblock_dio_out" RANGE=RAMB8_X1Y24:RAMB8_X1Y31;
INST "amb/gen_syn.pcie/core/rx" AREA_GROUP = "pblock_rx";
AREA_GROUP "pblock_rx" RANGE=SLICE_X0Y96:SLICE_X7Y111;
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