Subversion Repositories pcie_ds_dma

$WAVE4
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$ENDTIME 50400155100
I 1 "c#9#STD_LOGICc9 UX01ZWLH-"
$IN 1 1 "/stend_sp605_wishbone/dut/WB_SOPC/PCIE_CORE64_WB/PW_WB/reset"
$IN 2 1 55 0 clk
I 2 "r#14#type_pb_master5 stb0 c#9#STD_LOGICc9 UX01ZWLH-stb1 c#9#STD_LOGICc9 UX01ZWLH-cmd a#28#STD_LOGIC_VECTOR(2 downto 0)1 ricd2 0 c#9#STD_LOGICc9 UX01ZWLH-adr a#29#STD_LOGIC_VECTOR(31 downto 0)1 ricd31 0 c#9#STD_LOGICc9 UX01ZWLH-data a#29#STD_LOGIC_VECTOR(63 downto 0)1 ricd63 0 c#9#STD_LOGICc9 UX01ZWLH-"
I 3 "a#28#STD_LOGIC_VECTOR(2 downto 0)1 ricd2 0 c#9#STD_LOGICc9 UX01ZWLH-"
I 4 "a#29#STD_LOGIC_VECTOR(31 downto 0)1 ricd31 0 c#9#STD_LOGICc9 UX01ZWLH-"
I 5 "a#29#STD_LOGIC_VECTOR(63 downto 0)1 ricd63 0 c#9#STD_LOGICc9 UX01ZWLH-"
$BUS IN 3 2 5 55 0 pb_master
$CHILD 6 2 3
$CHILD +7 3 3
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I 7 "a#28#STD_LOGIC_VECTOR(1 downto 0)1 ricd1 0 c#9#STD_LOGICc9 UX01ZWLH-"
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=33 D 382000k 15
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=36 D 382000k 19
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=38 D 382000k 24
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*35
*38
$VALUES
V 3
U
X
0
$END
$WAVES +1
*0
*35
*38
$VALUES
V 3
U
X
0
$END
$WAVES +1
*0
*35
*38
$VALUES
V 3
U
X
0
$END
$WAVES +1
*0
*35
*38
$VALUES
V 3
U
X
0
$END
$WAVES +1
*0
*35
*38
$VALUES
V 3
U
X
0
$END
$WAVES +1
*0
*35
*38
$VALUES
V 3
U
X
0
$END
$WAVES +1
*0
*35
*38
$VALUES
V 3
U
X
0
$END
$WAVES +1
*0
*35
*38
$VALUES
V 3
U
X
0
$END
$WAVES +1
*0
*35
*38
$VALUES
V 3
U
X
0
$END
$WAVES +1
*0
*35
*38
$VALUES
V 3
U
X
0
$END
$WAVES +1
*0
*35
*38
$VALUES
V 3
U
X
0
$END
$WAVES +1
*0
*35
*34
$VALUES
V 3
U
X
0
$END
$WAVES +1
*0
*35
*1
$VALUES
V 3
U
X
0
$END
$WAVES +1
*0
*35
*1
$VALUES
V 3
U
X
0
$END
$WAVES +1
*0
$VALUES
V 1
0
$END
$WAVES +2
*0
=39 D 382000k 13
$VALUES
V 2
U
0
$END
$WAVES +1
*0
*13
$VALUES
V 2
U
0
$END
$ENDWAVE