Subversion Repositories pcie_mini

################################ PCIE EP IP #####################################
#
# SYS reset (input) signal.  The sys_reset_n signal should be
# obtained from the PCI Express interface if possible.  For
# slot based form factors, a system reset signal is usually
# present on the connector.  For cable based form factors, a
# system reset signal may not be available.  In this case, the
# system reset signal must be generated locally by some form of
# supervisory circuit.  You may change the IOSTANDARD and LOC
# to suit your requirements and VCCO voltage banking rules.
#
#NET sys_reset_n      LOC = XXX  | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY;
# SYS clock 125 or 250 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Spartan-6 GTP
# Transceiver architecture requires the use of dedicated clock
# resources (FPGA input pins) associated with each GTP Transceiver Tile.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in the example design.
# Please refer to the Spartan-6 GTP Transceiver User Guide
# for guidelines regarding clock resource selection.
#
INST "Inst_s6bfip_pcie/Inst_xilinx_pcie2wb/IBUFDS_inst" LOC = BUFDS_X1Y2;
NET "sys_clk_p" LOC = A10;
NET "sys_clk_n" LOC = B10;
#NET "sys_clk_p" LOC = A10;
#NET "sys_clk_n" LOC = B10;
#
# Transceiver instance placement.  This constraint selects the
# transceiver to be used, which also dictates the pinout for the
# transmit and receive differential pairs.  Please refer to the
# Spartan-6 GTP Transceiver User Guide for more
# information.
#
# PCIe Lane 0
#INST pcie_i/mgt/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i LOC = GTPA1_DUAL_X0Y0;
INST "Inst_s6bfip_pcie/Inst_xilinx_pcie2wb/inst_pcie/mgt/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i" LOC = GTPA1_DUAL_X0Y0;
NET "pci_exp_txn" LOC = A6;
NET "pci_exp_rxp" LOC = D7;
NET "pci_exp_rxn" LOC = C7;
NET "pci_exp_txp" LOC = B6;
#NET "pci_exp_rxp" LOC = D7;
#NET "pci_exp_rxn" LOC = C7;
#NET "pci_exp_txn" LOC = A6;
#NET "pci_exp_txp" LOC = B6;
#
# Ignore timing on asynchronous signals.
#
NET "sys_reset_n" TIG;
#
# Timing requirements and related constraints.
#
###NET sys_clk_c PERIOD = 10ns;
#NET pcie_i/gt_refclk_out TNM_NET = GT_REFCLK_OUT;
#TIMESPEC TS_GT_REFCLK_OUT = PERIOD GT_REFCLK_OUT 8ns HIGH 50 % ;
#
#Created by Constraints Editor (xc6slx45t-fgg484-2) - 2010/11/14
TIMESPEC TS_Inst_s6bfip_pcie_Inst_xilinx_pcie2wb_inst_pcie_gt_refclk_out = PERIOD "Inst_s6bfip_pcie/Inst_xilinx_pcie2wb/inst_pcie/gt_refclk_out" 10 ns HIGH 50 %;
#
NET "sys_clk_n" TNM_NET = "sys_clk_n";
NET "sys_clk_p" TNM_NET = "sys_clk_p";
TIMESPEC TS_sys_clk_p = PERIOD "sys_clk_p" 10 ns HIGH 50 %;
NET "Inst_s6bfip_pcie/Inst_xilinx_pcie2wb/inst_pcie/gt_refclk_out" TNM_NET = "Inst_s6bfip_pcie/Inst_xilinx_pcie2wb/inst_pcie/gt_refclk_out";
#
#FORCE BUFIO2 PLACEMENT, TO PREVENT RESOURCE CONFLICT
INST "Inst_s6bfip_pcie/Inst_xilinx_pcie2wb/inst_pcie/gt_refclk_bufio2" LOC = BUFIO2_X2Y28;
#
#
NET "sys_reset_n" LOC = F10;
NET "sys_reset_n" IOSTANDARD = LVCMOS33;
#
# The pcie_bar0_wb_clk_o also has to be constrained. On Spartan-6 with x1 interface its 62.5MHz
#