URL
https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk
Subversion Repositories pcie_sg_dma
[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [MyUserLogic/] [synopsis] - Rev 11
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{
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'register11rd_reg_ce' => {
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'register11td_reg_ce' => {
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'register11tv_reg_ce' => {
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'register12td_reg_ce' => {
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'register12tv_reg_ce' => {
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'register13rd_reg_ce' => {
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'register13rv_reg_ce' => {
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'register13td_reg_ce' => {
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'register13tv_reg_ce' => {
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'register14rd_reg_ce' => {
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'register14rv_reg_ce' => {
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'register14td_reg_ce' => {
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'register14tv_reg_ce' => {
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'sysgen_dut_to_register10_ce' => {
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'sysgen_dut_to_register10_clk' => {
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'sysgen_dut_to_register10_clk_x0' => {
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'sysgen_dut_to_register10_clr' => {
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'sysgen_dut_to_register10_clr_x0' => {
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'sysgen_dut_to_register10_data_in_x0' => {
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'sysgen_dut_to_register11_ce_x0' => {
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'sysgen_dut_to_register11_clk' => {
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'sysgen_dut_to_register11_clk_x0' => {
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'sysgen_dut_to_register11_clr' => {
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'sysgen_dut_to_register11_clr_x0' => {
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'sysgen_dut_to_register11_en' => {
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'sysgen_dut_to_register11_en_x0' => {
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'sysgen_dut_to_register12_ce' => {
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'sysgen_dut_to_register12_ce_x0' => {
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'sysgen_dut_to_register12_clk' => {
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'sysgen_dut_to_register12_clk_x0' => {
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'sysgen_dut_to_register12_clr' => {
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'sysgen_dut_to_register12_clr_x0' => {
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'sysgen_dut_to_register12_data_in_x0' => {
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'sysgen_dut_to_register12_en' => {
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'sysgen_dut_to_register12_en_x0' => {
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'sysgen_dut_to_register13_ce' => {
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'sysgen_dut_to_register13_ce_x0' => {
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'sysgen_dut_to_register13_clk' => {
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'sysgen_dut_to_register13_clk_x0' => {
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'sysgen_dut_to_register13_clr' => {
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'sysgen_dut_to_register13_clr_x0' => {
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'sysgen_dut_to_register13_data_in' => {
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'sysgen_dut_to_register13_data_in_x0' => {
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'sysgen_dut_to_register13_en' => {
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'sysgen_dut_to_register13_en_x0' => {
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'sysgen_dut_to_register14_ce' => {
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'sysgen_dut_to_register14_ce_x0' => {
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'sysgen_dut_to_register14_clk' => {
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'sysgen_dut_to_register14_clk_x0' => {
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'sysgen_dut_to_register14_clr' => {
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'sysgen_dut_to_register14_clr_x0' => {
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'sysgen_dut_to_register14_data_in' => {
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'sysgen_dut_to_register14_data_in_x0' => {
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'sysgen_dut_to_register14_en' => {
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'sysgen_dut_to_register14_en_x0' => {
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'sysgen_dut_to_register15_ce' => {
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'sysgen_dut_to_register15_ce_x0' => {
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'sysgen_dut_to_register15_clk' => {
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'sysgen_dut_to_register15_clk_x0' => {
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'sysgen_dut_to_register15_clr' => {
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'sysgen_dut_to_register15_clr_x0' => {
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'sysgen_dut_to_register15_data_in' => {
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'sysgen_dut_to_register15_data_in_x0' => {
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'sysgen_dut_to_register15_en' => {
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'sysgen_dut_to_register15_en_x0' => {
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'sysgen_dut_to_register16_ce' => {
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'sysgen_dut_to_register16_ce_x0' => {
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},
'sysgen_dut_to_register16_clk' => {
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},
'sysgen_dut_to_register16_clk_x0' => {
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},
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},
'sysgen_dut_to_register16_clr' => {
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},
'sysgen_dut_to_register16_clr_x0' => {
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},
'hdlType' => 'std_logic',
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},
'sysgen_dut_to_register16_data_in' => {
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},
'sysgen_dut_to_register16_data_in_x0' => {
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'hdlType' => 'std_logic',
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},
'sysgen_dut_to_register16_en' => {
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},
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},
'sysgen_dut_to_register16_en_x0' => {
'attributes' => {
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},
'hdlType' => 'std_logic',
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},
'sysgen_dut_to_register17_ce' => {
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'hdlType' => 'std_logic',
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},
'sysgen_dut_to_register17_ce_x0' => {
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},
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},
'sysgen_dut_to_register17_clk' => {
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},
'hdlType' => 'std_logic',
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},
'sysgen_dut_to_register17_clk_x0' => {
'attributes' => {
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},
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},
'sysgen_dut_to_register17_clr' => {
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},
'sysgen_dut_to_register17_clr_x0' => {
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},
'hdlType' => 'std_logic',
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},
'sysgen_dut_to_register17_data_in' => {
'attributes' => {
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},
'hdlType' => 'std_logic_vector(31 downto 0)',
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},
'sysgen_dut_to_register17_data_in_x0' => {
'attributes' => {
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},
'hdlType' => 'std_logic_vector(31 downto 0)',
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},
'sysgen_dut_to_register17_en' => {
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},
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},
'sysgen_dut_to_register17_en_x0' => {
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'hdlType' => 'std_logic',
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},
'sysgen_dut_to_register18_ce' => {
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},
'sysgen_dut_to_register18_ce_x0' => {
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},
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},
'sysgen_dut_to_register18_clk' => {
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},
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},
'sysgen_dut_to_register18_clk_x0' => {
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},
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},
'sysgen_dut_to_register18_clr' => {
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},
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},
'sysgen_dut_to_register18_clr_x0' => {
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},
'hdlType' => 'std_logic',
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},
'sysgen_dut_to_register18_data_in' => {
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},
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},
'sysgen_dut_to_register18_data_in_x0' => {
'attributes' => {
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'hdlType' => 'std_logic',
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},
'sysgen_dut_to_register18_en' => {
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},
'sysgen_dut_to_register18_en_x0' => {
'attributes' => {
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},
'hdlType' => 'std_logic',
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},
'sysgen_dut_to_register19_ce' => {
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},
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut_to_register19_ce_x0' => {
'attributes' => {
'hdlNetAttributes' => [
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'sysgen_dut_to_register30_ce' => {
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'sysgen_dut_to_register30_clk' => {
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_wr_din/FIFO_wr_din',
'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_wr_din',
'timingConstraint' => 'none',
'type' => 'UFix_72_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(71 downto 0)',
'width' => 72,
},
'fifo_wr_en' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_en.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_wr_en/FIFO_wr_en',
'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_wr_en',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'fifo_wr_full' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_full.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'fifo_wr_full',
'source_block' => '',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'fifo_wr_pfull' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_pfull.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'fifo_wr_pfull',
'source_block' => '',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'inout_logic_cw_ce' => {
'attributes' => {
'defaultHdlValue' => '\'1\'',
'domain' => 'default',
'group' => 4,
'isCe' => 1,
'period' => 1,
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'inout_logic_cw_clk' => {
'attributes' => {
'domain' => 'default',
'group' => 4,
'isClk' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg01_rd' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd/reg01_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg01_rv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv/reg01_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg01_td' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td/reg01_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg01_tv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv/reg01_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg02_rd' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd/reg02_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg02_rv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv/reg02_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg02_td' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td/reg02_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg02_tv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv/reg02_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg03_rd' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd/reg03_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg03_rv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv/reg03_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg03_td' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td/reg03_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg03_tv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv/reg03_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg04_rd' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd/reg04_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg04_rv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv/reg04_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg04_td' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td/reg04_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg04_tv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv/reg04_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg05_rd' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd/reg05_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg05_rv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv/reg05_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg05_td' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td/reg05_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg05_tv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv/reg05_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg06_rd' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd/reg06_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg06_rv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv/reg06_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg06_td' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td/reg06_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg06_tv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv/reg06_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg07_rd' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd/reg07_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg07_rv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv/reg07_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg07_td' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td/reg07_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg07_tv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv/reg07_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg08_rd' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd/reg08_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg08_rv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv/reg08_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg08_td' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td/reg08_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg08_tv' => {
'attributes' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv/reg08_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg09_rd' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd/reg09_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg09_rv' => {
'attributes' => {
'bin_pt' => 0,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv/reg09_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg09_td' => {
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'bin_pt' => 0,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td/reg09_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg09_tv' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv/reg09_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg10_rd' => {
'attributes' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg10_rv' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv/reg10_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv',
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},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg10_td' => {
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'bin_pt' => 0,
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td',
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},
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'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg10_tv' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv/reg10_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg11_rd' => {
'attributes' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd/reg11_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg11_rv' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg11_td' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
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},
'reg11_tv' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg12_rd' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg12_rv' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv',
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},
'direction' => 'out',
'hdlType' => 'std_logic',
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},
'reg12_td' => {
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},
'direction' => 'in',
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},
'reg12_tv' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv',
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},
'direction' => 'in',
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},
'reg13_rd' => {
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},
'direction' => 'out',
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},
'reg13_rv' => {
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},
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},
'reg13_td' => {
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},
'direction' => 'in',
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},
'reg13_tv' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv',
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},
'direction' => 'in',
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},
'reg14_rd' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
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},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg14_rv' => {
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},
'direction' => 'out',
'hdlType' => 'std_logic',
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},
'reg14_td' => {
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},
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},
'reg14_tv' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
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},
'rst_i' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_rst_i.dat',
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'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/rst_i/rst_i',
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'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'rst_o' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_rst_o.dat',
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'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/rst_o/rst_o',
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'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'user_int_1o' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_user_int_1o.dat',
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'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'user_int_2o' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_user_int_2o.dat',
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'is_gateway_port' => 1,
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'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o/user_int_2o',
'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'user_int_3o' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_user_int_3o.dat',
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'is_gateway_port' => 1,
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'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o/user_int_3o',
'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'user_logic_cw_ce' => {
'attributes' => {
'defaultHdlValue' => '\'1\'',
'domain' => 'default',
'group' => 6,
'isCe' => 1,
'period' => 1,
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'user_logic_cw_clk' => {
'attributes' => {
'domain' => 'default',
'group' => 6,
'isClk' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
},
'subblocks' => {
'DMA_Host2Board_Busy_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register18_ce',
'b' => 'sysgen_dut_to_register18_en',
'dout' => 'DMA_Host2Board_Busy_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'DMA_Host2Board_Busy_x0' => {
'connections' => {
'ce' => 'DMA_Host2Board_Busy_reg_ce',
'clk' => 'sysgen_dut_to_register18_clk',
'clr' => 'sysgen_dut_to_register18_clr',
'i' => 'sysgen_dut_to_register18_data_in',
'o' => 'from_register16_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'DMA_Host2Board_Done_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register19_ce',
'b' => 'sysgen_dut_to_register19_en',
'dout' => 'DMA_Host2Board_Done_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'DMA_Host2Board_Done_x0' => {
'connections' => {
'ce' => 'DMA_Host2Board_Done_reg_ce',
'clk' => 'sysgen_dut_to_register19_clk',
'clr' => 'sysgen_dut_to_register19_clr',
'i' => 'sysgen_dut_to_register19_data_in',
'o' => 'from_register15_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'debug1i' => {
'connections' => {
'ce' => 'debug1i_reg_ce',
'clk' => 'sysgen_dut_to_register6_clk',
'clr' => 'sysgen_dut_to_register6_clr',
'i' => 'sysgen_dut_to_register6_data_in',
'o' => 'from_register_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'debug1i_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register6_ce',
'b' => 'sysgen_dut_to_register6_en',
'dout' => 'debug1i_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'debug2i' => {
'connections' => {
'ce' => 'debug2i_reg_ce',
'clk' => 'sysgen_dut_to_register1_clk',
'clr' => 'sysgen_dut_to_register1_clr',
'i' => 'sysgen_dut_to_register1_data_in',
'o' => 'from_register1_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'debug2i_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register1_ce',
'b' => 'sysgen_dut_to_register1_en',
'dout' => 'debug2i_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'debug3i' => {
'connections' => {
'ce' => 'debug3i_reg_ce',
'clk' => 'sysgen_dut_to_register2_clk',
'clr' => 'sysgen_dut_to_register2_clr',
'i' => 'sysgen_dut_to_register2_data_in',
'o' => 'from_register2_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'debug3i_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register2_ce',
'b' => 'sysgen_dut_to_register2_en',
'dout' => 'debug3i_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'debug4i' => {
'connections' => {
'ce' => 'debug4i_reg_ce',
'clk' => 'sysgen_dut_to_register20_clk',
'clr' => 'sysgen_dut_to_register20_clr',
'i' => 'sysgen_dut_to_register20_data_in',
'o' => 'from_register19_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'debug4i_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register20_ce',
'b' => 'sysgen_dut_to_register20_en',
'dout' => 'debug4i_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register01rd' => {
'connections' => {
'ce' => 'register01rd_reg_ce',
'clk' => 'sysgen_dut_to_register_clk',
'clr' => 'sysgen_dut_to_register_clr',
'i' => 'sysgen_dut_to_register_data_in',
'o' => 'from_register3_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register01rd_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register_ce',
'b' => 'sysgen_dut_to_register_en',
'dout' => 'register01rd_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register01rv' => {
'connections' => {
'ce' => 'register01rv_reg_ce',
'clk' => 'sysgen_dut_to_register1_clk_x0',
'clr' => 'sysgen_dut_to_register1_clr_x0',
'i' => 'sysgen_dut_to_register1_data_in_x0',
'o' => 'from_register1_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register01rv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register1_ce_x0',
'b' => 'sysgen_dut_to_register1_en_x0',
'dout' => 'register01rv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register01td' => {
'connections' => {
'ce' => 'register01td_reg_ce',
'clk' => 'sysgen_dut_to_register7_clk',
'clr' => 'sysgen_dut_to_register7_clr',
'i' => 'sysgen_dut_to_register7_data_in',
'o' => 'from_register3_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register01td_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register7_ce',
'b' => 'sysgen_dut_to_register7_en',
'dout' => 'register01td_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register01tv' => {
'connections' => {
'ce' => 'register01tv_reg_ce',
'clk' => 'sysgen_dut_to_register3_clk',
'clr' => 'sysgen_dut_to_register3_clr',
'i' => 'sysgen_dut_to_register3_data_in',
'o' => 'from_register4_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register01tv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register3_ce',
'b' => 'sysgen_dut_to_register3_en',
'dout' => 'register01tv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register02rd' => {
'connections' => {
'ce' => 'register02rd_reg_ce',
'clk' => 'sysgen_dut_to_register2_clk_x0',
'clr' => 'sysgen_dut_to_register2_clr_x0',
'i' => 'sysgen_dut_to_register2_data_in_x0',
'o' => 'from_register5_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register02rd_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register2_ce_x0',
'b' => 'sysgen_dut_to_register2_en_x0',
'dout' => 'register02rd_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register02rv' => {
'connections' => {
'ce' => 'register02rv_reg_ce',
'clk' => 'sysgen_dut_to_register4_clk_x0',
'clr' => 'sysgen_dut_to_register4_clr_x0',
'i' => 'sysgen_dut_to_register4_data_in_x0',
'o' => 'from_register2_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register02rv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register4_ce_x0',
'b' => 'sysgen_dut_to_register4_en_x0',
'dout' => 'register02rv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register02td' => {
'connections' => {
'ce' => 'register02td_reg_ce',
'clk' => 'sysgen_dut_to_register5_clk',
'clr' => 'sysgen_dut_to_register5_clr',
'i' => 'sysgen_dut_to_register5_data_in',
'o' => 'from_register5_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register02td_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register5_ce',
'b' => 'sysgen_dut_to_register5_en',
'dout' => 'register02td_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register02tv' => {
'connections' => {
'ce' => 'register02tv_reg_ce',
'clk' => 'sysgen_dut_to_register4_clk',
'clr' => 'sysgen_dut_to_register4_clr',
'i' => 'sysgen_dut_to_register4_data_in',
'o' => 'from_register6_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register02tv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register4_ce',
'b' => 'sysgen_dut_to_register4_en',
'dout' => 'register02tv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register03rd' => {
'connections' => {
'ce' => 'register03rd_reg_ce',
'clk' => 'sysgen_dut_to_register3_clk_x0',
'clr' => 'sysgen_dut_to_register3_clr_x0',
'i' => 'sysgen_dut_to_register3_data_in_x0',
'o' => 'from_register7_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register03rd_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register3_ce_x0',
'b' => 'sysgen_dut_to_register3_en_x0',
'dout' => 'register03rd_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register03rv' => {
'connections' => {
'ce' => 'register03rv_reg_ce',
'clk' => 'sysgen_dut_to_register5_clk_x0',
'clr' => 'sysgen_dut_to_register5_clr_x0',
'i' => 'sysgen_dut_to_register5_data_in_x0',
'o' => 'from_register6_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register03rv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register5_ce_x0',
'b' => 'sysgen_dut_to_register5_en_x0',
'dout' => 'register03rv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register03td' => {
'connections' => {
'ce' => 'register03td_reg_ce',
'clk' => 'sysgen_dut_to_register9_clk',
'clr' => 'sysgen_dut_to_register9_clr',
'i' => 'sysgen_dut_to_register9_data_in',
'o' => 'from_register7_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register03td_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register9_ce',
'b' => 'sysgen_dut_to_register9_en',
'dout' => 'register03td_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register03tv' => {
'connections' => {
'ce' => 'register03tv_reg_ce',
'clk' => 'sysgen_dut_to_register8_clk',
'clr' => 'sysgen_dut_to_register8_clr',
'i' => 'sysgen_dut_to_register8_data_in',
'o' => 'from_register8_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register03tv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register8_ce',
'b' => 'sysgen_dut_to_register8_en',
'dout' => 'register03tv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register04rd' => {
'connections' => {
'ce' => 'register04rd_reg_ce',
'clk' => 'sysgen_dut_to_register6_clk_x0',
'clr' => 'sysgen_dut_to_register6_clr_x0',
'i' => 'sysgen_dut_to_register6_data_in_x0',
'o' => 'from_register8_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register04rd_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register6_ce_x0',
'b' => 'sysgen_dut_to_register6_en_x0',
'dout' => 'register04rd_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register04rv' => {
'connections' => {
'ce' => 'register04rv_reg_ce',
'clk' => 'sysgen_dut_to_register7_clk_x0',
'clr' => 'sysgen_dut_to_register7_clr_x0',
'i' => 'sysgen_dut_to_register7_data_in_x0',
'o' => 'from_register4_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register04rv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register7_ce_x0',
'b' => 'sysgen_dut_to_register7_en_x0',
'dout' => 'register04rv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register04td' => {
'connections' => {
'ce' => 'register04td_reg_ce',
'clk' => 'sysgen_dut_to_register11_clk',
'clr' => 'sysgen_dut_to_register11_clr',
'i' => 'sysgen_dut_to_register11_data_in',
'o' => 'from_register9_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register04td_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register11_ce',
'b' => 'sysgen_dut_to_register11_en',
'dout' => 'register04td_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register04tv' => {
'connections' => {
'ce' => 'register04tv_reg_ce',
'clk' => 'sysgen_dut_to_register10_clk',
'clr' => 'sysgen_dut_to_register10_clr',
'i' => 'sysgen_dut_to_register10_data_in',
'o' => 'from_register10_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register04tv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register10_ce',
'b' => 'sysgen_dut_to_register10_en',
'dout' => 'register04tv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register05rd' => {
'connections' => {
'ce' => 'register05rd_reg_ce',
'clk' => 'sysgen_dut_to_register8_clk_x0',
'clr' => 'sysgen_dut_to_register8_clr_x0',
'i' => 'sysgen_dut_to_register8_data_in_x0',
'o' => 'from_register10_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register05rd_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register8_ce_x0',
'b' => 'sysgen_dut_to_register8_en_x0',
'dout' => 'register05rd_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register05rv' => {
'connections' => {
'ce' => 'register05rv_reg_ce',
'clk' => 'sysgen_dut_to_register10_clk_x0',
'clr' => 'sysgen_dut_to_register10_clr_x0',
'i' => 'sysgen_dut_to_register10_data_in_x0',
'o' => 'from_register9_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register05rv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register10_ce_x0',
'b' => 'sysgen_dut_to_register10_en_x0',
'dout' => 'register05rv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register05td' => {
'connections' => {
'ce' => 'register05td_reg_ce',
'clk' => 'sysgen_dut_to_register13_clk',
'clr' => 'sysgen_dut_to_register13_clr',
'i' => 'sysgen_dut_to_register13_data_in',
'o' => 'from_register11_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register05td_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register13_ce',
'b' => 'sysgen_dut_to_register13_en',
'dout' => 'register05td_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register05tv' => {
'connections' => {
'ce' => 'register05tv_reg_ce',
'clk' => 'sysgen_dut_to_register12_clk',
'clr' => 'sysgen_dut_to_register12_clr',
'i' => 'sysgen_dut_to_register12_data_in',
'o' => 'from_register12_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register05tv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register12_ce',
'b' => 'sysgen_dut_to_register12_en',
'dout' => 'register05tv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register06rd' => {
'connections' => {
'ce' => 'register06rd_reg_ce',
'clk' => 'sysgen_dut_to_register9_clk_x0',
'clr' => 'sysgen_dut_to_register9_clr_x0',
'i' => 'sysgen_dut_to_register9_data_in_x0',
'o' => 'from_register11_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register06rd_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register9_ce_x0',
'b' => 'sysgen_dut_to_register9_en_x0',
'dout' => 'register06rd_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register06rv' => {
'connections' => {
'ce' => 'register06rv_reg_ce',
'clk' => 'sysgen_dut_to_register11_clk_x0',
'clr' => 'sysgen_dut_to_register11_clr_x0',
'i' => 'sysgen_dut_to_register11_data_in_x0',
'o' => 'from_register12_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register06rv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register11_ce_x0',
'b' => 'sysgen_dut_to_register11_en_x0',
'dout' => 'register06rv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register06td' => {
'connections' => {
'ce' => 'register06td_reg_ce',
'clk' => 'sysgen_dut_to_register15_clk',
'clr' => 'sysgen_dut_to_register15_clr',
'i' => 'sysgen_dut_to_register15_data_in',
'o' => 'from_register13_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register06td_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register15_ce',
'b' => 'sysgen_dut_to_register15_en',
'dout' => 'register06td_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register06tv' => {
'connections' => {
'ce' => 'register06tv_reg_ce',
'clk' => 'sysgen_dut_to_register14_clk',
'clr' => 'sysgen_dut_to_register14_clr',
'i' => 'sysgen_dut_to_register14_data_in',
'o' => 'from_register14_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register06tv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register14_ce',
'b' => 'sysgen_dut_to_register14_en',
'dout' => 'register06tv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register07rd' => {
'connections' => {
'ce' => 'register07rd_reg_ce',
'clk' => 'sysgen_dut_to_register13_clk_x0',
'clr' => 'sysgen_dut_to_register13_clr_x0',
'i' => 'sysgen_dut_to_register13_data_in_x0',
'o' => 'from_register13_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register07rd_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register13_ce_x0',
'b' => 'sysgen_dut_to_register13_en_x0',
'dout' => 'register07rd_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register07rv' => {
'connections' => {
'ce' => 'register07rv_reg_ce',
'clk' => 'sysgen_dut_to_register12_clk_x0',
'clr' => 'sysgen_dut_to_register12_clr_x0',
'i' => 'sysgen_dut_to_register12_data_in_x0',
'o' => 'from_register14_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register07rv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register12_ce_x0',
'b' => 'sysgen_dut_to_register12_en_x0',
'dout' => 'register07rv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register07td' => {
'connections' => {
'ce' => 'register07td_reg_ce',
'clk' => 'sysgen_dut_to_register17_clk',
'clr' => 'sysgen_dut_to_register17_clr',
'i' => 'sysgen_dut_to_register17_data_in',
'o' => 'from_register17_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register07td_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register17_ce',
'b' => 'sysgen_dut_to_register17_en',
'dout' => 'register07td_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register07tv' => {
'connections' => {
'ce' => 'register07tv_reg_ce',
'clk' => 'sysgen_dut_to_register16_clk',
'clr' => 'sysgen_dut_to_register16_clr',
'i' => 'sysgen_dut_to_register16_data_in',
'o' => 'from_register18_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register07tv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register16_ce',
'b' => 'sysgen_dut_to_register16_en',
'dout' => 'register07tv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register08rd' => {
'connections' => {
'ce' => 'register08rd_reg_ce',
'clk' => 'sysgen_dut_to_register15_clk_x0',
'clr' => 'sysgen_dut_to_register15_clr_x0',
'i' => 'sysgen_dut_to_register15_data_in_x0',
'o' => 'from_register15_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register08rd_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register15_ce_x0',
'b' => 'sysgen_dut_to_register15_en_x0',
'dout' => 'register08rd_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register08rv' => {
'connections' => {
'ce' => 'register08rv_reg_ce',
'clk' => 'sysgen_dut_to_register14_clk_x0',
'clr' => 'sysgen_dut_to_register14_clr_x0',
'i' => 'sysgen_dut_to_register14_data_in_x0',
'o' => 'from_register16_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register08rv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register14_ce_x0',
'b' => 'sysgen_dut_to_register14_en_x0',
'dout' => 'register08rv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register08td' => {
'connections' => {
'ce' => 'register08td_reg_ce',
'clk' => 'sysgen_dut_to_register26_clk',
'clr' => 'sysgen_dut_to_register26_clr',
'i' => 'sysgen_dut_to_register26_data_in',
'o' => 'from_register20_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register08td_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register26_ce',
'b' => 'sysgen_dut_to_register26_en',
'dout' => 'register08td_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register08tv' => {
'connections' => {
'ce' => 'register08tv_reg_ce',
'clk' => 'sysgen_dut_to_register25_clk',
'clr' => 'sysgen_dut_to_register25_clr',
'i' => 'sysgen_dut_to_register25_data_in',
'o' => 'from_register21_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register08tv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register25_ce',
'b' => 'sysgen_dut_to_register25_en',
'dout' => 'register08tv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register09rd' => {
'connections' => {
'ce' => 'register09rd_reg_ce',
'clk' => 'sysgen_dut_to_register17_clk_x0',
'clr' => 'sysgen_dut_to_register17_clr_x0',
'i' => 'sysgen_dut_to_register17_data_in_x0',
'o' => 'from_register17_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register09rd_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register17_ce_x0',
'b' => 'sysgen_dut_to_register17_en_x0',
'dout' => 'register09rd_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register09rv' => {
'connections' => {
'ce' => 'register09rv_reg_ce',
'clk' => 'sysgen_dut_to_register16_clk_x0',
'clr' => 'sysgen_dut_to_register16_clr_x0',
'i' => 'sysgen_dut_to_register16_data_in_x0',
'o' => 'from_register18_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register09rv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register16_ce_x0',
'b' => 'sysgen_dut_to_register16_en_x0',
'dout' => 'register09rv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register09td' => {
'connections' => {
'ce' => 'register09td_reg_ce',
'clk' => 'sysgen_dut_to_register22_clk',
'clr' => 'sysgen_dut_to_register22_clr',
'i' => 'sysgen_dut_to_register22_data_in',
'o' => 'from_register22_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register09td_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register22_ce',
'b' => 'sysgen_dut_to_register22_en',
'dout' => 'register09td_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register09tv' => {
'connections' => {
'ce' => 'register09tv_reg_ce',
'clk' => 'sysgen_dut_to_register21_clk',
'clr' => 'sysgen_dut_to_register21_clr',
'i' => 'sysgen_dut_to_register21_data_in',
'o' => 'from_register23_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register09tv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register21_ce',
'b' => 'sysgen_dut_to_register21_en',
'dout' => 'register09tv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register10rd' => {
'connections' => {
'ce' => 'register10rd_reg_ce',
'clk' => 'sysgen_dut_to_register19_clk_x0',
'clr' => 'sysgen_dut_to_register19_clr_x0',
'i' => 'sysgen_dut_to_register19_data_in_x0',
'o' => 'from_register19_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register10rd_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register19_ce_x0',
'b' => 'sysgen_dut_to_register19_en_x0',
'dout' => 'register10rd_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register10rv' => {
'connections' => {
'ce' => 'register10rv_reg_ce',
'clk' => 'sysgen_dut_to_register18_clk_x0',
'clr' => 'sysgen_dut_to_register18_clr_x0',
'i' => 'sysgen_dut_to_register18_data_in_x0',
'o' => 'from_register20_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register10rv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register18_ce_x0',
'b' => 'sysgen_dut_to_register18_en_x0',
'dout' => 'register10rv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register10td' => {
'connections' => {
'ce' => 'register10td_reg_ce',
'clk' => 'sysgen_dut_to_register24_clk',
'clr' => 'sysgen_dut_to_register24_clr',
'i' => 'sysgen_dut_to_register24_data_in',
'o' => 'from_register24_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register10td_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register24_ce',
'b' => 'sysgen_dut_to_register24_en',
'dout' => 'register10td_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register10tv' => {
'connections' => {
'ce' => 'register10tv_reg_ce',
'clk' => 'sysgen_dut_to_register23_clk',
'clr' => 'sysgen_dut_to_register23_clr',
'i' => 'sysgen_dut_to_register23_data_in',
'o' => 'from_register25_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register10tv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register23_ce',
'b' => 'sysgen_dut_to_register23_en',
'dout' => 'register10tv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register11rd' => {
'connections' => {
'ce' => 'register11rd_reg_ce',
'clk' => 'sysgen_dut_to_register21_clk_x0',
'clr' => 'sysgen_dut_to_register21_clr_x0',
'i' => 'sysgen_dut_to_register21_data_in_x0',
'o' => 'from_register21_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register11rd_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register21_ce_x0',
'b' => 'sysgen_dut_to_register21_en_x0',
'dout' => 'register11rd_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register11rv' => {
'connections' => {
'ce' => 'register11rv_reg_ce',
'clk' => 'sysgen_dut_to_register20_clk_x0',
'clr' => 'sysgen_dut_to_register20_clr_x0',
'i' => 'sysgen_dut_to_register20_data_in_x0',
'o' => 'from_register22_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register11rv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register20_ce_x0',
'b' => 'sysgen_dut_to_register20_en_x0',
'dout' => 'register11rv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register11td' => {
'connections' => {
'ce' => 'register11td_reg_ce',
'clk' => 'sysgen_dut_to_register28_clk',
'clr' => 'sysgen_dut_to_register28_clr',
'i' => 'sysgen_dut_to_register28_data_in',
'o' => 'from_register26_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register11td_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register28_ce',
'b' => 'sysgen_dut_to_register28_en',
'dout' => 'register11td_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register11tv' => {
'connections' => {
'ce' => 'register11tv_reg_ce',
'clk' => 'sysgen_dut_to_register27_clk',
'clr' => 'sysgen_dut_to_register27_clr',
'i' => 'sysgen_dut_to_register27_data_in',
'o' => 'from_register27_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register11tv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register27_ce',
'b' => 'sysgen_dut_to_register27_en',
'dout' => 'register11tv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register12rd' => {
'connections' => {
'ce' => 'register12rd_reg_ce',
'clk' => 'sysgen_dut_to_register23_clk_x0',
'clr' => 'sysgen_dut_to_register23_clr_x0',
'i' => 'sysgen_dut_to_register23_data_in_x0',
'o' => 'from_register23_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register12rd_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register23_ce_x0',
'b' => 'sysgen_dut_to_register23_en_x0',
'dout' => 'register12rd_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register12rv' => {
'connections' => {
'ce' => 'register12rv_reg_ce',
'clk' => 'sysgen_dut_to_register22_clk_x0',
'clr' => 'sysgen_dut_to_register22_clr_x0',
'i' => 'sysgen_dut_to_register22_data_in_x0',
'o' => 'from_register24_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register12rv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register22_ce_x0',
'b' => 'sysgen_dut_to_register22_en_x0',
'dout' => 'register12rv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register12td' => {
'connections' => {
'ce' => 'register12td_reg_ce',
'clk' => 'sysgen_dut_to_register30_clk',
'clr' => 'sysgen_dut_to_register30_clr',
'i' => 'sysgen_dut_to_register30_data_in',
'o' => 'from_register28_data_out_x0',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register12td_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register30_ce',
'b' => 'sysgen_dut_to_register30_en',
'dout' => 'register12td_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register12tv' => {
'connections' => {
'ce' => 'register12tv_reg_ce',
'clk' => 'sysgen_dut_to_register29_clk',
'clr' => 'sysgen_dut_to_register29_clr',
'i' => 'sysgen_dut_to_register29_data_in',
'o' => 'from_register29_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register12tv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register29_ce',
'b' => 'sysgen_dut_to_register29_en',
'dout' => 'register12tv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register13rd' => {
'connections' => {
'ce' => 'register13rd_reg_ce',
'clk' => 'sysgen_dut_to_register25_clk_x0',
'clr' => 'sysgen_dut_to_register25_clr_x0',
'i' => 'sysgen_dut_to_register25_data_in_x0',
'o' => 'from_register25_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register13rd_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register25_ce_x0',
'b' => 'sysgen_dut_to_register25_en_x0',
'dout' => 'register13rd_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register13rv' => {
'connections' => {
'ce' => 'register13rv_reg_ce',
'clk' => 'sysgen_dut_to_register24_clk_x0',
'clr' => 'sysgen_dut_to_register24_clr_x0',
'i' => 'sysgen_dut_to_register24_data_in_x0',
'o' => 'from_register26_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register13rv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register24_ce_x0',
'b' => 'sysgen_dut_to_register24_en_x0',
'dout' => 'register13rv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register13td' => {
'connections' => {
'ce' => 'register13td_reg_ce',
'clk' => 'sysgen_dut_to_register32_clk',
'clr' => 'sysgen_dut_to_register32_clr',
'i' => 'sysgen_dut_to_register32_data_in',
'o' => 'from_register30_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register13td_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register32_ce',
'b' => 'sysgen_dut_to_register32_en',
'dout' => 'register13td_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register13tv' => {
'connections' => {
'ce' => 'register13tv_reg_ce',
'clk' => 'sysgen_dut_to_register31_clk',
'clr' => 'sysgen_dut_to_register31_clr',
'i' => 'sysgen_dut_to_register31_data_in',
'o' => 'from_register31_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register13tv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register31_ce',
'b' => 'sysgen_dut_to_register31_en',
'dout' => 'register13tv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register14rd' => {
'connections' => {
'ce' => 'register14rd_reg_ce',
'clk' => 'sysgen_dut_to_register27_clk_x0',
'clr' => 'sysgen_dut_to_register27_clr_x0',
'i' => 'sysgen_dut_to_register27_data_in_x0',
'o' => 'from_register27_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register14rd_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register27_ce_x0',
'b' => 'sysgen_dut_to_register27_en_x0',
'dout' => 'register14rd_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register14rv' => {
'connections' => {
'ce' => 'register14rv_reg_ce',
'clk' => 'sysgen_dut_to_register26_clk_x0',
'clr' => 'sysgen_dut_to_register26_clr_x0',
'i' => 'sysgen_dut_to_register26_data_in_x0',
'o' => 'from_register28_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register14rv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register26_ce_x0',
'b' => 'sysgen_dut_to_register26_en_x0',
'dout' => 'register14rv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register14td' => {
'connections' => {
'ce' => 'register14td_reg_ce',
'clk' => 'sysgen_dut_to_register34_clk',
'clr' => 'sysgen_dut_to_register34_clr',
'i' => 'sysgen_dut_to_register34_data_in',
'o' => 'from_register32_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
32,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"00000000000000000000000000000000"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register14td_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register34_ce',
'b' => 'sysgen_dut_to_register34_en',
'dout' => 'register14td_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'register14tv' => {
'connections' => {
'ce' => 'register14tv_reg_ce',
'clk' => 'sysgen_dut_to_register33_clk',
'clr' => 'sysgen_dut_to_register33_clr',
'i' => 'sysgen_dut_to_register33_data_in',
'o' => 'from_register33_data_out',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'generics' => [
[
'width',
'integer',
1,
],
[
'init_index',
'integer',
2,
],
[
'init_value',
'bit_vector',
'b"0"',
],
[
'latency',
'integer',
1,
],
],
},
'entityName' => 'synth_reg_w_init',
'ports' => {
'ce' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'clr' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'i' => {
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'o' => {
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
},
'entityName' => 'synth_reg_w_init',
},
'register14tv_ce_and2_comp' => {
'connections' => {
'a' => 'sysgen_dut_to_register33_ce',
'b' => 'sysgen_dut_to_register33_en',
'dout' => 'register14tv_reg_ce',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
},
'entityName' => 'xland2',
'ports' => {
'a' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'b' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dout' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xland2',
},
'top_level_0' => {
'connections' => {
'ce' => 'x',
'clk' => 'x_x0',
'debug_in_1i' => 'x_x1',
'debug_in_2i' => 'x_x2',
'debug_in_3i' => 'x_x3',
'debug_in_4i' => 'x_x4',
'dma_host2board_busy' => 'x_x5',
'dma_host2board_done' => 'x_x6',
'from_register10_data_out' => 'from_register10_data_out',
'from_register11_data_out' => 'from_register11_data_out',
'from_register12_data_out' => 'from_register12_data_out',
'from_register13_data_out' => 'from_register13_data_out',
'from_register14_data_out' => 'from_register14_data_out',
'from_register15_data_out' => 'from_register15_data_out',
'from_register16_data_out' => 'from_register16_data_out',
'from_register17_data_out' => 'from_register17_data_out',
'from_register18_data_out' => 'from_register18_data_out',
'from_register19_data_out' => 'from_register19_data_out',
'from_register1_data_out' => 'from_register1_data_out',
'from_register20_data_out' => 'from_register20_data_out',
'from_register21_data_out' => 'from_register21_data_out',
'from_register22_data_out' => 'from_register22_data_out',
'from_register23_data_out' => 'from_register23_data_out',
'from_register24_data_out' => 'from_register24_data_out',
'from_register25_data_out' => 'from_register25_data_out',
'from_register26_data_out' => 'from_register26_data_out',
'from_register27_data_out' => 'from_register27_data_out',
'from_register28_data_out' => 'from_register28_data_out',
'from_register2_data_out' => 'from_register2_data_out',
'from_register3_data_out' => 'from_register3_data_out',
'from_register4_data_out' => 'from_register4_data_out',
'from_register5_data_out' => 'from_register5_data_out',
'from_register6_data_out' => 'from_register6_data_out',
'from_register7_data_out' => 'from_register7_data_out',
'from_register8_data_out' => 'from_register8_data_out',
'from_register9_data_out' => 'from_register9_data_out',
'reg01_rd' => 'x_x7',
'reg01_rv' => 'x_x8',
'reg01_td' => 'x_x9',
'reg01_tv' => 'x_x10',
'reg02_rd' => 'x_x11',
'reg02_rv' => 'x_x12',
'reg02_td' => 'x_x13',
'reg02_tv' => 'x_x14',
'reg03_rd' => 'x_x15',
'reg03_rv' => 'x_x16',
'reg03_td' => 'x_x17',
'reg03_tv' => 'x_x18',
'reg04_rd' => 'x_x19',
'reg04_rv' => 'x_x20',
'reg04_td' => 'x_x21',
'reg04_tv' => 'x_x22',
'reg05_rd' => 'x_x23',
'reg05_rv' => 'x_x24',
'reg05_td' => 'x_x25',
'reg05_tv' => 'x_x26',
'reg06_rd' => 'x_x27',
'reg06_rv' => 'x_x28',
'reg06_td' => 'x_x29',
'reg06_tv' => 'x_x30',
'reg07_rd' => 'x_x31',
'reg07_rv' => 'x_x32',
'reg07_td' => 'x_x33',
'reg07_tv' => 'x_x34',
'reg08_rd' => 'x_x35',
'reg08_rv' => 'x_x36',
'reg08_td' => 'x_x37',
'reg08_tv' => 'x_x38',
'reg09_rd' => 'x_x39',
'reg09_rv' => 'x_x40',
'reg09_td' => 'x_x41',
'reg09_tv' => 'x_x42',
'reg10_rd' => 'x_x43',
'reg10_rv' => 'x_x44',
'reg10_td' => 'x_x45',
'reg10_tv' => 'x_x46',
'reg11_rd' => 'x_x47',
'reg11_rv' => 'x_x48',
'reg11_td' => 'x_x49',
'reg11_tv' => 'x_x50',
'reg12_rd' => 'x_x51',
'reg12_rv' => 'x_x52',
'reg12_td' => 'x_x53',
'reg12_tv' => 'x_x54',
'reg13_rd' => 'x_x55',
'reg13_rv' => 'x_x56',
'reg13_td' => 'x_x57',
'reg13_tv' => 'x_x58',
'reg14_rd' => 'x_x59',
'reg14_rv' => 'x_x60',
'reg14_td' => 'x_x61',
'reg14_tv' => 'x_x62',
'to_register10_ce' => 'sysgen_dut_to_register10_ce',
'to_register10_clk' => 'sysgen_dut_to_register10_clk',
'to_register10_clr' => 'sysgen_dut_to_register10_clr',
'to_register10_data_in' => 'sysgen_dut_to_register10_data_in',
'to_register10_dout' => 'from_register10_data_out_x0',
'to_register10_en' => 'sysgen_dut_to_register10_en',
'to_register11_ce' => 'sysgen_dut_to_register11_ce',
'to_register11_clk' => 'sysgen_dut_to_register11_clk',
'to_register11_clr' => 'sysgen_dut_to_register11_clr',
'to_register11_data_in' => 'sysgen_dut_to_register11_data_in',
'to_register11_dout' => 'from_register9_data_out_x0',
'to_register11_en' => 'sysgen_dut_to_register11_en',
'to_register12_ce' => 'sysgen_dut_to_register12_ce',
'to_register12_clk' => 'sysgen_dut_to_register12_clk',
'to_register12_clr' => 'sysgen_dut_to_register12_clr',
'to_register12_data_in' => 'sysgen_dut_to_register12_data_in',
'to_register12_dout' => 'from_register12_data_out_x0',
'to_register12_en' => 'sysgen_dut_to_register12_en',
'to_register13_ce' => 'sysgen_dut_to_register13_ce',
'to_register13_clk' => 'sysgen_dut_to_register13_clk',
'to_register13_clr' => 'sysgen_dut_to_register13_clr',
'to_register13_data_in' => 'sysgen_dut_to_register13_data_in',
'to_register13_dout' => 'from_register11_data_out_x0',
'to_register13_en' => 'sysgen_dut_to_register13_en',
'to_register14_ce' => 'sysgen_dut_to_register14_ce',
'to_register14_clk' => 'sysgen_dut_to_register14_clk',
'to_register14_clr' => 'sysgen_dut_to_register14_clr',
'to_register14_data_in' => 'sysgen_dut_to_register14_data_in',
'to_register14_dout' => 'from_register14_data_out_x0',
'to_register14_en' => 'sysgen_dut_to_register14_en',
'to_register15_ce' => 'sysgen_dut_to_register15_ce',
'to_register15_clk' => 'sysgen_dut_to_register15_clk',
'to_register15_clr' => 'sysgen_dut_to_register15_clr',
'to_register15_data_in' => 'sysgen_dut_to_register15_data_in',
'to_register15_dout' => 'from_register13_data_out_x0',
'to_register15_en' => 'sysgen_dut_to_register15_en',
'to_register16_ce' => 'sysgen_dut_to_register16_ce',
'to_register16_clk' => 'sysgen_dut_to_register16_clk',
'to_register16_clr' => 'sysgen_dut_to_register16_clr',
'to_register16_data_in' => 'sysgen_dut_to_register16_data_in',
'to_register16_dout' => 'from_register18_data_out_x0',
'to_register16_en' => 'sysgen_dut_to_register16_en',
'to_register17_ce' => 'sysgen_dut_to_register17_ce',
'to_register17_clk' => 'sysgen_dut_to_register17_clk',
'to_register17_clr' => 'sysgen_dut_to_register17_clr',
'to_register17_data_in' => 'sysgen_dut_to_register17_data_in',
'to_register17_dout' => 'from_register17_data_out_x0',
'to_register17_en' => 'sysgen_dut_to_register17_en',
'to_register18_ce' => 'sysgen_dut_to_register18_ce',
'to_register18_clk' => 'sysgen_dut_to_register18_clk',
'to_register18_clr' => 'sysgen_dut_to_register18_clr',
'to_register18_data_in' => 'sysgen_dut_to_register18_data_in',
'to_register18_dout' => 'from_register16_data_out_x0',
'to_register18_en' => 'sysgen_dut_to_register18_en',
'to_register19_ce' => 'sysgen_dut_to_register19_ce',
'to_register19_clk' => 'sysgen_dut_to_register19_clk',
'to_register19_clr' => 'sysgen_dut_to_register19_clr',
'to_register19_data_in' => 'sysgen_dut_to_register19_data_in',
'to_register19_dout' => 'from_register15_data_out_x0',
'to_register19_en' => 'sysgen_dut_to_register19_en',
'to_register1_ce' => 'sysgen_dut_to_register1_ce',
'to_register1_clk' => 'sysgen_dut_to_register1_clk',
'to_register1_clr' => 'sysgen_dut_to_register1_clr',
'to_register1_data_in' => 'sysgen_dut_to_register1_data_in',
'to_register1_dout' => 'from_register1_data_out_x0',
'to_register1_en' => 'sysgen_dut_to_register1_en',
'to_register20_ce' => 'sysgen_dut_to_register20_ce',
'to_register20_clk' => 'sysgen_dut_to_register20_clk',
'to_register20_clr' => 'sysgen_dut_to_register20_clr',
'to_register20_data_in' => 'sysgen_dut_to_register20_data_in',
'to_register20_dout' => 'from_register19_data_out_x0',
'to_register20_en' => 'sysgen_dut_to_register20_en',
'to_register21_ce' => 'sysgen_dut_to_register21_ce',
'to_register21_clk' => 'sysgen_dut_to_register21_clk',
'to_register21_clr' => 'sysgen_dut_to_register21_clr',
'to_register21_data_in' => 'sysgen_dut_to_register21_data_in',
'to_register21_dout' => 'from_register23_data_out_x0',
'to_register21_en' => 'sysgen_dut_to_register21_en',
'to_register22_ce' => 'sysgen_dut_to_register22_ce',
'to_register22_clk' => 'sysgen_dut_to_register22_clk',
'to_register22_clr' => 'sysgen_dut_to_register22_clr',
'to_register22_data_in' => 'sysgen_dut_to_register22_data_in',
'to_register22_dout' => 'from_register22_data_out_x0',
'to_register22_en' => 'sysgen_dut_to_register22_en',
'to_register23_ce' => 'sysgen_dut_to_register23_ce',
'to_register23_clk' => 'sysgen_dut_to_register23_clk',
'to_register23_clr' => 'sysgen_dut_to_register23_clr',
'to_register23_data_in' => 'sysgen_dut_to_register23_data_in',
'to_register23_dout' => 'from_register25_data_out_x0',
'to_register23_en' => 'sysgen_dut_to_register23_en',
'to_register24_ce' => 'sysgen_dut_to_register24_ce',
'to_register24_clk' => 'sysgen_dut_to_register24_clk',
'to_register24_clr' => 'sysgen_dut_to_register24_clr',
'to_register24_data_in' => 'sysgen_dut_to_register24_data_in',
'to_register24_dout' => 'from_register24_data_out_x0',
'to_register24_en' => 'sysgen_dut_to_register24_en',
'to_register25_ce' => 'sysgen_dut_to_register25_ce',
'to_register25_clk' => 'sysgen_dut_to_register25_clk',
'to_register25_clr' => 'sysgen_dut_to_register25_clr',
'to_register25_data_in' => 'sysgen_dut_to_register25_data_in',
'to_register25_dout' => 'from_register21_data_out_x0',
'to_register25_en' => 'sysgen_dut_to_register25_en',
'to_register26_ce' => 'sysgen_dut_to_register26_ce',
'to_register26_clk' => 'sysgen_dut_to_register26_clk',
'to_register26_clr' => 'sysgen_dut_to_register26_clr',
'to_register26_data_in' => 'sysgen_dut_to_register26_data_in',
'to_register26_dout' => 'from_register20_data_out_x0',
'to_register26_en' => 'sysgen_dut_to_register26_en',
'to_register27_ce' => 'sysgen_dut_to_register27_ce',
'to_register27_clk' => 'sysgen_dut_to_register27_clk',
'to_register27_clr' => 'sysgen_dut_to_register27_clr',
'to_register27_data_in' => 'sysgen_dut_to_register27_data_in',
'to_register27_dout' => 'from_register27_data_out_x0',
'to_register27_en' => 'sysgen_dut_to_register27_en',
'to_register28_ce' => 'sysgen_dut_to_register28_ce',
'to_register28_clk' => 'sysgen_dut_to_register28_clk',
'to_register28_clr' => 'sysgen_dut_to_register28_clr',
'to_register28_data_in' => 'sysgen_dut_to_register28_data_in',
'to_register28_dout' => 'from_register26_data_out_x0',
'to_register28_en' => 'sysgen_dut_to_register28_en',
'to_register29_ce' => 'sysgen_dut_to_register29_ce',
'to_register29_clk' => 'sysgen_dut_to_register29_clk',
'to_register29_clr' => 'sysgen_dut_to_register29_clr',
'to_register29_data_in' => 'sysgen_dut_to_register29_data_in',
'to_register29_dout' => 'from_register29_data_out',
'to_register29_en' => 'sysgen_dut_to_register29_en',
'to_register2_ce' => 'sysgen_dut_to_register2_ce',
'to_register2_clk' => 'sysgen_dut_to_register2_clk',
'to_register2_clr' => 'sysgen_dut_to_register2_clr',
'to_register2_data_in' => 'sysgen_dut_to_register2_data_in',
'to_register2_dout' => 'from_register2_data_out_x0',
'to_register2_en' => 'sysgen_dut_to_register2_en',
'to_register30_ce' => 'sysgen_dut_to_register30_ce',
'to_register30_clk' => 'sysgen_dut_to_register30_clk',
'to_register30_clr' => 'sysgen_dut_to_register30_clr',
'to_register30_data_in' => 'sysgen_dut_to_register30_data_in',
'to_register30_dout' => 'from_register28_data_out_x0',
'to_register30_en' => 'sysgen_dut_to_register30_en',
'to_register31_ce' => 'sysgen_dut_to_register31_ce',
'to_register31_clk' => 'sysgen_dut_to_register31_clk',
'to_register31_clr' => 'sysgen_dut_to_register31_clr',
'to_register31_data_in' => 'sysgen_dut_to_register31_data_in',
'to_register31_dout' => 'from_register31_data_out',
'to_register31_en' => 'sysgen_dut_to_register31_en',
'to_register32_ce' => 'sysgen_dut_to_register32_ce',
'to_register32_clk' => 'sysgen_dut_to_register32_clk',
'to_register32_clr' => 'sysgen_dut_to_register32_clr',
'to_register32_data_in' => 'sysgen_dut_to_register32_data_in',
'to_register32_dout' => 'from_register30_data_out',
'to_register32_en' => 'sysgen_dut_to_register32_en',
'to_register33_ce' => 'sysgen_dut_to_register33_ce',
'to_register33_clk' => 'sysgen_dut_to_register33_clk',
'to_register33_clr' => 'sysgen_dut_to_register33_clr',
'to_register33_data_in' => 'sysgen_dut_to_register33_data_in',
'to_register33_dout' => 'from_register33_data_out',
'to_register33_en' => 'sysgen_dut_to_register33_en',
'to_register34_ce' => 'sysgen_dut_to_register34_ce',
'to_register34_clk' => 'sysgen_dut_to_register34_clk',
'to_register34_clr' => 'sysgen_dut_to_register34_clr',
'to_register34_data_in' => 'sysgen_dut_to_register34_data_in',
'to_register34_dout' => 'from_register32_data_out',
'to_register34_en' => 'sysgen_dut_to_register34_en',
'to_register3_ce' => 'sysgen_dut_to_register3_ce',
'to_register3_clk' => 'sysgen_dut_to_register3_clk',
'to_register3_clr' => 'sysgen_dut_to_register3_clr',
'to_register3_data_in' => 'sysgen_dut_to_register3_data_in',
'to_register3_dout' => 'from_register4_data_out_x0',
'to_register3_en' => 'sysgen_dut_to_register3_en',
'to_register4_ce' => 'sysgen_dut_to_register4_ce',
'to_register4_clk' => 'sysgen_dut_to_register4_clk',
'to_register4_clr' => 'sysgen_dut_to_register4_clr',
'to_register4_data_in' => 'sysgen_dut_to_register4_data_in',
'to_register4_dout' => 'from_register6_data_out_x0',
'to_register4_en' => 'sysgen_dut_to_register4_en',
'to_register5_ce' => 'sysgen_dut_to_register5_ce',
'to_register5_clk' => 'sysgen_dut_to_register5_clk',
'to_register5_clr' => 'sysgen_dut_to_register5_clr',
'to_register5_data_in' => 'sysgen_dut_to_register5_data_in',
'to_register5_dout' => 'from_register5_data_out_x0',
'to_register5_en' => 'sysgen_dut_to_register5_en',
'to_register6_ce' => 'sysgen_dut_to_register6_ce',
'to_register6_clk' => 'sysgen_dut_to_register6_clk',
'to_register6_clr' => 'sysgen_dut_to_register6_clr',
'to_register6_data_in' => 'sysgen_dut_to_register6_data_in',
'to_register6_dout' => 'from_register_data_out',
'to_register6_en' => 'sysgen_dut_to_register6_en',
'to_register7_ce' => 'sysgen_dut_to_register7_ce',
'to_register7_clk' => 'sysgen_dut_to_register7_clk',
'to_register7_clr' => 'sysgen_dut_to_register7_clr',
'to_register7_data_in' => 'sysgen_dut_to_register7_data_in',
'to_register7_dout' => 'from_register3_data_out_x0',
'to_register7_en' => 'sysgen_dut_to_register7_en',
'to_register8_ce' => 'sysgen_dut_to_register8_ce',
'to_register8_clk' => 'sysgen_dut_to_register8_clk',
'to_register8_clr' => 'sysgen_dut_to_register8_clr',
'to_register8_data_in' => 'sysgen_dut_to_register8_data_in',
'to_register8_dout' => 'from_register8_data_out_x0',
'to_register8_en' => 'sysgen_dut_to_register8_en',
'to_register9_ce' => 'sysgen_dut_to_register9_ce',
'to_register9_clk' => 'sysgen_dut_to_register9_clk',
'to_register9_clr' => 'sysgen_dut_to_register9_clr',
'to_register9_data_in' => 'sysgen_dut_to_register9_data_in',
'to_register9_dout' => 'from_register7_data_out_x0',
'to_register9_en' => 'sysgen_dut_to_register9_en',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'hdlArchAttributes' => [
],
'hdlCompAttributes' => [
[
'syn_black_box',
'boolean',
'true',
],
[
'box_type',
'string',
'"black_box"',
],
],
'hdlEntityAttributes' => [
],
'isClkWrapper' => 1,
'needsComponentDeclaration' => 1,
},
'connections' => {
'clk' => 'clkNet',
'debug_in_1i' => 'debug_in_1i_net',
'debug_in_2i' => 'debug_in_2i_net',
'debug_in_3i' => 'debug_in_3i_net',
'debug_in_4i' => 'debug_in_4i_net',
'dma_host2board_busy' => 'dma_host2board_busy_net',
'dma_host2board_done' => 'dma_host2board_done_net',
'from_register10_data_out' => 'from_register10_data_out_net',
'from_register11_data_out' => 'from_register11_data_out_net',
'from_register12_data_out' => 'from_register12_data_out_net',
'from_register13_data_out' => 'from_register13_data_out_net',
'from_register14_data_out' => 'from_register14_data_out_net',
'from_register15_data_out' => 'from_register15_data_out_net',
'from_register16_data_out' => 'from_register16_data_out_net',
'from_register17_data_out' => 'from_register17_data_out_net',
'from_register18_data_out' => 'from_register18_data_out_net',
'from_register19_data_out' => 'from_register19_data_out_net',
'from_register1_data_out' => 'from_register1_data_out_net',
'from_register20_data_out' => 'from_register20_data_out_net',
'from_register21_data_out' => 'from_register21_data_out_net',
'from_register22_data_out' => 'from_register22_data_out_net',
'from_register23_data_out' => 'from_register23_data_out_net',
'from_register24_data_out' => 'from_register24_data_out_net',
'from_register25_data_out' => 'from_register25_data_out_net',
'from_register26_data_out' => 'from_register26_data_out_net',
'from_register27_data_out' => 'from_register27_data_out_net',
'from_register28_data_out' => 'from_register28_data_out_net',
'from_register2_data_out' => 'from_register2_data_out_net',
'from_register3_data_out' => 'from_register3_data_out_net',
'from_register4_data_out' => 'from_register4_data_out_net',
'from_register5_data_out' => 'from_register5_data_out_net',
'from_register6_data_out' => 'from_register6_data_out_net',
'from_register7_data_out' => 'from_register7_data_out_net',
'from_register8_data_out' => 'from_register8_data_out_net',
'from_register9_data_out' => 'from_register9_data_out_net',
'reg01_rd' => 'from_register3_data_out_net_x0',
'reg01_rv' => 'from_register1_data_out_net_x0',
'reg01_td' => 'reg01_td_net',
'reg01_tv' => 'reg01_tv_net',
'reg02_rd' => 'from_register5_data_out_net_x0',
'reg02_rv' => 'from_register2_data_out_net_x0',
'reg02_td' => 'reg02_td_net',
'reg02_tv' => 'reg02_tv_net',
'reg03_rd' => 'from_register7_data_out_net_x0',
'reg03_rv' => 'from_register6_data_out_net_x0',
'reg03_td' => 'reg03_td_net',
'reg03_tv' => 'reg03_tv_net',
'reg04_rd' => 'from_register8_data_out_net_x0',
'reg04_rv' => 'from_register4_data_out_net_x0',
'reg04_td' => 'reg04_td_net',
'reg04_tv' => 'reg04_tv_net',
'reg05_rd' => 'from_register10_data_out_net_x0',
'reg05_rv' => 'from_register9_data_out_net_x0',
'reg05_td' => 'reg05_td_net',
'reg05_tv' => 'reg05_tv_net',
'reg06_rd' => 'from_register11_data_out_net_x0',
'reg06_rv' => 'from_register12_data_out_net_x0',
'reg06_td' => 'reg06_td_net',
'reg06_tv' => 'reg06_tv_net',
'reg07_rd' => 'from_register13_data_out_net_x0',
'reg07_rv' => 'from_register14_data_out_net_x0',
'reg07_td' => 'reg07_td_net',
'reg07_tv' => 'reg07_tv_net',
'reg08_rd' => 'from_register15_data_out_net_x0',
'reg08_rv' => 'from_register16_data_out_net_x0',
'reg08_td' => 'reg08_td_net',
'reg08_tv' => 'reg08_tv_net',
'reg09_rd' => 'from_register17_data_out_net_x0',
'reg09_rv' => 'from_register18_data_out_net_x0',
'reg09_td' => 'reg09_td_net',
'reg09_tv' => 'reg09_tv_net',
'reg10_rd' => 'from_register19_data_out_net_x0',
'reg10_rv' => 'from_register20_data_out_net_x0',
'reg10_td' => 'reg10_td_net',
'reg10_tv' => 'reg10_tv_net',
'reg11_rd' => 'from_register21_data_out_net_x0',
'reg11_rv' => 'from_register22_data_out_net_x0',
'reg11_td' => 'reg11_td_net',
'reg11_tv' => 'reg11_tv_net',
'reg12_rd' => 'from_register23_data_out_net_x0',
'reg12_rv' => 'from_register24_data_out_net_x0',
'reg12_td' => 'reg12_td_net',
'reg12_tv' => 'reg12_tv_net',
'reg13_rd' => 'from_register25_data_out_net_x0',
'reg13_rv' => 'from_register26_data_out_net_x0',
'reg13_td' => 'reg13_td_net',
'reg13_tv' => 'reg13_tv_net',
'reg14_rd' => 'from_register27_data_out_net_x0',
'reg14_rv' => 'from_register28_data_out_net_x0',
'reg14_td' => 'reg14_td_net',
'reg14_tv' => 'reg14_tv_net',
'to_register10_ce' => 'ce_1_sg',
'to_register10_clk' => 'clk_1_sg',
'to_register10_clr' => [
'constant',
'\'0\'',
],
'to_register10_data_in' => 'reg04_tv_net_x0',
'to_register10_dout' => 'to_register10_dout_net',
'to_register10_en' => 'constant5_op_net_x1',
'to_register11_ce' => 'ce_1_sg',
'to_register11_clk' => 'clk_1_sg',
'to_register11_clr' => [
'constant',
'\'0\'',
],
'to_register11_data_in' => 'reg04_td_net_x0',
'to_register11_dout' => 'to_register11_dout_net',
'to_register11_en' => 'constant5_op_net_x2',
'to_register12_ce' => 'ce_1_sg',
'to_register12_clk' => 'clk_1_sg',
'to_register12_clr' => [
'constant',
'\'0\'',
],
'to_register12_data_in' => 'reg05_tv_net_x0',
'to_register12_dout' => 'to_register12_dout_net',
'to_register12_en' => 'constant5_op_net_x3',
'to_register13_ce' => 'ce_1_sg',
'to_register13_clk' => 'clk_1_sg',
'to_register13_clr' => [
'constant',
'\'0\'',
],
'to_register13_data_in' => 'reg05_td_net_x0',
'to_register13_dout' => 'to_register13_dout_net',
'to_register13_en' => 'constant5_op_net_x4',
'to_register14_ce' => 'ce_1_sg',
'to_register14_clk' => 'clk_1_sg',
'to_register14_clr' => [
'constant',
'\'0\'',
],
'to_register14_data_in' => 'reg06_tv_net_x0',
'to_register14_dout' => 'to_register14_dout_net',
'to_register14_en' => 'constant5_op_net_x5',
'to_register15_ce' => 'ce_1_sg',
'to_register15_clk' => 'clk_1_sg',
'to_register15_clr' => [
'constant',
'\'0\'',
],
'to_register15_data_in' => 'reg06_td_net_x0',
'to_register15_dout' => 'to_register15_dout_net',
'to_register15_en' => 'constant5_op_net_x6',
'to_register16_ce' => 'ce_1_sg',
'to_register16_clk' => 'clk_1_sg',
'to_register16_clr' => [
'constant',
'\'0\'',
],
'to_register16_data_in' => 'reg07_tv_net_x0',
'to_register16_dout' => 'to_register16_dout_net',
'to_register16_en' => 'constant5_op_net_x7',
'to_register17_ce' => 'ce_1_sg',
'to_register17_clk' => 'clk_1_sg',
'to_register17_clr' => [
'constant',
'\'0\'',
],
'to_register17_data_in' => 'reg07_td_net_x0',
'to_register17_dout' => 'to_register17_dout_net',
'to_register17_en' => 'constant5_op_net_x8',
'to_register18_ce' => 'ce_1_sg',
'to_register18_clk' => 'clk_1_sg',
'to_register18_clr' => [
'constant',
'\'0\'',
],
'to_register18_data_in' => 'dma_host2board_busy_net_x0',
'to_register18_dout' => 'to_register18_dout_net',
'to_register18_en' => 'constant5_op_net_x9',
'to_register19_ce' => 'ce_1_sg',
'to_register19_clk' => 'clk_1_sg',
'to_register19_clr' => [
'constant',
'\'0\'',
],
'to_register19_data_in' => 'dma_host2board_done_net_x0',
'to_register19_dout' => 'to_register19_dout_net',
'to_register19_en' => 'constant5_op_net_x10',
'to_register1_ce' => 'ce_1_sg',
'to_register1_clk' => 'clk_1_sg',
'to_register1_clr' => [
'constant',
'\'0\'',
],
'to_register1_data_in' => 'debug_in_2i_net_x0',
'to_register1_dout' => 'to_register1_dout_net',
'to_register1_en' => 'constant5_op_net_x0',
'to_register20_ce' => 'ce_1_sg',
'to_register20_clk' => 'clk_1_sg',
'to_register20_clr' => [
'constant',
'\'0\'',
],
'to_register20_data_in' => 'debug_in_4i_net_x0',
'to_register20_dout' => 'to_register20_dout_net',
'to_register20_en' => 'constant5_op_net_x12',
'to_register21_ce' => 'ce_1_sg',
'to_register21_clk' => 'clk_1_sg',
'to_register21_clr' => [
'constant',
'\'0\'',
],
'to_register21_data_in' => 'reg09_tv_net_x0',
'to_register21_dout' => 'to_register21_dout_net',
'to_register21_en' => 'constant1_op_net_x0',
'to_register22_ce' => 'ce_1_sg',
'to_register22_clk' => 'clk_1_sg',
'to_register22_clr' => [
'constant',
'\'0\'',
],
'to_register22_data_in' => 'reg09_td_net_x0',
'to_register22_dout' => 'to_register22_dout_net',
'to_register22_en' => 'constant1_op_net_x1',
'to_register23_ce' => 'ce_1_sg',
'to_register23_clk' => 'clk_1_sg',
'to_register23_clr' => [
'constant',
'\'0\'',
],
'to_register23_data_in' => 'reg10_tv_net_x0',
'to_register23_dout' => 'to_register23_dout_net',
'to_register23_en' => 'constant1_op_net_x2',
'to_register24_ce' => 'ce_1_sg',
'to_register24_clk' => 'clk_1_sg',
'to_register24_clr' => [
'constant',
'\'0\'',
],
'to_register24_data_in' => 'reg10_td_net_x0',
'to_register24_dout' => 'to_register24_dout_net',
'to_register24_en' => 'constant1_op_net_x3',
'to_register25_ce' => 'ce_1_sg',
'to_register25_clk' => 'clk_1_sg',
'to_register25_clr' => [
'constant',
'\'0\'',
],
'to_register25_data_in' => 'reg08_tv_net_x0',
'to_register25_dout' => 'to_register25_dout_net',
'to_register25_en' => 'constant1_op_net_x4',
'to_register26_ce' => 'ce_1_sg',
'to_register26_clk' => 'clk_1_sg',
'to_register26_clr' => [
'constant',
'\'0\'',
],
'to_register26_data_in' => 'reg08_td_net_x0',
'to_register26_dout' => 'to_register26_dout_net',
'to_register26_en' => 'constant1_op_net_x5',
'to_register27_ce' => 'ce_1_sg',
'to_register27_clk' => 'clk_1_sg',
'to_register27_clr' => [
'constant',
'\'0\'',
],
'to_register27_data_in' => 'reg11_tv_net_x0',
'to_register27_dout' => 'to_register27_dout_net',
'to_register27_en' => 'constant1_op_net_x6',
'to_register28_ce' => 'ce_1_sg',
'to_register28_clk' => 'clk_1_sg',
'to_register28_clr' => [
'constant',
'\'0\'',
],
'to_register28_data_in' => 'reg11_td_net_x0',
'to_register28_dout' => 'to_register28_dout_net',
'to_register28_en' => 'constant1_op_net_x7',
'to_register29_ce' => 'ce_1_sg',
'to_register29_clk' => 'clk_1_sg',
'to_register29_clr' => [
'constant',
'\'0\'',
],
'to_register29_data_in' => 'reg12_tv_net_x0',
'to_register29_dout' => 'to_register29_dout_net',
'to_register29_en' => 'constant1_op_net_x8',
'to_register2_ce' => 'ce_1_sg',
'to_register2_clk' => 'clk_1_sg',
'to_register2_clr' => [
'constant',
'\'0\'',
],
'to_register2_data_in' => 'debug_in_3i_net_x0',
'to_register2_dout' => 'to_register2_dout_net',
'to_register2_en' => 'constant5_op_net_x11',
'to_register30_ce' => 'ce_1_sg',
'to_register30_clk' => 'clk_1_sg',
'to_register30_clr' => [
'constant',
'\'0\'',
],
'to_register30_data_in' => 'reg12_td_net_x0',
'to_register30_dout' => 'to_register30_dout_net',
'to_register30_en' => 'constant1_op_net_x9',
'to_register31_ce' => 'ce_1_sg',
'to_register31_clk' => 'clk_1_sg',
'to_register31_clr' => [
'constant',
'\'0\'',
],
'to_register31_data_in' => 'reg13_tv_net_x0',
'to_register31_dout' => 'to_register31_dout_net',
'to_register31_en' => 'constant1_op_net_x10',
'to_register32_ce' => 'ce_1_sg',
'to_register32_clk' => 'clk_1_sg',
'to_register32_clr' => [
'constant',
'\'0\'',
],
'to_register32_data_in' => 'reg13_td_net_x0',
'to_register32_dout' => 'to_register32_dout_net',
'to_register32_en' => 'constant1_op_net_x11',
'to_register33_ce' => 'ce_1_sg',
'to_register33_clk' => 'clk_1_sg',
'to_register33_clr' => [
'constant',
'\'0\'',
],
'to_register33_data_in' => 'reg14_tv_net_x0',
'to_register33_dout' => 'to_register33_dout_net',
'to_register33_en' => 'constant1_op_net_x12',
'to_register34_ce' => 'ce_1_sg',
'to_register34_clk' => 'clk_1_sg',
'to_register34_clr' => [
'constant',
'\'0\'',
],
'to_register34_data_in' => 'reg14_td_net_x0',
'to_register34_dout' => 'to_register34_dout_net',
'to_register34_en' => 'constant1_op_net_x13',
'to_register3_ce' => 'ce_1_sg',
'to_register3_clk' => 'clk_1_sg',
'to_register3_clr' => [
'constant',
'\'0\'',
],
'to_register3_data_in' => 'reg01_tv_net_x0',
'to_register3_dout' => 'to_register3_dout_net',
'to_register3_en' => 'constant5_op_net_x13',
'to_register4_ce' => 'ce_1_sg',
'to_register4_clk' => 'clk_1_sg',
'to_register4_clr' => [
'constant',
'\'0\'',
],
'to_register4_data_in' => 'reg02_tv_net_x0',
'to_register4_dout' => 'to_register4_dout_net',
'to_register4_en' => 'constant5_op_net_x14',
'to_register5_ce' => 'ce_1_sg',
'to_register5_clk' => 'clk_1_sg',
'to_register5_clr' => [
'constant',
'\'0\'',
],
'to_register5_data_in' => 'reg02_td_net_x0',
'to_register5_dout' => 'to_register5_dout_net',
'to_register5_en' => 'constant5_op_net_x15',
'to_register6_ce' => 'ce_1_sg',
'to_register6_clk' => 'clk_1_sg',
'to_register6_clr' => [
'constant',
'\'0\'',
],
'to_register6_data_in' => 'debug_in_1i_net_x0',
'to_register6_dout' => 'to_register6_dout_net',
'to_register6_en' => 'constant5_op_net_x16',
'to_register7_ce' => 'ce_1_sg',
'to_register7_clk' => 'clk_1_sg',
'to_register7_clr' => [
'constant',
'\'0\'',
],
'to_register7_data_in' => 'reg01_td_net_x0',
'to_register7_dout' => 'to_register7_dout_net',
'to_register7_en' => 'constant5_op_net_x17',
'to_register8_ce' => 'ce_1_sg',
'to_register8_clk' => 'clk_1_sg',
'to_register8_clr' => [
'constant',
'\'0\'',
],
'to_register8_data_in' => 'reg03_tv_net_x0',
'to_register8_dout' => 'to_register8_dout_net',
'to_register8_en' => 'constant5_op_net_x18',
'to_register9_ce' => 'ce_1_sg',
'to_register9_clk' => 'clk_1_sg',
'to_register9_clr' => [
'constant',
'\'0\'',
],
'to_register9_data_in' => 'reg03_td_net_x0',
'to_register9_dout' => 'to_register9_dout_net',
'to_register9_en' => 'constant5_op_net_x19',
},
'entityName' => 'inout_logic_cw',
'nets' => {
'ce_1_sg' => {
'attributes' => {
'hdlNetAttributes' => [
[
'MAX_FANOUT',
'string',
'"REDUCE"',
],
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'clkNet' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'clk_1_sg' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x1' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x10' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x11' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x12' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x13' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x2' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x3' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x4' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x5' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x6' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x7' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x8' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x9' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x1' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x10' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x11' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x12' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x13' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x14' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x15' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x16' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x17' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x18' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x19' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x2' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x3' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x4' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x5' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x6' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x7' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x8' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x9' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'debug_in_1i_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'debug_in_1i_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'debug_in_2i_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'debug_in_2i_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'debug_in_3i_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'debug_in_3i_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'debug_in_4i_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'debug_in_4i_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'dma_host2board_busy_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'dma_host2board_busy_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'dma_host2board_done_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'dma_host2board_done_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register10_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register10_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register11_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register11_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register12_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register12_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register13_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register13_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register14_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register14_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register15_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register15_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register16_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register16_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register17_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register17_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register18_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register18_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register19_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register19_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register1_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register1_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register20_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register20_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register21_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register21_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register22_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register22_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register23_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register23_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register24_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register24_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register25_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register25_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register26_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register26_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register27_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register27_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register28_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register28_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register2_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register2_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register3_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register3_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register4_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register4_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register5_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register5_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register6_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register6_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register7_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register7_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register8_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register8_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register9_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register9_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'persistentdff_inst_q' => {
'attributes' => {
'hdlNetAttributes' => [
[
'syn_keep',
'boolean',
'true',
],
[
'keep',
'boolean',
'true',
],
[
'preserve_signal',
'boolean',
'true',
],
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg01_td_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg01_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg01_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg01_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg02_td_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg02_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg02_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg02_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg03_td_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg03_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg03_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg03_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg04_td_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg04_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg04_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg04_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg05_td_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg05_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg05_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg05_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg06_td_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg06_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg06_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg06_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg07_td_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg07_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg07_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg07_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg08_td_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg08_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg08_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg08_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg09_td_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg09_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg09_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg09_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg10_td_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg10_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg10_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg10_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg11_td_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg11_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg11_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg11_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg12_td_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg12_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg12_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg12_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg13_td_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg13_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg13_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg13_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg14_td_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg14_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg14_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg14_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register10_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register11_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register12_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register13_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register14_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register15_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register16_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register17_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register18_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register19_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register1_dout_net' => {
'attributes' => {
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'to_register9_dout_net' => {
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},
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'from_register23_data_out' => {
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'from_register6_data_out' => {
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'reg01_rd' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd/reg01_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg01_rv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv/reg01_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg01_td' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
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'is_gateway_port' => 1,
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'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td/reg01_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg01_tv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
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'is_gateway_port' => 1,
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'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv/reg01_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg02_rd' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd/reg02_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg02_rv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv/reg02_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg02_td' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td/reg02_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg02_tv' => {
'attributes' => {
'bin_pt' => 0,
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv/reg02_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg03_rd' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd/reg03_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg03_rv' => {
'attributes' => {
'bin_pt' => 0,
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'is_gateway_port' => 1,
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'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv/reg03_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg03_td' => {
'attributes' => {
'bin_pt' => 0,
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'is_gateway_port' => 1,
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'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td/reg03_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg03_tv' => {
'attributes' => {
'bin_pt' => 0,
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv/reg03_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg04_rd' => {
'attributes' => {
'bin_pt' => 0,
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'is_gateway_port' => 1,
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'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd/reg04_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg04_rv' => {
'attributes' => {
'bin_pt' => 0,
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'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv/reg04_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg04_td' => {
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'bin_pt' => 0,
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'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td/reg04_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
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'width' => 32,
},
'reg04_tv' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv/reg04_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg05_rd' => {
'attributes' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd/reg05_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg05_rv' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv/reg05_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg05_td' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
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},
'reg05_tv' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg06_rd' => {
'attributes' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd/reg06_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg06_rv' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv/reg06_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg06_td' => {
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'bin_pt' => 0,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td/reg06_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
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'width' => 32,
},
'reg06_tv' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv/reg06_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg07_rd' => {
'attributes' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd/reg07_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg07_rv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv/reg07_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg07_td' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td/reg07_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
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'width' => 32,
},
'reg07_tv' => {
'attributes' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv/reg07_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg08_rd' => {
'attributes' => {
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'is_gateway_port' => 1,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd/reg08_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg08_rv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
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'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv/reg08_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg08_td' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td/reg08_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg08_tv' => {
'attributes' => {
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'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv/reg08_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg09_rd' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd/reg09_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg09_rv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv/reg09_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg09_td' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td/reg09_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg09_tv' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv/reg09_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'in',
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'width' => 1,
},
'reg10_rd' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd',
'timingConstraint' => 'none',
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},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg10_rv' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv',
'timingConstraint' => 'none',
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},
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'hdlType' => 'std_logic',
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},
'reg10_td' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td',
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},
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},
'reg10_tv' => {
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},
'reg11_rd' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd',
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},
'direction' => 'out',
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},
'reg11_rv' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv',
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},
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},
'reg11_td' => {
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},
'reg11_tv' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv',
'timingConstraint' => 'none',
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},
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'width' => 1,
},
'reg12_rd' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd',
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},
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},
'reg12_rv' => {
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},
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},
'reg12_td' => {
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},
'reg12_tv' => {
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},
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},
'reg13_rd' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd',
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},
'direction' => 'out',
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},
'reg13_rv' => {
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},
'reg13_td' => {
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},
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},
'reg14_rd' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
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},
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},
'reg14_rv' => {
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},
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},
'reg14_tv' => {
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},
'direction' => 'in',
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},
'to_register10_ce' => {
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},
'direction' => 'out',
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},
'to_register10_clk' => {
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},
'to_register10_clr' => {
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'type' => 'logic',
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},
'direction' => 'out',
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},
'to_register10_data_in' => {
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},
'direction' => 'out',
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},
'to_register10_dout' => {
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},
'to_register10_en' => {
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'to_register11_ce' => {
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'to_register11_clk' => {
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},
'to_register11_clr' => {
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},
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},
'to_register11_data_in' => {
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},
'to_register11_dout' => {
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'to_register11_en' => {
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'direction' => 'out',
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'to_register12_ce' => {
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},
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'to_register12_clk' => {
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},
'to_register12_clr' => {
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},
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},
'to_register12_data_in' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/data_in',
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},
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},
'to_register12_dout' => {
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},
'to_register12_en' => {
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'direction' => 'out',
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},
'to_register13_ce' => {
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},
'direction' => 'out',
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},
'to_register13_clk' => {
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},
'to_register13_clr' => {
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},
'direction' => 'out',
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'width' => 1,
},
'to_register13_data_in' => {
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'period' => 1,
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},
'to_register9_ce' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isCe' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register9_clk' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClk' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register9_clr' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClr' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
'valid_bit_used' => 0,
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register9_data_in' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register9_dout' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register9_en' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 1,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
'subblocks' => {
'default_clock_driver_x0' => {
'connections' => {
'ce_1' => 'ce_1_sg',
'clk_1' => 'clk_1_sg',
'sysce' => [
'constant',
'\'1\'',
],
'sysce_clr' => [
'constant',
'\'0\'',
],
'sysclk' => 'clkNet',
},
'entity' => {
'attributes' => {
'domain' => 'default',
'hdlArchAttributes' => [
[
'syn_noprune',
'boolean',
'true',
],
[
'optimize_primitives',
'boolean',
'false',
],
[
'dont_touch',
'boolean',
'true',
],
],
'hdlEntityAttributes' => [
],
'isClkDriver' => 1,
},
'entityName' => 'default_clock_driver',
'ports' => {
'ce_1' => {
'attributes' => {
'domain' => 'default',
'group' => 1,
'isCe' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk_1' => {
'attributes' => {
'domain' => 'default',
'group' => 1,
'isClk' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'sysce' => {
'attributes' => {
'group' => 4,
'isCe' => 1,
'period' => 1,
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'sysce_clr' => {
'attributes' => {
'group' => 4,
'isClr' => 1,
'period' => 1,
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'sysclk' => {
'attributes' => {
'group' => 4,
'isClk' => 1,
'period' => 1,
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'default_clock_driver',
},
'inout_logic_x0' => {
'connections' => {
'data_in' => 'debug_in_2i_net_x0',
'data_in_x0' => 'reg04_tv_net_x0',
'data_in_x1' => 'reg04_td_net_x0',
'data_in_x10' => 'debug_in_3i_net_x0',
'data_in_x11' => 'debug_in_4i_net_x0',
'data_in_x12' => 'reg09_tv_net_x0',
'data_in_x13' => 'reg09_td_net_x0',
'data_in_x14' => 'reg10_tv_net_x0',
'data_in_x15' => 'reg10_td_net_x0',
'data_in_x16' => 'reg08_tv_net_x0',
'data_in_x17' => 'reg08_td_net_x0',
'data_in_x18' => 'reg11_tv_net_x0',
'data_in_x19' => 'reg11_td_net_x0',
'data_in_x2' => 'reg05_tv_net_x0',
'data_in_x20' => 'reg12_tv_net_x0',
'data_in_x21' => 'reg01_tv_net_x0',
'data_in_x22' => 'reg12_td_net_x0',
'data_in_x23' => 'reg13_tv_net_x0',
'data_in_x24' => 'reg13_td_net_x0',
'data_in_x25' => 'reg14_tv_net_x0',
'data_in_x26' => 'reg14_td_net_x0',
'data_in_x27' => 'reg02_tv_net_x0',
'data_in_x28' => 'reg02_td_net_x0',
'data_in_x29' => 'debug_in_1i_net_x0',
'data_in_x3' => 'reg05_td_net_x0',
'data_in_x30' => 'reg01_td_net_x0',
'data_in_x31' => 'reg03_tv_net_x0',
'data_in_x32' => 'reg03_td_net_x0',
'data_in_x4' => 'reg06_tv_net_x0',
'data_in_x5' => 'reg06_td_net_x0',
'data_in_x6' => 'reg07_tv_net_x0',
'data_in_x7' => 'reg07_td_net_x0',
'data_in_x8' => 'dma_host2board_busy_net_x0',
'data_in_x9' => 'dma_host2board_done_net_x0',
'data_out' => 'from_register1_data_out_net',
'data_out_x0' => 'from_register10_data_out_net',
'data_out_x1' => 'from_register11_data_out_net',
'data_out_x10' => 'from_register2_data_out_net',
'data_out_x11' => 'from_register20_data_out_net',
'data_out_x12' => 'from_register21_data_out_net',
'data_out_x13' => 'from_register22_data_out_net',
'data_out_x14' => 'from_register23_data_out_net',
'data_out_x15' => 'from_register24_data_out_net',
'data_out_x16' => 'from_register25_data_out_net',
'data_out_x17' => 'from_register26_data_out_net',
'data_out_x18' => 'from_register27_data_out_net',
'data_out_x19' => 'from_register28_data_out_net',
'data_out_x2' => 'from_register12_data_out_net',
'data_out_x20' => 'from_register3_data_out_net',
'data_out_x21' => 'from_register4_data_out_net',
'data_out_x22' => 'from_register5_data_out_net',
'data_out_x23' => 'from_register6_data_out_net',
'data_out_x24' => 'from_register7_data_out_net',
'data_out_x25' => 'from_register8_data_out_net',
'data_out_x26' => 'from_register9_data_out_net',
'data_out_x3' => 'from_register13_data_out_net',
'data_out_x4' => 'from_register14_data_out_net',
'data_out_x5' => 'from_register15_data_out_net',
'data_out_x6' => 'from_register16_data_out_net',
'data_out_x7' => 'from_register17_data_out_net',
'data_out_x8' => 'from_register18_data_out_net',
'data_out_x9' => 'from_register19_data_out_net',
'debug_in_1i' => 'debug_in_1i_net',
'debug_in_2i' => 'debug_in_2i_net',
'debug_in_3i' => 'debug_in_3i_net',
'debug_in_4i' => 'debug_in_4i_net',
'dma_host2board_busy' => 'dma_host2board_busy_net',
'dma_host2board_done' => 'dma_host2board_done_net',
'en' => 'constant5_op_net_x0',
'en_x0' => 'constant5_op_net_x1',
'en_x1' => 'constant5_op_net_x2',
'en_x10' => 'constant5_op_net_x11',
'en_x11' => 'constant5_op_net_x12',
'en_x12' => 'constant1_op_net_x0',
'en_x13' => 'constant1_op_net_x1',
'en_x14' => 'constant1_op_net_x2',
'en_x15' => 'constant1_op_net_x3',
'en_x16' => 'constant1_op_net_x4',
'en_x17' => 'constant1_op_net_x5',
'en_x18' => 'constant1_op_net_x6',
'en_x19' => 'constant1_op_net_x7',
'en_x2' => 'constant5_op_net_x3',
'en_x20' => 'constant1_op_net_x8',
'en_x21' => 'constant5_op_net_x13',
'en_x22' => 'constant1_op_net_x9',
'en_x23' => 'constant1_op_net_x10',
'en_x24' => 'constant1_op_net_x11',
'en_x25' => 'constant1_op_net_x12',
'en_x26' => 'constant1_op_net_x13',
'en_x27' => 'constant5_op_net_x14',
'en_x28' => 'constant5_op_net_x15',
'en_x29' => 'constant5_op_net_x16',
'en_x3' => 'constant5_op_net_x4',
'en_x30' => 'constant5_op_net_x17',
'en_x31' => 'constant5_op_net_x18',
'en_x32' => 'constant5_op_net_x19',
'en_x4' => 'constant5_op_net_x5',
'en_x5' => 'constant5_op_net_x6',
'en_x6' => 'constant5_op_net_x7',
'en_x7' => 'constant5_op_net_x8',
'en_x8' => 'constant5_op_net_x9',
'en_x9' => 'constant5_op_net_x10',
'reg01_rd' => 'from_register3_data_out_net_x0',
'reg01_rv' => 'from_register1_data_out_net_x0',
'reg01_td' => 'reg01_td_net',
'reg01_tv' => 'reg01_tv_net',
'reg02_rd' => 'from_register5_data_out_net_x0',
'reg02_rv' => 'from_register2_data_out_net_x0',
'reg02_td' => 'reg02_td_net',
'reg02_tv' => 'reg02_tv_net',
'reg03_rd' => 'from_register7_data_out_net_x0',
'reg03_rv' => 'from_register6_data_out_net_x0',
'reg03_td' => 'reg03_td_net',
'reg03_tv' => 'reg03_tv_net',
'reg04_rd' => 'from_register8_data_out_net_x0',
'reg04_rv' => 'from_register4_data_out_net_x0',
'reg04_td' => 'reg04_td_net',
'reg04_tv' => 'reg04_tv_net',
'reg05_rd' => 'from_register10_data_out_net_x0',
'reg05_rv' => 'from_register9_data_out_net_x0',
'reg05_td' => 'reg05_td_net',
'reg05_tv' => 'reg05_tv_net',
'reg06_rd' => 'from_register11_data_out_net_x0',
'reg06_rv' => 'from_register12_data_out_net_x0',
'reg06_td' => 'reg06_td_net',
'reg06_tv' => 'reg06_tv_net',
'reg07_rd' => 'from_register13_data_out_net_x0',
'reg07_rv' => 'from_register14_data_out_net_x0',
'reg07_td' => 'reg07_td_net',
'reg07_tv' => 'reg07_tv_net',
'reg08_rd' => 'from_register15_data_out_net_x0',
'reg08_rv' => 'from_register16_data_out_net_x0',
'reg08_td' => 'reg08_td_net',
'reg08_tv' => 'reg08_tv_net',
'reg09_rd' => 'from_register17_data_out_net_x0',
'reg09_rv' => 'from_register18_data_out_net_x0',
'reg09_td' => 'reg09_td_net',
'reg09_tv' => 'reg09_tv_net',
'reg10_rd' => 'from_register19_data_out_net_x0',
'reg10_rv' => 'from_register20_data_out_net_x0',
'reg10_td' => 'reg10_td_net',
'reg10_tv' => 'reg10_tv_net',
'reg11_rd' => 'from_register21_data_out_net_x0',
'reg11_rv' => 'from_register22_data_out_net_x0',
'reg11_td' => 'reg11_td_net',
'reg11_tv' => 'reg11_tv_net',
'reg12_rd' => 'from_register23_data_out_net_x0',
'reg12_rv' => 'from_register24_data_out_net_x0',
'reg12_td' => 'reg12_td_net',
'reg12_tv' => 'reg12_tv_net',
'reg13_rd' => 'from_register25_data_out_net_x0',
'reg13_rv' => 'from_register26_data_out_net_x0',
'reg13_td' => 'reg13_td_net',
'reg13_tv' => 'reg13_tv_net',
'reg14_rd' => 'from_register27_data_out_net_x0',
'reg14_rv' => 'from_register28_data_out_net_x0',
'reg14_td' => 'reg14_td_net',
'reg14_tv' => 'reg14_tv_net',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'hdlKind' => 'vhdl',
'isDesign' => 1,
'simulinkName' => 'INOUT_LOGIC',
},
'entityName' => 'inout_logic',
'ports' => {
'data_in' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x0' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x1' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x10' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x11' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x12' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x13' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x14' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x15' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x16' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x17' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x18' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x19' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x2' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x20' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x21' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x22' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x23' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x24' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x25' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x26' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x27' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
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'type' => 'UFix_32_0',
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},
'reg06_rv' => {
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'type' => 'Bool',
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},
'reg07_rd' => {
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'reg07_rv' => {
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'reg07_td' => {
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'reg08_rd' => {
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'reg09_rv' => {
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'reg13_rd' => {
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'reg13_rv' => {
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},
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'd' => 'persistentdff_inst_q',
'q' => 'persistentdff_inst_q',
},
'entity' => {
'attributes' => {
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[
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},
'entityName' => 'xlpersistentdff',
'ports' => {
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},
'd' => {
'direction' => 'in',
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'q' => {
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},
},
},
'entityName' => 'xlpersistentdff',
},
},
},
'entityName' => 'inout_logic_cw',
},
'top_level_1' => {
'connections' => {
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'bram_rd_dout' => 'x_x64',
'bram_wr_addr' => 'x_x65',
'bram_wr_din' => 'x_x66',
'bram_wr_en' => 'x_x67',
'ce' => 'x_x68',
'clk' => 'x_x69',
'fifo_rd_count' => 'x_x70',
'fifo_rd_dout' => 'x_x71',
'fifo_rd_empty' => 'x_x72',
'fifo_rd_en' => 'x_x73',
'fifo_rd_pempty' => 'x_x74',
'fifo_rd_valid' => 'x_x75',
'fifo_wr_count' => 'x_x76',
'fifo_wr_din' => 'x_x77',
'fifo_wr_en' => 'x_x78',
'fifo_wr_full' => 'x_x79',
'fifo_wr_pfull' => 'x_x80',
'from_register10_data_out' => 'from_register10_data_out_x0',
'from_register11_data_out' => 'from_register11_data_out_x0',
'from_register12_data_out' => 'from_register12_data_out_x0',
'from_register13_data_out' => 'from_register13_data_out_x0',
'from_register14_data_out' => 'from_register14_data_out_x0',
'from_register15_data_out' => 'from_register15_data_out_x0',
'from_register16_data_out' => 'from_register16_data_out_x0',
'from_register17_data_out' => 'from_register17_data_out_x0',
'from_register18_data_out' => 'from_register18_data_out_x0',
'from_register19_data_out' => 'from_register19_data_out_x0',
'from_register1_data_out' => 'from_register1_data_out_x0',
'from_register20_data_out' => 'from_register20_data_out_x0',
'from_register21_data_out' => 'from_register21_data_out_x0',
'from_register22_data_out' => 'from_register22_data_out_x0',
'from_register23_data_out' => 'from_register23_data_out_x0',
'from_register24_data_out' => 'from_register24_data_out_x0',
'from_register25_data_out' => 'from_register25_data_out_x0',
'from_register26_data_out' => 'from_register26_data_out_x0',
'from_register27_data_out' => 'from_register27_data_out_x0',
'from_register28_data_out' => 'from_register28_data_out_x0',
'from_register29_data_out' => 'from_register29_data_out',
'from_register2_data_out' => 'from_register2_data_out_x0',
'from_register30_data_out' => 'from_register30_data_out',
'from_register31_data_out' => 'from_register31_data_out',
'from_register32_data_out' => 'from_register32_data_out',
'from_register33_data_out' => 'from_register33_data_out',
'from_register3_data_out' => 'from_register3_data_out_x0',
'from_register4_data_out' => 'from_register4_data_out_x0',
'from_register5_data_out' => 'from_register5_data_out_x0',
'from_register6_data_out' => 'from_register6_data_out_x0',
'from_register7_data_out' => 'from_register7_data_out_x0',
'from_register8_data_out' => 'from_register8_data_out_x0',
'from_register9_data_out' => 'from_register9_data_out_x0',
'from_register_data_out' => 'from_register_data_out',
'rst_i' => 'x_x81',
'rst_o' => 'x_x82',
'to_register10_ce' => 'sysgen_dut_to_register10_ce_x0',
'to_register10_clk' => 'sysgen_dut_to_register10_clk_x0',
'to_register10_clr' => 'sysgen_dut_to_register10_clr_x0',
'to_register10_data_in' => 'sysgen_dut_to_register10_data_in_x0',
'to_register10_dout' => 'from_register9_data_out',
'to_register10_en' => 'sysgen_dut_to_register10_en_x0',
'to_register11_ce' => 'sysgen_dut_to_register11_ce_x0',
'to_register11_clk' => 'sysgen_dut_to_register11_clk_x0',
'to_register11_clr' => 'sysgen_dut_to_register11_clr_x0',
'to_register11_data_in' => 'sysgen_dut_to_register11_data_in_x0',
'to_register11_dout' => 'from_register12_data_out',
'to_register11_en' => 'sysgen_dut_to_register11_en_x0',
'to_register12_ce' => 'sysgen_dut_to_register12_ce_x0',
'to_register12_clk' => 'sysgen_dut_to_register12_clk_x0',
'to_register12_clr' => 'sysgen_dut_to_register12_clr_x0',
'to_register12_data_in' => 'sysgen_dut_to_register12_data_in_x0',
'to_register12_dout' => 'from_register14_data_out',
'to_register12_en' => 'sysgen_dut_to_register12_en_x0',
'to_register13_ce' => 'sysgen_dut_to_register13_ce_x0',
'to_register13_clk' => 'sysgen_dut_to_register13_clk_x0',
'to_register13_clr' => 'sysgen_dut_to_register13_clr_x0',
'to_register13_data_in' => 'sysgen_dut_to_register13_data_in_x0',
'to_register13_dout' => 'from_register13_data_out',
'to_register13_en' => 'sysgen_dut_to_register13_en_x0',
'to_register14_ce' => 'sysgen_dut_to_register14_ce_x0',
'to_register14_clk' => 'sysgen_dut_to_register14_clk_x0',
'to_register14_clr' => 'sysgen_dut_to_register14_clr_x0',
'to_register14_data_in' => 'sysgen_dut_to_register14_data_in_x0',
'to_register14_dout' => 'from_register16_data_out',
'to_register14_en' => 'sysgen_dut_to_register14_en_x0',
'to_register15_ce' => 'sysgen_dut_to_register15_ce_x0',
'to_register15_clk' => 'sysgen_dut_to_register15_clk_x0',
'to_register15_clr' => 'sysgen_dut_to_register15_clr_x0',
'to_register15_data_in' => 'sysgen_dut_to_register15_data_in_x0',
'to_register15_dout' => 'from_register15_data_out',
'to_register15_en' => 'sysgen_dut_to_register15_en_x0',
'to_register16_ce' => 'sysgen_dut_to_register16_ce_x0',
'to_register16_clk' => 'sysgen_dut_to_register16_clk_x0',
'to_register16_clr' => 'sysgen_dut_to_register16_clr_x0',
'to_register16_data_in' => 'sysgen_dut_to_register16_data_in_x0',
'to_register16_dout' => 'from_register18_data_out',
'to_register16_en' => 'sysgen_dut_to_register16_en_x0',
'to_register17_ce' => 'sysgen_dut_to_register17_ce_x0',
'to_register17_clk' => 'sysgen_dut_to_register17_clk_x0',
'to_register17_clr' => 'sysgen_dut_to_register17_clr_x0',
'to_register17_data_in' => 'sysgen_dut_to_register17_data_in_x0',
'to_register17_dout' => 'from_register17_data_out',
'to_register17_en' => 'sysgen_dut_to_register17_en_x0',
'to_register18_ce' => 'sysgen_dut_to_register18_ce_x0',
'to_register18_clk' => 'sysgen_dut_to_register18_clk_x0',
'to_register18_clr' => 'sysgen_dut_to_register18_clr_x0',
'to_register18_data_in' => 'sysgen_dut_to_register18_data_in_x0',
'to_register18_dout' => 'from_register20_data_out',
'to_register18_en' => 'sysgen_dut_to_register18_en_x0',
'to_register19_ce' => 'sysgen_dut_to_register19_ce_x0',
'to_register19_clk' => 'sysgen_dut_to_register19_clk_x0',
'to_register19_clr' => 'sysgen_dut_to_register19_clr_x0',
'to_register19_data_in' => 'sysgen_dut_to_register19_data_in_x0',
'to_register19_dout' => 'from_register19_data_out',
'to_register19_en' => 'sysgen_dut_to_register19_en_x0',
'to_register1_ce' => 'sysgen_dut_to_register1_ce_x0',
'to_register1_clk' => 'sysgen_dut_to_register1_clk_x0',
'to_register1_clr' => 'sysgen_dut_to_register1_clr_x0',
'to_register1_data_in' => 'sysgen_dut_to_register1_data_in_x0',
'to_register1_dout' => 'from_register1_data_out',
'to_register1_en' => 'sysgen_dut_to_register1_en_x0',
'to_register20_ce' => 'sysgen_dut_to_register20_ce_x0',
'to_register20_clk' => 'sysgen_dut_to_register20_clk_x0',
'to_register20_clr' => 'sysgen_dut_to_register20_clr_x0',
'to_register20_data_in' => 'sysgen_dut_to_register20_data_in_x0',
'to_register20_dout' => 'from_register22_data_out',
'to_register20_en' => 'sysgen_dut_to_register20_en_x0',
'to_register21_ce' => 'sysgen_dut_to_register21_ce_x0',
'to_register21_clk' => 'sysgen_dut_to_register21_clk_x0',
'to_register21_clr' => 'sysgen_dut_to_register21_clr_x0',
'to_register21_data_in' => 'sysgen_dut_to_register21_data_in_x0',
'to_register21_dout' => 'from_register21_data_out',
'to_register21_en' => 'sysgen_dut_to_register21_en_x0',
'to_register22_ce' => 'sysgen_dut_to_register22_ce_x0',
'to_register22_clk' => 'sysgen_dut_to_register22_clk_x0',
'to_register22_clr' => 'sysgen_dut_to_register22_clr_x0',
'to_register22_data_in' => 'sysgen_dut_to_register22_data_in_x0',
'to_register22_dout' => 'from_register24_data_out',
'to_register22_en' => 'sysgen_dut_to_register22_en_x0',
'to_register23_ce' => 'sysgen_dut_to_register23_ce_x0',
'to_register23_clk' => 'sysgen_dut_to_register23_clk_x0',
'to_register23_clr' => 'sysgen_dut_to_register23_clr_x0',
'to_register23_data_in' => 'sysgen_dut_to_register23_data_in_x0',
'to_register23_dout' => 'from_register23_data_out',
'to_register23_en' => 'sysgen_dut_to_register23_en_x0',
'to_register24_ce' => 'sysgen_dut_to_register24_ce_x0',
'to_register24_clk' => 'sysgen_dut_to_register24_clk_x0',
'to_register24_clr' => 'sysgen_dut_to_register24_clr_x0',
'to_register24_data_in' => 'sysgen_dut_to_register24_data_in_x0',
'to_register24_dout' => 'from_register26_data_out',
'to_register24_en' => 'sysgen_dut_to_register24_en_x0',
'to_register25_ce' => 'sysgen_dut_to_register25_ce_x0',
'to_register25_clk' => 'sysgen_dut_to_register25_clk_x0',
'to_register25_clr' => 'sysgen_dut_to_register25_clr_x0',
'to_register25_data_in' => 'sysgen_dut_to_register25_data_in_x0',
'to_register25_dout' => 'from_register25_data_out',
'to_register25_en' => 'sysgen_dut_to_register25_en_x0',
'to_register26_ce' => 'sysgen_dut_to_register26_ce_x0',
'to_register26_clk' => 'sysgen_dut_to_register26_clk_x0',
'to_register26_clr' => 'sysgen_dut_to_register26_clr_x0',
'to_register26_data_in' => 'sysgen_dut_to_register26_data_in_x0',
'to_register26_dout' => 'from_register28_data_out',
'to_register26_en' => 'sysgen_dut_to_register26_en_x0',
'to_register27_ce' => 'sysgen_dut_to_register27_ce_x0',
'to_register27_clk' => 'sysgen_dut_to_register27_clk_x0',
'to_register27_clr' => 'sysgen_dut_to_register27_clr_x0',
'to_register27_data_in' => 'sysgen_dut_to_register27_data_in_x0',
'to_register27_dout' => 'from_register27_data_out',
'to_register27_en' => 'sysgen_dut_to_register27_en_x0',
'to_register2_ce' => 'sysgen_dut_to_register2_ce_x0',
'to_register2_clk' => 'sysgen_dut_to_register2_clk_x0',
'to_register2_clr' => 'sysgen_dut_to_register2_clr_x0',
'to_register2_data_in' => 'sysgen_dut_to_register2_data_in_x0',
'to_register2_dout' => 'from_register5_data_out',
'to_register2_en' => 'sysgen_dut_to_register2_en_x0',
'to_register3_ce' => 'sysgen_dut_to_register3_ce_x0',
'to_register3_clk' => 'sysgen_dut_to_register3_clk_x0',
'to_register3_clr' => 'sysgen_dut_to_register3_clr_x0',
'to_register3_data_in' => 'sysgen_dut_to_register3_data_in_x0',
'to_register3_dout' => 'from_register7_data_out',
'to_register3_en' => 'sysgen_dut_to_register3_en_x0',
'to_register4_ce' => 'sysgen_dut_to_register4_ce_x0',
'to_register4_clk' => 'sysgen_dut_to_register4_clk_x0',
'to_register4_clr' => 'sysgen_dut_to_register4_clr_x0',
'to_register4_data_in' => 'sysgen_dut_to_register4_data_in_x0',
'to_register4_dout' => 'from_register2_data_out',
'to_register4_en' => 'sysgen_dut_to_register4_en_x0',
'to_register5_ce' => 'sysgen_dut_to_register5_ce_x0',
'to_register5_clk' => 'sysgen_dut_to_register5_clk_x0',
'to_register5_clr' => 'sysgen_dut_to_register5_clr_x0',
'to_register5_data_in' => 'sysgen_dut_to_register5_data_in_x0',
'to_register5_dout' => 'from_register6_data_out',
'to_register5_en' => 'sysgen_dut_to_register5_en_x0',
'to_register6_ce' => 'sysgen_dut_to_register6_ce_x0',
'to_register6_clk' => 'sysgen_dut_to_register6_clk_x0',
'to_register6_clr' => 'sysgen_dut_to_register6_clr_x0',
'to_register6_data_in' => 'sysgen_dut_to_register6_data_in_x0',
'to_register6_dout' => 'from_register8_data_out',
'to_register6_en' => 'sysgen_dut_to_register6_en_x0',
'to_register7_ce' => 'sysgen_dut_to_register7_ce_x0',
'to_register7_clk' => 'sysgen_dut_to_register7_clk_x0',
'to_register7_clr' => 'sysgen_dut_to_register7_clr_x0',
'to_register7_data_in' => 'sysgen_dut_to_register7_data_in_x0',
'to_register7_dout' => 'from_register4_data_out',
'to_register7_en' => 'sysgen_dut_to_register7_en_x0',
'to_register8_ce' => 'sysgen_dut_to_register8_ce_x0',
'to_register8_clk' => 'sysgen_dut_to_register8_clk_x0',
'to_register8_clr' => 'sysgen_dut_to_register8_clr_x0',
'to_register8_data_in' => 'sysgen_dut_to_register8_data_in_x0',
'to_register8_dout' => 'from_register10_data_out',
'to_register8_en' => 'sysgen_dut_to_register8_en_x0',
'to_register9_ce' => 'sysgen_dut_to_register9_ce_x0',
'to_register9_clk' => 'sysgen_dut_to_register9_clk_x0',
'to_register9_clr' => 'sysgen_dut_to_register9_clr_x0',
'to_register9_data_in' => 'sysgen_dut_to_register9_data_in_x0',
'to_register9_dout' => 'from_register11_data_out',
'to_register9_en' => 'sysgen_dut_to_register9_en_x0',
'to_register_ce' => 'sysgen_dut_to_register_ce',
'to_register_clk' => 'sysgen_dut_to_register_clk',
'to_register_clr' => 'sysgen_dut_to_register_clr',
'to_register_data_in' => 'sysgen_dut_to_register_data_in',
'to_register_dout' => 'from_register3_data_out',
'to_register_en' => 'sysgen_dut_to_register_en',
'user_int_1o' => 'x_x83',
'user_int_2o' => 'x_x84',
'user_int_3o' => 'x_x85',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'hdlArchAttributes' => [
],
'hdlCompAttributes' => [
[
'syn_black_box',
'boolean',
'true',
],
[
'box_type',
'string',
'"black_box"',
],
],
'hdlEntityAttributes' => [
],
'isClkWrapper' => 1,
'needsComponentDeclaration' => 1,
},
'connections' => {
'bram_rd_addr' => 'bram_rd_addr_net',
'bram_rd_dout' => 'bram_rd_dout_net',
'bram_wr_addr' => 'bram_wr_addr_net',
'bram_wr_din' => 'bram_wr_din_net',
'bram_wr_en' => 'bram_wr_en_net',
'clk' => 'clkNet',
'fifo_rd_count' => 'fifo_rd_count_net',
'fifo_rd_dout' => 'fifo_rd_dout_net',
'fifo_rd_empty' => 'fifo_rd_empty_net',
'fifo_rd_en' => 'fifo_rd_en_net',
'fifo_rd_pempty' => 'fifo_rd_pempty_net',
'fifo_rd_valid' => 'fifo_rd_valid_net',
'fifo_wr_count' => 'fifo_wr_count_net',
'fifo_wr_din' => 'fifo_wr_din_net',
'fifo_wr_en' => 'fifo_wr_en_net',
'fifo_wr_full' => 'fifo_wr_full_net',
'fifo_wr_pfull' => 'fifo_wr_pfull_net',
'from_register10_data_out' => 'data_out_net',
'from_register11_data_out' => 'data_out_x0_net',
'from_register12_data_out' => 'data_out_x1_net',
'from_register13_data_out' => 'data_out_x2_net',
'from_register14_data_out' => 'data_out_x3_net',
'from_register15_data_out' => 'from_register15_data_out_net',
'from_register16_data_out' => 'from_register16_data_out_net',
'from_register17_data_out' => 'data_out_x6_net',
'from_register18_data_out' => 'data_out_x7_net',
'from_register19_data_out' => 'from_register19_data_out_net',
'from_register1_data_out' => 'from_register1_data_out_net',
'from_register20_data_out' => 'data_out_x8_net',
'from_register21_data_out' => 'data_out_x9_net',
'from_register22_data_out' => 'data_out_x10_net',
'from_register23_data_out' => 'data_out_x11_net',
'from_register24_data_out' => 'data_out_x12_net',
'from_register25_data_out' => 'data_out_x13_net',
'from_register26_data_out' => 'data_out_x14_net',
'from_register27_data_out' => 'data_out_x15_net',
'from_register28_data_out' => 'data_out_x16_net',
'from_register29_data_out' => 'data_out_x17_net',
'from_register2_data_out' => 'from_register2_data_out_net',
'from_register30_data_out' => 'data_out_x19_net',
'from_register31_data_out' => 'data_out_x20_net',
'from_register32_data_out' => 'data_out_x21_net',
'from_register33_data_out' => 'data_out_x22_net',
'from_register3_data_out' => 'data_out_x18_net',
'from_register4_data_out' => 'data_out_x23_net',
'from_register5_data_out' => 'data_out_x24_net',
'from_register6_data_out' => 'data_out_x25_net',
'from_register7_data_out' => 'data_out_x26_net',
'from_register8_data_out' => 'data_out_x27_net',
'from_register9_data_out' => 'data_out_x28_net',
'from_register_data_out' => 'from_register_data_out_net',
'rst_i' => 'rst_i_net',
'rst_o' => 'rst_o_net',
'to_register10_ce' => 'ce_1_sg_x0',
'to_register10_clk' => 'clk_1_sg_x0',
'to_register10_clr' => [
'constant',
'\'0\'',
],
'to_register10_data_in' => 'data_in_x1_net',
'to_register10_dout' => 'to_register10_dout_net',
'to_register10_en' => 'constant6_op_net_x2',
'to_register11_ce' => 'ce_1_sg_x0',
'to_register11_clk' => 'clk_1_sg_x0',
'to_register11_clr' => [
'constant',
'\'0\'',
],
'to_register11_data_in' => 'data_in_x2_net',
'to_register11_dout' => 'to_register11_dout_net',
'to_register11_en' => 'constant6_op_net_x3',
'to_register12_ce' => 'ce_1_sg_x0',
'to_register12_clk' => 'clk_1_sg_x0',
'to_register12_clr' => [
'constant',
'\'0\'',
],
'to_register12_data_in' => 'data_in_x3_net',
'to_register12_dout' => 'to_register12_dout_net',
'to_register12_en' => 'constant6_op_net_x4',
'to_register13_ce' => 'ce_1_sg_x0',
'to_register13_clk' => 'clk_1_sg_x0',
'to_register13_clr' => [
'constant',
'\'0\'',
],
'to_register13_data_in' => 'data_in_x4_net',
'to_register13_dout' => 'to_register13_dout_net',
'to_register13_en' => 'constant6_op_net_x5',
'to_register14_ce' => 'ce_1_sg_x0',
'to_register14_clk' => 'clk_1_sg_x0',
'to_register14_clr' => [
'constant',
'\'0\'',
],
'to_register14_data_in' => 'data_in_x5_net',
'to_register14_dout' => 'to_register14_dout_net',
'to_register14_en' => 'constant6_op_net_x6',
'to_register15_ce' => 'ce_1_sg_x0',
'to_register15_clk' => 'clk_1_sg_x0',
'to_register15_clr' => [
'constant',
'\'0\'',
],
'to_register15_data_in' => 'data_in_x6_net',
'to_register15_dout' => 'to_register15_dout_net',
'to_register15_en' => 'constant6_op_net_x7',
'to_register16_ce' => 'ce_1_sg_x0',
'to_register16_clk' => 'clk_1_sg_x0',
'to_register16_clr' => [
'constant',
'\'0\'',
],
'to_register16_data_in' => 'data_in_x7_net',
'to_register16_dout' => 'to_register16_dout_net',
'to_register16_en' => 'constant6_op_net_x8',
'to_register17_ce' => 'ce_1_sg_x0',
'to_register17_clk' => 'clk_1_sg_x0',
'to_register17_clr' => [
'constant',
'\'0\'',
],
'to_register17_data_in' => 'data_in_x8_net',
'to_register17_dout' => 'to_register17_dout_net',
'to_register17_en' => 'constant6_op_net_x9',
'to_register18_ce' => 'ce_1_sg_x0',
'to_register18_clk' => 'clk_1_sg_x0',
'to_register18_clr' => [
'constant',
'\'0\'',
],
'to_register18_data_in' => 'data_in_x9_net',
'to_register18_dout' => 'to_register18_dout_net',
'to_register18_en' => 'constant6_op_net_x10',
'to_register19_ce' => 'ce_1_sg_x0',
'to_register19_clk' => 'clk_1_sg_x0',
'to_register19_clr' => [
'constant',
'\'0\'',
],
'to_register19_data_in' => 'data_in_x10_net',
'to_register19_dout' => 'to_register19_dout_net',
'to_register19_en' => 'constant6_op_net_x11',
'to_register1_ce' => 'ce_1_sg_x0',
'to_register1_clk' => 'clk_1_sg_x0',
'to_register1_clr' => [
'constant',
'\'0\'',
],
'to_register1_data_in' => 'data_in_x0_net',
'to_register1_dout' => 'to_register1_dout_net',
'to_register1_en' => 'constant6_op_net_x1',
'to_register20_ce' => 'ce_1_sg_x0',
'to_register20_clk' => 'clk_1_sg_x0',
'to_register20_clr' => [
'constant',
'\'0\'',
],
'to_register20_data_in' => 'data_in_x12_net',
'to_register20_dout' => 'to_register20_dout_net',
'to_register20_en' => 'constant6_op_net_x13',
'to_register21_ce' => 'ce_1_sg_x0',
'to_register21_clk' => 'clk_1_sg_x0',
'to_register21_clr' => [
'constant',
'\'0\'',
],
'to_register21_data_in' => 'data_in_x13_net',
'to_register21_dout' => 'to_register21_dout_net',
'to_register21_en' => 'constant6_op_net_x14',
'to_register22_ce' => 'ce_1_sg_x0',
'to_register22_clk' => 'clk_1_sg_x0',
'to_register22_clr' => [
'constant',
'\'0\'',
],
'to_register22_data_in' => 'data_in_x14_net',
'to_register22_dout' => 'to_register22_dout_net',
'to_register22_en' => 'constant6_op_net_x15',
'to_register23_ce' => 'ce_1_sg_x0',
'to_register23_clk' => 'clk_1_sg_x0',
'to_register23_clr' => [
'constant',
'\'0\'',
],
'to_register23_data_in' => 'data_in_x15_net',
'to_register23_dout' => 'to_register23_dout_net',
'to_register23_en' => 'constant6_op_net_x16',
'to_register24_ce' => 'ce_1_sg_x0',
'to_register24_clk' => 'clk_1_sg_x0',
'to_register24_clr' => [
'constant',
'\'0\'',
],
'to_register24_data_in' => 'data_in_x16_net',
'to_register24_dout' => 'to_register24_dout_net',
'to_register24_en' => 'constant6_op_net_x17',
'to_register25_ce' => 'ce_1_sg_x0',
'to_register25_clk' => 'clk_1_sg_x0',
'to_register25_clr' => [
'constant',
'\'0\'',
],
'to_register25_data_in' => 'data_in_x17_net',
'to_register25_dout' => 'to_register25_dout_net',
'to_register25_en' => 'constant6_op_net_x18',
'to_register26_ce' => 'ce_1_sg_x0',
'to_register26_clk' => 'clk_1_sg_x0',
'to_register26_clr' => [
'constant',
'\'0\'',
],
'to_register26_data_in' => 'data_in_x18_net',
'to_register26_dout' => 'to_register26_dout_net',
'to_register26_en' => 'constant6_op_net_x19',
'to_register27_ce' => 'ce_1_sg_x0',
'to_register27_clk' => 'clk_1_sg_x0',
'to_register27_clr' => [
'constant',
'\'0\'',
],
'to_register27_data_in' => 'data_in_x19_net',
'to_register27_dout' => 'to_register27_dout_net',
'to_register27_en' => 'constant6_op_net_x20',
'to_register2_ce' => 'ce_1_sg_x0',
'to_register2_clk' => 'clk_1_sg_x0',
'to_register2_clr' => [
'constant',
'\'0\'',
],
'to_register2_data_in' => 'data_in_x11_net',
'to_register2_dout' => 'to_register2_dout_net',
'to_register2_en' => 'constant6_op_net_x12',
'to_register3_ce' => 'ce_1_sg_x0',
'to_register3_clk' => 'clk_1_sg_x0',
'to_register3_clr' => [
'constant',
'\'0\'',
],
'to_register3_data_in' => 'data_in_x20_net',
'to_register3_dout' => 'to_register3_dout_net',
'to_register3_en' => 'constant6_op_net_x21',
'to_register4_ce' => 'ce_1_sg_x0',
'to_register4_clk' => 'clk_1_sg_x0',
'to_register4_clr' => [
'constant',
'\'0\'',
],
'to_register4_data_in' => 'data_in_x21_net',
'to_register4_dout' => 'to_register4_dout_net',
'to_register4_en' => 'constant6_op_net_x22',
'to_register5_ce' => 'ce_1_sg_x0',
'to_register5_clk' => 'clk_1_sg_x0',
'to_register5_clr' => [
'constant',
'\'0\'',
],
'to_register5_data_in' => 'data_in_x22_net',
'to_register5_dout' => 'to_register5_dout_net',
'to_register5_en' => 'constant6_op_net_x23',
'to_register6_ce' => 'ce_1_sg_x0',
'to_register6_clk' => 'clk_1_sg_x0',
'to_register6_clr' => [
'constant',
'\'0\'',
],
'to_register6_data_in' => 'data_in_x23_net',
'to_register6_dout' => 'to_register6_dout_net',
'to_register6_en' => 'constant6_op_net_x24',
'to_register7_ce' => 'ce_1_sg_x0',
'to_register7_clk' => 'clk_1_sg_x0',
'to_register7_clr' => [
'constant',
'\'0\'',
],
'to_register7_data_in' => 'data_in_x24_net',
'to_register7_dout' => 'to_register7_dout_net',
'to_register7_en' => 'constant6_op_net_x25',
'to_register8_ce' => 'ce_1_sg_x0',
'to_register8_clk' => 'clk_1_sg_x0',
'to_register8_clr' => [
'constant',
'\'0\'',
],
'to_register8_data_in' => 'data_in_x25_net',
'to_register8_dout' => 'to_register8_dout_net',
'to_register8_en' => 'constant6_op_net_x26',
'to_register9_ce' => 'ce_1_sg_x0',
'to_register9_clk' => 'clk_1_sg_x0',
'to_register9_clr' => [
'constant',
'\'0\'',
],
'to_register9_data_in' => 'data_in_x26_net',
'to_register9_dout' => 'to_register9_dout_net',
'to_register9_en' => 'constant6_op_net_x27',
'to_register_ce' => 'ce_1_sg_x0',
'to_register_clk' => 'clk_1_sg_x0',
'to_register_clr' => [
'constant',
'\'0\'',
],
'to_register_data_in' => 'data_in_net',
'to_register_dout' => 'to_register_dout_net',
'to_register_en' => 'constant6_op_net_x0',
'user_int_1o' => 'user_int_1o_net',
'user_int_2o' => 'user_int_2o_net',
'user_int_3o' => 'user_int_3o_net',
},
'entityName' => 'user_logic_cw',
'nets' => {
'bram_rd_addr_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(11 downto 0)',
'width' => 12,
},
'bram_rd_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(63 downto 0)',
'width' => 64,
},
'bram_wr_addr_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(11 downto 0)',
'width' => 12,
},
'bram_wr_din_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(63 downto 0)',
'width' => 64,
},
'bram_wr_en_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(7 downto 0)',
'width' => 8,
},
'ce_1_sg_x0' => {
'attributes' => {
'hdlNetAttributes' => [
[
'MAX_FANOUT',
'string',
'"REDUCE"',
],
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'clkNet' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'clk_1_sg_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x1' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x10' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x11' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x12' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x13' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x14' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x15' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x16' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x17' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x18' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x19' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x2' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x20' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x21' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x22' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x23' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x24' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x25' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x26' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x27' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x3' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x4' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x5' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x6' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x7' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x8' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant6_op_net_x9' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x0_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x10_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x11_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x12_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x13_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x14_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x15_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x16_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x17_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x18_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x19_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x1_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x20_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x21_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x22_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x23_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x24_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x25_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x26_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x2_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x3_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x4_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x5_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x6_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x7_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x8_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x9_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_out_x0_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_out_x10_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_out_x11_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_out_x12_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_out_x13_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_out_x14_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_out_x15_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_out_x16_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_out_x17_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_out_x18_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_out_x19_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_out_x1_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_out_x20_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_out_x21_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_out_x22_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_out_x23_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'data_out_x24_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_out_x25_net' => {
'attributes' => {
'hdlNetAttributes' => [
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
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'direction' => 'out',
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'fifo_wr_full' => {
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'fifo_wr_pfull' => {
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'direction' => 'in',
'hdlType' => 'std_logic',
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},
'from_register10_data_out' => {
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},
'from_register11_data_out' => {
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'from_register13_data_out' => {
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'from_register20_data_out' => {
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'from_register21_data_out' => {
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},
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'to_register5_dout' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register5/dout',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'to_register5_en' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 1,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register5/en',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'to_register6_ce' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isCe' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register6_clk' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClk' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register6_clr' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClr' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
'valid_bit_used' => 0,
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register6_data_in' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register6/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register6_dout' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register6/dout',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register6_en' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 1,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register6/en',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'to_register7_ce' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isCe' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register7_clk' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClk' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register7_clr' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClr' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
'valid_bit_used' => 0,
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register7_data_in' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register7/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'to_register7_dout' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register7/dout',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'to_register7_en' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 1,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register7/en',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'to_register8_ce' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isCe' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register8_clk' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClk' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register8_clr' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClr' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
'valid_bit_used' => 0,
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register8_data_in' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register8/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register8_dout' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register8/dout',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register8_en' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 1,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register8/en',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'to_register9_ce' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isCe' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register9_clk' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClk' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register9_clr' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClr' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
'valid_bit_used' => 0,
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register9_data_in' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register9_dout' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/dout',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register9_en' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 1,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/en',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'to_register_ce' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isCe' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register_clk' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClk' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register_clr' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClr' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
'valid_bit_used' => 0,
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register_data_in' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register_dout' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/dout',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register_en' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 1,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/en',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'user_int_1o' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_user_int_1o.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o/user_int_1o',
'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'user_int_2o' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_user_int_2o.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o/user_int_2o',
'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'user_int_3o' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_user_int_3o.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o/user_int_3o',
'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
'subblocks' => {
'default_clock_driver_x0' => {
'connections' => {
'ce_1' => 'ce_1_sg_x0',
'clk_1' => 'clk_1_sg_x0',
'sysce' => [
'constant',
'\'1\'',
],
'sysce_clr' => [
'constant',
'\'0\'',
],
'sysclk' => 'clkNet',
},
'entity' => {
'attributes' => {
'domain' => 'default',
'hdlArchAttributes' => [
[
'syn_noprune',
'boolean',
'true',
],
[
'optimize_primitives',
'boolean',
'false',
],
[
'dont_touch',
'boolean',
'true',
],
],
'hdlEntityAttributes' => [
],
'isClkDriver' => 1,
},
'entityName' => 'default_clock_driver',
'ports' => {
'ce_1' => {
'attributes' => {
'domain' => 'default',
'group' => 1,
'isCe' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk_1' => {
'attributes' => {
'domain' => 'default',
'group' => 1,
'isClk' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'sysce' => {
'attributes' => {
'group' => 6,
'isCe' => 1,
'period' => 1,
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'sysce_clr' => {
'attributes' => {
'group' => 6,
'isClr' => 1,
'period' => 1,
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'sysclk' => {
'attributes' => {
'group' => 6,
'isClk' => 1,
'period' => 1,
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'default_clock_driver',
},
'persistentdff_inst' => {
'connections' => {
'clk' => 'clkNet',
'd' => 'persistentdff_inst_q',
'q' => 'persistentdff_inst_q',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'hdlCompAttributes' => [
[
'syn_black_box',
'boolean',
'true',
],
[
'box_type',
'string',
'"black_box"',
],
],
'is_persistent_dff' => 1,
'needsComponentDeclaration' => 1,
},
'entityName' => 'xlpersistentdff',
'ports' => {
'clk' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'd' => {
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'q' => {
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'xlpersistentdff',
},
'user_logic_x0' => {
'connections' => {
'bram_rd_addr' => 'bram_rd_addr_net',
'bram_rd_dout' => 'bram_rd_dout_net',
'bram_wr_addr' => 'bram_wr_addr_net',
'bram_wr_din' => 'bram_wr_din_net',
'bram_wr_en' => 'bram_wr_en_net',
'ce_1' => 'ce_1_sg_x0',
'clk_1' => 'clk_1_sg_x0',
'data_in' => 'data_in_net',
'data_in_x0' => 'data_in_x0_net',
'data_in_x1' => 'data_in_x1_net',
'data_in_x10' => 'data_in_x10_net',
'data_in_x11' => 'data_in_x11_net',
'data_in_x12' => 'data_in_x12_net',
'data_in_x13' => 'data_in_x13_net',
'data_in_x14' => 'data_in_x14_net',
'data_in_x15' => 'data_in_x15_net',
'data_in_x16' => 'data_in_x16_net',
'data_in_x17' => 'data_in_x17_net',
'data_in_x18' => 'data_in_x18_net',
'data_in_x19' => 'data_in_x19_net',
'data_in_x2' => 'data_in_x2_net',
'data_in_x20' => 'data_in_x20_net',
'data_in_x21' => 'data_in_x21_net',
'data_in_x22' => 'data_in_x22_net',
'data_in_x23' => 'data_in_x23_net',
'data_in_x24' => 'data_in_x24_net',
'data_in_x25' => 'data_in_x25_net',
'data_in_x26' => 'data_in_x26_net',
'data_in_x3' => 'data_in_x3_net',
'data_in_x4' => 'data_in_x4_net',
'data_in_x5' => 'data_in_x5_net',
'data_in_x6' => 'data_in_x6_net',
'data_in_x7' => 'data_in_x7_net',
'data_in_x8' => 'data_in_x8_net',
'data_in_x9' => 'data_in_x9_net',
'data_out' => 'data_out_net',
'data_out_x0' => 'data_out_x0_net',
'data_out_x1' => 'data_out_x1_net',
'data_out_x10' => 'data_out_x10_net',
'data_out_x11' => 'data_out_x11_net',
'data_out_x12' => 'data_out_x12_net',
'data_out_x13' => 'data_out_x13_net',
'data_out_x14' => 'data_out_x14_net',
'data_out_x15' => 'data_out_x15_net',
'data_out_x16' => 'data_out_x16_net',
'data_out_x17' => 'data_out_x17_net',
'data_out_x18' => 'data_out_x18_net',
'data_out_x19' => 'data_out_x19_net',
'data_out_x2' => 'data_out_x2_net',
'data_out_x20' => 'data_out_x20_net',
'data_out_x21' => 'data_out_x21_net',
'data_out_x22' => 'data_out_x22_net',
'data_out_x23' => 'data_out_x23_net',
'data_out_x24' => 'data_out_x24_net',
'data_out_x25' => 'data_out_x25_net',
'data_out_x26' => 'data_out_x26_net',
'data_out_x27' => 'data_out_x27_net',
'data_out_x28' => 'data_out_x28_net',
'data_out_x3' => 'data_out_x3_net',
'data_out_x6' => 'data_out_x6_net',
'data_out_x7' => 'data_out_x7_net',
'data_out_x8' => 'data_out_x8_net',
'data_out_x9' => 'data_out_x9_net',
'en' => 'constant6_op_net_x0',
'en_x0' => 'constant6_op_net_x1',
'en_x1' => 'constant6_op_net_x2',
'en_x10' => 'constant6_op_net_x11',
'en_x11' => 'constant6_op_net_x12',
'en_x12' => 'constant6_op_net_x13',
'en_x13' => 'constant6_op_net_x14',
'en_x14' => 'constant6_op_net_x15',
'en_x15' => 'constant6_op_net_x16',
'en_x16' => 'constant6_op_net_x17',
'en_x17' => 'constant6_op_net_x18',
'en_x18' => 'constant6_op_net_x19',
'en_x19' => 'constant6_op_net_x20',
'en_x2' => 'constant6_op_net_x3',
'en_x20' => 'constant6_op_net_x21',
'en_x21' => 'constant6_op_net_x22',
'en_x22' => 'constant6_op_net_x23',
'en_x23' => 'constant6_op_net_x24',
'en_x24' => 'constant6_op_net_x25',
'en_x25' => 'constant6_op_net_x26',
'en_x26' => 'constant6_op_net_x27',
'en_x3' => 'constant6_op_net_x4',
'en_x4' => 'constant6_op_net_x5',
'en_x5' => 'constant6_op_net_x6',
'en_x6' => 'constant6_op_net_x7',
'en_x7' => 'constant6_op_net_x8',
'en_x8' => 'constant6_op_net_x9',
'en_x9' => 'constant6_op_net_x10',
'fifo_rd_count' => 'fifo_rd_count_net',
'fifo_rd_dout' => 'fifo_rd_dout_net',
'fifo_rd_empty' => 'fifo_rd_empty_net',
'fifo_rd_en' => 'fifo_rd_en_net',
'fifo_rd_pempty' => 'fifo_rd_pempty_net',
'fifo_rd_valid' => 'fifo_rd_valid_net',
'fifo_wr_count' => 'fifo_wr_count_net',
'fifo_wr_din' => 'fifo_wr_din_net',
'fifo_wr_en' => 'fifo_wr_en_net',
'fifo_wr_full' => 'fifo_wr_full_net',
'fifo_wr_pfull' => 'fifo_wr_pfull_net',
'rst_i' => 'rst_i_net',
'rst_o' => 'rst_o_net',
'user_int_1o' => 'user_int_1o_net',
'user_int_2o' => 'user_int_2o_net',
'user_int_3o' => 'user_int_3o_net',
},
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'rst_o' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_rst_o.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 19,
'simulinkName' => 'USER_LOGIC/rst_o',
'source_block' => 'USER_LOGIC',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'user_int_1o' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_user_int_1o.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 20,
'simulinkName' => 'USER_LOGIC/user_int_1o',
'source_block' => 'USER_LOGIC',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'user_int_2o' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_user_int_2o.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 30,
'simulinkName' => 'USER_LOGIC/user_int_2o',
'source_block' => 'USER_LOGIC',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'user_int_3o' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_user_logic_user_int_3o.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 25,
'simulinkName' => 'USER_LOGIC/user_int_3o',
'source_block' => 'USER_LOGIC',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'user_logic',
},
},
},
'entityName' => 'user_logic_cw',
},
},
},
'entityName' => 'PCIe_UserLogic_00',
},
},
}