URL
https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk
Subversion Repositories pcie_sg_dma
[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [MyUserLogic/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [sysgen/] [synopsis_com.xilinx.sysgen.netlister.CfWriter] - Rev 11
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{
'attributes' => {
'HDLCodeGenStatus' => 0,
'HDL_PATH' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen',
'Impl_file' => 'ISE Defaults',
'Impl_file_sgadvanced' => '',
'Synth_file' => 'XST Defaults',
'Synth_file_sgadvanced' => '',
'TEMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
'TMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
'Temp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
'Tmp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
'base_system_period_hardware' => 5,
'base_system_period_simulink' => '8e-009',
'block_icon_display' => 'Default',
'block_type' => 'sysgen',
'block_version' => '',
'ce_clr' => 0,
'clkWrapper' => 'inout_logic_cw',
'clkWrapperFile' => 'inout_logic_cw.vhd',
'clock_loc' => '',
'clock_wrapper' => 'Clock Enables',
'clock_wrapper_sgadvanced' => '',
'compilation' => 'NGC Netlist',
'compilation_lut' => {
'keys' => [
'HDL Netlist',
'Bitstream',
'NGC Netlist',
],
'values' => [
'target1',
'target2',
'target3',
],
},
'compilation_target' => 'NGC Netlist',
'core_generation' => 1,
'core_generation_sgadvanced' => '',
'core_is_deployed' => 0,
'coregen_core_generation_tmpdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root/cg_wk/c00613f6911dfdaa6',
'coregen_part_family' => 'virtex6',
'createTestbench' => 0,
'create_interface_document' => 'off',
'dbl_ovrd' => -1,
'dbl_ovrd_sgadvanced' => '',
'dcm_info' => {},
'dcm_input_clock_period' => 5,
'deprecated_control' => 'off',
'deprecated_control_sgadvanced' => '',
'design' => 'inout_logic',
'designFile' => 'inout_logic.vhd',
'design_full_path' => 'C:\\Temp\\Xilinx PCI Express\\pcie-v6-ml605_ISE12_OpenCores\\MySysGen\\PCIe_UserLogic_00.mdl',
'device' => 'xc6vlx240t-3ff784',
'device_speed' => -3,
'directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
'dsp_cache_root_path' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
'entityNamingInstrs' => {
'nameMap' => undef,
'namesAlreadyUsed' => {
'default_clock_driver' => 1,
'inout_logic_cw' => 1,
},
},
'eval_field' => 0,
'fileAttributes' => {
'nonleaf_results.vhd' => { 'producer' => 'nonleafNetlister', },
},
'files' => [
'xlpersistentdff.ngc',
'synopsis',
'inout_logic.vhd',
'xlpersistentdff.ngc',
'inout_logic_cw.vhd',
'inout_logic_cw.ucf',
'inout_logic_cw.xcf',
'inout_logic_cw.sdc',
],
'fxdptinstalled' => 1,
'generateUsing71FrontEnd' => 1,
'generating_island_subsystem_handle' => 4.0009765625,
'generating_subsystem_handle' => 4.0009765625,
'generation_directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
'has_advanced_control' => 0,
'hdlDir' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen/hdl',
'hdlKind' => 'vhdl',
'hdl_path' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen',
'impl_file' => 'ISE Defaults*',
'incr_netlist' => 'off',
'incr_netlist_sgadvanced' => '',
'infoedit' => ' System Generator',
'isCombinatorial' => 1,
'isdeployed' => 0,
'ise_version' => '12.3i',
'master_sysgen_token_handle' => 5.0009765625,
'matlab' => 'C:/Programmi/MATLAB/R2010a',
'matlab_fixedpoint' => 1,
'mdlHandle' => 3.0009765625,
'mdlPath' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen/PCIe_UserLogic_00.mdl',
'modelDiagnostics' => [
{
'count' => 339,
'isMask' => 0,
'type' => 'PCIe_UserLogic_00 Total blocks',
},
{
'count' => 4,
'isMask' => 0,
'type' => 'DiscretePulseGenerator',
},
{
'count' => 327,
'isMask' => 0,
'type' => 'S-Function',
},
{
'count' => 4,
'isMask' => 0,
'type' => 'SubSystem',
},
{
'count' => 4,
'isMask' => 0,
'type' => 'Terminator',
},
{
'count' => 23,
'isMask' => 1,
'type' => 'Xilinx Constant Block Block',
},
{
'count' => 1,
'isMask' => 1,
'type' => 'Xilinx Counter Block',
},
{
'count' => 44,
'isMask' => 1,
'type' => 'Xilinx Gateway In Block',
},
{
'count' => 39,
'isMask' => 1,
'type' => 'Xilinx Gateway Out Block',
},
{
'count' => 2,
'isMask' => 1,
'type' => 'Xilinx Inverter Block',
},
{
'count' => 1,
'isMask' => 1,
'type' => 'Xilinx Logical Block Block',
},
{
'count' => 78,
'isMask' => 1,
'type' => 'Xilinx Register Block',
},
{
'count' => 62,
'isMask' => 1,
'type' => 'Xilinx Shared Memory Based From Register Block',
},
{
'count' => 62,
'isMask' => 1,
'type' => 'Xilinx Shared Memory Based To Register Block',
},
{
'count' => 1,
'isMask' => 1,
'type' => 'Xilinx Subsystem Generator Block',
},
{
'count' => 2,
'isMask' => 1,
'type' => 'Xilinx System Generator Block',
},
{
'count' => 14,
'isMask' => 1,
'type' => 'Xilinx Type Converter Block',
},
],
'model_globals_initialized' => 1,
'model_path' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySysGen/PCIe_UserLogic_00.mdl',
'myxilinx' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE',
'netlistingWrapupScript' => 'java:com.xilinx.sysgen.netlister.DefaultWrapupNetlister',
'ngc_config' => {
'include_cf' => 1,
'include_clockwrapper' => 1,
},
'ngc_files' => [ 'xlpersistentdff.ngc', ],
'num_sim_cycles' => 1250000000,
'package' => 'ff784',
'part' => 'xc6vlx240t',
'partFamily' => 'virtex6',
'port_data_types_enabled' => 1,
'postgeneration_fcn' => 'xlNGCPostGeneration',
'preserve_hierarchy' => 0,
'proj_type' => 'Project Navigator',
'proj_type_sgadvanced' => '',
'run_coregen' => 'off',
'run_coregen_sgadvanced' => '',
'sample_time_colors_enabled' => 1,
'sampletimecolors' => 1,
'sdcFile' => 'inout_logic_cw.sdc',
'settings_fcn' => 'xlngcsettings',
'sg_blockgui_xml' => '',
'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
'sg_list_contents' => '',
'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
fprintf(\'\',\'COMMENT: end icon graphics\');
fprintf(\'\',\'COMMENT: begin icon text\');
fprintf(\'\',\'COMMENT: end icon text\');',
'sg_version' => '',
'sggui_pos' => '-1,-1,-1,-1',
'simulation_island_subsystem_handle' => 4.0009765625,
'simulinkName' => 'parking_lot',
'simulink_accelerator_running' => 0,
'simulink_debugger_running' => 0,
'simulink_period' => '8e-009',
'speed' => -3,
'synth_file' => 'XST Defaults*',
'synthesisTool' => 'XST',
'synthesis_language' => 'vhdl',
'synthesis_tool' => 'XST',
'synthesis_tool_sgadvanced' => '',
'sysclk_period' => 5,
'sysgen' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
'sysgenRoot' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
'sysgenTokenSettings' => {
'Impl_file' => 'ISE Defaults',
'Impl_file_sgadvanced' => '',
'Synth_file' => 'XST Defaults',
'Synth_file_sgadvanced' => '',
'base_system_period_hardware' => 5,
'base_system_period_simulink' => '8e-009',
'block_icon_display' => 'Default',
'block_type' => 'sysgen',
'block_version' => '',
'ce_clr' => 0,
'clock_loc' => '',
'clock_wrapper' => 'Clock Enables',
'clock_wrapper_sgadvanced' => '',
'compilation' => 'NGC Netlist',
'compilation_lut' => {
'keys' => [
'HDL Netlist',
'Bitstream',
'NGC Netlist',
],
'values' => [
'target1',
'target2',
'target3',
],
},
'core_generation' => 1,
'core_generation_sgadvanced' => '',
'coregen_part_family' => 'virtex6',
'create_interface_document' => 'off',
'dbl_ovrd' => -1,
'dbl_ovrd_sgadvanced' => '',
'dcm_input_clock_period' => 5,
'deprecated_control' => 'off',
'deprecated_control_sgadvanced' => '',
'directory' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
'eval_field' => 0,
'has_advanced_control' => 0,
'impl_file' => 'ISE Defaults*',
'incr_netlist' => 'off',
'incr_netlist_sgadvanced' => '',
'infoedit' => ' System Generator',
'master_sysgen_token_handle' => 5.0009765625,
'ngc_config' => {
'include_cf' => 1,
'include_clockwrapper' => 1,
},
'package' => 'ff784',
'part' => 'xc6vlx240t',
'postgeneration_fcn' => 'xlNGCPostGeneration',
'preserve_hierarchy' => 0,
'proj_type' => 'Project Navigator',
'proj_type_sgadvanced' => '',
'run_coregen' => 'off',
'run_coregen_sgadvanced' => '',
'settings_fcn' => 'xlngcsettings',
'sg_blockgui_xml' => '',
'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
'sg_list_contents' => '',
'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
fprintf(\'\',\'COMMENT: end icon graphics\');
fprintf(\'\',\'COMMENT: begin icon text\');
fprintf(\'\',\'COMMENT: end icon text\');',
'sggui_pos' => '-1,-1,-1,-1',
'simulation_island_subsystem_handle' => 4.0009765625,
'simulink_period' => '8e-009',
'speed' => -3,
'synth_file' => 'XST Defaults*',
'synthesis_language' => 'vhdl',
'synthesis_tool' => 'XST',
'synthesis_tool_sgadvanced' => '',
'sysclk_period' => 5,
'testbench' => 0,
'testbench_sgadvanced' => '',
'trim_vbits' => 1,
'trim_vbits_sgadvanced' => '',
'xilinx_device' => 'xc6vlx240t-3ff784',
'xilinxfamily' => 'virtex6',
},
'sysgen_Root' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE/sysgen',
'systemClockPeriod' => 5,
'tempdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
'testbench' => 0,
'testbench_sgadvanced' => '',
'tmpDir' => 'C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MyUserLogic/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/sysgen',
'trim_vbits' => 1,
'trim_vbits_sgadvanced' => '',
'ucfFile' => 'inout_logic_cw.ucf',
'use_ce_syn_keep' => 1,
'use_strict_names' => 1,
'user_tips_enabled' => 0,
'usertemp' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
'using71Netlister' => 1,
'verilog_files' => [
'conv_pkg.v',
'synth_reg.v',
'synth_reg_w_init.v',
'convert_type.v',
],
'version' => '',
'vhdl_files' => [
'conv_pkg.vhd',
'synth_reg.vhd',
'synth_reg_w_init.vhd',
],
'vsimtime' => '6875000275.000000 ns',
'xcfFile' => 'inout_logic_cw.xcf',
'xilinx' => 'C:/Programmi/Xilinx/12.3/ISE_DS/ISE',
'xilinx_device' => 'xc6vlx240t-3ff784',
'xilinx_family' => 'virtex6',
'xilinx_package' => 'ff784',
'xilinx_part' => 'xc6vlx240t',
'xilinxdevice' => 'xc6vlx240t-3ff784',
'xilinxfamily' => 'virtex6',
'xilinxpart' => 'xc6vlx240t',
},
'entityName' => '',
'nets' => {
'.clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.debug_in_1i' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.debug_in_2i' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.debug_in_3i' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.debug_in_4i' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.dma_host2board_busy' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.dma_host2board_done' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.reg01_td' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.reg01_tv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.reg02_td' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.reg02_tv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.reg03_td' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.reg03_tv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.reg04_td' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.reg04_tv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.reg05_td' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.reg05_tv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.reg06_td' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.reg06_tv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.reg07_td' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.reg07_tv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.reg08_td' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.reg08_tv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.reg09_td' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.reg09_tv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.reg10_td' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.reg10_tv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.reg11_td' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.reg11_tv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.reg12_td' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.reg12_tv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.reg13_td' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.reg13_tv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'.reg14_td' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'.reg14_tv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register1.data_out' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register10.data_out' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register11.data_out' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register12.data_out' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register13.data_out' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register14.data_out' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register15.data_out' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register16.data_out' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register17.data_out' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register18.data_out' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register19.data_out' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register2.data_out' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register20.data_out' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register21.data_out' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register22.data_out' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register23.data_out' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register24.data_out' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register25.data_out' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register26.data_out' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register27.data_out' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register28.data_out' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register3.data_out' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register4.data_out' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register5.data_out' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register6.data_out' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register7.data_out' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register8.data_out' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register9.data_out' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.reg01_rd' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.reg01_rv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.reg02_rd' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.reg02_rv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.reg03_rd' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.reg03_rv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.reg04_rd' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.reg04_rv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.reg05_rd' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.reg05_rv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.reg06_rd' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.reg06_rv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.reg07_rd' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.reg07_rv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.reg08_rd' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.reg08_rv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.reg09_rd' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.reg09_rv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.reg10_rd' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.reg10_rv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.reg11_rd' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.reg11_rv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.reg12_rd' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.reg12_rv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.reg13_rd' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.reg13_rv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.reg14_rd' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.reg14_rv' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register10_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register10_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register10_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register10_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register10_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register11_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register11_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register11_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register11_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register11_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register12_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register12_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register12_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register12_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register12_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register13_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register13_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register13_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register13_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register13_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register14_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register14_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register14_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register14_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register14_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register15_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register15_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register15_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register15_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register15_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register16_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register16_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register16_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register16_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register16_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register17_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register17_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register17_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register17_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register17_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register18_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register18_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register18_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register18_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register18_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register19_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register19_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register19_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register19_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register19_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register1_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register1_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register1_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register1_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register1_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register20_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register20_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register20_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register20_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register20_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register21_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register21_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register21_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register21_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register21_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register22_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register22_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register22_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register22_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register22_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register23_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register23_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register23_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register23_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register23_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register24_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register24_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register24_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register24_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register24_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register25_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register25_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register25_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register25_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register25_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register26_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register26_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register26_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register26_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register26_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register27_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register27_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register27_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register27_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register27_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register28_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register28_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register28_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register28_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register28_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register29_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register29_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register29_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register29_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register29_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register2_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register2_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register2_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register2_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register2_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register30_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register30_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register30_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register30_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register30_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register31_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register31_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register31_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register31_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register31_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register32_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register32_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register32_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register32_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register32_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register33_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register33_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register33_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register33_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register33_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register34_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register34_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register34_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register34_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register34_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register3_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register3_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register3_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register3_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register3_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register4_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register4_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register4_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register4_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register4_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register5_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register5_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register5_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register5_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register5_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register6_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register6_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register6_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register6_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register6_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register7_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register7_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register7_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register7_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register7_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register8_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register8_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register8_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register8_data_in' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register8_en' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register9_ce' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register9_clk' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register9_clr' => {
'hdlType' => 'std_logic',
'width' => 1,
},
'sysgen_dut.to_register9_data_in' => {
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'sysgen_dut.to_register9_en' => {
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'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv/reg13_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'reg13_tv',
},
'reg14_rd' => {
'connections' => { 'reg14_rd' => 'sysgen_dut.reg14_rd', },
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'isGateway' => 1,
'is_floating_block' => 1,
},
'entityName' => 'reg14_rd',
'ports' => {
'reg14_rd' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd/reg14_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'reg14_rd',
},
'reg14_rv' => {
'connections' => { 'reg14_rv' => 'sysgen_dut.reg14_rv', },
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'isGateway' => 1,
'is_floating_block' => 1,
},
'entityName' => 'reg14_rv',
'ports' => {
'reg14_rv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv/reg14_rv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'reg14_rv',
},
'reg14_td' => {
'connections' => { 'reg14_td' => '.reg14_td', },
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'isGateway' => 1,
'is_floating_block' => 1,
},
'entityName' => 'reg14_td',
'ports' => {
'reg14_td' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td/reg14_td',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
},
'entityName' => 'reg14_td',
},
'reg14_tv' => {
'connections' => { 'reg14_tv' => '.reg14_tv', },
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'isGateway' => 1,
'is_floating_block' => 1,
},
'entityName' => 'reg14_tv',
'ports' => {
'reg14_tv' => {
'attributes' => {
'bin_pt' => 0,
'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
'is_floating_block' => 1,
'is_gateway_port' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv/reg14_tv',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
'timingConstraint' => 'none',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'reg14_tv',
},
'sysgen_dut' => {
'connections' => {
'clk' => '.clk',
'debug_in_1i' => '.debug_in_1i',
'debug_in_2i' => '.debug_in_2i',
'debug_in_3i' => '.debug_in_3i',
'debug_in_4i' => '.debug_in_4i',
'dma_host2board_busy' => '.dma_host2board_busy',
'dma_host2board_done' => '.dma_host2board_done',
'from_register10_data_out' => 'from_register10.data_out',
'from_register11_data_out' => 'from_register11.data_out',
'from_register12_data_out' => 'from_register12.data_out',
'from_register13_data_out' => 'from_register13.data_out',
'from_register14_data_out' => 'from_register14.data_out',
'from_register15_data_out' => 'from_register15.data_out',
'from_register16_data_out' => 'from_register16.data_out',
'from_register17_data_out' => 'from_register17.data_out',
'from_register18_data_out' => 'from_register18.data_out',
'from_register19_data_out' => 'from_register19.data_out',
'from_register1_data_out' => 'from_register1.data_out',
'from_register20_data_out' => 'from_register20.data_out',
'from_register21_data_out' => 'from_register21.data_out',
'from_register22_data_out' => 'from_register22.data_out',
'from_register23_data_out' => 'from_register23.data_out',
'from_register24_data_out' => 'from_register24.data_out',
'from_register25_data_out' => 'from_register25.data_out',
'from_register26_data_out' => 'from_register26.data_out',
'from_register27_data_out' => 'from_register27.data_out',
'from_register28_data_out' => 'from_register28.data_out',
'from_register2_data_out' => 'from_register2.data_out',
'from_register3_data_out' => 'from_register3.data_out',
'from_register4_data_out' => 'from_register4.data_out',
'from_register5_data_out' => 'from_register5.data_out',
'from_register6_data_out' => 'from_register6.data_out',
'from_register7_data_out' => 'from_register7.data_out',
'from_register8_data_out' => 'from_register8.data_out',
'from_register9_data_out' => 'from_register9.data_out',
'reg01_rd' => 'sysgen_dut.reg01_rd',
'reg01_rv' => 'sysgen_dut.reg01_rv',
'reg01_td' => '.reg01_td',
'reg01_tv' => '.reg01_tv',
'reg02_rd' => 'sysgen_dut.reg02_rd',
'reg02_rv' => 'sysgen_dut.reg02_rv',
'reg02_td' => '.reg02_td',
'reg02_tv' => '.reg02_tv',
'reg03_rd' => 'sysgen_dut.reg03_rd',
'reg03_rv' => 'sysgen_dut.reg03_rv',
'reg03_td' => '.reg03_td',
'reg03_tv' => '.reg03_tv',
'reg04_rd' => 'sysgen_dut.reg04_rd',
'reg04_rv' => 'sysgen_dut.reg04_rv',
'reg04_td' => '.reg04_td',
'reg04_tv' => '.reg04_tv',
'reg05_rd' => 'sysgen_dut.reg05_rd',
'reg05_rv' => 'sysgen_dut.reg05_rv',
'reg05_td' => '.reg05_td',
'reg05_tv' => '.reg05_tv',
'reg06_rd' => 'sysgen_dut.reg06_rd',
'reg06_rv' => 'sysgen_dut.reg06_rv',
'reg06_td' => '.reg06_td',
'reg06_tv' => '.reg06_tv',
'reg07_rd' => 'sysgen_dut.reg07_rd',
'reg07_rv' => 'sysgen_dut.reg07_rv',
'reg07_td' => '.reg07_td',
'reg07_tv' => '.reg07_tv',
'reg08_rd' => 'sysgen_dut.reg08_rd',
'reg08_rv' => 'sysgen_dut.reg08_rv',
'reg08_td' => '.reg08_td',
'reg08_tv' => '.reg08_tv',
'reg09_rd' => 'sysgen_dut.reg09_rd',
'reg09_rv' => 'sysgen_dut.reg09_rv',
'reg09_td' => '.reg09_td',
'reg09_tv' => '.reg09_tv',
'reg10_rd' => 'sysgen_dut.reg10_rd',
'reg10_rv' => 'sysgen_dut.reg10_rv',
'reg10_td' => '.reg10_td',
'reg10_tv' => '.reg10_tv',
'reg11_rd' => 'sysgen_dut.reg11_rd',
'reg11_rv' => 'sysgen_dut.reg11_rv',
'reg11_td' => '.reg11_td',
'reg11_tv' => '.reg11_tv',
'reg12_rd' => 'sysgen_dut.reg12_rd',
'reg12_rv' => 'sysgen_dut.reg12_rv',
'reg12_td' => '.reg12_td',
'reg12_tv' => '.reg12_tv',
'reg13_rd' => 'sysgen_dut.reg13_rd',
'reg13_rv' => 'sysgen_dut.reg13_rv',
'reg13_td' => '.reg13_td',
'reg13_tv' => '.reg13_tv',
'reg14_rd' => 'sysgen_dut.reg14_rd',
'reg14_rv' => 'sysgen_dut.reg14_rv',
'reg14_td' => '.reg14_td',
'reg14_tv' => '.reg14_tv',
'to_register10_ce' => 'sysgen_dut.to_register10_ce',
'to_register10_clk' => 'sysgen_dut.to_register10_clk',
'to_register10_clr' => 'sysgen_dut.to_register10_clr',
'to_register10_data_in' => 'sysgen_dut.to_register10_data_in',
'to_register10_dout' => 'to_register10.dout',
'to_register10_en' => 'sysgen_dut.to_register10_en',
'to_register11_ce' => 'sysgen_dut.to_register11_ce',
'to_register11_clk' => 'sysgen_dut.to_register11_clk',
'to_register11_clr' => 'sysgen_dut.to_register11_clr',
'to_register11_data_in' => 'sysgen_dut.to_register11_data_in',
'to_register11_dout' => 'to_register11.dout',
'to_register11_en' => 'sysgen_dut.to_register11_en',
'to_register12_ce' => 'sysgen_dut.to_register12_ce',
'to_register12_clk' => 'sysgen_dut.to_register12_clk',
'to_register12_clr' => 'sysgen_dut.to_register12_clr',
'to_register12_data_in' => 'sysgen_dut.to_register12_data_in',
'to_register12_dout' => 'to_register12.dout',
'to_register12_en' => 'sysgen_dut.to_register12_en',
'to_register13_ce' => 'sysgen_dut.to_register13_ce',
'to_register13_clk' => 'sysgen_dut.to_register13_clk',
'to_register13_clr' => 'sysgen_dut.to_register13_clr',
'to_register13_data_in' => 'sysgen_dut.to_register13_data_in',
'to_register13_dout' => 'to_register13.dout',
'to_register13_en' => 'sysgen_dut.to_register13_en',
'to_register14_ce' => 'sysgen_dut.to_register14_ce',
'to_register14_clk' => 'sysgen_dut.to_register14_clk',
'to_register14_clr' => 'sysgen_dut.to_register14_clr',
'to_register14_data_in' => 'sysgen_dut.to_register14_data_in',
'to_register14_dout' => 'to_register14.dout',
'to_register14_en' => 'sysgen_dut.to_register14_en',
'to_register15_ce' => 'sysgen_dut.to_register15_ce',
'to_register15_clk' => 'sysgen_dut.to_register15_clk',
'to_register15_clr' => 'sysgen_dut.to_register15_clr',
'to_register15_data_in' => 'sysgen_dut.to_register15_data_in',
'to_register15_dout' => 'to_register15.dout',
'to_register15_en' => 'sysgen_dut.to_register15_en',
'to_register16_ce' => 'sysgen_dut.to_register16_ce',
'to_register16_clk' => 'sysgen_dut.to_register16_clk',
'to_register16_clr' => 'sysgen_dut.to_register16_clr',
'to_register16_data_in' => 'sysgen_dut.to_register16_data_in',
'to_register16_dout' => 'to_register16.dout',
'to_register16_en' => 'sysgen_dut.to_register16_en',
'to_register17_ce' => 'sysgen_dut.to_register17_ce',
'to_register17_clk' => 'sysgen_dut.to_register17_clk',
'to_register17_clr' => 'sysgen_dut.to_register17_clr',
'to_register17_data_in' => 'sysgen_dut.to_register17_data_in',
'to_register17_dout' => 'to_register17.dout',
'to_register17_en' => 'sysgen_dut.to_register17_en',
'to_register18_ce' => 'sysgen_dut.to_register18_ce',
'to_register18_clk' => 'sysgen_dut.to_register18_clk',
'to_register18_clr' => 'sysgen_dut.to_register18_clr',
'to_register18_data_in' => 'sysgen_dut.to_register18_data_in',
'to_register18_dout' => 'to_register18.dout',
'to_register18_en' => 'sysgen_dut.to_register18_en',
'to_register19_ce' => 'sysgen_dut.to_register19_ce',
'to_register19_clk' => 'sysgen_dut.to_register19_clk',
'to_register19_clr' => 'sysgen_dut.to_register19_clr',
'to_register19_data_in' => 'sysgen_dut.to_register19_data_in',
'to_register19_dout' => 'to_register19.dout',
'to_register19_en' => 'sysgen_dut.to_register19_en',
'to_register1_ce' => 'sysgen_dut.to_register1_ce',
'to_register1_clk' => 'sysgen_dut.to_register1_clk',
'to_register1_clr' => 'sysgen_dut.to_register1_clr',
'to_register1_data_in' => 'sysgen_dut.to_register1_data_in',
'to_register1_dout' => 'to_register1.dout',
'to_register1_en' => 'sysgen_dut.to_register1_en',
'to_register20_ce' => 'sysgen_dut.to_register20_ce',
'to_register20_clk' => 'sysgen_dut.to_register20_clk',
'to_register20_clr' => 'sysgen_dut.to_register20_clr',
'to_register20_data_in' => 'sysgen_dut.to_register20_data_in',
'to_register20_dout' => 'to_register20.dout',
'to_register20_en' => 'sysgen_dut.to_register20_en',
'to_register21_ce' => 'sysgen_dut.to_register21_ce',
'to_register21_clk' => 'sysgen_dut.to_register21_clk',
'to_register21_clr' => 'sysgen_dut.to_register21_clr',
'to_register21_data_in' => 'sysgen_dut.to_register21_data_in',
'to_register21_dout' => 'to_register21.dout',
'to_register21_en' => 'sysgen_dut.to_register21_en',
'to_register22_ce' => 'sysgen_dut.to_register22_ce',
'to_register22_clk' => 'sysgen_dut.to_register22_clk',
'to_register22_clr' => 'sysgen_dut.to_register22_clr',
'to_register22_data_in' => 'sysgen_dut.to_register22_data_in',
'to_register22_dout' => 'to_register22.dout',
'to_register22_en' => 'sysgen_dut.to_register22_en',
'to_register23_ce' => 'sysgen_dut.to_register23_ce',
'to_register23_clk' => 'sysgen_dut.to_register23_clk',
'to_register23_clr' => 'sysgen_dut.to_register23_clr',
'to_register23_data_in' => 'sysgen_dut.to_register23_data_in',
'to_register23_dout' => 'to_register23.dout',
'to_register23_en' => 'sysgen_dut.to_register23_en',
'to_register24_ce' => 'sysgen_dut.to_register24_ce',
'to_register24_clk' => 'sysgen_dut.to_register24_clk',
'to_register24_clr' => 'sysgen_dut.to_register24_clr',
'to_register24_data_in' => 'sysgen_dut.to_register24_data_in',
'to_register24_dout' => 'to_register24.dout',
'to_register24_en' => 'sysgen_dut.to_register24_en',
'to_register25_ce' => 'sysgen_dut.to_register25_ce',
'to_register25_clk' => 'sysgen_dut.to_register25_clk',
'to_register25_clr' => 'sysgen_dut.to_register25_clr',
'to_register25_data_in' => 'sysgen_dut.to_register25_data_in',
'to_register25_dout' => 'to_register25.dout',
'to_register25_en' => 'sysgen_dut.to_register25_en',
'to_register26_ce' => 'sysgen_dut.to_register26_ce',
'to_register26_clk' => 'sysgen_dut.to_register26_clk',
'to_register26_clr' => 'sysgen_dut.to_register26_clr',
'to_register26_data_in' => 'sysgen_dut.to_register26_data_in',
'to_register26_dout' => 'to_register26.dout',
'to_register26_en' => 'sysgen_dut.to_register26_en',
'to_register27_ce' => 'sysgen_dut.to_register27_ce',
'to_register27_clk' => 'sysgen_dut.to_register27_clk',
'to_register27_clr' => 'sysgen_dut.to_register27_clr',
'to_register27_data_in' => 'sysgen_dut.to_register27_data_in',
'to_register27_dout' => 'to_register27.dout',
'to_register27_en' => 'sysgen_dut.to_register27_en',
'to_register28_ce' => 'sysgen_dut.to_register28_ce',
'to_register28_clk' => 'sysgen_dut.to_register28_clk',
'to_register28_clr' => 'sysgen_dut.to_register28_clr',
'to_register28_data_in' => 'sysgen_dut.to_register28_data_in',
'to_register28_dout' => 'to_register28.dout',
'to_register28_en' => 'sysgen_dut.to_register28_en',
'to_register29_ce' => 'sysgen_dut.to_register29_ce',
'to_register29_clk' => 'sysgen_dut.to_register29_clk',
'to_register29_clr' => 'sysgen_dut.to_register29_clr',
'to_register29_data_in' => 'sysgen_dut.to_register29_data_in',
'to_register29_dout' => 'to_register29.dout',
'to_register29_en' => 'sysgen_dut.to_register29_en',
'to_register2_ce' => 'sysgen_dut.to_register2_ce',
'to_register2_clk' => 'sysgen_dut.to_register2_clk',
'to_register2_clr' => 'sysgen_dut.to_register2_clr',
'to_register2_data_in' => 'sysgen_dut.to_register2_data_in',
'to_register2_dout' => 'to_register2.dout',
'to_register2_en' => 'sysgen_dut.to_register2_en',
'to_register30_ce' => 'sysgen_dut.to_register30_ce',
'to_register30_clk' => 'sysgen_dut.to_register30_clk',
'to_register30_clr' => 'sysgen_dut.to_register30_clr',
'to_register30_data_in' => 'sysgen_dut.to_register30_data_in',
'to_register30_dout' => 'to_register30.dout',
'to_register30_en' => 'sysgen_dut.to_register30_en',
'to_register31_ce' => 'sysgen_dut.to_register31_ce',
'to_register31_clk' => 'sysgen_dut.to_register31_clk',
'to_register31_clr' => 'sysgen_dut.to_register31_clr',
'to_register31_data_in' => 'sysgen_dut.to_register31_data_in',
'to_register31_dout' => 'to_register31.dout',
'to_register31_en' => 'sysgen_dut.to_register31_en',
'to_register32_ce' => 'sysgen_dut.to_register32_ce',
'to_register32_clk' => 'sysgen_dut.to_register32_clk',
'to_register32_clr' => 'sysgen_dut.to_register32_clr',
'to_register32_data_in' => 'sysgen_dut.to_register32_data_in',
'to_register32_dout' => 'to_register32.dout',
'to_register32_en' => 'sysgen_dut.to_register32_en',
'to_register33_ce' => 'sysgen_dut.to_register33_ce',
'to_register33_clk' => 'sysgen_dut.to_register33_clk',
'to_register33_clr' => 'sysgen_dut.to_register33_clr',
'to_register33_data_in' => 'sysgen_dut.to_register33_data_in',
'to_register33_dout' => 'to_register33.dout',
'to_register33_en' => 'sysgen_dut.to_register33_en',
'to_register34_ce' => 'sysgen_dut.to_register34_ce',
'to_register34_clk' => 'sysgen_dut.to_register34_clk',
'to_register34_clr' => 'sysgen_dut.to_register34_clr',
'to_register34_data_in' => 'sysgen_dut.to_register34_data_in',
'to_register34_dout' => 'to_register34.dout',
'to_register34_en' => 'sysgen_dut.to_register34_en',
'to_register3_ce' => 'sysgen_dut.to_register3_ce',
'to_register3_clk' => 'sysgen_dut.to_register3_clk',
'to_register3_clr' => 'sysgen_dut.to_register3_clr',
'to_register3_data_in' => 'sysgen_dut.to_register3_data_in',
'to_register3_dout' => 'to_register3.dout',
'to_register3_en' => 'sysgen_dut.to_register3_en',
'to_register4_ce' => 'sysgen_dut.to_register4_ce',
'to_register4_clk' => 'sysgen_dut.to_register4_clk',
'to_register4_clr' => 'sysgen_dut.to_register4_clr',
'to_register4_data_in' => 'sysgen_dut.to_register4_data_in',
'to_register4_dout' => 'to_register4.dout',
'to_register4_en' => 'sysgen_dut.to_register4_en',
'to_register5_ce' => 'sysgen_dut.to_register5_ce',
'to_register5_clk' => 'sysgen_dut.to_register5_clk',
'to_register5_clr' => 'sysgen_dut.to_register5_clr',
'to_register5_data_in' => 'sysgen_dut.to_register5_data_in',
'to_register5_dout' => 'to_register5.dout',
'to_register5_en' => 'sysgen_dut.to_register5_en',
'to_register6_ce' => 'sysgen_dut.to_register6_ce',
'to_register6_clk' => 'sysgen_dut.to_register6_clk',
'to_register6_clr' => 'sysgen_dut.to_register6_clr',
'to_register6_data_in' => 'sysgen_dut.to_register6_data_in',
'to_register6_dout' => 'to_register6.dout',
'to_register6_en' => 'sysgen_dut.to_register6_en',
'to_register7_ce' => 'sysgen_dut.to_register7_ce',
'to_register7_clk' => 'sysgen_dut.to_register7_clk',
'to_register7_clr' => 'sysgen_dut.to_register7_clr',
'to_register7_data_in' => 'sysgen_dut.to_register7_data_in',
'to_register7_dout' => 'to_register7.dout',
'to_register7_en' => 'sysgen_dut.to_register7_en',
'to_register8_ce' => 'sysgen_dut.to_register8_ce',
'to_register8_clk' => 'sysgen_dut.to_register8_clk',
'to_register8_clr' => 'sysgen_dut.to_register8_clr',
'to_register8_data_in' => 'sysgen_dut.to_register8_data_in',
'to_register8_dout' => 'to_register8.dout',
'to_register8_en' => 'sysgen_dut.to_register8_en',
'to_register9_ce' => 'sysgen_dut.to_register9_ce',
'to_register9_clk' => 'sysgen_dut.to_register9_clk',
'to_register9_clr' => 'sysgen_dut.to_register9_clr',
'to_register9_data_in' => 'sysgen_dut.to_register9_data_in',
'to_register9_dout' => 'to_register9.dout',
'to_register9_en' => 'sysgen_dut.to_register9_en',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'hdlArchAttributes' => [],
'hdlEntityAttributes' => [],
'isClkWrapper' => 1,
},
'connections' => {
'clk' => 'clkNet',
'debug_in_1i' => 'debug_in_1i_net',
'debug_in_2i' => 'debug_in_2i_net',
'debug_in_3i' => 'debug_in_3i_net',
'debug_in_4i' => 'debug_in_4i_net',
'dma_host2board_busy' => 'dma_host2board_busy_net',
'dma_host2board_done' => 'dma_host2board_done_net',
'from_register10_data_out' => 'from_register10_data_out_net',
'from_register11_data_out' => 'from_register11_data_out_net',
'from_register12_data_out' => 'from_register12_data_out_net',
'from_register13_data_out' => 'from_register13_data_out_net',
'from_register14_data_out' => 'from_register14_data_out_net',
'from_register15_data_out' => 'from_register15_data_out_net',
'from_register16_data_out' => 'from_register16_data_out_net',
'from_register17_data_out' => 'from_register17_data_out_net',
'from_register18_data_out' => 'from_register18_data_out_net',
'from_register19_data_out' => 'from_register19_data_out_net',
'from_register1_data_out' => 'from_register1_data_out_net',
'from_register20_data_out' => 'from_register20_data_out_net',
'from_register21_data_out' => 'from_register21_data_out_net',
'from_register22_data_out' => 'from_register22_data_out_net',
'from_register23_data_out' => 'from_register23_data_out_net',
'from_register24_data_out' => 'from_register24_data_out_net',
'from_register25_data_out' => 'from_register25_data_out_net',
'from_register26_data_out' => 'from_register26_data_out_net',
'from_register27_data_out' => 'from_register27_data_out_net',
'from_register28_data_out' => 'from_register28_data_out_net',
'from_register2_data_out' => 'from_register2_data_out_net',
'from_register3_data_out' => 'from_register3_data_out_net',
'from_register4_data_out' => 'from_register4_data_out_net',
'from_register5_data_out' => 'from_register5_data_out_net',
'from_register6_data_out' => 'from_register6_data_out_net',
'from_register7_data_out' => 'from_register7_data_out_net',
'from_register8_data_out' => 'from_register8_data_out_net',
'from_register9_data_out' => 'from_register9_data_out_net',
'reg01_rd' => 'from_register3_data_out_net_x0',
'reg01_rv' => 'from_register1_data_out_net_x0',
'reg01_td' => 'reg01_td_net',
'reg01_tv' => 'reg01_tv_net',
'reg02_rd' => 'from_register5_data_out_net_x0',
'reg02_rv' => 'from_register2_data_out_net_x0',
'reg02_td' => 'reg02_td_net',
'reg02_tv' => 'reg02_tv_net',
'reg03_rd' => 'from_register7_data_out_net_x0',
'reg03_rv' => 'from_register6_data_out_net_x0',
'reg03_td' => 'reg03_td_net',
'reg03_tv' => 'reg03_tv_net',
'reg04_rd' => 'from_register8_data_out_net_x0',
'reg04_rv' => 'from_register4_data_out_net_x0',
'reg04_td' => 'reg04_td_net',
'reg04_tv' => 'reg04_tv_net',
'reg05_rd' => 'from_register10_data_out_net_x0',
'reg05_rv' => 'from_register9_data_out_net_x0',
'reg05_td' => 'reg05_td_net',
'reg05_tv' => 'reg05_tv_net',
'reg06_rd' => 'from_register11_data_out_net_x0',
'reg06_rv' => 'from_register12_data_out_net_x0',
'reg06_td' => 'reg06_td_net',
'reg06_tv' => 'reg06_tv_net',
'reg07_rd' => 'from_register13_data_out_net_x0',
'reg07_rv' => 'from_register14_data_out_net_x0',
'reg07_td' => 'reg07_td_net',
'reg07_tv' => 'reg07_tv_net',
'reg08_rd' => 'from_register15_data_out_net_x0',
'reg08_rv' => 'from_register16_data_out_net_x0',
'reg08_td' => 'reg08_td_net',
'reg08_tv' => 'reg08_tv_net',
'reg09_rd' => 'from_register17_data_out_net_x0',
'reg09_rv' => 'from_register18_data_out_net_x0',
'reg09_td' => 'reg09_td_net',
'reg09_tv' => 'reg09_tv_net',
'reg10_rd' => 'from_register19_data_out_net_x0',
'reg10_rv' => 'from_register20_data_out_net_x0',
'reg10_td' => 'reg10_td_net',
'reg10_tv' => 'reg10_tv_net',
'reg11_rd' => 'from_register21_data_out_net_x0',
'reg11_rv' => 'from_register22_data_out_net_x0',
'reg11_td' => 'reg11_td_net',
'reg11_tv' => 'reg11_tv_net',
'reg12_rd' => 'from_register23_data_out_net_x0',
'reg12_rv' => 'from_register24_data_out_net_x0',
'reg12_td' => 'reg12_td_net',
'reg12_tv' => 'reg12_tv_net',
'reg13_rd' => 'from_register25_data_out_net_x0',
'reg13_rv' => 'from_register26_data_out_net_x0',
'reg13_td' => 'reg13_td_net',
'reg13_tv' => 'reg13_tv_net',
'reg14_rd' => 'from_register27_data_out_net_x0',
'reg14_rv' => 'from_register28_data_out_net_x0',
'reg14_td' => 'reg14_td_net',
'reg14_tv' => 'reg14_tv_net',
'to_register10_ce' => 'ce_1_sg',
'to_register10_clk' => 'clk_1_sg',
'to_register10_clr' => [
'constant',
'\'0\'',
],
'to_register10_data_in' => 'reg04_tv_net_x0',
'to_register10_dout' => 'to_register10_dout_net',
'to_register10_en' => 'constant5_op_net_x1',
'to_register11_ce' => 'ce_1_sg',
'to_register11_clk' => 'clk_1_sg',
'to_register11_clr' => [
'constant',
'\'0\'',
],
'to_register11_data_in' => 'reg04_td_net_x0',
'to_register11_dout' => 'to_register11_dout_net',
'to_register11_en' => 'constant5_op_net_x2',
'to_register12_ce' => 'ce_1_sg',
'to_register12_clk' => 'clk_1_sg',
'to_register12_clr' => [
'constant',
'\'0\'',
],
'to_register12_data_in' => 'reg05_tv_net_x0',
'to_register12_dout' => 'to_register12_dout_net',
'to_register12_en' => 'constant5_op_net_x3',
'to_register13_ce' => 'ce_1_sg',
'to_register13_clk' => 'clk_1_sg',
'to_register13_clr' => [
'constant',
'\'0\'',
],
'to_register13_data_in' => 'reg05_td_net_x0',
'to_register13_dout' => 'to_register13_dout_net',
'to_register13_en' => 'constant5_op_net_x4',
'to_register14_ce' => 'ce_1_sg',
'to_register14_clk' => 'clk_1_sg',
'to_register14_clr' => [
'constant',
'\'0\'',
],
'to_register14_data_in' => 'reg06_tv_net_x0',
'to_register14_dout' => 'to_register14_dout_net',
'to_register14_en' => 'constant5_op_net_x5',
'to_register15_ce' => 'ce_1_sg',
'to_register15_clk' => 'clk_1_sg',
'to_register15_clr' => [
'constant',
'\'0\'',
],
'to_register15_data_in' => 'reg06_td_net_x0',
'to_register15_dout' => 'to_register15_dout_net',
'to_register15_en' => 'constant5_op_net_x6',
'to_register16_ce' => 'ce_1_sg',
'to_register16_clk' => 'clk_1_sg',
'to_register16_clr' => [
'constant',
'\'0\'',
],
'to_register16_data_in' => 'reg07_tv_net_x0',
'to_register16_dout' => 'to_register16_dout_net',
'to_register16_en' => 'constant5_op_net_x7',
'to_register17_ce' => 'ce_1_sg',
'to_register17_clk' => 'clk_1_sg',
'to_register17_clr' => [
'constant',
'\'0\'',
],
'to_register17_data_in' => 'reg07_td_net_x0',
'to_register17_dout' => 'to_register17_dout_net',
'to_register17_en' => 'constant5_op_net_x8',
'to_register18_ce' => 'ce_1_sg',
'to_register18_clk' => 'clk_1_sg',
'to_register18_clr' => [
'constant',
'\'0\'',
],
'to_register18_data_in' => 'dma_host2board_busy_net_x0',
'to_register18_dout' => 'to_register18_dout_net',
'to_register18_en' => 'constant5_op_net_x9',
'to_register19_ce' => 'ce_1_sg',
'to_register19_clk' => 'clk_1_sg',
'to_register19_clr' => [
'constant',
'\'0\'',
],
'to_register19_data_in' => 'dma_host2board_done_net_x0',
'to_register19_dout' => 'to_register19_dout_net',
'to_register19_en' => 'constant5_op_net_x10',
'to_register1_ce' => 'ce_1_sg',
'to_register1_clk' => 'clk_1_sg',
'to_register1_clr' => [
'constant',
'\'0\'',
],
'to_register1_data_in' => 'debug_in_2i_net_x0',
'to_register1_dout' => 'to_register1_dout_net',
'to_register1_en' => 'constant5_op_net_x0',
'to_register20_ce' => 'ce_1_sg',
'to_register20_clk' => 'clk_1_sg',
'to_register20_clr' => [
'constant',
'\'0\'',
],
'to_register20_data_in' => 'debug_in_4i_net_x0',
'to_register20_dout' => 'to_register20_dout_net',
'to_register20_en' => 'constant5_op_net_x12',
'to_register21_ce' => 'ce_1_sg',
'to_register21_clk' => 'clk_1_sg',
'to_register21_clr' => [
'constant',
'\'0\'',
],
'to_register21_data_in' => 'reg09_tv_net_x0',
'to_register21_dout' => 'to_register21_dout_net',
'to_register21_en' => 'constant1_op_net_x0',
'to_register22_ce' => 'ce_1_sg',
'to_register22_clk' => 'clk_1_sg',
'to_register22_clr' => [
'constant',
'\'0\'',
],
'to_register22_data_in' => 'reg09_td_net_x0',
'to_register22_dout' => 'to_register22_dout_net',
'to_register22_en' => 'constant1_op_net_x1',
'to_register23_ce' => 'ce_1_sg',
'to_register23_clk' => 'clk_1_sg',
'to_register23_clr' => [
'constant',
'\'0\'',
],
'to_register23_data_in' => 'reg10_tv_net_x0',
'to_register23_dout' => 'to_register23_dout_net',
'to_register23_en' => 'constant1_op_net_x2',
'to_register24_ce' => 'ce_1_sg',
'to_register24_clk' => 'clk_1_sg',
'to_register24_clr' => [
'constant',
'\'0\'',
],
'to_register24_data_in' => 'reg10_td_net_x0',
'to_register24_dout' => 'to_register24_dout_net',
'to_register24_en' => 'constant1_op_net_x3',
'to_register25_ce' => 'ce_1_sg',
'to_register25_clk' => 'clk_1_sg',
'to_register25_clr' => [
'constant',
'\'0\'',
],
'to_register25_data_in' => 'reg08_tv_net_x0',
'to_register25_dout' => 'to_register25_dout_net',
'to_register25_en' => 'constant1_op_net_x4',
'to_register26_ce' => 'ce_1_sg',
'to_register26_clk' => 'clk_1_sg',
'to_register26_clr' => [
'constant',
'\'0\'',
],
'to_register26_data_in' => 'reg08_td_net_x0',
'to_register26_dout' => 'to_register26_dout_net',
'to_register26_en' => 'constant1_op_net_x5',
'to_register27_ce' => 'ce_1_sg',
'to_register27_clk' => 'clk_1_sg',
'to_register27_clr' => [
'constant',
'\'0\'',
],
'to_register27_data_in' => 'reg11_tv_net_x0',
'to_register27_dout' => 'to_register27_dout_net',
'to_register27_en' => 'constant1_op_net_x6',
'to_register28_ce' => 'ce_1_sg',
'to_register28_clk' => 'clk_1_sg',
'to_register28_clr' => [
'constant',
'\'0\'',
],
'to_register28_data_in' => 'reg11_td_net_x0',
'to_register28_dout' => 'to_register28_dout_net',
'to_register28_en' => 'constant1_op_net_x7',
'to_register29_ce' => 'ce_1_sg',
'to_register29_clk' => 'clk_1_sg',
'to_register29_clr' => [
'constant',
'\'0\'',
],
'to_register29_data_in' => 'reg12_tv_net_x0',
'to_register29_dout' => 'to_register29_dout_net',
'to_register29_en' => 'constant1_op_net_x8',
'to_register2_ce' => 'ce_1_sg',
'to_register2_clk' => 'clk_1_sg',
'to_register2_clr' => [
'constant',
'\'0\'',
],
'to_register2_data_in' => 'debug_in_3i_net_x0',
'to_register2_dout' => 'to_register2_dout_net',
'to_register2_en' => 'constant5_op_net_x11',
'to_register30_ce' => 'ce_1_sg',
'to_register30_clk' => 'clk_1_sg',
'to_register30_clr' => [
'constant',
'\'0\'',
],
'to_register30_data_in' => 'reg12_td_net_x0',
'to_register30_dout' => 'to_register30_dout_net',
'to_register30_en' => 'constant1_op_net_x9',
'to_register31_ce' => 'ce_1_sg',
'to_register31_clk' => 'clk_1_sg',
'to_register31_clr' => [
'constant',
'\'0\'',
],
'to_register31_data_in' => 'reg13_tv_net_x0',
'to_register31_dout' => 'to_register31_dout_net',
'to_register31_en' => 'constant1_op_net_x10',
'to_register32_ce' => 'ce_1_sg',
'to_register32_clk' => 'clk_1_sg',
'to_register32_clr' => [
'constant',
'\'0\'',
],
'to_register32_data_in' => 'reg13_td_net_x0',
'to_register32_dout' => 'to_register32_dout_net',
'to_register32_en' => 'constant1_op_net_x11',
'to_register33_ce' => 'ce_1_sg',
'to_register33_clk' => 'clk_1_sg',
'to_register33_clr' => [
'constant',
'\'0\'',
],
'to_register33_data_in' => 'reg14_tv_net_x0',
'to_register33_dout' => 'to_register33_dout_net',
'to_register33_en' => 'constant1_op_net_x12',
'to_register34_ce' => 'ce_1_sg',
'to_register34_clk' => 'clk_1_sg',
'to_register34_clr' => [
'constant',
'\'0\'',
],
'to_register34_data_in' => 'reg14_td_net_x0',
'to_register34_dout' => 'to_register34_dout_net',
'to_register34_en' => 'constant1_op_net_x13',
'to_register3_ce' => 'ce_1_sg',
'to_register3_clk' => 'clk_1_sg',
'to_register3_clr' => [
'constant',
'\'0\'',
],
'to_register3_data_in' => 'reg01_tv_net_x0',
'to_register3_dout' => 'to_register3_dout_net',
'to_register3_en' => 'constant5_op_net_x13',
'to_register4_ce' => 'ce_1_sg',
'to_register4_clk' => 'clk_1_sg',
'to_register4_clr' => [
'constant',
'\'0\'',
],
'to_register4_data_in' => 'reg02_tv_net_x0',
'to_register4_dout' => 'to_register4_dout_net',
'to_register4_en' => 'constant5_op_net_x14',
'to_register5_ce' => 'ce_1_sg',
'to_register5_clk' => 'clk_1_sg',
'to_register5_clr' => [
'constant',
'\'0\'',
],
'to_register5_data_in' => 'reg02_td_net_x0',
'to_register5_dout' => 'to_register5_dout_net',
'to_register5_en' => 'constant5_op_net_x15',
'to_register6_ce' => 'ce_1_sg',
'to_register6_clk' => 'clk_1_sg',
'to_register6_clr' => [
'constant',
'\'0\'',
],
'to_register6_data_in' => 'debug_in_1i_net_x0',
'to_register6_dout' => 'to_register6_dout_net',
'to_register6_en' => 'constant5_op_net_x16',
'to_register7_ce' => 'ce_1_sg',
'to_register7_clk' => 'clk_1_sg',
'to_register7_clr' => [
'constant',
'\'0\'',
],
'to_register7_data_in' => 'reg01_td_net_x0',
'to_register7_dout' => 'to_register7_dout_net',
'to_register7_en' => 'constant5_op_net_x17',
'to_register8_ce' => 'ce_1_sg',
'to_register8_clk' => 'clk_1_sg',
'to_register8_clr' => [
'constant',
'\'0\'',
],
'to_register8_data_in' => 'reg03_tv_net_x0',
'to_register8_dout' => 'to_register8_dout_net',
'to_register8_en' => 'constant5_op_net_x18',
'to_register9_ce' => 'ce_1_sg',
'to_register9_clk' => 'clk_1_sg',
'to_register9_clr' => [
'constant',
'\'0\'',
],
'to_register9_data_in' => 'reg03_td_net_x0',
'to_register9_dout' => 'to_register9_dout_net',
'to_register9_en' => 'constant5_op_net_x19',
},
'entityName' => 'inout_logic_cw',
'nets' => {
'ce_1_sg' => {
'attributes' => {
'hdlNetAttributes' => [
[
'MAX_FANOUT',
'string',
'"REDUCE"',
],
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'clkNet' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'clk_1_sg' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x1' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x10' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x11' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x12' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x13' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x2' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x3' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x4' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x5' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x6' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x7' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x8' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant1_op_net_x9' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x1' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x10' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x11' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x12' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x13' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x14' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x15' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x16' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x17' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x18' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x19' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x2' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x3' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x4' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x5' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x6' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x7' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x8' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'constant5_op_net_x9' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'debug_in_1i_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'debug_in_1i_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'debug_in_2i_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'debug_in_2i_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'debug_in_3i_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'debug_in_3i_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'debug_in_4i_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'debug_in_4i_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'dma_host2board_busy_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'dma_host2board_busy_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'dma_host2board_done_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'dma_host2board_done_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register10_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register10_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register11_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register11_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register12_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register12_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register13_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register13_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register14_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register14_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register15_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register15_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register16_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register16_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register17_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register17_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register18_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register18_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register19_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register19_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register1_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register1_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register20_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register20_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register21_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register21_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register22_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register22_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register23_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register23_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register24_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register24_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register25_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register25_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register26_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register26_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register27_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register27_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register28_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register28_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register2_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register2_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register3_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register3_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register4_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register4_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register5_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register5_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register6_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register6_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register7_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register7_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register8_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register8_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'from_register9_data_out_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register9_data_out_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'persistentdff_inst_q' => {
'attributes' => {
'hdlNetAttributes' => [
[
'syn_keep',
'boolean',
'true',
],
[
'keep',
'boolean',
'true',
],
[
'preserve_signal',
'boolean',
'true',
],
],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg01_td_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg01_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg01_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg01_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg02_td_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg02_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg02_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg02_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg03_td_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg03_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg03_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg03_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg04_td_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg04_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg04_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg04_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg05_td_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg05_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg05_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg05_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg06_td_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg06_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg06_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg06_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg07_td_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg07_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg07_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg07_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg08_td_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg08_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg08_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg08_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg09_td_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg09_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg09_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg09_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg10_td_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg10_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg10_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg10_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg11_td_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg11_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg11_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
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},
'reg11_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'reg12_td_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg12_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'reg12_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
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},
'reg12_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
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},
'reg13_td_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg13_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg13_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
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},
'reg13_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
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'reg14_td_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'reg14_td_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'reg14_tv_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
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'reg14_tv_net_x0' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
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'to_register10_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
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'to_register11_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register12_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
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'to_register13_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'to_register14_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
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'to_register15_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register16_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
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'to_register17_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'to_register18_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
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},
'to_register19_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
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'to_register1_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'to_register20_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register21_dout_net' => {
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'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register22_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register23_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
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'to_register24_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register25_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
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'to_register26_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register27_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register28_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register29_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register2_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register30_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register31_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register32_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register33_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register34_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register3_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register4_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register5_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register6_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register7_dout_net' => {
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'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register8_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register9_dout_net' => {
'attributes' => {
'hdlNetAttributes' => [],
},
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
},
'ports' => {
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'attributes' => {
'defaultHdlValue' => '\'1\'',
'domain' => 'default',
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'isCe' => 1,
'period' => 1,
},
'direction' => 'in',
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'width' => 1,
},
'clk' => {
'attributes' => {
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'period' => 1,
'type' => 'logic',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'debug_in_1i' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i/debug_in_1i',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'debug_in_2i' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i',
'timingConstraint' => 'none',
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},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'debug_in_3i' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i/debug_in_3i',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i',
'timingConstraint' => 'none',
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},
'direction' => 'in',
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'debug_in_4i' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i/debug_in_4i',
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'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
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'dma_host2board_busy' => {
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'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
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'period' => 1,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy/DMA_Host2Board_Busy',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'dma_host2board_done' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done/DMA_Host2Board_Done',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
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'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'from_register10_data_out' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10/data_out',
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'direction' => 'in',
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'from_register11_data_out' => {
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'period' => 1,
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'direction' => 'in',
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'from_register12_data_out' => {
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'period' => 1,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12/data_out',
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'direction' => 'in',
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'from_register13_data_out' => {
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13/data_out',
'type' => 'UFix_32_0',
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'direction' => 'in',
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'from_register14_data_out' => {
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'period' => 1,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14/data_out',
'type' => 'UFix_1_0',
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'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
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'from_register15_data_out' => {
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'period' => 1,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15/data_out',
'type' => 'UFix_32_0',
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'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'from_register16_data_out' => {
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'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16/data_out',
'type' => 'UFix_1_0',
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'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
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'from_register17_data_out' => {
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'period' => 1,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17/data_out',
'type' => 'UFix_32_0',
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'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'from_register18_data_out' => {
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'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18/data_out',
'type' => 'UFix_1_0',
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'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
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'from_register19_data_out' => {
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'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19/data_out',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'from_register1_data_out' => {
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'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1/data_out',
'type' => 'UFix_1_0',
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'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
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'from_register20_data_out' => {
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'must_be_hdl_vector' => 1,
'period' => 1,
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'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20/data_out',
'type' => 'UFix_1_0',
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'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
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'from_register21_data_out' => {
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'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21/data_out',
'type' => 'UFix_32_0',
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'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'from_register22_data_out' => {
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'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22/data_out',
'type' => 'UFix_1_0',
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'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
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'from_register23_data_out' => {
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'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23/data_out',
'type' => 'UFix_32_0',
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'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'from_register24_data_out' => {
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'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24/data_out',
'type' => 'UFix_1_0',
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'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
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'from_register25_data_out' => {
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'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25/data_out',
'type' => 'UFix_32_0',
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'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'from_register26_data_out' => {
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'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26/data_out',
'type' => 'UFix_1_0',
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'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
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'from_register27_data_out' => {
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'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27/data_out',
'type' => 'UFix_32_0',
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'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
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'from_register28_data_out' => {
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'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28/data_out',
'type' => 'UFix_1_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'from_register2_data_out' => {
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'reg07_rd' => {
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'reg07_rv' => {
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'reg07_td' => {
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'reg07_tv' => {
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'timingConstraint' => 'none',
'type' => 'Bool',
},
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},
'reg08_rd' => {
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'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd/reg08_rd',
'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd',
'timingConstraint' => 'none',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'reg08_rv' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv',
'timingConstraint' => 'none',
'type' => 'UFix_1_0',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'reg08_td' => {
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'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td',
'timingConstraint' => 'none',
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},
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},
'reg08_tv' => {
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'type' => 'Bool',
},
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},
'reg09_rd' => {
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'timingConstraint' => 'none',
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'reg09_rv' => {
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},
'reg09_td' => {
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'reg09_tv' => {
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},
'reg10_rd' => {
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'reg10_rv' => {
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'reg10_td' => {
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},
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'reg12_rv' => {
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'reg12_td' => {
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'reg13_rd' => {
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'reg13_rv' => {
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'reg13_td' => {
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},
'reg14_rd' => {
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'reg14_rv' => {
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},
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'to_register10_clk' => {
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'to_register10_clr' => {
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},
'to_register10_data_in' => {
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'direction' => 'out',
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'to_register10_dout' => {
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},
'to_register10_en' => {
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'direction' => 'out',
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},
'to_register11_ce' => {
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'to_register11_clk' => {
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},
'to_register11_clr' => {
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},
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},
'to_register11_data_in' => {
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'type' => 'UFix_32_0',
},
'direction' => 'out',
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},
'to_register11_dout' => {
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'direction' => 'in',
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'to_register7_clr' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClr' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
'valid_bit_used' => 0,
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register7_data_in' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register7_dout' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/dout',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register7_en' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 1,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/en',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'to_register8_ce' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isCe' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register8_clk' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClk' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register8_clr' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClr' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
'valid_bit_used' => 0,
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register8_data_in' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'to_register8_dout' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
'type' => 'Bool',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'to_register8_en' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 1,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
'to_register9_ce' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isCe' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register9_clk' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClk' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register9_clr' => {
'attributes' => {
'domain' => '',
'group' => 1,
'isClr' => 1,
'is_floating_block' => 1,
'period' => 1,
'type' => 'logic',
'valid_bit_used' => 0,
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'to_register9_data_in' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register9_dout' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
'type' => 'UFix_32_0',
},
'direction' => 'in',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'to_register9_en' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 1,
'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(0 downto 0)',
'width' => 1,
},
},
'subblocks' => {
'default_clock_driver_x0' => {
'connections' => {
'ce_1' => 'ce_1_sg',
'clk_1' => 'clk_1_sg',
'sysce' => [
'constant',
'\'1\'',
],
'sysce_clr' => [
'constant',
'\'0\'',
],
'sysclk' => 'clkNet',
},
'entity' => {
'attributes' => {
'domain' => 'default',
'hdlArchAttributes' => [
[
'syn_noprune',
'boolean',
'true',
],
[
'optimize_primitives',
'boolean',
'false',
],
[
'dont_touch',
'boolean',
'true',
],
],
'hdlEntityAttributes' => [],
'isClkDriver' => 1,
},
'entityName' => 'default_clock_driver',
'ports' => {
'ce_1' => {
'attributes' => {
'domain' => 'default',
'group' => 1,
'isCe' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'clk_1' => {
'attributes' => {
'domain' => 'default',
'group' => 1,
'isClk' => 1,
'period' => 1,
'type' => 'logic',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'sysce' => {
'attributes' => {
'group' => 4,
'isCe' => 1,
'period' => 1,
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'sysce_clr' => {
'attributes' => {
'group' => 4,
'isClr' => 1,
'period' => 1,
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
'sysclk' => {
'attributes' => {
'group' => 4,
'isClk' => 1,
'period' => 1,
},
'direction' => 'in',
'hdlType' => 'std_logic',
'width' => 1,
},
},
},
'entityName' => 'default_clock_driver',
},
'inout_logic_x0' => {
'connections' => {
'data_in' => 'debug_in_2i_net_x0',
'data_in_x0' => 'reg04_tv_net_x0',
'data_in_x1' => 'reg04_td_net_x0',
'data_in_x10' => 'debug_in_3i_net_x0',
'data_in_x11' => 'debug_in_4i_net_x0',
'data_in_x12' => 'reg09_tv_net_x0',
'data_in_x13' => 'reg09_td_net_x0',
'data_in_x14' => 'reg10_tv_net_x0',
'data_in_x15' => 'reg10_td_net_x0',
'data_in_x16' => 'reg08_tv_net_x0',
'data_in_x17' => 'reg08_td_net_x0',
'data_in_x18' => 'reg11_tv_net_x0',
'data_in_x19' => 'reg11_td_net_x0',
'data_in_x2' => 'reg05_tv_net_x0',
'data_in_x20' => 'reg12_tv_net_x0',
'data_in_x21' => 'reg01_tv_net_x0',
'data_in_x22' => 'reg12_td_net_x0',
'data_in_x23' => 'reg13_tv_net_x0',
'data_in_x24' => 'reg13_td_net_x0',
'data_in_x25' => 'reg14_tv_net_x0',
'data_in_x26' => 'reg14_td_net_x0',
'data_in_x27' => 'reg02_tv_net_x0',
'data_in_x28' => 'reg02_td_net_x0',
'data_in_x29' => 'debug_in_1i_net_x0',
'data_in_x3' => 'reg05_td_net_x0',
'data_in_x30' => 'reg01_td_net_x0',
'data_in_x31' => 'reg03_tv_net_x0',
'data_in_x32' => 'reg03_td_net_x0',
'data_in_x4' => 'reg06_tv_net_x0',
'data_in_x5' => 'reg06_td_net_x0',
'data_in_x6' => 'reg07_tv_net_x0',
'data_in_x7' => 'reg07_td_net_x0',
'data_in_x8' => 'dma_host2board_busy_net_x0',
'data_in_x9' => 'dma_host2board_done_net_x0',
'data_out' => 'from_register1_data_out_net',
'data_out_x0' => 'from_register10_data_out_net',
'data_out_x1' => 'from_register11_data_out_net',
'data_out_x10' => 'from_register2_data_out_net',
'data_out_x11' => 'from_register20_data_out_net',
'data_out_x12' => 'from_register21_data_out_net',
'data_out_x13' => 'from_register22_data_out_net',
'data_out_x14' => 'from_register23_data_out_net',
'data_out_x15' => 'from_register24_data_out_net',
'data_out_x16' => 'from_register25_data_out_net',
'data_out_x17' => 'from_register26_data_out_net',
'data_out_x18' => 'from_register27_data_out_net',
'data_out_x19' => 'from_register28_data_out_net',
'data_out_x2' => 'from_register12_data_out_net',
'data_out_x20' => 'from_register3_data_out_net',
'data_out_x21' => 'from_register4_data_out_net',
'data_out_x22' => 'from_register5_data_out_net',
'data_out_x23' => 'from_register6_data_out_net',
'data_out_x24' => 'from_register7_data_out_net',
'data_out_x25' => 'from_register8_data_out_net',
'data_out_x26' => 'from_register9_data_out_net',
'data_out_x3' => 'from_register13_data_out_net',
'data_out_x4' => 'from_register14_data_out_net',
'data_out_x5' => 'from_register15_data_out_net',
'data_out_x6' => 'from_register16_data_out_net',
'data_out_x7' => 'from_register17_data_out_net',
'data_out_x8' => 'from_register18_data_out_net',
'data_out_x9' => 'from_register19_data_out_net',
'debug_in_1i' => 'debug_in_1i_net',
'debug_in_2i' => 'debug_in_2i_net',
'debug_in_3i' => 'debug_in_3i_net',
'debug_in_4i' => 'debug_in_4i_net',
'dma_host2board_busy' => 'dma_host2board_busy_net',
'dma_host2board_done' => 'dma_host2board_done_net',
'en' => 'constant5_op_net_x0',
'en_x0' => 'constant5_op_net_x1',
'en_x1' => 'constant5_op_net_x2',
'en_x10' => 'constant5_op_net_x11',
'en_x11' => 'constant5_op_net_x12',
'en_x12' => 'constant1_op_net_x0',
'en_x13' => 'constant1_op_net_x1',
'en_x14' => 'constant1_op_net_x2',
'en_x15' => 'constant1_op_net_x3',
'en_x16' => 'constant1_op_net_x4',
'en_x17' => 'constant1_op_net_x5',
'en_x18' => 'constant1_op_net_x6',
'en_x19' => 'constant1_op_net_x7',
'en_x2' => 'constant5_op_net_x3',
'en_x20' => 'constant1_op_net_x8',
'en_x21' => 'constant5_op_net_x13',
'en_x22' => 'constant1_op_net_x9',
'en_x23' => 'constant1_op_net_x10',
'en_x24' => 'constant1_op_net_x11',
'en_x25' => 'constant1_op_net_x12',
'en_x26' => 'constant1_op_net_x13',
'en_x27' => 'constant5_op_net_x14',
'en_x28' => 'constant5_op_net_x15',
'en_x29' => 'constant5_op_net_x16',
'en_x3' => 'constant5_op_net_x4',
'en_x30' => 'constant5_op_net_x17',
'en_x31' => 'constant5_op_net_x18',
'en_x32' => 'constant5_op_net_x19',
'en_x4' => 'constant5_op_net_x5',
'en_x5' => 'constant5_op_net_x6',
'en_x6' => 'constant5_op_net_x7',
'en_x7' => 'constant5_op_net_x8',
'en_x8' => 'constant5_op_net_x9',
'en_x9' => 'constant5_op_net_x10',
'reg01_rd' => 'from_register3_data_out_net_x0',
'reg01_rv' => 'from_register1_data_out_net_x0',
'reg01_td' => 'reg01_td_net',
'reg01_tv' => 'reg01_tv_net',
'reg02_rd' => 'from_register5_data_out_net_x0',
'reg02_rv' => 'from_register2_data_out_net_x0',
'reg02_td' => 'reg02_td_net',
'reg02_tv' => 'reg02_tv_net',
'reg03_rd' => 'from_register7_data_out_net_x0',
'reg03_rv' => 'from_register6_data_out_net_x0',
'reg03_td' => 'reg03_td_net',
'reg03_tv' => 'reg03_tv_net',
'reg04_rd' => 'from_register8_data_out_net_x0',
'reg04_rv' => 'from_register4_data_out_net_x0',
'reg04_td' => 'reg04_td_net',
'reg04_tv' => 'reg04_tv_net',
'reg05_rd' => 'from_register10_data_out_net_x0',
'reg05_rv' => 'from_register9_data_out_net_x0',
'reg05_td' => 'reg05_td_net',
'reg05_tv' => 'reg05_tv_net',
'reg06_rd' => 'from_register11_data_out_net_x0',
'reg06_rv' => 'from_register12_data_out_net_x0',
'reg06_td' => 'reg06_td_net',
'reg06_tv' => 'reg06_tv_net',
'reg07_rd' => 'from_register13_data_out_net_x0',
'reg07_rv' => 'from_register14_data_out_net_x0',
'reg07_td' => 'reg07_td_net',
'reg07_tv' => 'reg07_tv_net',
'reg08_rd' => 'from_register15_data_out_net_x0',
'reg08_rv' => 'from_register16_data_out_net_x0',
'reg08_td' => 'reg08_td_net',
'reg08_tv' => 'reg08_tv_net',
'reg09_rd' => 'from_register17_data_out_net_x0',
'reg09_rv' => 'from_register18_data_out_net_x0',
'reg09_td' => 'reg09_td_net',
'reg09_tv' => 'reg09_tv_net',
'reg10_rd' => 'from_register19_data_out_net_x0',
'reg10_rv' => 'from_register20_data_out_net_x0',
'reg10_td' => 'reg10_td_net',
'reg10_tv' => 'reg10_tv_net',
'reg11_rd' => 'from_register21_data_out_net_x0',
'reg11_rv' => 'from_register22_data_out_net_x0',
'reg11_td' => 'reg11_td_net',
'reg11_tv' => 'reg11_tv_net',
'reg12_rd' => 'from_register23_data_out_net_x0',
'reg12_rv' => 'from_register24_data_out_net_x0',
'reg12_td' => 'reg12_td_net',
'reg12_tv' => 'reg12_tv_net',
'reg13_rd' => 'from_register25_data_out_net_x0',
'reg13_rv' => 'from_register26_data_out_net_x0',
'reg13_td' => 'reg13_td_net',
'reg13_tv' => 'reg13_tv_net',
'reg14_rd' => 'from_register27_data_out_net_x0',
'reg14_rv' => 'from_register28_data_out_net_x0',
'reg14_td' => 'reg14_td_net',
'reg14_tv' => 'reg14_tv_net',
},
'entity' => {
'attributes' => {
'entityAlreadyNetlisted' => 1,
'hdlKind' => 'vhdl',
'isDesign' => 1,
'simulinkName' => 'INOUT_LOGIC',
},
'entityName' => 'inout_logic',
'ports' => {
'data_in' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x0' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x1' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x10' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x11' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x12' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x13' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x14' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x15' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x16' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'Bool',
},
'direction' => 'out',
'hdlType' => 'std_logic',
'width' => 1,
},
'data_in_x17' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
'port_id' => 0,
'simulinkName' => 'INOUT_LOGIC/data_in',
'type' => 'UFix_32_0',
},
'direction' => 'out',
'hdlType' => 'std_logic_vector(31 downto 0)',
'width' => 32,
},
'data_in_x18' => {
'attributes' => {
'bin_pt' => 0,
'is_floating_block' => 1,
'must_be_hdl_vector' => 1,
'period' => 1,
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'reg06_rd' => {
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'reg13_rd' => {
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'reg13_rv' => {
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'reg13_td' => {
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'reg13_tv' => {
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