URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk
Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [PCIe_UserLogic_00.cdc] - Rev 13

Compare with Previous | Blame | View Log
#ChipScope Core Generator Project File Version 3.0
# Produced by System Generator
SignalExport.clockChannel=CLK
SignalExport.bus<0>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 
SignalExport.bus<0>.name=BRAM_addr
SignalExport.bus<0>.offset=0.0
SignalExport.bus<0>.precision=0
SignalExport.bus<0>.radix=Unsigned
SignalExport.bus<0>.scaleFactor=1.0
SignalExport.bus<1>.channelList=12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 
SignalExport.bus<1>.name=BRAM_data
SignalExport.bus<1>.offset=0.0
SignalExport.bus<1>.precision=0
SignalExport.bus<1>.radix=Unsigned
SignalExport.bus<1>.scaleFactor=1.0
SignalExport.bus<2>.channelList=76 
SignalExport.bus<2>.name=FIFO_empty
SignalExport.bus<2>.offset=0.0
SignalExport.bus<2>.precision=0
SignalExport.bus<2>.radix=Unsigned
SignalExport.bus<2>.scaleFactor=1.0
SignalExport.bus<3>.channelList=77 
SignalExport.bus<3>.name=FIFo_rd_en
SignalExport.bus<3>.offset=0.0
SignalExport.bus<3>.precision=0
SignalExport.bus<3>.radix=Unsigned
SignalExport.bus<3>.scaleFactor=1.0
SignalExport.bus<4>.channelList=78 
SignalExport.bus<4>.name=FIFO_wr_en
SignalExport.bus<4>.offset=0.0
SignalExport.bus<4>.precision=0
SignalExport.bus<4>.radix=Unsigned
SignalExport.bus<4>.scaleFactor=1.0
SignalExport.bus<5>.channelList=79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 
SignalExport.bus<5>.name=FIFO_data_in_out
SignalExport.bus<5>.offset=0.0
SignalExport.bus<5>.precision=0
SignalExport.bus<5>.radix=Unsigned
SignalExport.bus<5>.scaleFactor=1.0
SignalExport.bus<6>.channelList=151 
SignalExport.bus<6>.name=FIFO_rd_pempty
SignalExport.bus<6>.offset=0.0
SignalExport.bus<6>.precision=0
SignalExport.bus<6>.radix=Unsigned
SignalExport.bus<6>.scaleFactor=1.0
SignalExport.bus<7>.channelList=152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 
SignalExport.bus<7>.name=FIFO_rd_count
SignalExport.bus<7>.offset=0.0
SignalExport.bus<7>.precision=0
SignalExport.bus<7>.radix=Unsigned
SignalExport.bus<7>.scaleFactor=1.0
SignalExport.bus<8>.channelList=167 
SignalExport.bus<8>.name=FIFO_wr_full
SignalExport.bus<8>.offset=0.0
SignalExport.bus<8>.precision=0
SignalExport.bus<8>.radix=Unsigned
SignalExport.bus<8>.scaleFactor=1.0
SignalExport.bus<9>.channelList=168 
SignalExport.bus<9>.name=FIFO_wr_pfull
SignalExport.bus<9>.offset=0.0
SignalExport.bus<9>.precision=0
SignalExport.bus<9>.radix=Unsigned
SignalExport.bus<9>.scaleFactor=1.0
SignalExport.bus<10>.channelList=169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 
SignalExport.bus<10>.name=FIFO_wr_count
SignalExport.bus<10>.offset=0.0
SignalExport.bus<10>.precision=0
SignalExport.bus<10>.radix=Unsigned
SignalExport.bus<10>.scaleFactor=1.0
SignalExport.dataEqualsTrigger=true
SignalExport.triggerPortIsData<0>=true
SignalExport.triggerPortIsData<1>=true
SignalExport.triggerPortIsData<2>=true
SignalExport.triggerPortIsData<3>=true
SignalExport.triggerPortIsData<4>=true
SignalExport.triggerPortIsData<5>=true
SignalExport.triggerPortIsData<6>=true
SignalExport.triggerPortIsData<7>=true
SignalExport.triggerPortIsData<8>=true
SignalExport.triggerPortIsData<9>=true
SignalExport.triggerPortIsData<10>=true
SignalExport.triggerChannel<0><000>=BRAM_addr[0]
SignalExport.triggerChannel<0><001>=BRAM_addr[1]
SignalExport.triggerChannel<0><002>=BRAM_addr[2]
SignalExport.triggerChannel<0><003>=BRAM_addr[3]
SignalExport.triggerChannel<0><004>=BRAM_addr[4]
SignalExport.triggerChannel<0><005>=BRAM_addr[5]
SignalExport.triggerChannel<0><006>=BRAM_addr[6]
SignalExport.triggerChannel<0><007>=BRAM_addr[7]
SignalExport.triggerChannel<0><008>=BRAM_addr[8]
SignalExport.triggerChannel<0><009>=BRAM_addr[9]
SignalExport.triggerChannel<0><010>=BRAM_addr[10]
SignalExport.triggerChannel<0><011>=BRAM_addr[11]
SignalExport.triggerChannel<1><000>=BRAM_data[0]
SignalExport.triggerChannel<1><001>=BRAM_data[1]
SignalExport.triggerChannel<1><002>=BRAM_data[2]
SignalExport.triggerChannel<1><003>=BRAM_data[3]
SignalExport.triggerChannel<1><004>=BRAM_data[4]
SignalExport.triggerChannel<1><005>=BRAM_data[5]
SignalExport.triggerChannel<1><006>=BRAM_data[6]
SignalExport.triggerChannel<1><007>=BRAM_data[7]
SignalExport.triggerChannel<1><008>=BRAM_data[8]
SignalExport.triggerChannel<1><009>=BRAM_data[9]
SignalExport.triggerChannel<1><010>=BRAM_data[10]
SignalExport.triggerChannel<1><011>=BRAM_data[11]
SignalExport.triggerChannel<1><012>=BRAM_data[12]
SignalExport.triggerChannel<1><013>=BRAM_data[13]
SignalExport.triggerChannel<1><014>=BRAM_data[14]
SignalExport.triggerChannel<1><015>=BRAM_data[15]
SignalExport.triggerChannel<1><016>=BRAM_data[16]
SignalExport.triggerChannel<1><017>=BRAM_data[17]
SignalExport.triggerChannel<1><018>=BRAM_data[18]
SignalExport.triggerChannel<1><019>=BRAM_data[19]
SignalExport.triggerChannel<1><020>=BRAM_data[20]
SignalExport.triggerChannel<1><021>=BRAM_data[21]
SignalExport.triggerChannel<1><022>=BRAM_data[22]
SignalExport.triggerChannel<1><023>=BRAM_data[23]
SignalExport.triggerChannel<1><024>=BRAM_data[24]
SignalExport.triggerChannel<1><025>=BRAM_data[25]
SignalExport.triggerChannel<1><026>=BRAM_data[26]
SignalExport.triggerChannel<1><027>=BRAM_data[27]
SignalExport.triggerChannel<1><028>=BRAM_data[28]
SignalExport.triggerChannel<1><029>=BRAM_data[29]
SignalExport.triggerChannel<1><030>=BRAM_data[30]
SignalExport.triggerChannel<1><031>=BRAM_data[31]
SignalExport.triggerChannel<1><032>=BRAM_data[32]
SignalExport.triggerChannel<1><033>=BRAM_data[33]
SignalExport.triggerChannel<1><034>=BRAM_data[34]
SignalExport.triggerChannel<1><035>=BRAM_data[35]
SignalExport.triggerChannel<1><036>=BRAM_data[36]
SignalExport.triggerChannel<1><037>=BRAM_data[37]
SignalExport.triggerChannel<1><038>=BRAM_data[38]
SignalExport.triggerChannel<1><039>=BRAM_data[39]
SignalExport.triggerChannel<1><040>=BRAM_data[40]
SignalExport.triggerChannel<1><041>=BRAM_data[41]
SignalExport.triggerChannel<1><042>=BRAM_data[42]
SignalExport.triggerChannel<1><043>=BRAM_data[43]
SignalExport.triggerChannel<1><044>=BRAM_data[44]
SignalExport.triggerChannel<1><045>=BRAM_data[45]
SignalExport.triggerChannel<1><046>=BRAM_data[46]
SignalExport.triggerChannel<1><047>=BRAM_data[47]
SignalExport.triggerChannel<1><048>=BRAM_data[48]
SignalExport.triggerChannel<1><049>=BRAM_data[49]
SignalExport.triggerChannel<1><050>=BRAM_data[50]
SignalExport.triggerChannel<1><051>=BRAM_data[51]
SignalExport.triggerChannel<1><052>=BRAM_data[52]
SignalExport.triggerChannel<1><053>=BRAM_data[53]
SignalExport.triggerChannel<1><054>=BRAM_data[54]
SignalExport.triggerChannel<1><055>=BRAM_data[55]
SignalExport.triggerChannel<1><056>=BRAM_data[56]
SignalExport.triggerChannel<1><057>=BRAM_data[57]
SignalExport.triggerChannel<1><058>=BRAM_data[58]
SignalExport.triggerChannel<1><059>=BRAM_data[59]
SignalExport.triggerChannel<1><060>=BRAM_data[60]
SignalExport.triggerChannel<1><061>=BRAM_data[61]
SignalExport.triggerChannel<1><062>=BRAM_data[62]
SignalExport.triggerChannel<1><063>=BRAM_data[63]
SignalExport.triggerChannel<2><000>=FIFO_empty[0]
SignalExport.triggerChannel<3><000>=FIFo_rd_en[0]
SignalExport.triggerChannel<4><000>=FIFO_wr_en[0]
SignalExport.triggerChannel<5><000>=FIFO_data_in_out[0]
SignalExport.triggerChannel<5><001>=FIFO_data_in_out[1]
SignalExport.triggerChannel<5><002>=FIFO_data_in_out[2]
SignalExport.triggerChannel<5><003>=FIFO_data_in_out[3]
SignalExport.triggerChannel<5><004>=FIFO_data_in_out[4]
SignalExport.triggerChannel<5><005>=FIFO_data_in_out[5]
SignalExport.triggerChannel<5><006>=FIFO_data_in_out[6]
SignalExport.triggerChannel<5><007>=FIFO_data_in_out[7]
SignalExport.triggerChannel<5><008>=FIFO_data_in_out[8]
SignalExport.triggerChannel<5><009>=FIFO_data_in_out[9]
SignalExport.triggerChannel<5><010>=FIFO_data_in_out[10]
SignalExport.triggerChannel<5><011>=FIFO_data_in_out[11]
SignalExport.triggerChannel<5><012>=FIFO_data_in_out[12]
SignalExport.triggerChannel<5><013>=FIFO_data_in_out[13]
SignalExport.triggerChannel<5><014>=FIFO_data_in_out[14]
SignalExport.triggerChannel<5><015>=FIFO_data_in_out[15]
SignalExport.triggerChannel<5><016>=FIFO_data_in_out[16]
SignalExport.triggerChannel<5><017>=FIFO_data_in_out[17]
SignalExport.triggerChannel<5><018>=FIFO_data_in_out[18]
SignalExport.triggerChannel<5><019>=FIFO_data_in_out[19]
SignalExport.triggerChannel<5><020>=FIFO_data_in_out[20]
SignalExport.triggerChannel<5><021>=FIFO_data_in_out[21]
SignalExport.triggerChannel<5><022>=FIFO_data_in_out[22]
SignalExport.triggerChannel<5><023>=FIFO_data_in_out[23]
SignalExport.triggerChannel<5><024>=FIFO_data_in_out[24]
SignalExport.triggerChannel<5><025>=FIFO_data_in_out[25]
SignalExport.triggerChannel<5><026>=FIFO_data_in_out[26]
SignalExport.triggerChannel<5><027>=FIFO_data_in_out[27]
SignalExport.triggerChannel<5><028>=FIFO_data_in_out[28]
SignalExport.triggerChannel<5><029>=FIFO_data_in_out[29]
SignalExport.triggerChannel<5><030>=FIFO_data_in_out[30]
SignalExport.triggerChannel<5><031>=FIFO_data_in_out[31]
SignalExport.triggerChannel<5><032>=FIFO_data_in_out[32]
SignalExport.triggerChannel<5><033>=FIFO_data_in_out[33]
SignalExport.triggerChannel<5><034>=FIFO_data_in_out[34]
SignalExport.triggerChannel<5><035>=FIFO_data_in_out[35]
SignalExport.triggerChannel<5><036>=FIFO_data_in_out[36]
SignalExport.triggerChannel<5><037>=FIFO_data_in_out[37]
SignalExport.triggerChannel<5><038>=FIFO_data_in_out[38]
SignalExport.triggerChannel<5><039>=FIFO_data_in_out[39]
SignalExport.triggerChannel<5><040>=FIFO_data_in_out[40]
SignalExport.triggerChannel<5><041>=FIFO_data_in_out[41]
SignalExport.triggerChannel<5><042>=FIFO_data_in_out[42]
SignalExport.triggerChannel<5><043>=FIFO_data_in_out[43]
SignalExport.triggerChannel<5><044>=FIFO_data_in_out[44]
SignalExport.triggerChannel<5><045>=FIFO_data_in_out[45]
SignalExport.triggerChannel<5><046>=FIFO_data_in_out[46]
SignalExport.triggerChannel<5><047>=FIFO_data_in_out[47]
SignalExport.triggerChannel<5><048>=FIFO_data_in_out[48]
SignalExport.triggerChannel<5><049>=FIFO_data_in_out[49]
SignalExport.triggerChannel<5><050>=FIFO_data_in_out[50]
SignalExport.triggerChannel<5><051>=FIFO_data_in_out[51]
SignalExport.triggerChannel<5><052>=FIFO_data_in_out[52]
SignalExport.triggerChannel<5><053>=FIFO_data_in_out[53]
SignalExport.triggerChannel<5><054>=FIFO_data_in_out[54]
SignalExport.triggerChannel<5><055>=FIFO_data_in_out[55]
SignalExport.triggerChannel<5><056>=FIFO_data_in_out[56]
SignalExport.triggerChannel<5><057>=FIFO_data_in_out[57]
SignalExport.triggerChannel<5><058>=FIFO_data_in_out[58]
SignalExport.triggerChannel<5><059>=FIFO_data_in_out[59]
SignalExport.triggerChannel<5><060>=FIFO_data_in_out[60]
SignalExport.triggerChannel<5><061>=FIFO_data_in_out[61]
SignalExport.triggerChannel<5><062>=FIFO_data_in_out[62]
SignalExport.triggerChannel<5><063>=FIFO_data_in_out[63]
SignalExport.triggerChannel<5><064>=FIFO_data_in_out[64]
SignalExport.triggerChannel<5><065>=FIFO_data_in_out[65]
SignalExport.triggerChannel<5><066>=FIFO_data_in_out[66]
SignalExport.triggerChannel<5><067>=FIFO_data_in_out[67]
SignalExport.triggerChannel<5><068>=FIFO_data_in_out[68]
SignalExport.triggerChannel<5><069>=FIFO_data_in_out[69]
SignalExport.triggerChannel<5><070>=FIFO_data_in_out[70]
SignalExport.triggerChannel<5><071>=FIFO_data_in_out[71]
SignalExport.triggerChannel<6><000>=FIFO_rd_pempty[0]
SignalExport.triggerChannel<7><000>=FIFO_rd_count[0]
SignalExport.triggerChannel<7><001>=FIFO_rd_count[1]
SignalExport.triggerChannel<7><002>=FIFO_rd_count[2]
SignalExport.triggerChannel<7><003>=FIFO_rd_count[3]
SignalExport.triggerChannel<7><004>=FIFO_rd_count[4]
SignalExport.triggerChannel<7><005>=FIFO_rd_count[5]
SignalExport.triggerChannel<7><006>=FIFO_rd_count[6]
SignalExport.triggerChannel<7><007>=FIFO_rd_count[7]
SignalExport.triggerChannel<7><008>=FIFO_rd_count[8]
SignalExport.triggerChannel<7><009>=FIFO_rd_count[9]
SignalExport.triggerChannel<7><010>=FIFO_rd_count[10]
SignalExport.triggerChannel<7><011>=FIFO_rd_count[11]
SignalExport.triggerChannel<7><012>=FIFO_rd_count[12]
SignalExport.triggerChannel<7><013>=FIFO_rd_count[13]
SignalExport.triggerChannel<7><014>=FIFO_rd_count[14]
SignalExport.triggerChannel<8><000>=FIFO_wr_full[0]
SignalExport.triggerChannel<9><000>=FIFO_wr_pfull[0]
SignalExport.triggerChannel<10><000>=FIFO_wr_count[0]
SignalExport.triggerChannel<10><001>=FIFO_wr_count[1]
SignalExport.triggerChannel<10><002>=FIFO_wr_count[2]
SignalExport.triggerChannel<10><003>=FIFO_wr_count[3]
SignalExport.triggerChannel<10><004>=FIFO_wr_count[4]
SignalExport.triggerChannel<10><005>=FIFO_wr_count[5]
SignalExport.triggerChannel<10><006>=FIFO_wr_count[6]
SignalExport.triggerChannel<10><007>=FIFO_wr_count[7]
SignalExport.triggerChannel<10><008>=FIFO_wr_count[8]
SignalExport.triggerChannel<10><009>=FIFO_wr_count[9]
SignalExport.triggerChannel<10><010>=FIFO_wr_count[10]
SignalExport.triggerChannel<10><011>=FIFO_wr_count[11]
SignalExport.triggerChannel<10><012>=FIFO_wr_count[12]
SignalExport.triggerChannel<10><013>=FIFO_wr_count[13]
SignalExport.triggerChannel<10><014>=FIFO_wr_count[14]
SignalExport.triggerPort<0>.name=BRAM_addr
SignalExport.triggerPort<1>.name=BRAM_data
SignalExport.triggerPort<2>.name=FIFO_empty
SignalExport.triggerPort<3>.name=FIFo_rd_en
SignalExport.triggerPort<4>.name=FIFO_wr_en
SignalExport.triggerPort<5>.name=FIFO_data_in_out
SignalExport.triggerPort<6>.name=FIFO_rd_pempty
SignalExport.triggerPort<7>.name=FIFO_rd_count
SignalExport.triggerPort<8>.name=FIFO_wr_full
SignalExport.triggerPort<9>.name=FIFO_wr_pfull
SignalExport.triggerPort<10>.name=FIFO_wr_count
SignalExport.triggerPortCount=11
SignalExport.triggerPortWidth<0>=12
SignalExport.triggerPortWidth<1>=64
SignalExport.triggerPortWidth<2>=1
SignalExport.triggerPortWidth<3>=1
SignalExport.triggerPortWidth<4>=1
SignalExport.triggerPortWidth<5>=72
SignalExport.triggerPortWidth<6>=1
SignalExport.triggerPortWidth<7>=15
SignalExport.triggerPortWidth<8>=1
SignalExport.triggerPortWidth<9>=1
SignalExport.triggerPortWidth<10>=15
SignalExport.type=ila
Compare with Previous | Blame | View Log
Browse

Tools

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [PCIe_UserLogic_00.cdc] - Rev 13
