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https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk
Subversion Repositories pcie_sg_dma
[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [synth_model/] [_xmsgs/] [ngcbuild.xmsgs] - Rev 13
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="ConstraintSystem" num="191" delta="new" >The <arg fmt="%s" index="1">TNM</arg> '<arg fmt="%s" index="2">clk_5cc36873</arg>', does not directly or indirectly drive any flip-flops, latches and/or RAMS and cannot be actively used by the referencing <arg fmt="%s" index="3">Period</arg> constraint '<arg fmt="%s" index="4">TS_clk_5cc36873</arg>'. If clock manager blocks are directly or indirectly driven, a new TNM constraint will not be derived even though the referencing constraint is a PERIOD constraint unless an output of the clock manager drives flip-flops, latches or RAMs. This TNM is used in the following user PERIOD specification:
<arg fmt="%s" index="5"><TIMESPEC "TS_clk_5cc36873" = PERIOD "clk_5cc36873" 5.0 ns HIGH 50 %;> [user_logic_cw.ucf(5)]
</arg></msg>
<msg type="warning" file="ConstraintSystem" num="197" delta="new" >The following specification is invalid because the referenced TNM constraint was removed:
<arg fmt="%s" index="1"><TIMESPEC "TS_clk_5cc36873" = PERIOD "clk_5cc36873" 5.0 ns HIGH 50 %;> [user_logic_cw.ucf(5)]</arg>
</msg>
<msg type="warning" file="NgdBuild" num="981" delta="new" >Could not find any associations for the following constraint:
'<arg fmt="%s" index="1"><NET "clk" TNM_NET = "clk_5cc36873";> [user_logic_cw.ucf(4)]</arg>'
</msg>
</messages>