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-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file cntr_11_0_341fbb8cfa0e669e.vhd when simulating -- the core, cntr_11_0_341fbb8cfa0e669e. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY cntr_11_0_341fbb8cfa0e669e IS PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END cntr_11_0_341fbb8cfa0e669e; ARCHITECTURE cntr_11_0_341fbb8cfa0e669e_a OF cntr_11_0_341fbb8cfa0e669e IS -- synthesis translate_off COMPONENT wrapped_cntr_11_0_341fbb8cfa0e669e PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; sinit : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_cntr_11_0_341fbb8cfa0e669e USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral) GENERIC MAP ( c_ainit_val => "0", c_ce_overrides_sync => 0, c_count_by => "1", c_count_mode => 0, c_count_to => "1", c_fb_latency => 0, c_has_ce => 1, c_has_load => 0, c_has_sclr => 0, c_has_sinit => 1, c_has_sset => 0, c_has_thresh0 => 0, c_implementation => 0, c_latency => 1, c_load_low => 0, c_restrict_count => 0, c_sclr_overrides_sset => 1, c_sinit_val => "0", c_thresh0_value => "1", c_verbosity => 0, c_width => 12, c_xdevicefamily => "virtex6" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_cntr_11_0_341fbb8cfa0e669e PORT MAP ( clk => clk, ce => ce, sinit => sinit, q => q ); -- synthesis translate_on END cntr_11_0_341fbb8cfa0e669e_a; ------------------------------------------------------------------------------- -- Copyright (c) 2012 Xilinx, Inc. -- All Rights Reserved ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 13.3 -- \ \ Application: XILINX CORE Generator -- / / Filename : icon_1_06_a_87e2f476e984e565.vhd -- /___/ /\ Timestamp : Tue Feb 07 11:26:21 ora solare Europa occidentale 2012 -- \ \ / \ -- \___\/\___\ -- -- Design Name: VHDL Synthesis Wrapper ------------------------------------------------------------------------------- -- This wrapper is used to integrate with Project Navigator and PlanAhead LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY icon_1_06_a_87e2f476e984e565 IS port ( CONTROL0: inout std_logic_vector(35 downto 0)); END icon_1_06_a_87e2f476e984e565; ARCHITECTURE icon_1_06_a_87e2f476e984e565_a OF icon_1_06_a_87e2f476e984e565 IS BEGIN END icon_1_06_a_87e2f476e984e565_a; ------------------------------------------------------------------------------- -- Copyright (c) 2012 Xilinx, Inc. -- All Rights Reserved ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 13.3 -- \ \ Application: XILINX CORE Generator -- / / Filename : ila_1_05_a_b6735eb4b876dee5.vhd -- /___/ /\ Timestamp : Mon Mar 26 13:34:48 ora legale Europa occidentale 2012 -- \ \ / \ -- \___\/\___\ -- -- Design Name: VHDL Synthesis Wrapper ------------------------------------------------------------------------------- -- This wrapper is used to integrate with Project Navigator and PlanAhead LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY ila_1_05_a_b6735eb4b876dee5 IS port ( CONTROL: inout std_logic_vector(35 downto 0); CLK: in std_logic; TRIG0: in std_logic_vector(11 downto 0); TRIG1: in std_logic_vector(63 downto 0); TRIG2: in std_logic_vector(0 to 0); TRIG3: in std_logic_vector(0 to 0); TRIG4: in std_logic_vector(0 to 0); TRIG5: in std_logic_vector(71 downto 0); TRIG6: in std_logic_vector(0 to 0); TRIG7: in std_logic_vector(14 downto 0); TRIG8: in std_logic_vector(0 to 0); TRIG9: in std_logic_vector(0 to 0); TRIG10: in std_logic_vector(14 downto 0)); END ila_1_05_a_b6735eb4b876dee5; ARCHITECTURE ila_1_05_a_b6735eb4b876dee5_a OF ila_1_05_a_b6735eb4b876dee5 IS BEGIN END ila_1_05_a_b6735eb4b876dee5_a; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package conv_pkg is constant simulating : boolean := false -- synopsys translate_off or true -- synopsys translate_on ; constant xlUnsigned : integer := 1; constant xlSigned : integer := 2; constant xlFloat : integer := 3; constant xlWrap : integer := 1; constant xlSaturate : integer := 2; constant xlTruncate : integer := 1; constant xlRound : integer := 2; constant xlRoundBanker : integer := 3; constant xlAddMode : integer := 1; constant xlSubMode : integer := 2; attribute black_box : boolean; attribute syn_black_box : boolean; attribute fpga_dont_touch: string; attribute box_type : string; attribute keep : string; attribute syn_keep : boolean; function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; function std_logic_vector_to_signed(inp : std_logic_vector) return signed; function signed_to_std_logic_vector(inp : signed) return std_logic_vector; function unsigned_to_signed(inp : unsigned) return signed; function signed_to_unsigned(inp : signed) return unsigned; function pos(inp : std_logic_vector; arith : INTEGER) return boolean; function all_same(inp: std_logic_vector) return boolean; function all_zeros(inp: std_logic_vector) return boolean; function is_point_five(inp: std_logic_vector) return boolean; function all_ones(inp: std_logic_vector) return boolean; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function shift_division_result(quotient, fraction: std_logic_vector; fraction_width, shift_value, shift_dir: INTEGER) return std_logic_vector; function shift_op (inp: std_logic_vector; result_width, shift_value, shift_dir: INTEGER) return std_logic_vector; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function max_signed(width : INTEGER) return std_logic_vector; function min_signed(width : INTEGER) return std_logic_vector; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width: integer) return std_logic_vector; function pad_LSB(inp : std_logic_vector; new_width, arith : integer) return std_logic_vector; function max(L, R: INTEGER) return INTEGER; function min(L, R: INTEGER) return INTEGER; function "="(left,right: STRING) return boolean; function boolean_to_signed (inp : boolean; width: integer) return signed; function boolean_to_unsigned (inp : boolean; width: integer) return unsigned; function boolean_to_vector (inp : boolean) return std_logic_vector; function std_logic_to_vector (inp : std_logic) return std_logic_vector; function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer; function std_logic_to_integer(constant inp : std_logic := '0') return integer; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector; function hex_string_to_std_logic_vector (inp : string; width : integer) return std_logic_vector; function makeZeroBinStr (width : integer) return STRING; function and_reduce(inp: std_logic_vector) return std_logic; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean; function is_binary_string_undefined (inp : string) return boolean; function is_XorU(inp : std_logic_vector) return boolean; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector; function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector; constant display_precision : integer := 20; function real_to_string (inp : real) return string; function valid_bin_string(inp : string) return boolean; function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; function std_logic_to_bin_string(inp : std_logic) return string; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string; type stdlogic_to_char_t is array(std_logic) of character; constant to_char : stdlogic_to_char_t := ( 'U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-'); -- synopsys translate_on end conv_pkg; package body conv_pkg is function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned is begin return unsigned (inp); end; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector is begin return std_logic_vector(inp); end; function std_logic_vector_to_signed(inp : std_logic_vector) return signed is begin return signed (inp); end; function signed_to_std_logic_vector(inp : signed) return std_logic_vector is begin return std_logic_vector(inp); end; function unsigned_to_signed (inp : unsigned) return signed is begin return signed(std_logic_vector(inp)); end; function signed_to_unsigned (inp : signed) return unsigned is begin return unsigned(std_logic_vector(inp)); end; function pos(inp : std_logic_vector; arith : INTEGER) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; if arith = xlUnsigned then return true; else if vec(width-1) = '0' then return true; else return false; end if; end if; return true; end; function max_signed(width : INTEGER) return std_logic_vector is variable ones : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin ones := (others => '1'); result(width-1) := '0'; result(width-2 downto 0) := ones; return result; end; function min_signed(width : INTEGER) return std_logic_vector is variable zeros : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin zeros := (others => '0'); result(width-1) := '1'; result(width-2 downto 0) := zeros; return result; end; function and_reduce(inp: std_logic_vector) return std_logic is variable result: std_logic; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := vec(0); if width > 1 then for i in 1 to width-1 loop result := result and vec(i); end loop; end if; return result; end; function all_same(inp: std_logic_vector) return boolean is variable result: boolean; constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); begin vec := inp; result := true; if width > 0 then for i in 1 to width-1 loop if vec(i) /= vec(0) then result := false; end if; end loop; end if; return result; end; function all_zeros(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable zero : std_logic_vector(width-1 downto 0); variable result : boolean; begin zero := (others => '0'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then result := true; else result := false; end if; return result; end; function is_point_five(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (width > 1) then if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then result := true; else result := false; end if; else if (vec(width-1) = '1') then result := true; else result := false; end if; end if; return result; end; function all_ones(inp: std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable one : std_logic_vector(width-1 downto 0); variable result : boolean; begin one := (others => '1'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then result := true; else result := false; end if; return result; end; function full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable result : integer; begin result := old_width + 2; return result; end; function quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return integer is variable right_of_dp, left_of_dp, result : integer; begin right_of_dp := max(new_bin_pt, old_bin_pt); left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); result := (old_width + 2) + (new_bin_pt - old_bin_pt); return result; end; function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith, quantization, overflow : INTEGER) return std_logic_vector is constant fp_width : integer := full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant fp_bin_pt : integer := old_bin_pt; constant fp_arith : integer := old_arith; variable full_precision_result : std_logic_vector(fp_width-1 downto 0); constant q_width : integer := quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith); constant q_bin_pt : integer := new_bin_pt; constant q_arith : integer := old_arith; variable quantized_result : std_logic_vector(q_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin result := (others => '0'); full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, fp_arith); if (quantization = xlRound) then quantized_result := round_towards_inf(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); elsif (quantization = xlRoundBanker) then quantized_result := round_towards_even(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); else quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith); end if; if (overflow = xlSaturate) then result := saturation_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); else result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); end if; return result; end; function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; constant left_of_dp : integer := (new_width - new_bin_pt) - (old_width - old_bin_pt); constant right_of_dp : integer := (new_bin_pt - old_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable j : integer; begin vec := inp; for i in new_width-1 downto 0 loop j := i - right_of_dp; if ( j > old_width-1) then if (new_arith = xlUnsigned) then result(i) := '0'; else result(i) := vec(old_width-1); end if; elsif ( j >= 0) then result(i) := vec(j); else result(i) := '0'; end if; end loop; return result; end; function shift_division_result(quotient, fraction: std_logic_vector; fraction_width, shift_value, shift_dir: INTEGER) return std_logic_vector is constant q_width : integer := quotient'length; constant f_width : integer := fraction'length; constant vec_MSB : integer := q_width+f_width-1; constant result_MSB : integer := q_width+fraction_width-1; constant result_LSB : integer := vec_MSB-result_MSB; variable vec : std_logic_vector(vec_MSB downto 0); variable result : std_logic_vector(result_MSB downto 0); begin vec := ( quotient & fraction ); if shift_dir = 1 then for i in vec_MSB downto 0 loop if (i < shift_value) then vec(i) := '0'; else vec(i) := vec(i-shift_value); end if; end loop; else for i in 0 to vec_MSB loop if (i > vec_MSB-shift_value) then vec(i) := vec(vec_MSB); else vec(i) := vec(i+shift_value); end if; end loop; end if; result := vec(vec_MSB downto result_LSB); return result; end; function shift_op (inp: std_logic_vector; result_width, shift_value, shift_dir: INTEGER) return std_logic_vector is constant inp_width : integer := inp'length; constant vec_MSB : integer := inp_width-1; constant result_MSB : integer := result_width-1; constant result_LSB : integer := vec_MSB-result_MSB; variable vec : std_logic_vector(vec_MSB downto 0); variable result : std_logic_vector(result_MSB downto 0); begin vec := inp; if shift_dir = 1 then for i in vec_MSB downto 0 loop if (i < shift_value) then vec(i) := '0'; else vec(i) := vec(i-shift_value); end if; end loop; else for i in 0 to vec_MSB loop if (i > vec_MSB-shift_value) then vec(i) := vec(vec_MSB); else vec(i) := vec(i+shift_value); end if; end loop; end if; result := vec(vec_MSB downto result_LSB); return result; end; function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector is begin return inp(upper downto lower); end; function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned is begin return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end; function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); end; function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed is begin return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned is begin return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); end; function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); end; function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector is begin return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); end; function boolean_to_signed (inp : boolean; width : integer) return signed is variable result : signed(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_unsigned (inp : boolean; width : integer) return unsigned is variable result : unsigned(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function boolean_to_vector (inp : boolean) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end; function std_logic_to_vector (inp : std_logic) return std_logic_vector is variable result : std_logic_vector(1 - 1 downto 0); begin result(0) := inp; return result; end; function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then result := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else result := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; return result; end; function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (new_arith = xlSigned) then if (vec(old_width-1) = '0') then one_or_zero(0) := '1'; end if; if (right_of_dp >= 2) and (right_of_dp <= old_width) then if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then one_or_zero(0) := '1'; end if; end if; if (right_of_dp >= 1) and (right_of_dp <= old_width) then if vec(right_of_dp-1) = '0' then one_or_zero(0) := '0'; end if; else one_or_zero(0) := '0'; end if; else if (right_of_dp >= 1) and (right_of_dp <= old_width) then one_or_zero(0) := vec(right_of_dp-1); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant right_of_dp : integer := (old_bin_pt - new_bin_pt); constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0); variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if right_of_dp >= 0 then if new_arith = xlUnsigned then truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if; else if new_arith = xlUnsigned then truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if; end if; one_or_zero := (others => '0'); if (right_of_dp >= 1) and (right_of_dp <= old_width) then if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then one_or_zero(0) := vec(right_of_dp-1); else one_or_zero(0) := vec(right_of_dp); end if; end if; if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end; function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is constant left_of_dp : integer := (old_width - old_bin_pt) - (new_width - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable overflow : boolean; begin vec := inp; overflow := true; result := (others => '0'); if (new_width >= old_width) then overflow := false; end if; if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if (old_arith = xlSigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then if (vec(new_width-1) = '0') then overflow := false; end if; end if; end if; end if; if (old_arith = xlUnsigned and new_arith = xlUnsigned) then if (old_width > new_width) then if all_zeros(vec(old_width-1 downto new_width)) then overflow := false; end if; else if (old_width = new_width) then overflow := false; end if; end if; end if; if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then if all_same(vec(old_width-1 downto new_width-1)) then overflow := false; end if; end if; if overflow then if new_arith = xlSigned then if vec(old_width-1) = '0' then result := max_signed(new_width); else result := min_signed(new_width); end if; else if ((old_arith = xlSigned) and vec(old_width-1) = '1') then result := (others => '0'); else result := (others => '1'); end if; end if; else if (old_arith = xlSigned) and (new_arith = xlUnsigned) then if (vec(old_width-1) = '1') then vec := (others => '0'); end if; end if; if new_width <= old_width then result := vec(new_width-1 downto 0); else if new_arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; end if; end if; return result; end; function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); variable result_arith : integer; begin if (old_arith = xlSigned) and (new_arith = xlUnsigned) then result_arith := xlSigned; end if; result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); return result; end; function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is begin return max(a_bin_pt, b_bin_pt); end; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER is begin return max(a_width - a_bin_pt, b_width - b_bin_pt); end; function pad_LSB(inp : std_logic_vector; new_width: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; constant pad_pos : integer := new_width - orig_width - 1; begin vec := inp; pos := new_width-1; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pad_pos >= 0 then for i in pad_pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := vec(old_width-1); end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector is constant old_width : integer := inp'length; variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if new_width >= old_width then result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then for i in new_width-1 downto old_width loop result(i) := '0'; end loop; end if; else result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if; return result; end; function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector is variable result : std_logic_vector(new_width-1 downto 0); begin result(0) := inp; for i in new_width-1 downto 1 loop result(i) := '0'; end loop; return result; end; function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if arith = xlUnsigned then result := zero_ext(vec, new_width); else result := sign_ext(vec, new_width); end if; return result; end; function pad_LSB(inp : std_logic_vector; new_width, arith: integer) return STD_LOGIC_VECTOR is constant orig_width : integer := inp'length; variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer; begin vec := inp; pos := new_width-1; if (arith = xlUnsigned) then result(pos) := '0'; pos := pos - 1; else result(pos) := vec(orig_width-1); pos := pos - 1; end if; if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i); pos := pos - 1; end loop; if pos >= 0 then for i in pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end; function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER) return std_logic_vector is variable vec : std_logic_vector(old_width-1 downto 0); variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin vec := inp; if delta > 0 then padded_inp := pad_LSB(vec, old_width+delta); result := extend_MSB(padded_inp, new_width, new_arith); else result := extend_MSB(vec, new_width, new_arith); end if; return result; end; function max(L, R: INTEGER) return INTEGER is begin if L > R then return L; else return R; end if; end; function min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; function "="(left,right: STRING) return boolean is begin if (left'length /= right'length) then return false; else test : for i in 1 to left'length loop if left(i) /= right(i) then return false; end if; end loop test; return true; end if; end; -- synopsys translate_off function is_binary_string_invalid (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'X' ) then result := true; end if; end loop; return result; end; function is_binary_string_undefined (inp : string) return boolean is variable vec : string(1 to inp'length); variable result : boolean; begin vec := inp; result := false; for i in 1 to vec'length loop if ( vec(i) = 'U' ) then result := true; end if; end loop; return result; end; function is_XorU(inp : std_logic_vector) return boolean is constant width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable result : boolean; begin vec := inp; result := false; for i in 0 to width-1 loop if (vec(i) = 'U') or (vec(i) = 'X') then result := true; end if; end loop; return result; end; function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real is variable vec : std_logic_vector(inp'length-1 downto 0); variable result, shift_val, undefined_real : real; variable neg_num : boolean; begin vec := inp; result := 0.0; neg_num := false; if vec(inp'length-1) = '1' then neg_num := true; end if; for i in 0 to inp'length-1 loop if vec(i) = 'U' or vec(i) = 'X' then return undefined_real; end if; if arith = xlSigned then if neg_num then if vec(i) = '0' then result := result + 2.0**i; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; else if vec(i) = '1' then result := result + 2.0**i; end if; end if; end loop; if arith = xlSigned then if neg_num then result := result + 1.0; result := result * (-1.0); end if; end if; shift_val := 2.0**(-1*bin_pt); result := result * shift_val; return result; end; function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real is variable result : real := 0.0; begin if inp = '1' then result := 1.0; end if; if arith = xlSigned then assert false report "It doesn't make sense to convert a 1 bit number to a signed real."; end if; return result; end; -- synopsys translate_on function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); begin if (arith = xlSigned) then signed_val := to_signed(inp, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(inp, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer is constant width : integer := inp'length; variable unsigned_val : unsigned(width-1 downto 0); variable signed_val : signed(width-1 downto 0); variable result : integer; begin if (arith = xlSigned) then signed_val := std_logic_vector_to_signed(inp); result := to_integer(signed_val); else unsigned_val := std_logic_vector_to_unsigned(inp); result := to_integer(unsigned_val); end if; return result; end; function std_logic_to_integer(constant inp : std_logic := '0') return integer is begin if inp = '1' then return 1; else return 0; end if; end; function makeZeroBinStr (width : integer) return STRING is variable result : string(1 to width+3); begin result(1) := '0'; result(2) := 'b'; for i in 3 to width+2 loop result(i) := '0'; end loop; result(width+3) := '.'; return result; end; -- synopsys translate_off function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector is variable result : std_logic_vector(width-1 downto 0); begin result := (others => '0'); return result; end; function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector is variable real_val : real; variable int_val : integer; variable result : std_logic_vector(width-1 downto 0) := (others => '0'); variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); variable signed_val : signed(width-1 downto 0) := (others => '0'); begin real_val := inp; int_val := integer(real_val * 2.0**(bin_pt)); if (arith = xlSigned) then signed_val := to_signed(int_val, width); result := signed_to_std_logic_vector(signed_val); else unsigned_val := to_unsigned(int_val, width); result := unsigned_to_std_logic_vector(unsigned_val); end if; return result; end; -- synopsys translate_on function valid_bin_string (inp : string) return boolean is variable vec : string(1 to inp'length); begin vec := inp; if (vec(1) = '0' and vec(2) = 'b') then return true; else return false; end if; end; function hex_string_to_std_logic_vector(inp: string; width : integer) return std_logic_vector is constant strlen : integer := inp'LENGTH; variable result : std_logic_vector(width-1 downto 0); variable bitval : std_logic_vector((strlen*4)-1 downto 0); variable posn : integer; variable ch : character; variable vec : string(1 to strlen); begin vec := inp; result := (others => '0'); posn := (strlen*4)-1; for i in 1 to strlen loop ch := vec(i); case ch is when '0' => bitval(posn downto posn-3) := "0000"; when '1' => bitval(posn downto posn-3) := "0001"; when '2' => bitval(posn downto posn-3) := "0010"; when '3' => bitval(posn downto posn-3) := "0011"; when '4' => bitval(posn downto posn-3) := "0100"; when '5' => bitval(posn downto posn-3) := "0101"; when '6' => bitval(posn downto posn-3) := "0110"; when '7' => bitval(posn downto posn-3) := "0111"; when '8' => bitval(posn downto posn-3) := "1000"; when '9' => bitval(posn downto posn-3) := "1001"; when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; when others => bitval(posn downto posn-3) := "XXXX"; -- synopsys translate_off ASSERT false REPORT "Invalid hex value" SEVERITY ERROR; -- synopsys translate_on end case; posn := posn - 4; end loop; if (width <= strlen*4) then result := bitval(width-1 downto 0); else result((strlen*4)-1 downto 0) := bitval; end if; return result; end; function bin_string_to_std_logic_vector (inp : string) return std_logic_vector is variable pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(inp'length-1 downto 0); begin vec := inp; pos := inp'length-1; result := (others => '0'); for i in 1 to vec'length loop -- synopsys translate_off if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then assert false report "Input string is larger than output std_logic_vector. Truncating output."; return result; end if; -- synopsys translate_on if vec(i) = '0' then result(pos) := '0'; pos := pos - 1; end if; if vec(i) = '1' then result(pos) := '1'; pos := pos - 1; end if; -- synopsys translate_off if (vec(i) = 'X' or vec(i) = 'U') then result(pos) := 'U'; pos := pos - 1; end if; -- synopsys translate_on end loop; return result; end; function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) return std_logic_vector is constant str_width : integer := width + 4; constant inp_len : integer := inp'length; constant num_elements : integer := (inp_len + 1)/str_width; constant reverse_index : integer := (num_elements-1) - index; variable left_pos : integer; variable right_pos : integer; variable vec : string(1 to inp'length); variable result : std_logic_vector(width-1 downto 0); begin vec := inp; result := (others => '0'); if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := 1; right_pos := width + 3; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then left_pos := (reverse_index * str_width) + 1; right_pos := left_pos + width + 2; result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); end if; return result; end; -- synopsys translate_off function std_logic_vector_to_bin_string(inp : std_logic_vector) return string is variable vec : std_logic_vector(1 to inp'length); variable result : string(vec'range); begin vec := inp; for i in vec'range loop result(i) := to_char(vec(i)); end loop; return result; end; function std_logic_to_bin_string(inp : std_logic) return string is variable result : string(1 to 3); begin result(1) := '0'; result(2) := 'b'; result(3) := to_char(inp); return result; end; function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) return string is variable width : integer := inp'length; variable vec : std_logic_vector(width-1 downto 0); variable str_pos : integer; variable result : string(1 to width+3); begin vec := inp; str_pos := 1; result(str_pos) := '0'; str_pos := 2; result(str_pos) := 'b'; str_pos := 3; for i in width-1 downto 0 loop if (((width+3) - bin_pt) = str_pos) then result(str_pos) := '.'; str_pos := str_pos + 1; end if; result(str_pos) := to_char(vec(i)); str_pos := str_pos + 1; end loop; if (bin_pt = 0) then result(str_pos) := '.'; end if; return result; end; function real_to_bin_string(inp : real; width, bin_pt, arith : integer) return string is variable result : string(1 to width); variable vec : std_logic_vector(width-1 downto 0); begin vec := real_to_std_logic_vector(inp, width, bin_pt, arith); result := std_logic_vector_to_bin_string(vec); return result; end; function real_to_string (inp : real) return string is variable result : string(1 to display_precision) := (others => ' '); begin result(real'image(inp)'range) := real'image(inp); return result; end; -- synopsys translate_on end conv_pkg; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity srl17e is generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end srl17e; architecture structural of srl17e is component SRL16E port (D : in STD_ULOGIC; CE : in STD_ULOGIC; CLK : in STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; Q : out STD_ULOGIC); end component; attribute syn_black_box of SRL16E : component is true; attribute fpga_dont_touch of SRL16E : component is "true"; component FDE port( Q : out STD_ULOGIC; D : in STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC); end component; attribute syn_black_box of FDE : component is true; attribute fpga_dont_touch of FDE : component is "true"; constant a : std_logic_vector(4 downto 0) := integer_to_std_logic_vector(latency-2,5,xlSigned); signal d_delayed : std_logic_vector(width-1 downto 0); signal srl16_out : std_logic_vector(width-1 downto 0); begin d_delayed <= d after 200 ps; reg_array : for i in 0 to width-1 generate srl16_used: if latency > 1 generate u1 : srl16e port map(clk => clk, d => d_delayed(i), q => srl16_out(i), ce => ce, a0 => a(0), a1 => a(1), a2 => a(2), a3 => a(3)); end generate; srl16_not_used: if latency <= 1 generate srl16_out(i) <= d_delayed(i); end generate; fde_used: if latency /= 0 generate u2 : fde port map(c => clk, d => srl16_out(i), q => q(i), ce => ce); end generate; fde_not_used: if latency = 0 generate q(i) <= srl16_out(i); end generate; end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg; architecture structural of synth_reg is component srl17e generic (width : integer:=16; latency : integer :=8); port (clk : in std_logic; ce : in std_logic; d : in std_logic_vector(width-1 downto 0); q : out std_logic_vector(width-1 downto 0)); end component; function calc_num_srl17es (latency : integer) return integer is variable remaining_latency : integer; variable result : integer; begin result := latency / 17; remaining_latency := latency - (result * 17); if (remaining_latency /= 0) then result := result + 1; end if; return result; end; constant complete_num_srl17es : integer := latency / 17; constant num_srl17es : integer := calc_num_srl17es(latency); constant remaining_latency : integer := latency - (complete_num_srl17es * 17); type register_array is array (num_srl17es downto 0) of std_logic_vector(width-1 downto 0); signal z : register_array; begin z(0) <= i; complete_ones : if complete_num_srl17es > 0 generate srl17e_array: for i in 0 to complete_num_srl17es-1 generate delay_comp : srl17e generic map (width => width, latency => 17) port map (clk => clk, ce => ce, d => z(i), q => z(i+1)); end generate; end generate; partial_one : if remaining_latency > 0 generate last_srl17e : srl17e generic map (width => width, latency => remaining_latency) port map (clk => clk, ce => ce, d => z(num_srl17es-1), q => z(num_srl17es)); end generate; o <= z(num_srl17es); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_reg is generic (width : integer := 8; latency : integer := 1); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end synth_reg_reg; architecture behav of synth_reg_reg is type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0); signal reg_bank : reg_array_type := (others => (others => '0')); signal reg_bank_in : reg_array_type := (others => (others => '0')); attribute syn_allow_retiming : boolean; attribute syn_srlstyle : string; attribute syn_allow_retiming of reg_bank : signal is true; attribute syn_allow_retiming of reg_bank_in : signal is true; attribute syn_srlstyle of reg_bank : signal is "registers"; attribute syn_srlstyle of reg_bank_in : signal is "registers"; begin latency_eq_0: if latency = 0 generate o <= i; end generate latency_eq_0; latency_gt_0: if latency >= 1 generate o <= reg_bank(latency-1); reg_bank_in(0) <= i; loop_gen: for idx in latency-2 downto 0 generate reg_bank_in(idx+1) <= reg_bank(idx); end generate loop_gen; sync_loop: for sync_idx in latency-1 downto 0 generate sync_proc: process (clk) begin if clk'event and clk = '1' then if clr = '1' then reg_bank_in <= (others => (others => '0')); elsif ce = '1' then reg_bank(sync_idx) <= reg_bank_in(sync_idx); end if; end if; end process sync_proc; end generate sync_loop; end generate latency_gt_0; end behav; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity single_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end single_reg_w_init; architecture structural of single_reg_w_init is function build_init_const(width: integer; init_index: integer; init_value: bit_vector) return std_logic_vector is variable result: std_logic_vector(width - 1 downto 0); begin if init_index = 0 then result := (others => '0'); elsif init_index = 1 then result := (others => '0'); result(0) := '1'; else result := to_stdlogicvector(init_value); end if; return result; end; component fdre port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; r: in std_ulogic ); end component; attribute syn_black_box of fdre: component is true; attribute fpga_dont_touch of fdre: component is "true"; component fdse port ( q: out std_ulogic; d: in std_ulogic; c: in std_ulogic; ce: in std_ulogic; s: in std_ulogic ); end component; attribute syn_black_box of fdse: component is true; attribute fpga_dont_touch of fdse: component is "true"; constant init_const: std_logic_vector(width - 1 downto 0) := build_init_const(width, init_index, init_value); begin fd_prim_array: for index in 0 to width - 1 generate bit_is_0: if (init_const(index) = '0') generate fdre_comp: fdre port map ( c => clk, d => i(index), q => o(index), ce => ce, r => clr ); end generate; bit_is_1: if (init_const(index) = '1') generate fdse_comp: fdse port map ( c => clk, d => i(index), q => o(index), ce => ce, s => clr ); end generate; end generate; end architecture structural; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity synth_reg_w_init is generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000"; latency: integer := 1 ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end synth_reg_w_init; architecture structural of synth_reg_w_init is component single_reg_w_init generic ( width: integer := 8; init_index: integer := 0; init_value: bit_vector := b"0000" ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); signal dly_clr: std_logic; begin latency_eq_0: if (latency = 0) generate o <= i; end generate; latency_gt_0: if (latency >= 1) generate dly_i((latency + 1) * width - 1 downto latency * width) <= i after 200 ps; dly_clr <= clr after 200 ps; fd_array: for index in latency downto 1 generate reg_comp: single_reg_w_init generic map ( width => width, init_index => init_index, init_value => init_value ) port map ( clk => clk, i => dly_i((index + 1) * width - 1 downto index * width), o => dly_i(index * width - 1 downto (index - 1) * width), ce => ce, clr => dly_clr ); end generate; o <= dly_i(width - 1 downto 0); end generate; end structural; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_963ed6358a is port ( op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_963ed6358a; architecture behavior of constant_963ed6358a is begin op <= "0"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_6293007044 is port ( op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_6293007044; architecture behavior of constant_6293007044 is begin op <= "1"; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity constant_19562ab42f is port ( op : out std_logic_vector((8 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end constant_19562ab42f; architecture behavior of constant_19562ab42f is begin op <= "11111111"; end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity convert_func_call is generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); result : out std_logic_vector (dout_width-1 downto 0)); end convert_func_call; architecture behavior of convert_func_call is begin result <= convert_type(din, din_width, din_bin_pt, din_arith, dout_width, dout_bin_pt, dout_arith, quantization, overflow); end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlconvert is generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; en_width : integer := 1; en_bin_pt : integer := 0; en_arith : integer := xlUnsigned; bool_conversion : integer :=0; latency : integer := 0; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); en : in std_logic_vector (en_width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; dout : out std_logic_vector (dout_width-1 downto 0)); end xlconvert; architecture behavior of xlconvert is component synth_reg generic (width : integer; latency : integer); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end component; component convert_func_call generic ( din_width : integer := 16; din_bin_pt : integer := 4; din_arith : integer := xlUnsigned; dout_width : integer := 8; dout_bin_pt : integer := 2; dout_arith : integer := xlUnsigned; quantization : integer := xlTruncate; overflow : integer := xlWrap); port ( din : in std_logic_vector (din_width-1 downto 0); result : out std_logic_vector (dout_width-1 downto 0)); end component; -- synopsys translate_off -- synopsys translate_on signal result : std_logic_vector(dout_width-1 downto 0); signal internal_ce : std_logic; begin -- synopsys translate_off -- synopsys translate_on internal_ce <= ce and en(0); bool_conversion_generate : if (bool_conversion = 1) generate result <= din; end generate; std_conversion_generate : if (bool_conversion = 0) generate convert : convert_func_call generic map ( din_width => din_width, din_bin_pt => din_bin_pt, din_arith => din_arith, dout_width => dout_width, dout_bin_pt => dout_bin_pt, dout_arith => dout_arith, quantization => quantization, overflow => overflow) port map ( din => din, result => result); end generate; latency_test : if (latency > 0) generate reg : synth_reg generic map ( width => dout_width, latency => latency ) port map ( i => result, ce => internal_ce, clr => clr, clk => clk, o => dout ); end generate; latency0 : if (latency = 0) generate dout <= result; end generate latency0; end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- -- synopsys translate_off library XilinxCoreLib; -- synopsys translate_on library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlcounter_free is generic ( core_name0: string := ""; op_width: integer := 5; op_arith: integer := xlSigned ); port ( ce: in std_logic; clr: in std_logic; clk: in std_logic; op: out std_logic_vector(op_width - 1 downto 0); up: in std_logic_vector(0 downto 0) := (others => '0'); load: in std_logic_vector(0 downto 0) := (others => '0'); din: in std_logic_vector(op_width - 1 downto 0) := (others => '0'); en: in std_logic_vector(0 downto 0); rst: in std_logic_vector(0 downto 0) ); end xlcounter_free ; architecture behavior of xlcounter_free is component cntr_11_0_341fbb8cfa0e669e port ( clk: in std_logic; ce: in std_logic; SINIT: in std_logic; q: out std_logic_vector(op_width - 1 downto 0) ); end component; attribute syn_black_box of cntr_11_0_341fbb8cfa0e669e: component is true; attribute fpga_dont_touch of cntr_11_0_341fbb8cfa0e669e: component is "true"; attribute box_type of cntr_11_0_341fbb8cfa0e669e: component is "black_box"; -- synopsys translate_off constant zeroVec: std_logic_vector(op_width - 1 downto 0) := (others => '0'); constant oneVec: std_logic_vector(op_width - 1 downto 0) := (others => '1'); constant zeroStr: string(1 to op_width) := std_logic_vector_to_bin_string(zeroVec); constant oneStr: string(1 to op_width) := std_logic_vector_to_bin_string(oneVec); -- synopsys translate_on signal core_sinit: std_logic; signal core_ce: std_logic; signal op_net: std_logic_vector(op_width - 1 downto 0); begin core_ce <= ce and en(0); core_sinit <= (clr or rst(0)) and ce; op <= op_net; comp0: if ((core_name0 = "cntr_11_0_341fbb8cfa0e669e")) generate core_instance0: cntr_11_0_341fbb8cfa0e669e port map ( clk => clk, ce => core_ce, SINIT => core_sinit, q => op_net ); end generate; end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity inverter_e5b38cca3b is port ( ip : in std_logic_vector((1 - 1) downto 0); op : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end inverter_e5b38cca3b; architecture behavior of inverter_e5b38cca3b is signal ip_1_26: boolean; type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean; signal op_mem_22_20: array_type_op_mem_22_20 := ( 0 => false); signal op_mem_22_20_front_din: boolean; signal op_mem_22_20_back: boolean; signal op_mem_22_20_push_front_pop_back_en: std_logic; signal internal_ip_12_1_bitnot: boolean; begin ip_1_26 <= ((ip) = "1"); op_mem_22_20_back <= op_mem_22_20(0); proc_op_mem_22_20: process (clk) is variable i: integer; begin if (clk'event and (clk = '1')) then if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then op_mem_22_20(0) <= op_mem_22_20_front_din; end if; end if; end process proc_op_mem_22_20; internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1"); op_mem_22_20_push_front_pop_back_en <= '0'; op <= boolean_to_vector(internal_ip_12_1_bitnot); end behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; entity logical_80f90b97d0 is port ( d0 : in std_logic_vector((1 - 1) downto 0); d1 : in std_logic_vector((1 - 1) downto 0); y : out std_logic_vector((1 - 1) downto 0); clk : in std_logic; ce : in std_logic; clr : in std_logic); end logical_80f90b97d0; architecture behavior of logical_80f90b97d0 is signal d0_1_24: std_logic; signal d1_1_27: std_logic; signal fully_2_1_bit: std_logic; begin d0_1_24 <= d0(0); d1_1_27 <= d1(0); fully_2_1_bit <= d0_1_24 and d1_1_27; y <= std_logic_to_vector(fully_2_1_bit); end behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity xlregister is generic (d_width : integer := 5; init_value : bit_vector := b"00"); port (d : in std_logic_vector (d_width-1 downto 0); rst : in std_logic_vector(0 downto 0) := "0"; en : in std_logic_vector(0 downto 0) := "1"; ce : in std_logic; clk : in std_logic; q : out std_logic_vector (d_width-1 downto 0)); end xlregister; architecture behavior of xlregister is component synth_reg_w_init generic (width : integer; init_index : integer; init_value : bit_vector; latency : integer); port (i : in std_logic_vector(width-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic; o : out std_logic_vector(width-1 downto 0)); end component; -- synopsys translate_off signal real_d, real_q : real; -- synopsys translate_on signal internal_clr : std_logic; signal internal_ce : std_logic; begin internal_clr <= rst(0) and ce; internal_ce <= en(0) and ce; synth_reg_inst : synth_reg_w_init generic map (width => d_width, init_index => 2, init_value => init_value, latency => 1) port map (i => d, ce => internal_ce, clr => internal_clr, clk => clk, o => q); end architecture behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity xlchipscope is port ( trig0 : in std_logic_vector(12-1 downto 0); trig1 : in std_logic_vector(64-1 downto 0); trig2 : in std_logic_vector(1-1 downto 0); trig3 : in std_logic_vector(1-1 downto 0); trig4 : in std_logic_vector(1-1 downto 0); trig5 : in std_logic_vector(72-1 downto 0); trig6 : in std_logic_vector(1-1 downto 0); trig7 : in std_logic_vector(15-1 downto 0); trig8 : in std_logic_vector(1-1 downto 0); trig9 : in std_logic_vector(1-1 downto 0); trig10 : in std_logic_vector(15-1 downto 0); ce : in std_logic; clr : in std_logic; clk : in std_logic); end xlchipscope; architecture behavior of xlchipscope is attribute syn_noprune : boolean; attribute syn_black_box : boolean; attribute box_type : string; attribute syn_noprune of behavior : architecture is true; signal data : std_logic_vector (184-1 downto 0); signal control : std_logic_vector (35 downto 0); component ila_1_05_a_b6735eb4b876dee5 port (control : inout std_logic_vector(35 downto 0); trig0 : in std_logic_vector(12-1 downto 0); trig1 : in std_logic_vector(64-1 downto 0); trig2 : in std_logic_vector(1-1 downto 0); trig3 : in std_logic_vector(1-1 downto 0); trig4 : in std_logic_vector(1-1 downto 0); trig5 : in std_logic_vector(72-1 downto 0); trig6 : in std_logic_vector(1-1 downto 0); trig7 : in std_logic_vector(15-1 downto 0); trig8 : in std_logic_vector(1-1 downto 0); trig9 : in std_logic_vector(1-1 downto 0); trig10 : in std_logic_vector(15-1 downto 0); clk : in std_logic ); end component; attribute syn_black_box of ila_1_05_a_b6735eb4b876dee5 : component is TRUE; attribute box_type of ila_1_05_a_b6735eb4b876dee5 : component is "black_box"; attribute syn_noprune of ila_1_05_a_b6735eb4b876dee5 : component is TRUE; component icon_1_06_a_87e2f476e984e565 port (control0 : inout std_logic_vector(35 downto 0) ); end component; attribute syn_black_box of icon_1_06_a_87e2f476e984e565 : component is TRUE; attribute box_type of icon_1_06_a_87e2f476e984e565 : component is "black_box"; attribute syn_noprune of icon_1_06_a_87e2f476e984e565 : component is TRUE; begin i_ila : ila_1_05_a_b6735eb4b876dee5 port map ( control => control, trig0 => trig0, trig1 => trig1, trig2 => trig2, trig3 => trig3, trig4 => trig4, trig5 => trig5, trig6 => trig6, trig7 => trig7, trig8 => trig8, trig9 => trig9, trig10 => trig10, clk => clk ); i_icon_for_syn : icon_1_06_a_87e2f476e984e565 port map ( control0 => control ); end architecture behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; -- Generated from Simulink block "USER_LOGIC" entity user_logic is port ( bram_rd_dout: in std_logic_vector(63 downto 0); ce_1: in std_logic; clk_1: in std_logic; data_out_x1: in std_logic; data_out_x12: in std_logic_vector(31 downto 0); data_out_x13: in std_logic; data_out_x14: in std_logic_vector(31 downto 0); data_out_x15: in std_logic; data_out_x16: in std_logic_vector(31 downto 0); data_out_x17: in std_logic; data_out_x18: in std_logic_vector(31 downto 0); data_out_x19: in std_logic; data_out_x2: in std_logic_vector(31 downto 0); data_out_x20: in std_logic_vector(31 downto 0); data_out_x21: in std_logic; data_out_x22: in std_logic_vector(31 downto 0); data_out_x23: in std_logic_vector(31 downto 0); data_out_x24: in std_logic; data_out_x25: in std_logic_vector(31 downto 0); data_out_x26: in std_logic; data_out_x27: in std_logic; data_out_x28: in std_logic_vector(31 downto 0); data_out_x29: in std_logic; data_out_x3: in std_logic; data_out_x30: in std_logic_vector(31 downto 0); data_out_x31: in std_logic; data_out_x32: in std_logic_vector(31 downto 0); data_out_x4: in std_logic_vector(31 downto 0); data_out_x5: in std_logic; data_out_x8: in std_logic_vector(31 downto 0); data_out_x9: in std_logic; fifo_rd_count_x0: in std_logic_vector(14 downto 0); fifo_rd_dout: in std_logic_vector(71 downto 0); fifo_rd_empty: in std_logic; fifo_rd_pempty_x0: in std_logic; fifo_rd_valid: in std_logic; fifo_wr_count_x0: in std_logic_vector(14 downto 0); fifo_wr_full_x0: in std_logic; fifo_wr_pfull_x0: in std_logic; rst_i: in std_logic; bram_rd_addr: out std_logic_vector(11 downto 0); bram_wr_addr: out std_logic_vector(11 downto 0); bram_wr_din: out std_logic_vector(63 downto 0); bram_wr_en: out std_logic_vector(7 downto 0); data_in: out std_logic_vector(31 downto 0); data_in_x0: out std_logic; data_in_x1: out std_logic; data_in_x10: out std_logic_vector(31 downto 0); data_in_x11: out std_logic_vector(31 downto 0); data_in_x12: out std_logic; data_in_x13: out std_logic_vector(31 downto 0); data_in_x14: out std_logic; data_in_x15: out std_logic_vector(31 downto 0); data_in_x16: out std_logic; data_in_x17: out std_logic_vector(31 downto 0); data_in_x18: out std_logic; data_in_x19: out std_logic_vector(31 downto 0); data_in_x2: out std_logic; data_in_x20: out std_logic_vector(31 downto 0); data_in_x21: out std_logic; data_in_x22: out std_logic; data_in_x23: out std_logic_vector(31 downto 0); data_in_x24: out std_logic; data_in_x25: out std_logic_vector(31 downto 0); data_in_x26: out std_logic_vector(31 downto 0); data_in_x3: out std_logic; data_in_x4: out std_logic_vector(31 downto 0); data_in_x5: out std_logic; data_in_x6: out std_logic_vector(31 downto 0); data_in_x7: out std_logic; data_in_x8: out std_logic_vector(31 downto 0); data_in_x9: out std_logic; en: out std_logic; en_x0: out std_logic; en_x1: out std_logic; en_x10: out std_logic; en_x11: out std_logic; en_x12: out std_logic; en_x13: out std_logic; en_x14: out std_logic; en_x15: out std_logic; en_x16: out std_logic; en_x17: out std_logic; en_x18: out std_logic; en_x19: out std_logic; en_x2: out std_logic; en_x20: out std_logic; en_x21: out std_logic; en_x22: out std_logic; en_x23: out std_logic; en_x24: out std_logic; en_x25: out std_logic; en_x26: out std_logic; en_x3: out std_logic; en_x4: out std_logic; en_x5: out std_logic; en_x6: out std_logic; en_x7: out std_logic; en_x8: out std_logic; en_x9: out std_logic; fifo_rd_en_x1: out std_logic; fifo_wr_din: out std_logic_vector(71 downto 0); fifo_wr_en_x0: out std_logic; rst_o: out std_logic; user_int_1o: out std_logic; user_int_2o: out std_logic; user_int_3o: out std_logic ); end user_logic; architecture structural of user_logic is attribute core_generation_info: string; attribute core_generation_info of structural : architecture is "PCIe_UserLogic_00,sysgen_core,{clock_period=5.00000000,clocking=Clock_Enables,compilation=NGC_Netlist,sample_periods=1.00000000000,testbench=0,total_blocks=351,xilinx_chipscope_block=1,xilinx_constant_block_block=23,xilinx_counter_block=1,xilinx_gateway_in_block=44,xilinx_gateway_out_block=39,xilinx_inverter_block=2,xilinx_logical_block_block=1,xilinx_register_block=89,xilinx_shared_memory_based_from_register_block=62,xilinx_shared_memory_based_to_register_block=62,xilinx_subsystem_generator_block=1,xilinx_system_generator_block=2,xilinx_type_converter_block=14,}"; signal bram_addr: std_logic_vector(11 downto 0); signal bram_addr_x0: std_logic_vector(11 downto 0); signal bram_data: std_logic_vector(63 downto 0); signal bram_rd_addr_net: std_logic_vector(11 downto 0); signal bram_rd_dout_net: std_logic_vector(63 downto 0); signal bram_wr_addr_net: std_logic_vector(11 downto 0); signal bram_wr_din_net: std_logic_vector(63 downto 0); signal bram_wr_en_net: std_logic_vector(7 downto 0); signal ce_1_sg_x0: std_logic; signal clk_1_sg_x0: std_logic; signal constant10_op_net: std_logic; signal constant11_op_net: std_logic; signal constant12_op_net: std_logic; signal constant14_op_net: std_logic; signal constant15_op_net: std_logic; signal constant19_op_net: std_logic; signal constant1_op_net: std_logic; signal constant20_op_net: std_logic; signal constant21_op_net: std_logic; signal constant22_op_net: std_logic; signal constant23_op_net: std_logic; signal constant24_op_net: std_logic; signal constant25_op_net: std_logic; signal constant26_op_net: std_logic; signal constant2_op_net: std_logic_vector(7 downto 0); signal constant3_op_net: std_logic; signal constant4_op_net: std_logic; signal constant6_op_net_x0: std_logic; signal constant7_op_net: std_logic; signal constant8_op_net: std_logic; signal constant9_op_net: std_logic; signal convert11_dout_net: std_logic; signal convert12_dout_net: std_logic; signal convert14_dout_net: std_logic; signal convert15_dout_net: std_logic; signal convert16_dout_net: std_logic; signal convert17_dout_net: std_logic; signal convert1_dout_net: std_logic; signal convert4_dout_net: std_logic; signal convert5_dout_net: std_logic; signal convert6_dout_net: std_logic; signal convert7_dout_net: std_logic; signal convert8_dout_net: std_logic; signal counter4_op_net: std_logic_vector(11 downto 0); signal data_in_net: std_logic_vector(31 downto 0); signal data_in_x0_net: std_logic; signal data_in_x10_net: std_logic_vector(31 downto 0); signal data_in_x11_net: std_logic_vector(31 downto 0); signal data_in_x12_net: std_logic; signal data_in_x13_net: std_logic_vector(31 downto 0); signal data_in_x14_net: std_logic; signal data_in_x15_net: std_logic_vector(31 downto 0); signal data_in_x16_net: std_logic; signal data_in_x17_net: std_logic_vector(31 downto 0); signal data_in_x18_net: std_logic; signal data_in_x19_net: std_logic_vector(31 downto 0); signal data_in_x1_net: std_logic; signal data_in_x20_net: std_logic_vector(31 downto 0); signal data_in_x21_net: std_logic; signal data_in_x22_net: std_logic; signal data_in_x23_net: std_logic_vector(31 downto 0); signal data_in_x24_net: std_logic; signal data_in_x25_net: std_logic_vector(31 downto 0); signal data_in_x26_net: std_logic_vector(31 downto 0); signal data_in_x2_net: std_logic; signal data_in_x3_net: std_logic; signal data_in_x4_net: std_logic_vector(31 downto 0); signal data_in_x5_net: std_logic; signal data_in_x6_net: std_logic_vector(31 downto 0); signal data_in_x7_net: std_logic; signal data_in_x8_net: std_logic_vector(31 downto 0); signal data_in_x9_net: std_logic; signal data_out_x12_net: std_logic_vector(31 downto 0); signal data_out_x13_net: std_logic; signal data_out_x14_net: std_logic_vector(31 downto 0); signal data_out_x15_net: std_logic; signal data_out_x16_net: std_logic_vector(31 downto 0); signal data_out_x17_net: std_logic; signal data_out_x18_net: std_logic_vector(31 downto 0); signal data_out_x19_net: std_logic; signal data_out_x1_net: std_logic; signal data_out_x20_net: std_logic_vector(31 downto 0); signal data_out_x21_net: std_logic; signal data_out_x22_net: std_logic_vector(31 downto 0); signal data_out_x23_net: std_logic_vector(31 downto 0); signal data_out_x24_net: std_logic; signal data_out_x25_net: std_logic_vector(31 downto 0); signal data_out_x26_net: std_logic; signal data_out_x27_net: std_logic; signal data_out_x28_net: std_logic_vector(31 downto 0); signal data_out_x29_net: std_logic; signal data_out_x2_net: std_logic_vector(31 downto 0); signal data_out_x30_net: std_logic_vector(31 downto 0); signal data_out_x31_net: std_logic; signal data_out_x32_net: std_logic_vector(31 downto 0); signal data_out_x3_net: std_logic; signal data_out_x4_net: std_logic_vector(31 downto 0); signal data_out_x5_net: std_logic; signal data_out_x8_net: std_logic_vector(31 downto 0); signal data_out_x9_net: std_logic; signal dinb: std_logic_vector(31 downto 0); signal dinb_x0: std_logic_vector(31 downto 0); signal fifo_data_in_out: std_logic_vector(71 downto 0); signal fifo_empty: std_logic; signal fifo_empty_x0: std_logic; signal fifo_rd_count: std_logic_vector(14 downto 0); signal fifo_rd_count_net: std_logic_vector(14 downto 0); signal fifo_rd_dout_net: std_logic_vector(71 downto 0); signal fifo_rd_empty_net: std_logic; signal fifo_rd_en: std_logic; signal fifo_rd_en_net: std_logic; signal fifo_rd_en_x0: std_logic; signal fifo_rd_pempty: std_logic; signal fifo_rd_pempty_net: std_logic; signal fifo_rd_valid_net: std_logic; signal fifo_wr_count: std_logic_vector(14 downto 0); signal fifo_wr_count_net: std_logic_vector(14 downto 0); signal fifo_wr_din_net: std_logic_vector(71 downto 0); signal fifo_wr_en: std_logic; signal fifo_wr_en_net: std_logic; signal fifo_wr_full: std_logic; signal fifo_wr_full_net: std_logic; signal fifo_wr_pfull: std_logic; signal fifo_wr_pfull_net: std_logic; signal inverter3_op_net: std_logic; signal inverter5_op_net: std_logic; signal rst_i_net: std_logic; signal rst_o_net: std_logic; signal timecountreset: std_logic; signal timecounttrigger: std_logic; signal tx_en_in107_q_net: std_logic; signal tx_en_in116_q_net: std_logic; signal tx_en_in117_q_net: std_logic_vector(31 downto 0); signal tx_en_in119_q_net: std_logic; signal tx_en_in120_q_net: std_logic_vector(31 downto 0); signal tx_en_in123_q_net: std_logic; signal tx_en_in124_q_net: std_logic_vector(31 downto 0); signal tx_en_in127_q_net: std_logic; signal tx_en_in128_q_net: std_logic_vector(31 downto 0); signal tx_en_in12_q_net: std_logic_vector(31 downto 0); signal tx_en_in17_q_net: std_logic_vector(11 downto 0); signal tx_en_in18_q_net: std_logic_vector(7 downto 0); signal tx_en_in30_q_net: std_logic_vector(11 downto 0); signal tx_en_in4_q_net: std_logic; signal tx_en_in52_q_net: std_logic_vector(31 downto 0); signal tx_en_in58_q_net: std_logic; signal tx_en_in59_q_net: std_logic; signal tx_en_in5_q_net: std_logic; signal tx_en_in60_q_net: std_logic_vector(31 downto 0); signal tx_en_in61_q_net: std_logic; signal tx_en_in65_q_net: std_logic_vector(31 downto 0); signal tx_en_in67_q_net: std_logic; signal tx_en_in6_q_net: std_logic_vector(31 downto 0); signal tx_en_in86_q_net: std_logic; signal tx_en_in87_q_net: std_logic_vector(31 downto 0); signal tx_en_in89_q_net: std_logic; signal tx_en_in8_q_net: std_logic; signal tx_en_in90_q_net: std_logic_vector(31 downto 0); signal tx_en_in92_q_net: std_logic; signal tx_en_in93_q_net: std_logic_vector(31 downto 0); signal user_int_1o_net: std_logic; signal user_int_2o_net: std_logic; signal user_int_3o_net: std_logic; begin bram_rd_dout_net <= bram_rd_dout; ce_1_sg_x0 <= ce_1; clk_1_sg_x0 <= clk_1; data_out_x1_net <= data_out_x1; data_out_x12_net <= data_out_x12; data_out_x13_net <= data_out_x13; data_out_x14_net <= data_out_x14; data_out_x15_net <= data_out_x15; data_out_x16_net <= data_out_x16; data_out_x17_net <= data_out_x17; data_out_x18_net <= data_out_x18; data_out_x19_net <= data_out_x19; data_out_x2_net <= data_out_x2; data_out_x20_net <= data_out_x20; data_out_x21_net <= data_out_x21; data_out_x22_net <= data_out_x22; data_out_x23_net <= data_out_x23; data_out_x24_net <= data_out_x24; data_out_x25_net <= data_out_x25; data_out_x26_net <= data_out_x26; data_out_x27_net <= data_out_x27; data_out_x28_net <= data_out_x28; data_out_x29_net <= data_out_x29; data_out_x3_net <= data_out_x3; data_out_x30_net <= data_out_x30; data_out_x31_net <= data_out_x31; data_out_x32_net <= data_out_x32; data_out_x4_net <= data_out_x4; data_out_x5_net <= data_out_x5; data_out_x8_net <= data_out_x8; data_out_x9_net <= data_out_x9; fifo_rd_count_net <= fifo_rd_count_x0; fifo_rd_dout_net <= fifo_rd_dout; fifo_rd_empty_net <= fifo_rd_empty; fifo_rd_pempty_net <= fifo_rd_pempty_x0; fifo_rd_valid_net <= fifo_rd_valid; fifo_wr_count_net <= fifo_wr_count_x0; fifo_wr_full_net <= fifo_wr_full_x0; fifo_wr_pfull_net <= fifo_wr_pfull_x0; rst_i_net <= rst_i; bram_rd_addr <= bram_rd_addr_net; bram_wr_addr <= bram_wr_addr_net; bram_wr_din <= bram_wr_din_net; bram_wr_en <= bram_wr_en_net; data_in <= data_in_net; data_in_x0 <= data_in_x0_net; data_in_x1 <= data_in_x1_net; data_in_x10 <= data_in_x10_net; data_in_x11 <= data_in_x11_net; data_in_x12 <= data_in_x12_net; data_in_x13 <= data_in_x13_net; data_in_x14 <= data_in_x14_net; data_in_x15 <= data_in_x15_net; data_in_x16 <= data_in_x16_net; data_in_x17 <= data_in_x17_net; data_in_x18 <= data_in_x18_net; data_in_x19 <= data_in_x19_net; data_in_x2 <= data_in_x2_net; data_in_x20 <= data_in_x20_net; data_in_x21 <= data_in_x21_net; data_in_x22 <= data_in_x22_net; data_in_x23 <= data_in_x23_net; data_in_x24 <= data_in_x24_net; data_in_x25 <= data_in_x25_net; data_in_x26 <= data_in_x26_net; data_in_x3 <= data_in_x3_net; data_in_x4 <= data_in_x4_net; data_in_x5 <= data_in_x5_net; data_in_x6 <= data_in_x6_net; data_in_x7 <= data_in_x7_net; data_in_x8 <= data_in_x8_net; data_in_x9 <= data_in_x9_net; en <= constant6_op_net_x0; en_x0 <= constant6_op_net_x0; en_x1 <= constant6_op_net_x0; en_x10 <= constant6_op_net_x0; en_x11 <= constant6_op_net_x0; en_x12 <= constant6_op_net_x0; en_x13 <= constant6_op_net_x0; en_x14 <= constant6_op_net_x0; en_x15 <= constant6_op_net_x0; en_x16 <= constant6_op_net_x0; en_x17 <= constant6_op_net_x0; en_x18 <= constant6_op_net_x0; en_x19 <= constant6_op_net_x0; en_x2 <= constant6_op_net_x0; en_x20 <= constant6_op_net_x0; en_x21 <= constant6_op_net_x0; en_x22 <= constant6_op_net_x0; en_x23 <= constant6_op_net_x0; en_x24 <= constant6_op_net_x0; en_x25 <= constant6_op_net_x0; en_x26 <= constant6_op_net_x0; en_x3 <= constant6_op_net_x0; en_x4 <= constant6_op_net_x0; en_x5 <= constant6_op_net_x0; en_x6 <= constant6_op_net_x0; en_x7 <= constant6_op_net_x0; en_x8 <= constant6_op_net_x0; en_x9 <= constant6_op_net_x0; fifo_rd_en_x1 <= fifo_rd_en_net; fifo_wr_din <= fifo_wr_din_net; fifo_wr_en_x0 <= fifo_wr_en_net; rst_o <= rst_o_net; user_int_1o <= user_int_1o_net; user_int_2o <= user_int_2o_net; user_int_3o <= user_int_3o_net; chipscope: entity work.xlchipscope port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', trig0 => bram_addr, trig1 => bram_data, trig10 => fifo_wr_count, trig2(0) => fifo_empty_x0, trig3(0) => fifo_rd_en_x0, trig4(0) => fifo_wr_en, trig5 => fifo_data_in_out, trig6(0) => fifo_rd_pempty, trig7 => fifo_rd_count, trig8(0) => fifo_wr_full, trig9(0) => fifo_wr_pfull ); constant1: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant1_op_net ); constant10: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant10_op_net ); constant11: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant11_op_net ); constant12: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant12_op_net ); constant14: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => constant14_op_net ); constant15: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => constant15_op_net ); constant19: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant19_op_net ); constant2: entity work.constant_19562ab42f port map ( ce => '0', clk => '0', clr => '0', op => constant2_op_net ); constant20: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant20_op_net ); constant21: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant21_op_net ); constant22: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant22_op_net ); constant23: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant23_op_net ); constant24: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant24_op_net ); constant25: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant25_op_net ); constant26: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant26_op_net ); constant3: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant3_op_net ); constant4: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant4_op_net ); constant6: entity work.constant_6293007044 port map ( ce => '0', clk => '0', clr => '0', op(0) => constant6_op_net_x0 ); constant7: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant7_op_net ); constant8: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant8_op_net ); constant9: entity work.constant_963ed6358a port map ( ce => '0', clk => '0', clr => '0', op(0) => constant9_op_net ); convert1: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => tx_en_in5_q_net, en => "1", dout(0) => convert1_dout_net ); convert11: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => tx_en_in89_q_net, en => "1", dout(0) => convert11_dout_net ); convert12: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => tx_en_in92_q_net, en => "1", dout(0) => convert12_dout_net ); convert14: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => tx_en_in116_q_net, en => "1", dout(0) => convert14_dout_net ); convert15: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => tx_en_in119_q_net, en => "1", dout(0) => convert15_dout_net ); convert16: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => tx_en_in123_q_net, en => "1", dout(0) => convert16_dout_net ); convert17: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => tx_en_in127_q_net, en => "1", dout(0) => convert17_dout_net ); convert3: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => tx_en_in4_q_net, en => "1", dout(0) => timecountreset ); convert4: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => tx_en_in86_q_net, en => "1", dout(0) => convert4_dout_net ); convert5: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => tx_en_in58_q_net, en => "1", dout(0) => convert5_dout_net ); convert6: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => tx_en_in59_q_net, en => "1", dout(0) => convert6_dout_net ); convert7: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => tx_en_in61_q_net, en => "1", dout(0) => convert7_dout_net ); convert8: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => tx_en_in67_q_net, en => "1", dout(0) => convert8_dout_net ); convert9: entity work.xlconvert generic map ( bool_conversion => 1, din_arith => 1, din_bin_pt => 0, din_width => 1, dout_arith => 1, dout_bin_pt => 0, dout_width => 1, latency => 0, overflow => xlWrap, quantization => xlTruncate ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', din(0) => tx_en_in8_q_net, en => "1", dout(0) => timecounttrigger ); counter4: entity work.xlcounter_free generic map ( core_name0 => "cntr_11_0_341fbb8cfa0e669e", op_arith => xlUnsigned, op_width => 12 ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', en => "1", rst => "0", op => counter4_op_net ); inverter3: entity work.inverter_e5b38cca3b port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', ip(0) => rst_i_net, op(0) => inverter3_op_net ); inverter5: entity work.inverter_e5b38cca3b port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, clr => '0', ip(0) => tx_en_in107_q_net, op(0) => inverter5_op_net ); logical4: entity work.logical_80f90b97d0 port map ( ce => '0', clk => '0', clr => '0', d0(0) => constant15_op_net, d1(0) => inverter5_op_net, y(0) => fifo_rd_en ); tx_en_in1: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => timecountreset, en => "1", rst => "0", q(0) => data_in_x0_net ); tx_en_in10: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in12_q_net, en(0) => timecounttrigger, rst(0) => constant3_op_net, q => data_in_x20_net ); tx_en_in100: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => convert12_dout_net, en => "1", rst => "0", q(0) => data_in_x9_net ); tx_en_in105: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => fifo_rd_empty_net, en => "1", rst => "0", q(0) => fifo_empty ); tx_en_in107: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => fifo_empty, en => "1", rst => "0", q(0) => tx_en_in107_q_net ); tx_en_in108: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => fifo_rd_en, en(0) => constant14_op_net, rst => "0", q(0) => fifo_rd_en_net ); tx_en_in109: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => fifo_rd_valid_net, en => "1", rst => "0", q(0) => fifo_wr_en_net ); tx_en_in11: entity work.xlregister generic map ( d_width => 12, init_value => b"000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => bram_addr_x0, en => "1", rst => "0", q => bram_addr ); tx_en_in113: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => convert14_dout_net, en => "1", rst => "0", q(0) => data_in_x12_net ); tx_en_in114: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => convert15_dout_net, en => "1", rst => "0", q(0) => data_in_x14_net ); tx_en_in115: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000110000110100100011" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in117_q_net, en(0) => convert14_dout_net, rst(0) => constant19_op_net, q => data_in_x13_net ); tx_en_in116: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => data_out_x19_net, en => "1", rst => "0", q(0) => tx_en_in116_q_net ); tx_en_in117: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => data_out_x18_net, en => "1", rst => "0", q => tx_en_in117_q_net ); tx_en_in118: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000100101011000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in120_q_net, en(0) => convert15_dout_net, rst(0) => constant21_op_net, q => data_in_x15_net ); tx_en_in119: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => data_out_x21_net, en => "1", rst => "0", q(0) => tx_en_in119_q_net ); tx_en_in12: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => data_out_x30_net, en => "1", rst => "0", q => tx_en_in12_q_net ); tx_en_in120: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => data_out_x20_net, en => "1", rst => "0", q => tx_en_in120_q_net ); tx_en_in121: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => convert16_dout_net, en => "1", rst => "0", q(0) => data_in_x16_net ); tx_en_in122: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in124_q_net, en(0) => convert16_dout_net, rst(0) => constant22_op_net, q => data_in_x17_net ); tx_en_in123: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => data_out_x24_net, en => "1", rst => "0", q(0) => tx_en_in123_q_net ); tx_en_in124: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => data_out_x23_net, en => "1", rst => "0", q => tx_en_in124_q_net ); tx_en_in125: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => convert17_dout_net, en => "1", rst => "0", q(0) => data_in_x18_net ); tx_en_in126: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in128_q_net, en(0) => convert17_dout_net, rst(0) => constant23_op_net, q => data_in_x19_net ); tx_en_in127: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => data_out_x26_net, en => "1", rst => "0", q(0) => tx_en_in127_q_net ); tx_en_in128: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => data_out_x25_net, en => "1", rst => "0", q => tx_en_in128_q_net ); tx_en_in13: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => convert8_dout_net, en => "1", rst => "0", q(0) => data_in_x3_net ); tx_en_in14: entity work.xlregister generic map ( d_width => 64, init_value => b"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => bram_rd_dout_net, en => "1", rst => "0", q => bram_data ); tx_en_in15: entity work.xlregister generic map ( d_width => 12, init_value => b"000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => counter4_op_net, en => "1", rst => "0", q => bram_rd_addr_net ); tx_en_in16: entity work.xlregister generic map ( d_width => 12, init_value => b"000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in30_q_net, en => "1", rst => "0", q => bram_addr_x0 ); tx_en_in17: entity work.xlregister generic map ( d_width => 12, init_value => b"000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => counter4_op_net, en => "1", rst => "0", q => tx_en_in17_q_net ); tx_en_in18: entity work.xlregister generic map ( d_width => 8, init_value => b"00000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => constant2_op_net, en => "1", rst => "0", q => tx_en_in18_q_net ); tx_en_in19: entity work.xlregister generic map ( d_width => 12, init_value => b"000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => bram_addr_x0, en => "1", rst => "0", q => bram_wr_addr_net ); tx_en_in2: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => dinb_x0, en(0) => timecountreset, rst(0) => constant1_op_net, q => data_in_net ); tx_en_in20: entity work.xlregister generic map ( d_width => 64, init_value => b"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => bram_rd_dout_net, en => "1", rst => "0", q => bram_wr_din_net ); tx_en_in21: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => fifo_empty, en => "1", rst => "0", q(0) => fifo_empty_x0 ); tx_en_in22: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => fifo_rd_en, en => "1", rst => "0", q(0) => fifo_rd_en_x0 ); tx_en_in23: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => fifo_rd_valid_net, en => "1", rst => "0", q(0) => fifo_wr_en ); tx_en_in24: entity work.xlregister generic map ( d_width => 72, init_value => b"000000000000000000000000000000000000000000000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => fifo_rd_dout_net, en => "1", rst => "0", q => fifo_data_in_out ); tx_en_in25: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => fifo_rd_pempty_net, en => "1", rst => "0", q(0) => fifo_rd_pempty ); tx_en_in26: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => inverter3_op_net, en => "1", rst => "0", q(0) => rst_o_net ); tx_en_in27: entity work.xlregister generic map ( d_width => 15, init_value => b"000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => fifo_rd_count_net, en => "1", rst => "0", q => fifo_rd_count ); tx_en_in28: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => fifo_wr_full_net, en => "1", rst => "0", q(0) => fifo_wr_full ); tx_en_in29: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => fifo_wr_pfull_net, en => "1", rst => "0", q(0) => fifo_wr_pfull ); tx_en_in3: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => constant8_op_net, en => "1", rst => "0", q(0) => user_int_1o_net ); tx_en_in30: entity work.xlregister generic map ( d_width => 12, init_value => b"000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in17_q_net, en => "1", rst => "0", q => tx_en_in30_q_net ); tx_en_in31: entity work.xlregister generic map ( d_width => 15, init_value => b"000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => fifo_wr_count_net, en => "1", rst => "0", q => fifo_wr_count ); tx_en_in33: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in6_q_net, en(0) => convert1_dout_net, rst(0) => constant26_op_net, q => data_in_x11_net ); tx_en_in38: entity work.xlregister generic map ( d_width => 72, init_value => b"000000000000000000000000000000000000000000000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => fifo_rd_dout_net, en => "1", rst => "0", q => fifo_wr_din_net ); tx_en_in4: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => data_out_x27_net, en => "1", rst => "0", q(0) => tx_en_in4_q_net ); tx_en_in43: entity work.xlregister generic map ( d_width => 8, init_value => b"00000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in18_q_net, en => "1", rst => "0", q => bram_wr_en_net ); tx_en_in5: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => data_out_x29_net, en => "1", rst => "0", q(0) => tx_en_in5_q_net ); tx_en_in50: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => dinb, en(0) => convert5_dout_net, rst(0) => constant25_op_net, q => data_in_x23_net ); tx_en_in51: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => constant11_op_net, en => "1", rst => "0", q(0) => user_int_3o_net ); tx_en_in52: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => data_out_x4_net, en => "1", rst => "0", q => tx_en_in52_q_net ); tx_en_in53: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in60_q_net, en(0) => convert6_dout_net, rst(0) => constant24_op_net, q => data_in_x25_net ); tx_en_in54: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in52_q_net, en(0) => convert7_dout_net, rst(0) => constant20_op_net, q => data_in_x26_net ); tx_en_in58: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => data_out_x1_net, en => "1", rst => "0", q(0) => tx_en_in58_q_net ); tx_en_in59: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => data_out_x3_net, en => "1", rst => "0", q(0) => tx_en_in59_q_net ); tx_en_in6: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => data_out_x28_net, en => "1", rst => "0", q => tx_en_in6_q_net ); tx_en_in60: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => data_out_x2_net, en => "1", rst => "0", q => tx_en_in60_q_net ); tx_en_in61: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => data_out_x5_net, en => "1", rst => "0", q(0) => tx_en_in61_q_net ); tx_en_in62: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => data_out_x32_net, en => "1", rst => "0", q => dinb ); tx_en_in65: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => data_out_x8_net, en => "1", rst => "0", q => tx_en_in65_q_net ); tx_en_in66: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in65_q_net, en(0) => convert8_dout_net, rst(0) => constant12_op_net, q => data_in_x4_net ); tx_en_in67: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => data_out_x9_net, en => "1", rst => "0", q(0) => tx_en_in67_q_net ); tx_en_in7: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => timecounttrigger, en => "1", rst => "0", q(0) => data_in_x22_net ); tx_en_in75: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => constant10_op_net, en => "1", rst => "0", q(0) => user_int_2o_net ); tx_en_in8: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => data_out_x31_net, en => "1", rst => "0", q(0) => tx_en_in8_q_net ); tx_en_in85: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000001" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in87_q_net, en(0) => convert4_dout_net, rst(0) => constant7_op_net, q => data_in_x6_net ); tx_en_in86: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => data_out_x13_net, en => "1", rst => "0", q(0) => tx_en_in86_q_net ); tx_en_in87: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => data_out_x12_net, en => "1", rst => "0", q => tx_en_in87_q_net ); tx_en_in88: entity work.xlregister generic map ( d_width => 32, init_value => b"10000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in90_q_net, en(0) => convert11_dout_net, rst(0) => constant4_op_net, q => data_in_x8_net ); tx_en_in89: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => data_out_x15_net, en => "1", rst => "0", q(0) => tx_en_in89_q_net ); tx_en_in9: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => data_out_x22_net, en => "1", rst => "0", q => dinb_x0 ); tx_en_in90: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => data_out_x14_net, en => "1", rst => "0", q => tx_en_in90_q_net ); tx_en_in91: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => tx_en_in93_q_net, en(0) => convert12_dout_net, rst(0) => constant9_op_net, q => data_in_x10_net ); tx_en_in92: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => data_out_x17_net, en => "1", rst => "0", q(0) => tx_en_in92_q_net ); tx_en_in93: entity work.xlregister generic map ( d_width => 32, init_value => b"00000000000000000000000000000000" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d => data_out_x16_net, en => "1", rst => "0", q => tx_en_in93_q_net ); tx_en_in94: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => convert1_dout_net, en => "1", rst => "0", q(0) => data_in_x21_net ); tx_en_in95: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => convert5_dout_net, en => "1", rst => "0", q(0) => data_in_x24_net ); tx_en_in96: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => convert6_dout_net, en => "1", rst => "0", q(0) => data_in_x1_net ); tx_en_in97: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => convert7_dout_net, en => "1", rst => "0", q(0) => data_in_x2_net ); tx_en_in98: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => convert4_dout_net, en => "1", rst => "0", q(0) => data_in_x5_net ); tx_en_in99: entity work.xlregister generic map ( d_width => 1, init_value => b"0" ) port map ( ce => ce_1_sg_x0, clk => clk_1_sg_x0, d(0) => convert11_dout_net, en => "1", rst => "0", q(0) => data_in_x7_net ); end structural;