URL
https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk
Subversion Repositories pcie_sg_dma
[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [ipcore_dir_ISE13.3/] [v6_bram4096x64_ste/] [implement/] [implement.bat] - Rev 13
Compare with Previous | Blame | View Log
rem Clean up the results directory
rmdir /S /Q results
mkdir results
rem Synthesize the VHDL Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
copy v6_bram4096x64_top.ngc .\results\
rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\v6_bram4096x64.ngc results\
rem Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\v6_bram4096x64_top.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -p xc6vlx240t-ff1156-1 v6_bram4096x64_top
echo 'Running map'
map v6_bram4096x64_top -o mapped.ncd -pr i
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -tm v6_bram4096x64_top -pcf mapped.pcf -w routed.ncd routed.vhd