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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [ipcore_dir_ISE13.3/] [v6_pcie_v1_7_x4/] [example_design/] [PIO.v] - Rev 13
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//----------------------------------------------------------------------------- // // (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // Project : Virtex-6 Integrated Block for PCI Express // File : PIO.v // Version : 1.7 // // Description: Programmed I/O module. Design implements 8 KBytes of programmable //-- memory space. Host processor can access this memory space using //-- Memory Read 32 and Memory Write 32 TLPs. Design accepts //-- 1 Double Word (DW) payload length on Memory Write 32 TLP and //-- responds to 1 DW length Memory Read 32 TLPs with a Completion //-- with Data TLP (1DW payload). //-- //-- The module designed to operate with 32 bit and 64 bit interfaces. //-- //-------------------------------------------------------------------------------- `timescale 1ns/1ns module PIO ( trn_clk, trn_reset_n, trn_lnk_up_n, trn_td, `ifndef PIO_32 trn_trem_n, `endif // not PIO_32 trn_tsof_n, trn_teof_n, trn_tsrc_rdy_n, trn_tsrc_dsc_n, trn_tdst_rdy_n, trn_tdst_dsc_n, trn_rd, `ifndef PIO_32 trn_rrem_n, `endif // not PIO_32 trn_rsof_n, trn_reof_n, trn_rsrc_rdy_n, trn_rsrc_dsc_n, trn_rbar_hit_n, trn_rdst_rdy_n, cfg_to_turnoff_n, cfg_turnoff_ok_n, cfg_completer_id, cfg_bus_mstr_enable ); // synthesis syn_hier = "hard" /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input trn_clk; input trn_reset_n; input trn_lnk_up_n; `ifdef PIO_64 output [63:0] trn_td; output [7:0] trn_trem_n; `else // PIO_64 `ifdef PIO_128 output [127:0] trn_td; output [1:0] trn_trem_n; `else output [31:0] trn_td; `endif `endif // PIO_64 output trn_tsof_n; output trn_teof_n; output trn_tsrc_rdy_n; output trn_tsrc_dsc_n; input trn_tdst_rdy_n; input trn_tdst_dsc_n; `ifdef PIO_64 input [63:0] trn_rd; input [7:0] trn_rrem_n; `else // PIO_64 `ifdef PIO_128 input [127:0] trn_rd; input [1:0] trn_rrem_n; `else input [31:0] trn_rd; `endif `endif // PIO_64 input trn_rsof_n; input trn_reof_n; input trn_rsrc_rdy_n; input trn_rsrc_dsc_n; input [6:0] trn_rbar_hit_n; output trn_rdst_rdy_n; input cfg_to_turnoff_n; output cfg_turnoff_ok_n; input [15:0] cfg_completer_id; input cfg_bus_mstr_enable; // Local wires wire req_compl; wire compl_done; wire pio_reset_n = ~trn_lnk_up_n; // // PIO instance // PIO_EP PIO_EP ( .clk ( trn_clk ), // I .rst_n ( pio_reset_n ), // I .trn_td ( trn_td ), // O [63/31:0] `ifndef PIO_32 .trn_trem_n ( trn_trem_n ), // O [7:0] `endif // not PIO_32 .trn_tsof_n ( trn_tsof_n ), // O .trn_teof_n ( trn_teof_n ), // O .trn_tsrc_rdy_n ( trn_tsrc_rdy_n ), // O .trn_tsrc_dsc_n ( trn_tsrc_dsc_n ), // O .trn_tdst_rdy_n ( trn_tdst_rdy_n ), // I .trn_tdst_dsc_n ( trn_tdst_dsc_n ), // I .trn_rd ( trn_rd ), // I [63/31:0] `ifndef PIO_32 .trn_rrem_n ( trn_rrem_n ), // I `endif // not PIO_32 .trn_rsof_n ( trn_rsof_n ), // I .trn_reof_n ( trn_reof_n ), // I .trn_rsrc_rdy_n ( trn_rsrc_rdy_n ), // I .trn_rsrc_dsc_n ( trn_rsrc_dsc_n ), // I .trn_rbar_hit_n ( trn_rbar_hit_n ), // I [6:0] .trn_rdst_rdy_n ( trn_rdst_rdy_n ), // O .req_compl_o(req_compl), // O .compl_done_o(compl_done), // O .cfg_completer_id ( cfg_completer_id ), // I [15:0] .cfg_bus_mstr_enable ( cfg_bus_mstr_enable ) // I ); // // Turn-Off controller // PIO_TO_CTRL PIO_TO ( .clk( trn_clk ), // I .rst_n( pio_reset_n ), // I .req_compl_i( req_compl ), // I .compl_done_i( compl_done ), // I .cfg_to_turnoff_n( cfg_to_turnoff_n ), // I .cfg_turnoff_ok_n( cfg_turnoff_ok_n ) // O ); endmodule // PIO