URL
https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk
Subversion Repositories pcie_sg_dma
[/] [pcie_sg_dma/] [trunk/] [xise/] [dma_top.xise] - Rev 3
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xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Verilog" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Verilog Include Directories" xil_pn:value="remote_sources/_/CAG_Link/includes|remote_sources/_/CAG_Link/avnet_det_lat_16bit/include|remote_sources/_/CAG_Link/avnet_det_lat_16bit" xil_pn:valueState="non-default"/><property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Verilog Standard" xil_pn:value="Verilog 2001" xil_pn:valueState="default"/><property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/><property xil_pn:name="Wait for DLL Lock (Output Events) virtex5" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/><property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/><property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/><property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/><property xil_pn:name="Write Mapped VHDL Netlist" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Write Mapped Verilog Netlist" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Write Vendor Constraint File" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/><!-- --><!-- The following properties are for internal use only. These should not be modified.--><!-- --><property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|tf64_pcie_trn" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_DesignName" xil_pn:value="Optic_v5DMA" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex5" xil_pn:valueState="default"/><property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="Module|ddr2module" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|ddr2module" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="Module|ddr2module" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Module|ddr2module" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/><property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-04-06T11:00:02" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E6E20F45F0464B5AAB05A7A63AB2D4E6" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/></properties><bindings><binding xil_pn:location="/v5pcieDMA" xil_pn:name="../ucf/pcie_x4_dma.ucf"/></bindings><libraries/></project>