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[/] [phr/] [branches/] [placas_1.0/] [placas/] [FPGA/] [libreria/] [DIP4-8_OSC.emp] - Rev 387

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PCBNEW-LibModule-V1  mar 28 feb 2012 17:29:06 ART
# encoding utf-8
$INDEX
DIP4-8_OSC
$EndINDEX
$MODULE DIP4-8_OSC
Po 0 0 0 15 4AAE6004 4F4D38FC ~~
Li DIP4-8_OSC
Cd Module Dil 14 pins, pads ronds
Kw DIL
Sc 4F4D38FC
AR DIP4-8_OSC
Op 0 0 0
T0 -3000 0 400 400 900 70 N V 21 N "OSC1"
T1 1100 0 400 400 0 80 N I 21 N "OSC"
T2 -2000 1100 300 300 0 60 N V 21 N "NC"
T2 -2100 -1050 300 300 0 60 N V 21 N "Vcc"
DS 0 750 0 1050 60 21
DS 950 750 0 750 60 21
DS 2150 750 3000 750 60 21
DS 3000 750 3000 1050 60 21
T2 1550 750 300 300 0 60 N V 21 N "GND"
DS 1100 -800 0 -800 60 21
DS 0 -800 0 -1100 60 21
DS 2250 -800 3000 -800 60 21
DS 3000 -800 3000 -1100 60 21
T2 1700 -800 300 300 0 60 N V 21 N "CLK"
DS 500 1500 2500 1500 60 21
DS -2500 1500 -500 1500 60 21
DS 500 -1500 2500 -1500 60 21
DS -2500 -1500 -500 -1500 60 21
DS -3500 1500 -4000 1500 80 21
DS 4000 1500 3500 1500 80 21
DS 3500 -1500 4000 -1500 80 21
DS -4000 -1500 -3500 -1500 80 21
DS 4000 -1500 4000 1500 80 21
DS -4000 1500 -4000 -1500 80 21
DS -4000 -500 -3500 -500 80 21
DS -3500 -500 -3500 500 80 21
DS -3500 500 -4000 500 80 21
$PAD
Sh "NC" R 600 600 0 0 0
Dr 280 0 0
At STD N 00C0FFFF
Ne 0 ""
Po -3000 1500
$EndPAD
$PAD
Sh "GND" C 500 500 0 0 0
Dr 280 0 0
At STD N 00E0FFFF
Ne 1 "DGND_1"
Po 3000 1500
$EndPAD
$PAD
Sh "CLK" C 500 500 0 0 0
Dr 280 0 0
At STD N 00E0FFFF
Ne 2 "N-000019"
Po 3000 -1500
$EndPAD
$PAD
Sh "Vcc" C 500 500 0 0 0
Dr 280 0 0
At STD N 00E0FFFF
Ne 3 "Vcco_1"
Po -3000 -1500
$EndPAD
$PAD
Sh "GND" C 500 500 0 0 0
Dr 280 0 0
At STD N 00E0FFFF
Ne 1 "DGND_1"
Po 0 1500
$EndPAD
$PAD
Sh "CLK" C 500 500 0 0 0
Dr 280 0 0
At STD N 00E0FFFF
Ne 2 "N-000019"
Po 0 -1500
$EndPAD
$SHAPE3D
Na "../libs/xtal_ret.wrl"
Sc 1.000000 1.000000 1.000000
Of 0.000000 0.000000 0.100000
Ro 0.000000 0.000000 0.000000
$EndSHAPE3D
$EndMODULE  DIP4-8_OSC
$EndLIBRARY

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