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[/] [phr/] [branches/] [placas_1.0/] [placas/] [FPGA/] [tmp/] [fpga_2.pro] - Rev 405

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update=vie 20 abr 2012 20:27:30 ART
last_client=pcbnew
[pcbnew]
version=1
PadDrlX=320
PadDimH=600
PadDimV=600
BoardThickness=630
RouteTo=15
RouteBo=0
Segm45=1
Racc45=1
SgPcb45=1
TxtPcbV=800
TxtPcbH=600
TxtModV=600
TxtModH=600
TxtModW=120
VEgarde=100
DrawLar=150
EdgeLar=150
TxtLar=120
MSegLar=150
WpenSer=10
[pcbnew/libraries]
LibDir=
LibName1=sockets
LibName2=connect
LibName3=discret
LibName4=pin_array
LibName5=divers
LibName6=libcms
LibName7=display
LibName8=valves
LibName9=led
LibName10=dip_sockets
LibName11=xilinx_spartan3_virtex4_and_5
LibName12=xilinx_virtexii-xc2v80&flashprom
LibName13=libreria/DIP4-8_OSC
LibName14=libreria/HOLE
LibName15=libreria/pin_array_x1
LibName16=libreria/TPS75003_PM_INV

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