OpenCores
URL https://opencores.org/ocsvn/phr/phr/trunk

Subversion Repositories phr

[/] [phr/] [trunk/] [doc/] [financiamiento/] [adec/] [informes/] [informe_final/] [informe_final.aux] - Rev 103

Go to most recent revision | Compare with Previous | Blame | View Log

\relax 
\catcode`"\active
\catcode`<\active
\catcode`>\active
\@nameuse{es@quoting}
\select@language{spanish}
\@writefile{toc}{\select@language{spanish}}
\@writefile{lof}{\select@language{spanish}}
\@writefile{lot}{\select@language{spanish}}
\@writefile{toc}{\contentsline {chapter}{\numberline {1}Hardware}{1}}
\@writefile{lof}{\addvspace {10\p@ }}
\@writefile{lot}{\addvspace {10\p@ }}
\newlabel{chap:hw}{{1}{1}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.1}{\ignorespaces Proceso de dise\IeC {\~n}o de las placas\relax }}{1}}
\providecommand*\caption@xref[2]{\@setref\relax\@undefined{#1}}
\newlabel{fig:hw-ciclo}{{1.1}{1}}
\@writefile{toc}{\contentsline {section}{\numberline {1.1}Plataforma de Hardware Reconfigurable (PHR)}{2}}
\newlabel{sec:phr}{{1.1}{2}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.1.1}Recursos de \textsl  {hardware}}{2}}
\newlabel{sec:phr-recursos-hw}{{1.1.1}{2}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.1.2}Esquem\IeC {\'a}tico}{3}}
\newlabel{sec:phr-dia-electrico}{{1.1.2}{3}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.1.3}\textsl  {Printed Circuit Board} (PCB)}{3}}
\newlabel{sec:phr-pcb}{{1.1.3}{3}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.2}{\ignorespaces Esquem\IeC {\'a}tico TOP de la placa \emph  {PHR}.\relax }}{4}}
\newlabel{fig:phr-sch-top}{{1.2}{4}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.3}{\ignorespaces Bloque interno al diagrama TOP, denominado ``power'' debido a que contiene la conexi\IeC {\'o}n con la placa \emph  {S3power} y capacitores que evitan interferencias el\IeC {\'e}ctricas.\relax }}{5}}
\newlabel{fig:phr-sch-power}{{1.3}{5}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.4}{\ignorespaces Bloque con todos los perif\IeC {\'e}ricos. Aqu\IeC {\'\i } se observa la ventaja del dise\IeC {\~n}o jerarquizado, pues si se tendr\IeC {\'\i }an todos estos componentes junto a los de la Figura \ref  {fig:phr-sch-top} y \ref  {fig:phr-sch-power}, presentar\IeC {\'\i }a inconvenientes para su entendimiento.\relax }}{6}}
\newlabel{fig:phr-sch-ioports}{{1.4}{6}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.5}{\ignorespaces Distribuci\IeC {\'o}n de los componentes en la placa.\relax }}{7}}
\newlabel{fig:phr-pcb-pcbnew-top}{{1.5}{7}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.6}{\ignorespaces Modelo en 3D de la placa \emph  {PHR} (Perspectiva 1).\relax }}{7}}
\newlabel{fig:phr-pcb-3d-1}{{1.6}{7}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.7}{\ignorespaces Modelo en 3D de la placa \emph  {PHR} (Perspectiva 2).\relax }}{8}}
\newlabel{fig:phr-pcb-3d-2}{{1.7}{8}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.8}{\ignorespaces Fotograf\IeC {\'\i }a de la placa \emph  {PHR} (Perspectiva 1).\relax }}{8}}
\newlabel{fig:phr-pcb-foto-1}{{1.8}{8}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.9}{\ignorespaces Fotograf\IeC {\'\i }a de la placa \emph  {PHR} (Perspectiva 2).\relax }}{9}}
\newlabel{fig:phr-pcb-foto-2}{{1.9}{9}}
\@writefile{toc}{\contentsline {section}{\numberline {1.2}S3Power}{10}}
\newlabel{sec:s3power}{{1.2}{10}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.2.1}Esquem\IeC {\'a}tico y PCB}{10}}
\newlabel{sec:s3power-sch-pcb}{{1.2.1}{10}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.10}{\ignorespaces Esquem\IeC {\'a}tico de la placa \emph  {S3Power}.\relax }}{10}}
\newlabel{fig:s3power-sch}{{1.10}{10}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.11}{\ignorespaces Distribuci\IeC {\'o}n de los componentes en la placa.\relax }}{11}}
\newlabel{fig:s3power-pcb-layers}{{1.11}{11}}
\newlabel{fig:s3power-pcb-3d-1}{{1.12a}{11}}
\newlabel{sub@fig:s3power-pcb-3d-1}{{a}{11}}
\newlabel{fig:s3power-pcb-3d-2}{{1.12b}{11}}
\newlabel{sub@fig:s3power-pcb-3d-2}{{b}{11}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.12}{\ignorespaces Modelo en 3D de la placa \emph  {S3Power}.\relax }}{11}}
\newlabel{fig:s3power-pcb-3d}{{1.12}{11}}
\newlabel{fig:s3power-foto-1}{{1.13a}{11}}
\newlabel{sub@fig:s3power-foto-1}{{a}{11}}
\newlabel{fig:s3power-foto-2}{{1.13b}{11}}
\newlabel{sub@fig:s3power-foto-2}{{b}{11}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.13}{\ignorespaces Fotograf\IeC {\'\i }as de la placa \emph  {S3Power}.\relax }}{11}}
\newlabel{fig:s3power-foto}{{1.13}{11}}
\@writefile{toc}{\contentsline {section}{\numberline {1.3}OOCDLink}{12}}
\newlabel{sec:oocdlink}{{1.3}{12}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.3.1}Esquem\IeC {\'a}tico y PCB}{12}}
\newlabel{sec:oocdlink-sch-pcb}{{1.3.1}{12}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.14}{\ignorespaces Esquem\IeC {\'a}tico de la placa \emph  {OOCDLink}.\relax }}{12}}
\newlabel{fig:oocdlink-sch}{{1.14}{12}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.15}{\ignorespaces Distribuci\IeC {\'o}n de los componentes en la placa \emph  {OOCDLink}.\relax }}{13}}
\newlabel{fig:oocdlik-pcb-layers}{{1.15}{13}}
\@writefile{toc}{\contentsline {section}{\numberline {1.4}Gastos en recursos de \textsl  {hardware}}{13}}
\newlabel{sec:hw-gastos}{{1.4}{13}}
\@writefile{toc}{\contentsline {section}{\numberline {1.5}Observaciones}{13}}
\newlabel{sec:hw-obs}{{1.5}{13}}
\newlabel{fig:oocdlink-pcb-3d-1}{{1.16a}{14}}
\newlabel{sub@fig:oocdlink-pcb-3d-1}{{a}{14}}
\newlabel{fig:oocdlink-pcb-3d-2}{{1.16b}{14}}
\newlabel{sub@fig:oocdlink-pcb-3d-2}{{b}{14}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.16}{\ignorespaces Modelo en 3D de la placa \emph  {OOCDLink}.\relax }}{14}}
\newlabel{fig:oocdlink-pcb-3d}{{1.16}{14}}
\newlabel{fig:oocdlink-foto-1}{{1.17a}{14}}
\newlabel{sub@fig:oocdlink-foto-1}{{a}{14}}
\newlabel{fig:oocdlink-foto-2}{{1.17b}{14}}
\newlabel{sub@fig:oocdlink-foto-2}{{b}{14}}
\@writefile{lof}{\contentsline {figure}{\numberline {1.17}{\ignorespaces Fotograf\IeC {\'\i }as de la placa \emph  {OOCDLink}.\relax }}{14}}
\newlabel{fig:oocdlink-foto}{{1.17}{14}}
\@writefile{toc}{\contentsline {chapter}{\numberline {2}Software}{15}}
\@writefile{lof}{\addvspace {10\p@ }}
\@writefile{lot}{\addvspace {10\p@ }}
\newlabel{chap:sw}{{2}{15}}
\@writefile{toc}{\contentsline {section}{\numberline {2.1}Herramientas utilizadas}{15}}
\newlabel{sec:herramientas-sw}{{2.1}{15}}
\@writefile{toc}{\contentsline {section}{\numberline {2.2}Desarrollo de \textsl  {Scripts}}{16}}
\newlabel{sec:scripts-sw}{{2.2}{16}}
\@writefile{lof}{\contentsline {figure}{\numberline {2.1}{\ignorespaces Diagrama en bloque de la conexi\IeC {\'o}n entre el \textsl  {Software} y el \textsl  {Hardware}.\relax }}{16}}
\newlabel{fig:scripts-diagrama}{{2.1}{16}}
\@writefile{toc}{\contentsline {section}{\numberline {2.3}Repositorio del proyecto}{16}}
\newlabel{sec:sw-repo}{{2.3}{16}}
\@writefile{toc}{\contentsline {section}{\numberline {2.4}Observaciones}{17}}
\newlabel{sec:sw-obs}{{2.4}{17}}
\@writefile{toc}{\contentsline {chapter}{\numberline {3}Conclusiones}{18}}
\@writefile{lof}{\addvspace {10\p@ }}
\@writefile{lot}{\addvspace {10\p@ }}
\newlabel{chap:conclusiones}{{3}{18}}

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.