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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %NEW CHAPTER NEW CHAPTER NEW CHAPTER NEW CHAPTER NEW CHAPTER% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \chapter{La placa PHR} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %NEW SECTION NEW SECTION NEW SECTION NEW SECTION NEW SECTION% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{El chip FPGA} \section{Memoria del FPGA} \section{Interfaz JTAG} \section{Fuentes de \textsl{clock}} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %NEW SECTION NEW SECTION NEW SECTION NEW SECTION NEW SECTION% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Periféricos} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{LEDs} En la placa se encuentran ocho LEDs de montaje superficial indicados con el numero 9 en la Fig. \ref{intro:componentes}. Son etiquetados desde LED1 a LED8 y su relación con los pines de la FPGA se muestra en la Tabla \ref{phr:LEDpins}. \begin{table}[h] \begin{center} \begin{tabular}{|c|c|c|c|c|c|c|c|c|} \hline \textbf{Periférico} & LED1 & LED2 & LED3 & LED4 & LED5 & LED6 & LED7 & LED8 \\ \hline \textbf{Pin} & 84 & 86 & 89 & 93 & 98 & 3 & 5 & 7 \\ \hline \end{tabular} \end{center} \caption[Pines para los LEDs]{Correspondencia entre los pines de la FPGA y los LEDs (periféricos).} \label{phr:LEDpins} \end{table} Los cátodos de cada LED se conectan a potencial cero y los ánodos se conectan a los pines respectivos de la FPGA mediante un resistencia de 330 $\Omega$. Para enecender un determinado LED basta con poner la señal de control en alto. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Pulsadores (\textsl{Tact switches})} Están disponibles cuatro botones pulsadores como los esquematizados en la Fig. \ref{phr:tact} y son identificados con el numero 12 en la Fig. \ref{intro:componentes}. Los mismos son etiquetados como PBTN1, PBTN2, PBTN3 y PBTN4. Los pines de la FPGA relacionados con éstos periféricos se identifican en la Tabla \ref{phr:PBTNpins}. El esquemático detallado del circuito puede encontrarse en el Apéndice refAPENDICE. \begin{figure}[b] \begin{center} \includegraphics{./img/phr/tact_switch.pdf} \end{center} \caption{\textsl{Tact switches}.} \label{phr:tact} \end{figure} \begin{table}[h] \begin{center} \begin{tabular}{|c|c|c|c|c|} \hline \textbf{Periférico} & PBTN1 & PBTN2 & PBTN3 & PBTN4 \\ \hline \textbf{Pin} & 77 & 78 & 82 & 83 \\ \hline \end{tabular} \end{center} \caption[Pines para los \textsl{tact switches}]{Correspondencia entre los pines de la FPGA y los botones.} \label{phr:PBTNpins} \end{table} Cuando se presiona alguno de los botones se genera un valor lógico alto en el pin asociado de la FPGA. No hay circuito antirrebote y ésto debe ser tenido en cuenta al momento de escribir el código que luego vaya a cargarse en el dispositivo. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Llaves DIP} \begin{table}[h] \begin{center} \begin{tabular}{|c|c|c|c|c|c|c|c|c|} \hline \textbf{Periférico} & SW1 & SW2 & SW3 & SW4 & SW5 & SW6 & SW7 & SW8 \\ \hline \textbf{Pin} & 85 & 88 & 90 & 94 & 97 & 4 & 6 & 9 \\ \hline \end{tabular} \end{center} \caption[Pines para las llavess]{Correspondencia entre los pines de la FPGA y las llaves.} \label{phr:DIPSpins} \end{table} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Display de segmentos} La placa PHR cuenta con un display siete segmentos cuádruple de \emph{ánado comun} indicado con el índice 13 en la Fig. \ref{intro:componentes}. El circuito de conexión entre la FPGA y el display se muestra en la Fig. \ref{phr:quad7seg} y se resalta la denominación alfabética para los segmentos de los caracteres. Ésta misma figura además muestra como ejemplo, el estado de los pines de la FPGA para indicar el numero 3 en la posición 2. Al tener ésta configuración, cada LED encenderá con un \emph{nivel bajo} en el pin correspondiente al segmento pero además necesitará que el ánodo del caracter particular esté energizado. Éste ultimo también es activo por bajo (\textsl{active low}). \begin{figure}[h] \begin{center} \includegraphics{./img/phr/quad7seg.pdf} \end{center} \caption[Circuito del display de segmentos]{Conexionado del display de seite segmentos cuádruple.} \label{phr:quad7seg} \end{figure} Para dar el efecto deseado de representar una cifra de 4 dígitos se recurre a la técnica de multiplexación en el dominio del tiempo. La técnica consiste en mostrar uno a uno y ciclicamente cada caracter a una frecuencia suficientemente alta para que el ojo humano persiva una imagen completa. Un diagrama temporal de las señales se muestra en la Fig. ref. \begin{figure}[h] \begin{center} \includegraphics{./img/phr/multiplex.pdf} \end{center} \caption[Diagrama de multiplexado]{Diagrama temporal de la multiplexación.} \label{phr:multiplex} \end{figure} Si bien el método requiere algo mas de complejidad que la conexion directa a cada segmento de cada caracter, reduce el numero de pines necesarios de $8 \times 4=32$ a $8+4=12$ lo cuál representa un significativo ahorro en recursos de hardware. La Tabla \ref{phr:quad7seg:pines} muestra los pines de conexión de la FPGA a las distintas entradas del periférico. La Tabla \ref{phr:quad7seg:chars} tiene valores de control para que los segmentos muestren digitos y las letras desde la \emph{A} hasta la \emph{F} para poder representar números en formato hexadecimal. \begin{table}[h] \begin{center} \begin{tabular}{|c|c|c|c|c|} \hline \textbf{Periférico} & Caracter1 & Caracter2 & Caracter3 & Caracter4 \\ \hline \textbf{Pin} & 59 & 57 & 61 & 60 \\ \hline \end{tabular} \vspace{.2cm} \begin{tabular}{|c|c|c|c|c|c|c|c|c|} \hline \textbf{Segmento} & A & B & C & D & E & F & G & DP \\ \hline \textbf{Pin} & 65 & 64 & 72 & 70 & 68 & 62 & 73 & 71 \\ \hline \end{tabular} \end{center} \caption[Pines para el diplay de segmentos]{Conexionado del diplay de 7 segmentos cuádruple a la FPGA.} \label{phr:quad7seg:pines} \end{table} \begin{figure}[h] \begin{center} \includegraphics{./img/phr/chars.pdf} \end{center} \caption[Display: caracteres comunes]{Representaciones de caracteres comunes en los displays de siete segmentos.} \label{phr:quad7seg:chars} \end{figure} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Puerto serie} \begin{figure}[h] \begin{center} \includegraphics{./img/phr/3232.pdf} \end{center} \caption{Circuito de la interfaz RS-232} \label{phr:3232} \end{figure} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %NEW SECTION NEW SECTION NEW SECTION NEW SECTION NEW SECTION% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Entradas y salidas de propósito general} \begin{figure}[h] \begin{center} \includegraphics{./img/phr/gpio_header.pdf} \end{center} \caption{Conector para entradas y salidas de propósito general.} \label{phr:gpio} \end{figure}
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