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[/] [phr/] [trunk/] [doc/] [informe-tesis/] [reports/] [schedule_2013-03-20/] [schedule.aux] - Rev 79

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\newacro{PHR}[\AC@hyperlink{PHR}{PHR}]{Plataforma de Hardware Reconfigurable}
\newacro{openocd}[\AC@hyperlink{openocd}{OpenOCD}]{\textsl  {Open On-Chip Debugger}}
\newacro{jtag}[\AC@hyperlink{jtag}{JTAG}]{\textsl  {Joint Test Action Group}}
\newacro{TAP}[\AC@hyperlink{TAP}{TAP}]{\textsl  {Test Access Port}}
\newacro{SVF}[\AC@hyperlink{SVF}{SVF}]{\textsl  {Serial Vector Format}}
\newacro{CPLD}[\AC@hyperlink{CPLD}{CPLD}]{\textsl  {Complex Programmable Logical Device}}
\newacro{FPGA}[\AC@hyperlink{FPGA}{FPGA}]{\textsl  {Field Programmable Gate Array}}
\newacro{PROM}[\AC@hyperlink{PROM}{PROM}]{\textsl  {Programmable Read-Only Memory}}
\newacro{SO}[\AC@hyperlink{SO}{SO}]{sistema operativo}
\newacro{GPL}[\AC@hyperlink{GPL}{GPL}]{\textsl  {General Public License}}
\newacro{UTN-FRC}[\AC@hyperlink{UTN-FRC}{UTN-FRC}]{Universidad Tecnol\IeC {\'o}gica Nacional -- Facultad Regional C\IeC {\'o}rdoba}
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