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[/] [phr/] [trunk/] [doc/] [informe-tesis/] [reports/] [schedule_2013-03-20/] [schedule.toc] - Rev 420
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\select@language {spanish}
\contentsline {section}{\numberline {1}Introducci\IeC {\'o}n}{2}
\contentsline {section}{\numberline {2}\textsl {Software} \ac {openocd}}{2}
\contentsline {subsection}{\numberline {2.1}Instalaci\IeC {\'o}n del \textsl {software} \ac {openocd}}{2}
\contentsline {subsection}{\numberline {2.2}\textsl {Interface}}{2}
\contentsline {subsection}{\numberline {2.3}Documentaci\IeC {\'o}n de comandos y \textsl {scripts}}{3}
\contentsline {subsection}{\numberline {2.4}Agregar un \ac {TAP}}{4}
\contentsline {subsection}{\numberline {2.5}Multiples \ac {TAP}}{5}
\contentsline {subsection}{\numberline {2.6}Programaci\IeC {\'o}n del \ac {CPLD}}{5}
\contentsline {subsection}{\numberline {2.7}\textsl {Debugging}}{6}
\contentsline {section}{\numberline {3}\textsl {Software} \emph {xc3sprog}}{7}
\contentsline {subsection}{\numberline {3.1}Instalaci\IeC {\'o}n del \textsl {software} xc3sprog}{7}
\contentsline {subsection}{\numberline {3.2}Documentaci\IeC {\'o}n de comandos y \textsl {scripts}}{8}
\contentsline {subsubsection}{\numberline {3.2.1}Configuraci\IeC {\'o}n del \textsl {interface}}{8}
\contentsline {subsubsection}{\numberline {3.2.2}Dispositivos soportados}{9}
\contentsline {subsubsection}{\numberline {3.2.3}Comandos b\IeC {\'a}sicos}{10}
\contentsline {subsection}{\numberline {3.3}Programaci\IeC {\'o}n de \ac {FPGA} y memoria PROM}{13}
\contentsline {subsubsection}{\numberline {3.3.1}Programaci\IeC {\'o}n de la FPGA}{13}
\contentsline {subsubsection}{\numberline {3.3.2}Programaci\IeC {\'o}n de la memoria PROM}{14}
\contentsline {subsection}{\numberline {3.4}Programaci\IeC {\'o}n del \ac {CPLD}}{15}
\contentsline {section}{\numberline {4}Documentaci\IeC {\'o}n}{15}
\contentsline {section}{\numberline {A}Acr\IeC {\'o}nimos}{16}
\contentsline {section}{\numberline {B}Repositorio de proyecto}{16}
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