OpenCores
URL https://opencores.org/ocsvn/phr/phr/trunk

Subversion Repositories phr

[/] [phr/] [trunk/] [doc/] [informe-tesis/] [tesis-beamer/] [PrimeraVersion.tex] - Rev 317

Go to most recent revision | Compare with Previous | Blame | View Log

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section[Desarrollo]{Desarrollo del Proyecto PHR}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
\begin{frame}
\frametitle{El proyecto PHR} 
\begin{center}
\includegraphics[width=\textwidth]{phr_small.png}
\end{center}
\end{frame}
 
 
\begin{frame}
  \frametitle{Recursos de hardware vs. Nivel de enseñanza}  
  % \transfade
 
  \begin{block}{Consideración}
    En función del perfil del usuario de la plataforma se definen los dispositivos que se utilizarán
  \end{block}
 
  \vfill
 
  \begin{center}
      \begin{tabular}{|l|c|c|c|}
        \hline
        \multirow{2}{*}{Nivel} & Llaves/pulsadores & ADC\&DAC/SPI & USB/ETH \\
        & Diodos LED & Display LCD/VGA & HDMI \\ \hline
        \hline
        Inicial & $\checkmark$ & & \\
        \hline
        Medio & $\checkmark$ & $\checkmark$ & \\
        \hline
        Avanzado & $\checkmark$ & $\checkmark$ & $\checkmark$ \\
        \hline
      \end{tabular}
 
  \end{center}
\end{frame}
 
 
\subsection{Diagrama en bloques}
 
\begin{frame}
\frametitle{Diagrama de bloques del Hardware} 
%\transfade
\begin{center}
    \includegraphics<1>[width=0.9\textwidth]{block1.pdf}
    \includegraphics<2>[width=0.9\textwidth]{block2.pdf}
    \includegraphics<3>[width=0.9\textwidth]{block3.pdf}
\end{center}
\end{frame}
 
 
\subsection{Placa PHRBoard} %%%%%%%%%%%%%%%%%%%%%%%%%%%
 
\begin{frame}
\frametitle{Características} 
 
\begin{description}[Memoria PROM:]
 
\item [FPGA:] Xilinx Spartan-3A XC3S200A (VQG100)
\pause
\item [Memoria PROM:] Xilinx XCF02S
\pause
\item [Voltaje entrada:] 5V
\pause
\item [Relojes:] Un reloj fijo y tres seleccionables:
 
	\begin{enumerate}
	\item 50 MHz
	\item 16 MHz, 1 MHz, 500 kHz y 250 kHz
	\item 125 kHz, 62.5 kHz, 31.25 kHz, 15.625 kHz
	\item 3.9062 kHz, 1.9531 kHz, 976,56251 Hz
   \end{enumerate}
\pause
\item [GPIO:] 28 pines en total
\end{description}
 
\end{frame}
 
\begin{frame}[b]
\frametitle{Periféricos} 
\only<1-5>{
\begin{itemize}
\item \textbf<1>{8 LEDs}
\item \textbf<2>{8 llaves (\emph{DIP switch})}
\item \textbf<3>{4 pulsadores}
\item \textbf<4>{Display de 7 segmentos cuádruple}
\item \textbf<5>{Puerto serie}
\end{itemize}
}
 
%\vspace{3cm} 
\begin{center}
\includegraphics<1>[width=1\textwidth]{phr_top_leds.png}
\includegraphics<2>[width=1\textwidth]{phr_top_switches.png}
\includegraphics<3>[width=1\textwidth]{phr_top_botones.png}
\includegraphics<4>[width=1\textwidth]{phr_top_display.png}
\includegraphics<5>[width=1\textwidth]{phr_top_nada.png}
\includegraphics<6>[width=1\textwidth]{phr_top.png}
\end{center}
 
\vspace{1ex}
 
\end{frame}
 
 
\subsection{Placa S3Power} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
\begin{frame}
\frametitle{Placa S3Power} 
\begin{center}
\includegraphics[width=0.8\textwidth]{s3power_small.png}
\end{center}
\end{frame}
 
\begin{frame}
\frametitle{Voltajes elegidos} 
\begin{itemize}
\item 1.2V y 2.5A para la lógica interna.
\item 3.3V y 2.5A para los bancos de pines.
\item 2.5V y 200mA para el módulo de comunicación JTAG.
\end{itemize}
\end{frame}
 
\begin{frame}
\frametitle{El chip TPS75003} 
\begin{itemize}
\item<1-> Posee tres reguladores de tensión: Dos tipo Buck de 3A y eficiencia del 95\% y otro regulador lineal de 300 mA.
\item<2-> Voltaje de entrada de entre 2.2V y 6.5 V.
\item<3-> Arranque suave e independiente para cada regulador.
\item<4-> Tensiones ajustables de 1.2 V a 6.5 V para los convertidores Buck y de 1.0 V a 6.5 V para el convertidor lineal.
\end{itemize}
\end{frame}
 
\begin{frame}
\frametitle{Arranque} 
\begin{center}
\includegraphics[width=0.9\textwidth]{arranque.pdf}
\end{center}
\end{frame}
 
 
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Placa OOCDLink}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
\begin{frame}
\frametitle{Placa OOCDLink} 
\begin{center}
\includegraphics[width=0.8\textwidth]{oocdlink_small.png}
\end{center}
\end{frame}
 
 
\subsubsection{FTDI chip} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
\begin{frame}
\frametitle{El chip FT2232D} 
\begin{itemize}
\item <1->Cumple con USB 2.0 Full Speed (12 Mbits/sec)
\item <2->Tiene una tasa de transferencia de entre 300 y 3 MBaud
\item <3->Forma dos canales de comunicación
\item <4->Desde el SO, la interfaz puede verse como un \emph{puerto serie virtual}
\item <5->Existen librerías para implementar JTAG, I2C y SPI
\end{itemize}
\end{frame}
 
\begin{frame}
\frametitle{El chip FT2232D} 
\begin{center}
\includegraphics[width=1\textwidth]{FTblock.pdf}
\end{center}
\end{frame}
 
\subsection{Software} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
\begin{frame} 
\frametitle{Selección de los modos de configuración} 
\includegraphics[width=1\textwidth]{config_modes.pdf}
\end{frame}
 
\begin{frame}
\frametitle{xc3sprog} 
\begin{center}
\includegraphics[width=1\textwidth]{xc3sprog.pdf}
\end{center}
\end{frame}
 
\begin{frame}
\frametitle{PHR GUI (utiliza el \textsl{software} xc3sprog)} 
\begin{center}
\includegraphics[width=0.8\textwidth]{front-end.pdf}
\end{center}
\end{frame}
 
 
 
 
 

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.