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https://opencores.org/ocsvn/pit/pit/trunk
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[/] [pit/] [trunk/] [sim/] [verilog/] [run/] [run_iverilog] - Rev 13
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#!/bin/csh
set pit = ../../..
set bench = $pit/bench
set wave_dir = $pit/sim/rtl_sim/pit_verilog/waves
iverilog \
\
-I $bench/verilog \
-I $pit/rtl/verilog \
\
-o pit_compiled \
-D WAVES_V \
\
$pit/rtl/verilog/pit_top.v \
$pit/rtl/verilog/pit_wb_bus.v \
$pit/rtl/verilog/pit_regs.v \
$pit/rtl/verilog/pit_prescale.v \
$pit/rtl/verilog/pit_count.v \
\
$bench/verilog/wb_master_model.v \
$bench/verilog/tst_bench_top.v
@ good_compile = $status
if ($good_compile == 0) then
echo "Compile was Good"
vvp pit_compiled -lxt2
else
echo "Compile Failed"
endif
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