Subversion Repositories plb2wbbridge

Device_Family           = virtex5
Device                  = xc5vlx50
Package                 = ff676
Speedgrade              = -2


# Path to the vhdl and implementation directory
PLB2WB_Bridge_VHDL_DIR  = ../../systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/
PLB2WB_Bridge_NGC_DIR   = ../../systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/ise/work/

Address_Buffer_Size     = 16  # valid values: 16, 32, ... 4194304
Read_Buffer_Size        = 16  # valid values: 16, 32, ... 4194304
Write_Buffer_Size       = 16  # valid values: 16, 32, ... 4194304
Stat2WB_Buffer_Size     = 16  # valid values: 16, 32, ... 4194304
Stat2PLB_Buffer_Size    = 16  # valid values: 16, 32, ... 4194304
WB_Clk_Frequency        = 66 # MHz
PLB_Clk_Frequency       = 100 # MHz


################################
# Do not change below unless 
# you know what you are doing

Address_Buffer_minDWidth   = 42 # 32 bit address, 4 bit BE, 4 bit size, 1 RNW, minimum 1 bit master-id
Read_Buffer_DWidth         = 33 # 32 bit datum and 1 bit error
Write_Buffer_DWidth        = 32
Stat2PLB_Buffer_minDWidth  = 100   # 32 bit address, 32 bit datum, 3 bit status info, 1-4 bit master-id, 32 bit irq-info
Stat2WB_Buffer_DWidth      = 1