Subversion Repositories plb2wbbridge

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68
# Fri Mar  5 18:02:26 2010
# Target Board:  Xilinx Virtex 5 ML501 Evaluation Platform Rev 1
# Family:    virtex5
# Device:    xc5vlx50
# Package:   ff676
# Speed Grade:  -1
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 125.0
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT sys_clk_pin = clk_100MHz, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT to_synch_in_pin = synch_in, DIR = I, VEC = [0:31]
 PORT from_synch_out_pin = synch_out, DIR = O, VEC = [0:31]


BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_DCR_INTFCE = 1
 PARAMETER C_BASEADDR = 0b0000000000
 PARAMETER C_HIGHADDR = 0b1111111111
 PORT PLB_Clk = clk_100MHz
 PORT SYS_Rst = sys_rst_s
END

BEGIN plbv46_master_bfm
 PARAMETER INSTANCE = plb_bfm_master_32
 PARAMETER HW_VER = 1.00.a
 PARAMETER PLB_MASTER_SIZE = 0b10
 PARAMETER PLB_MASTER_NUM = 0b0000
 PARAMETER C_MPLB_NATIVE_DWIDTH = 128
 PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
 BUS_INTERFACE MPLB = mb_plb
 PORT SYNCH_OUT = bfm_synch_out_0
 PORT SYNCH_IN = synch_in
END

BEGIN plbv46_master_bfm
 PARAMETER INSTANCE = plb_bfm_master_64
 PARAMETER HW_VER = 1.00.a
 PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
 PARAMETER PLB_MASTER_SIZE = 0b10
 PARAMETER PLB_MASTER_NUM = 0b0001
 PARAMETER C_MPLB_NATIVE_DWIDTH = 128
 BUS_INTERFACE MPLB = mb_plb
 PORT SYNCH_OUT = bfm_synch_out_1
 PORT SYNCH_IN = synch_in
END

BEGIN plbv46_master_bfm
 PARAMETER INSTANCE = plb_bfm_master_128
 PARAMETER HW_VER = 1.00.a
 PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
 PARAMETER C_MPLB_NATIVE_DWIDTH = 128
 PARAMETER PLB_MASTER_NUM = 0b0010
 BUS_INTERFACE MPLB = mb_plb
 PORT SYNCH_OUT = bfm_synch_out_2
 PORT SYNCH_IN = synch_in
END

BEGIN plbv46_monitor_bfm
 PARAMETER INSTANCE = plb_bfm_monitor
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE MON_PLB = mb_plb
 PORT SYNCH_OUT = bfm_synch_out_3
 PORT SYNCH_IN = synch_in
END

BEGIN plbv46_slave_bfm
 PARAMETER INSTANCE = plb_bfm_slave
 PARAMETER HW_VER = 1.00.a
 PARAMETER PLB_SLAVE_ADDR_LO_0 = 0xF8000000
 PARAMETER PLB_SLAVE_ADDR_HI_0 = 0xFFFFfFFF
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 PARAMETER PLB_SLAVE_SIZE = 0b00
 BUS_INTERFACE SPLB = mb_plb
 PORT SYNCH_IN = synch_in
 PORT SYNCH_OUT = bfm_synch_out_4
END

BEGIN bfm_synch
 PARAMETER INSTANCE = plb_bfm_synch
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_NUM_SYNCH = 5
 PORT TO_SYNCH_IN = synch_out
 PORT FROM_SYNCH_OUT = bfm_synch_out_0 & bfm_synch_out_1 & bfm_synch_out_2 & bfm_synch_out_3 & bfm_synch_out_4
END

BEGIN plb2wb_bridge
 PARAMETER INSTANCE = plb2wb_bridge_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0xf0000000
 PARAMETER C_HIGHADDR = 0xf7ffffff
 PARAMETER WB_ADR_OFFSET = 0xf0000000
 PARAMETER WB_ADR_OFFSET_NEG = 1
 PARAMETER WB_PIC_INTS = 1
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MWB = wb_conbus_0
 PORT SPLB_Clk = clk_100MHz
 PORT wb_clk_i = clk_100MHz
 PORT wb_rst_i = sys_rst_s
 PORT wb_pic_int_i = net_gnd
END

BEGIN wb_conbus
 PARAMETER INSTANCE = wb_conbus_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER wb_s0_addr = 0x00
 PARAMETER wb_s27_addr_w = 8
 PARAMETER wb_s1_addr = 0x01
 PARAMETER wb_s2_addr = 0x02
 PARAMETER wb_s3_addr = 0x03
 PARAMETER wb_s4_addr = 0x04
 PARAMETER wb_s5_addr = 0x05
 PARAMETER wb_s6_addr = 0x06
 PARAMETER wb_s7_addr = 0x07
 PARAMETER wb_s0_addr_w = 8
 PARAMETER wb_s1_addr_w = 8
 PORT wb_rst_i = sys_rst_s
 PORT wb_clk_i = clk_100MHz
END

BEGIN testram
 PARAMETER INSTANCE = onchip_ram_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER RD_DELAY = 0
 PARAMETER WR_DELAY = 0
 BUS_INTERFACE SWB = wb_conbus_0
 PORT wb_rst_i = sys_rst_s
 PORT wb_clk_i = clk_100MHz
END

BEGIN testram
 PARAMETER INSTANCE = onchip_ram_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER RD_DELAY = 1
 PARAMETER WR_DELAY = 1
 BUS_INTERFACE SWB = wb_conbus_0
 PORT wb_clk_i = clk_100MHz
 PORT wb_rst_i = sys_rst_s
END

BEGIN testram
 PARAMETER INSTANCE = onchip_ram_2
 PARAMETER HW_VER = 1.00.a
 PARAMETER RD_DELAY = 3
 PARAMETER WR_DELAY = 3
 BUS_INTERFACE SWB = wb_conbus_0
 PORT wb_clk_i = clk_100MHz
 PORT wb_rst_i = sys_rst_s
END

BEGIN testram
 PARAMETER INSTANCE = onchip_ram_3
 PARAMETER HW_VER = 1.00.a
 PARAMETER RD_DELAY = 5
 PARAMETER WR_DELAY = 5
 BUS_INTERFACE SWB = wb_conbus_0
 PORT wb_clk_i = clk_100MHz
 PORT wb_rst_i = sys_rst_s
END