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[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [simple/] [data/] [system.ucf] - Rev 2
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# Virtex 5 ML501 Evaluation PlatformNet fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;Net fpga_0_clk_1_sys_clk_pin LOC = AD8 | IOSTANDARD=LVCMOS33;Net fpga_0_rst_1_sys_rst_pin TIG;Net fpga_0_rst_1_sys_rst_pin LOC = T23 | IOSTANDARD=LVCMOS33 | PULLUP;