URL
https://opencores.org/ocsvn/potato/potato/trunk
Subversion Repositories potato
[/] [potato/] [tags/] [v0.1/] [README] - Rev 53
Go to most recent revision | Compare with Previous | Blame | View Log
# The Potato Processor
Potato is a simple processor for use in FPGAs, implementing the RV32I subset of the RISC-V ISA specification.
## Features
* Supports the full RV32I (RISC-V 32-bit integer subset) ISA.
* Additionally supports the csrr\* and sret instructions from the (previous) supervisor extension (draft).
* Includes an interface for the HTIF (Host/Target interface) registers, TOHOST and FROMHOST.
* Wishbone interface.
## Wishbone details
The wishbone interface for the processor is provided by the pp_wb_adapter module. Its details are as follows:
|-----------------------|---------------|
| Name | Value |
| --------------------- | ------------- |
| Wishbone revision | B4 |
| Interface type | Master |
| Address port width | 32 bits |
| Data port width | 32 bits |
| Data port granularity | 8 bits |
| Maximum operand size | 32 bits |
| Endianess | Little endian |
| Sequence of data xfer | Undefined |
|---------------------------------------|
For all Wishbone interfaces included in this project, the Wishbone signals are prefixed with `wb` and suffixed by the
signal direction.
## Potato Processor Quick Start
To instantiate the processor, add the source files from the `src/` folder to your project. Use the `pp_potato` core to
instantiate a processor core with a Wishbone interface. Additional peripherals for use in Wishbone-based Potato systems
can be found in the `soc/` folder.
Use the `pp_core` module to instantiate a processor core with a more generic interface, for instance for use with block
memories. In this instance, connect the data and instruction memory ports directly to the block RAM modules/interfaces
and set the acknowledge inputs to `'1'`.
Interrupts are triggered when an IRQ signal is high and the corresponding mask bit is set in the control/status register.
Go to most recent revision | Compare with Previous | Blame | View Log