Subversion Repositories powerseq

----------------------------------------------------------------------------------
-- Engineer: Istvan Nagy
-- Create Date: 10/06/2024 10:10:13 AM
---Version 1.0
-- License: 0BSD, no restrictions for use, no need to publish modified versions. 
--   The BSD 0-clause license: Copyright (C) 2024 by Istvan Nagy buenoshun@gmail.com 
--   Permission to use, copy, modify, and/or distribute this software for any purpose 
--   with or without fee is hereby granted. THE SOFTWARE IS PROVIDED "AS IS" AND 
--   THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE.
-- Module Name: example - Behavioral
-- Target devices: Microchip Igloo preferred, due to attributes.
-- This code shows how a sequencer is typically used on a simpler board.
-- Synthesis statistics: 489 registers, 1340 LUTs. 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--entity header  ----------------------------------------------------------------
entity example is
    Port ( 
           clk  : in std_logic; --25MHz clock
           reset_n  : in std_logic; --FPGA reset, needs 1ms from standby 3.3V on
           forcepoweron  : in std_logic; --from dip switch, avoid failure response
           thermal_n : in std_logic; --thermal shutdown, externally combine multiple sources 
           pfailure : out std_logic; --assers during failure --1 if one or more railes failed.
           pseqstate_out  : out std_logic_vector(3 downto 0); --we can monitor status through a pin with TopJtag
           --rails:
           P3V3_EN : out std_logic;
           P2V5_EN : out std_logic;
           P1V8_EN : out std_logic;
           P1V5_EN : out std_logic;
           P1V2_EN : out std_logic;
           P1V0_CORE_EN : out std_logic;
           PCH_PWRGD : out std_logic; --glue logic output to chipset
           board_reset_n : out std_logic; 
           P3V3_OK : in std_logic;
           P2V5_OK : in std_logic;
           P1V8_OK : in std_logic;
           P1V5_OK : in std_logic;
           P1V2_OK : in std_logic;
           P1V0_CORE_PGOOD : in std_logic;
           CK505_PLL_LOCK : in std_logic;
           --from IPMC or BMC:
           all_on  : in std_logic; --power master ordered the sequence to commence on
           all_pgood: out std_logic --tell the power master that all is on
           );
end example;
 
--architecture start ------------------------------------------------------------
architecture Behavioral of example is
 
-- INTERNAL SIGNALS -------------------------------------------------------------
 
           SIGNAL PSEQ_RAIL_PG :  std_logic_vector(127 downto 0); --map to rails
           SIGNAL PSEQ_RAIL_EN :  std_logic_vector(127 downto 0); --map to rails
           SIGNAL failed_rails :  std_logic_vector(255 downto 0); --bits=1 for failed rails
           SIGNAL tick_out :  std_logic; --available if needed outside, 1pulse in every several thousand clk
 
           SIGNAL delaysig_out1 :  std_logic;
           SIGNAL delaysig_in1  :  std_logic;
           SIGNAL delaycounter1  :  std_logic_vector(19 downto 0); 
 
 
--------- COMPONENT DECLARATIONS (introducing the IPs) --------------------------
	COMPONENT pseq_3redundant
	PORT(
		clk : IN std_logic;
		reset_n : IN std_logic;
		forcepoweron : IN std_logic;
		PSEQ_RAIL_PG : IN std_logic_vector(127 downto 0);
		thermal_n : IN std_logic;
		all_on : IN std_logic;          
		PSEQ_RAIL_EN : OUT std_logic_vector(127 downto 0);
		failed_rails : OUT std_logic_vector(255 downto 0);
		pfailure : OUT std_logic;
		tick_out : OUT std_logic;
		pseqstate_out : OUT std_logic_vector(3 downto 0);
		all_pgood : OUT std_logic
		);
	END COMPONENT;
 
 
--architecture body start -------------------------------------------------------
begin
 
	Inst_pseq_3redundant: pseq_3redundant PORT MAP(
		clk => clk,
		reset_n => reset_n,
		forcepoweron => forcepoweron,
		PSEQ_RAIL_EN => PSEQ_RAIL_EN,
		PSEQ_RAIL_PG => PSEQ_RAIL_PG,
		thermal_n => thermal_n,
		failed_rails => failed_rails,
		pfailure => pfailure,
		tick_out => tick_out,
		pseqstate_out => pseqstate_out,
		all_on => all_on,
		all_pgood => all_pgood
	);
 
 
 
-- Rail assignments:
 
P3V3_EN <= PSEQ_RAIL_EN(0);
P2V5_EN <= PSEQ_RAIL_EN(1);
P1V8_EN <= PSEQ_RAIL_EN(2);
P1V5_EN <= PSEQ_RAIL_EN(3);
P1V2_EN <= PSEQ_RAIL_EN(4);
P1V0_CORE_EN <= PSEQ_RAIL_EN(5);
-- <= PSEQ_RAIL_EN(6); unused, wait for pll
PCH_PWRGD <= PSEQ_RAIL_EN(7);
delaysig_in1 <= PSEQ_RAIL_EN(8);
-- <= PSEQ_RAIL_EN(127 downto 9); unused
 
PSEQ_RAIL_PG(0) <= P3V3_OK;
PSEQ_RAIL_PG(1) <= P2V5_OK;
PSEQ_RAIL_PG(2) <= P1V8_OK;
PSEQ_RAIL_PG(3) <= P1V5_OK;
PSEQ_RAIL_PG(4) <= P1V2_OK;
PSEQ_RAIL_PG(5) <= P1V0_CORE_PGOOD;
PSEQ_RAIL_PG(6) <= CK505_PLL_LOCK;
PSEQ_RAIL_PG(7) <= '1'; --just a chipset powergood, no need to wait.
PSEQ_RAIL_PG(8) <= delaysig_out1; --waiting for the 20m reset delay
PSEQ_RAIL_PG(127 downto 9) <= (others => '1'); --unused
 
 
--simple DELAY:
process ( reset_n, clk, delaysig_in1 )
   begin
     if ( reset_n='0' or delaysig_in1='0') then
        delaysig_out1 <= '0';
        delaycounter1 <= (others => '0');
     elsif (clk'event and clk='1') then
        if ( delaycounter1 = "01111010000100100000" ) then --after 20msec (40ns clk period)
           delaysig_out1 <= '1';
           delaycounter1 <= delaycounter1; --stop counting
        else
           delaycounter1 <= delaycounter1 +1;
           delaysig_out1 <= '0';
        end if;
     end if; 
   end process;
 
board_reset_n <= delaysig_out1;
 
 
 
 
--end file ----------------------------------------------------------------------
end Behavioral;