Subversion Repositories powerseq

-- VHDL Instantiation Created from source file powerseq_mod.vhd -- 12:46:39 10/06/2024
-- 
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

        COMPONENT powerseq_mod
        PORT(
                clk : IN std_logic;
                reset_n : IN std_logic;
                forcepoweron : IN std_logic;
                PSEQ_RAIL_PG : IN std_logic_vector(127 downto 0);
                thermal_n : IN std_logic;
                all_on : IN std_logic;          
                PSEQ_RAIL_EN : OUT std_logic_vector(127 downto 0);
                failed_rails : OUT std_logic_vector(255 downto 0);
                pfailure : OUT std_logic;
                tick_out : OUT std_logic;
                pseqstate_out : OUT std_logic_vector(3 downto 0);
                all_pgood : OUT std_logic
                );
        END COMPONENT;

        Inst_powerseq_mod: powerseq_mod PORT MAP(
                clk => ,
                reset_n => ,
                forcepoweron => ,
                PSEQ_RAIL_EN => ,
                PSEQ_RAIL_PG => ,
                thermal_n => ,
                failed_rails => ,
                pfailure => ,
                tick_out => ,
                pseqstate_out => ,
                all_on => ,
                all_pgood => 
        );