Subversion Repositories powerseq

----------------------------------------------------------------------------------
-- Engineer: Istvan Nagy
-- Create Date: 10/06/2024 10:10:13 AM 
---Version 1.0
-- License: 0BSD, no restrictions for use, no need to publish modified versions. 
--   The BSD 0-clause license: Copyright (C) 2024 by Istvan Nagy buenoshun@gmail.com 
--   Permission to use, copy, modify, and/or distribute this software for any purpose 
--   with or without fee is hereby granted. THE SOFTWARE IS PROVIDED "AS IS" AND 
--   THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE.
-- Module Name: pseq_3redundant - Behavioral
-- Target devices: Microchip Igloo preferred, due to attributes.
-- This code is a wrapper for the powerseq_mod.
--   It creates a triple-redundant and SEU-immune sequencer by using 3 instances
--   of the original sequencer and voting logic on its outputs.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--entity header  ----------------------------------------------------------------
entity pseq_3redundant is
    Port ( 
           clk  : in std_logic; --25MHz clock
           reset_n  : in std_logic; --FPGA reset, needs 1ms from standby 3.3V on
           forcepoweron  : in std_logic; --from dip switch, avoid failure response
           PSEQ_RAIL_EN : out std_logic_vector(127 downto 0); --map to rails
           PSEQ_RAIL_PG : in std_logic_vector(127 downto 0); --map to rails
           thermal_n : in std_logic; --thermal shutdown, externally combine multiple sources 
           failed_rails : out std_logic_vector(255 downto 0); --bits=1 for failed rails
           pfailure : out std_logic; --assers during failure --1 if one or more railes failed.
           tick_out : out std_logic; --available if needed outside, 1pulse in every several thousand clk
           pseqstate_out  : out std_logic_vector(3 downto 0); --we can monitor status through a pin with TopJtag
           all_on  : in std_logic; --power master ordered the sequence to commence on
           all_pgood: out std_logic --tell the power master that all is on
           );
 
 end pseq_3redundant;
 
 
--architecture start ------------------------------------------------------------
architecture Behavioral of pseq_3redundant is
 
attribute syn_preserve : boolean;
attribute syn_preserve of Behavioral: architecture is true;
 
-- INTERNAL SIGNALS -------------------------------------------------------------
 
           SIGNAL PSEQ_RAIL_ENa :  std_logic_vector(127 downto 0); --map to rails
           SIGNAL failed_railsa :  std_logic_vector(255 downto 0); --bits=1 for failed rails
           SIGNAL pfailurea :  std_logic; --assers during failure --1 if one or more railes failed.
           SIGNAL tick_outa :  std_logic; --available if needed outside, 1pulse in every several thousand clk
           SIGNAL pseqstate_outa  :  std_logic_vector(3 downto 0); --we can monitor status through a pin with TopJtag
           SIGNAL all_pgooda:  std_logic; --tell the power master that all is on
 
           SIGNAL PSEQ_RAIL_ENb :  std_logic_vector(127 downto 0); --map to rails
           SIGNAL failed_railsb :  std_logic_vector(255 downto 0); --bits=1 for failed rails
           SIGNAL pfailureb :  std_logic; --assers during failure --1 if one or more railes failed.
           SIGNAL tick_outb :  std_logic; --available if needed outside, 1pulse in every several thousand clk
           SIGNAL pseqstate_outb  :  std_logic_vector(3 downto 0); --we can monitor status through a pin with TopJtag
           SIGNAL all_pgoodb:  std_logic; --tell the power master that all is on
 
           SIGNAL PSEQ_RAIL_ENc :  std_logic_vector(127 downto 0); --map to rails
           SIGNAL failed_railsc :  std_logic_vector(255 downto 0); --bits=1 for failed rails
           SIGNAL pfailurec :  std_logic; --assers during failure --1 if one or more railes failed.
           SIGNAL tick_outc :  std_logic; --available if needed outside, 1pulse in every several thousand clk
           SIGNAL pseqstate_outc  :  std_logic_vector(3 downto 0); --we can monitor status through a pin with TopJtag
           SIGNAL all_pgoodc:  std_logic; --tell the power master that all is on
 
 
--------- COMPONENT DECLARATIONS (introducing the IPs) --------------------------
	COMPONENT powerseq_mod
	PORT(
		clk : IN std_logic;
		reset_n : IN std_logic;
		forcepoweron : IN std_logic;
		PSEQ_RAIL_PG : IN std_logic_vector(127 downto 0);
		thermal_n : IN std_logic;
		all_on : IN std_logic;          
		PSEQ_RAIL_EN : OUT std_logic_vector(127 downto 0);
		failed_rails : OUT std_logic_vector(255 downto 0);
		pfailure : OUT std_logic;
		tick_out : OUT std_logic;
		pseqstate_out : OUT std_logic_vector(3 downto 0);
		all_pgood : OUT std_logic
		);
	END COMPONENT;
 
 
--architecture body start -------------------------------------------------------
begin
 
 
	Inst_powerseq_mod1: powerseq_mod PORT MAP(
		clk => clk,
		reset_n => reset_n,
		forcepoweron => forcepoweron,
		PSEQ_RAIL_EN => PSEQ_RAIL_ENa,
		PSEQ_RAIL_PG => PSEQ_RAIL_PG,
		thermal_n => thermal_n,
		failed_rails => failed_railsa,
		pfailure => pfailurea,
		tick_out => tick_outa,
		pseqstate_out => pseqstate_outa,
		all_on => all_on,
		all_pgood => all_pgooda
	);
	Inst_powerseq_mod2: powerseq_mod PORT MAP(
		clk => clk,
		reset_n => reset_n,
		forcepoweron => forcepoweron,
		PSEQ_RAIL_EN => PSEQ_RAIL_ENb,
		PSEQ_RAIL_PG => PSEQ_RAIL_PG,
		thermal_n => thermal_n,
		failed_rails => failed_railsb,
		pfailure => pfailureb,
		tick_out => tick_outb,
		pseqstate_out => pseqstate_outb,
		all_on => all_on,
		all_pgood => all_pgoodb
	);
	Inst_powerseq_mod3: powerseq_mod PORT MAP(
		clk => clk,
		reset_n => reset_n,
		forcepoweron => forcepoweron,
		PSEQ_RAIL_EN => PSEQ_RAIL_ENc,
		PSEQ_RAIL_PG => PSEQ_RAIL_PG,
		thermal_n => thermal_n,
		failed_rails => failed_railsc,
		pfailure => pfailurec,
		tick_out => tick_outc,
		pseqstate_out => pseqstate_outc,
		all_on => all_on,
		all_pgood => all_pgoodc
	);
 
 
--3 input voting logic:
--T = (A * B) + (B * C) + (C * A)
 
PSEQ_RAIL_EN <= (PSEQ_RAIL_ENa AND PSEQ_RAIL_ENb) OR (PSEQ_RAIL_ENa AND PSEQ_RAIL_ENc) OR (PSEQ_RAIL_ENb AND PSEQ_RAIL_ENc); 
failed_rails <= (failed_railsa AND failed_railsb) OR (failed_railsa AND failed_railsc) OR (failed_railsb AND failed_railsc); 
pfailure <= (pfailurea AND pfailureb) OR (pfailurea AND pfailurec) OR (pfailureb AND pfailurec);  
tick_out <= (tick_outa AND tick_outb) OR (tick_outa AND tick_outc) OR (tick_outb AND tick_outc); 
pseqstate_out <= (pseqstate_outa AND pseqstate_outb) OR (pseqstate_outa AND pseqstate_outc) OR (pseqstate_outb AND pseqstate_outc); 
all_pgood <= (all_pgooda AND all_pgoodb) OR (all_pgooda AND all_pgoodc) OR (all_pgoodb AND all_pgoodc); 
 
 
--end file ----------------------------------------------------------------------
end Behavioral;