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[/] [ps2_keyboard_interface/] [Keyboard_Controller.syr] - Rev 2
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Release 12.3 - xst M.70d (lin64)Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.-->Parameter TMPDIR set to xst/projnav.tmpTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.04 secs-->Parameter xsthdpdir set to xstTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.04 secs-->Reading design: Keyboard_Controller.prjTABLE OF CONTENTS1) Synthesis Options Summary2) HDL Compilation3) Design Hierarchy Analysis4) HDL Analysis5) HDL Synthesis5.1) HDL Synthesis Report6) Advanced HDL Synthesis6.1) Advanced HDL Synthesis Report7) Low Level Synthesis8) Partition Report9) Final Report9.1) Device utilization summary9.2) Partition Resource Summary9.3) TIMING REPORT=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "Keyboard_Controller.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "Keyboard_Controller"Output Format : NGCTarget Device : xc3s200-5-ft256---- Source OptionsTop Module Name : Keyboard_ControllerAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoSafe Implementation : NoFSM Style : LUTRAM Extraction : YesRAM Style : AutoROM Extraction : YesMux Style : AutoDecoder Extraction : YESPriority Encoder Extraction : YesShift Register Extraction : YESLogical Shifter Extraction : YESXOR Collapsing : YESROM Style : AutoMux Extraction : YesResource Sharing : YESAsynchronous To Synchronous : NOMultiplier Style : AutoAutomatic Register Balancing : No---- Target OptionsAdd IO Buffers : YESGlobal Maximum Fanout : 500Add Generic Clock Buffer(BUFG) : 8Register Duplication : YESSlice Packing : YESOptimize Instantiated Primitives : NOUse Clock Enable : YesUse Synchronous Set : YesUse Synchronous Reset : YesPack IO Registers into IOBs : AutoEquivalent register Removal : YES---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Keep Hierarchy : NoNetlist Hierarchy : As_OptimizedRTL Output : YesGlobal Optimization : AllClockNetsRead Cores : YESWrite Timing Constraints : NOCross Clock Analysis : NOHierarchy Separator : /Bus Delimiter : <>Case Specifier : MaintainSlice Utilization Ratio : 100BRAM Utilization Ratio : 100Verilog 2001 : YESAuto BRAM Packing : NOSlice Utilization Ratio Delta : 5==================================================================================================================================================* HDL Compilation *=========================================================================Compiling vhdl file "/home/omar/Mano/Mano/SevenSegment.vhd" in Library work.Architecture behavioral of Entity sevensegment is up to date.Compiling vhdl file "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.vhd" in Library work.Entity <keyboard_controller> compiled.Entity <keyboard_controller> (Architecture <behavioral>) compiled.=========================================================================* Design Hierarchy Analysis *=========================================================================Analyzing hierarchy for entity <Keyboard_Controller> in library <work> (architecture <behavioral>).Analyzing hierarchy for entity <SevenSegment> in library <work> (architecture <behavioral>).=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <Keyboard_Controller> in library <work> (Architecture <behavioral>).Entity <Keyboard_Controller> analyzed. Unit <Keyboard_Controller> generated.Analyzing Entity <SevenSegment> in library <work> (Architecture <behavioral>).Entity <SevenSegment> analyzed. Unit <SevenSegment> generated.=========================================================================* HDL Synthesis *=========================================================================Performing bidirectional port resolution...Synthesizing Unit <SevenSegment>.Related source file is "/home/omar/Mano/Mano/SevenSegment.vhd".Found 16x8-bit ROM for signal <Segments>.Found 1-of-4 decoder for signal <Enables>.Found 4-bit 4-to-1 multiplexer for signal <Chosen>.Found 13-bit up counter for signal <Counter>.Summary:inferred 1 ROM(s).inferred 1 Counter(s).inferred 4 Multiplexer(s).inferred 1 Decoder(s).Unit <SevenSegment> synthesized.Synthesizing Unit <Keyboard_Controller>.Related source file is "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.vhd".WARNING:Xst:646 - Signal <data<21>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.Found 5-bit up counter for signal <Counter>.Found 21-bit register for signal <data<20:0>>.Found 8-bit register for signal <OutByte1>.Found 8-bit register for signal <OutByte2>.Found 8-bit up counter for signal <presses>.Summary:inferred 2 Counter(s).inferred 37 D-type flip-flop(s).Unit <Keyboard_Controller> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 116x8-bit ROM : 1# Counters : 313-bit up counter : 15-bit up counter : 18-bit up counter : 1# Registers : 231-bit register : 218-bit register : 2# Multiplexers : 14-bit 4-to-1 multiplexer : 1# Decoders : 11-of-4 decoder : 1==================================================================================================================================================* Advanced HDL Synthesis *==================================================================================================================================================Advanced HDL Synthesis ReportMacro Statistics# ROMs : 116x8-bit ROM : 1# Counters : 313-bit up counter : 15-bit up counter : 18-bit up counter : 1# Registers : 37Flip-Flops : 37# Multiplexers : 14-bit 4-to-1 multiplexer : 1# Decoders : 11-of-4 decoder : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <Keyboard_Controller> ...Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block Keyboard_Controller, actual ratio is 2.Final Macro Processing ...Processing Unit <Keyboard_Controller> :Found 3-bit shift register for signal <data_2>.Found 4-bit shift register for signal <data_13>.Unit <Keyboard_Controller> processed.=========================================================================Final Register ReportMacro Statistics# Registers : 56Flip-Flops : 56# Shift Registers : 23-bit shift register : 14-bit shift register : 1==================================================================================================================================================* Partition Report *=========================================================================Partition Implementation Status-------------------------------No Partitions were found in this design.-------------------------------=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : Keyboard_Controller.ngrTop Level Output File Name : Keyboard_ControllerOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : NoDesign Statistics# IOs : 23Cell Usage :# BELS : 97# GND : 1# INV : 4# LUT1 : 19# LUT2 : 5# LUT2_D : 1# LUT3 : 10# LUT3_L : 1# LUT4 : 11# MUXCY : 19# MUXF5 : 4# VCC : 1# XORCY : 21# FlipFlops/Latches : 58# FD : 13# FD_1 : 16# FDE : 8# FDE_1 : 16# FDR : 5# Shift Registers : 2# SRL16_1 : 2# Clock Buffers : 2# BUFGP : 2# IO Buffers : 21# IBUF : 1# OBUF : 20=========================================================================Device utilization summary:---------------------------Selected Device : 3s200ft256-5Number of Slices: 40 out of 1920 2%Number of Slice Flip Flops: 58 out of 3840 1%Number of 4 input LUTs: 53 out of 3840 1%Number used as logic: 51Number used as Shift registers: 2Number of IOs: 23Number of bonded IOBs: 23 out of 173 13%Number of GCLKs: 2 out of 8 25%---------------------------Partition Resource Summary:---------------------------No Partitions were found in this design.---------------------------=========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORTGENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+Clk | BUFGP | 47 |Clk2 | BUFGP | 13 |-----------------------------------+------------------------+-------+Asynchronous Control Signals Information:----------------------------------------No asynchronous control signals found in this designTiming Summary:---------------Speed Grade: -5Minimum period: 5.006ns (Maximum Frequency: 199.770MHz)Minimum input arrival time before clock: 1.778nsMaximum output required time after clock: 9.978nsMaximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'Clk'Clock period: 5.006ns (frequency: 199.770MHz)Total number of paths / destination ports: 229 / 75-------------------------------------------------------------------------Delay: 5.006ns (Levels of Logic = 2)Source: Counter_1 (FF)Destination: OutByte1_0 (FF)Source Clock: Clk fallingDestination Clock: Clk fallingData Path: Counter_1 to OutByte1_0Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDR:C->Q 5 0.626 1.078 Counter_1 (Counter_1)LUT2_D:I0->O 2 0.479 0.768 OutByte1_cmp_eq0000_SW0 (N14)LUT4:I3->O 16 0.479 1.051 OutByte1_cmp_eq0000_1 (OutByte1_cmp_eq00001)FDE_1:CE 0.524 OutByte2_0----------------------------------------Total 5.006ns (2.108ns logic, 2.898ns route)(42.1% logic, 57.9% route)=========================================================================Timing constraint: Default period analysis for Clock 'Clk2'Clock period: 4.033ns (frequency: 247.964MHz)Total number of paths / destination ports: 91 / 13-------------------------------------------------------------------------Delay: 4.033ns (Levels of Logic = 13)Source: Inst_SevenSegment/Counter_1 (FF)Destination: Inst_SevenSegment/Counter_12 (FF)Source Clock: Clk2 risingDestination Clock: Clk2 risingData Path: Inst_SevenSegment/Counter_1 to Inst_SevenSegment/Counter_12Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FD:C->Q 1 0.626 0.976 Inst_SevenSegment/Counter_1 (Inst_SevenSegment/Counter_1)LUT1:I0->O 1 0.479 0.000 Inst_SevenSegment/Mcount_Counter_cy<1>_rt (Inst_SevenSegment/Mcount_Counter_cy<1>_rt)MUXCY:S->O 1 0.435 0.000 Inst_SevenSegment/Mcount_Counter_cy<1> (Inst_SevenSegment/Mcount_Counter_cy<1>)MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<2> (Inst_SevenSegment/Mcount_Counter_cy<2>)MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<3> (Inst_SevenSegment/Mcount_Counter_cy<3>)MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<4> (Inst_SevenSegment/Mcount_Counter_cy<4>)MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<5> (Inst_SevenSegment/Mcount_Counter_cy<5>)MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<6> (Inst_SevenSegment/Mcount_Counter_cy<6>)MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<7> (Inst_SevenSegment/Mcount_Counter_cy<7>)MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<8> (Inst_SevenSegment/Mcount_Counter_cy<8>)MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<9> (Inst_SevenSegment/Mcount_Counter_cy<9>)MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<10> (Inst_SevenSegment/Mcount_Counter_cy<10>)MUXCY:CI->O 0 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<11> (Inst_SevenSegment/Mcount_Counter_cy<11>)XORCY:CI->O 1 0.786 0.000 Inst_SevenSegment/Mcount_Counter_xor<12> (Result<12>)FD:D 0.176 Inst_SevenSegment/Counter_12----------------------------------------Total 4.033ns (3.057ns logic, 0.976ns route)(75.8% logic, 24.2% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'Total number of paths / destination ports: 1 / 1-------------------------------------------------------------------------Offset: 1.778ns (Levels of Logic = 1)Source: DataIn (PAD)Destination: Mshreg_data_2 (FF)Destination Clock: Clk fallingData Path: DataIn to Mshreg_data_2Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------IBUF:I->O 1 0.715 0.681 DataIn_IBUF (DataIn_IBUF)SRL16_1:D 0.382 Mshreg_data_2----------------------------------------Total 1.778ns (1.097ns logic, 0.681ns route)(61.7% logic, 38.3% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk2'Total number of paths / destination ports: 92 / 11-------------------------------------------------------------------------Offset: 9.978ns (Levels of Logic = 4)Source: Inst_SevenSegment/Counter_11 (FF)Destination: Segments<6> (PAD)Source Clock: Clk2 risingData Path: Inst_SevenSegment/Counter_11 to Segments<6>Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FD:C->Q 13 0.626 1.290 Inst_SevenSegment/Counter_11 (Inst_SevenSegment/Counter_11)LUT3:I0->O 1 0.479 0.000 Inst_SevenSegment/Mmux_Chosen_3 (Inst_SevenSegment/Mmux_Chosen_3)MUXF5:I1->O 7 0.314 1.201 Inst_SevenSegment/Mmux_Chosen_2_f5 (Inst_SevenSegment/Chosen<0>)LUT4:I0->O 1 0.479 0.681 Inst_SevenSegment/Mrom_Segments111 (Segments_1_OBUF)OBUF:I->O 4.909 Segments_1_OBUF (Segments<1>)----------------------------------------Total 9.978ns (6.807ns logic, 3.171ns route)(68.2% logic, 31.8% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'Total number of paths / destination ports: 120 / 15-------------------------------------------------------------------------Offset: 9.540ns (Levels of Logic = 4)Source: OutByte1_5 (FF)Destination: Segments<6> (PAD)Source Clock: Clk fallingData Path: OutByte1_5 to Segments<6>Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDE_1:C->Q 1 0.626 0.851 OutByte1_5 (OutByte1_5)LUT3:I1->O 1 0.479 0.000 Inst_SevenSegment/Mmux_Chosen_41 (Inst_SevenSegment/Mmux_Chosen_41)MUXF5:I0->O 7 0.314 1.201 Inst_SevenSegment/Mmux_Chosen_2_f5_0 (Inst_SevenSegment/Chosen<1>)LUT4:I0->O 1 0.479 0.681 Inst_SevenSegment/Mrom_Segments21 (Segments_2_OBUF)OBUF:I->O 4.909 Segments_2_OBUF (Segments<2>)----------------------------------------Total 9.540ns (6.807ns logic, 2.733ns route)(71.4% logic, 28.6% route)=========================================================================Total REAL time to Xst completion: 5.00 secsTotal CPU time to Xst completion: 4.77 secs-->Total memory usage is 339112 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 1 ( 0 filtered)Number of infos : 0 ( 0 filtered)