OpenCores
URL https://opencores.org/ocsvn/pss/pss/trunk

Subversion Repositories pss

[/] [pss/] [trunk/] [pss/] [SW/] [onboard/] [Interrupts/] [Interrupts.c] - Rev 3

Compare with Previous | Blame | View Log

#define IO_GPR                  (*(volatile unsigned int *)(0x8A000000))
 
#define REG_CPU_CONTROL         (*(volatile unsigned int *)(0x40000000))
#define REG_CPU_PC              (*(volatile unsigned int *)(0x40000004))
#define REG_CPU_A31             (*(volatile unsigned int *)(0x40000008))
#define REG_DBG_A31             (*(volatile unsigned int *)(0x4000000C))
 
#define REG_INTC_CONTROL        (*(volatile unsigned int *)(0x40000010))
#define REG_INTC_MASK           (*(volatile unsigned int *)(0x40000014))
#define REG_INTC_REQ            (*(volatile unsigned int *)(0x40000018))
#define REG_MEM_SIZE_KB         (*(volatile unsigned int *)(0x4000001C))
 
#define REG_DMA_CONTROL         (*(volatile unsigned int *)(0x40000020))
#define REG_DMA_SOURCEADDR      (*(volatile unsigned int *)(0x40000024))
#define REG_DMA_DESTADDR        (*(volatile unsigned int *)(0x40000028))
#define REG_DMA_SIZE            (*(volatile unsigned int *)(0x4000002C))
 
#define REG_SGI                 (*(volatile unsigned int *)(0x40000030))
 
#define REG_BUS_ERROR_ADDR      (*(volatile unsigned int *)(0x40000038))
#define REG_BUS_ERROR_PC        (*(volatile unsigned int *)(0x4000003C))
 
#define REG_TRAP_CONTROL        (*(volatile unsigned int *)(0x40000040))
#define REG_TRAP_ADDR           (*(volatile unsigned int *)(0x40000044))
 
#define REG_INTC_CONTROL        (*(volatile unsigned int *)(0x40000010))
#define REG_INTC_MASK           (*(volatile unsigned int *)(0x40000014))
#define REG_INTC_REQ            (*(volatile unsigned int *)(0x40000018))
 
int inc_data;
 
void _zpu_interrupt(void)
{
    inc_data++;
	IO_GPR = inc_data;
 
    REG_INTC_REQ = 0xFF;			// deasserting requests
}
 
int main()
{
    inc_data = 0x81;
    IO_GPR = inc_data;
 
    REG_INTC_MASK = 0xFF;
 
    REG_INTC_CONTROL = 0x01;        // enabling IE
 
    while (1)
    {
    	REG_INTC_CONTROL = 0x01;	// enabling IE
    }
}
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.