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[/] [pss/] [trunk/] [pss/] [hdl/] [debouncer.v] - Rev 4
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module debouncer ( input clk_i, rst_i, input in_i, output out_o ); reg [7:0] state; assign out_o = state[7]; always @(posedge clk_i) begin if (rst_i) begin state <= 8'h0; end else begin if (in_i == 1'b1) begin if (state != 8'hFF) state <= state + 8'h1; end else begin if (state != 8'h00) state <= state - 8'h1; end end end endmodule
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