Subversion Repositories pss

/*
 PSS
 
 Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
 All rights reserved.
 
 Version 0.99
 
 The FreeBSD license
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions
 are met:
 
 1. Redistributions of source code must retain the above copyright
    notice, this list of conditions and the following disclaimer.
 2. Redistributions in binary form must reproduce the above
    copyright notice, this list of conditions and the following
    disclaimer in the documentation and/or other materials
    provided with the distribution.
 
 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
 
module pss
#(
	parameter CPU_PRESENT = 1,
	parameter CPU_RESET_DEFAULT = 1,
	parameter EXT_RESET_DEFAULT = 1,
	parameter A31_DEFAULT = 1,
	parameter MEM_SIZE_KB = 1,
	parameter MEM_DATA = ""
)
(
	input  clk_i,
	input  arst_i, srst_i,
	output srst_o, ext_rst_o,
 
	input  rx_i,
	output tx_o,
 
	input [3:0] INT_bi,
 
	// Expansion bus
	output xport_req_o,
	input  xport_ack_i,
	input  xport_err_i,
	output xport_we_o,
	output [31:0] xport_addr_bo,
	output [31:0] xport_wdata_bo,
	input  xport_resp_i,
	input  [31:0] xport_rdata_bi
);
 
wire zpu_uc_srst, udm_rst;
assign zpu_uc_srst = srst_i | udm_rst;
 
wire dbg_bus_enb;
wire dbg_bus_we;
wire [31:0] dbg_bus_addr;
wire [31:0] dbg_bus_wdata;
wire [31:0] dbg_bus_rdata;
wire dbg_bus_resp;
 
udm udm
(
	.clk_i(clk_i),
	.rst_i(srst_o),
 
	.rx_i(rx_i),
	.tx_o(tx_o),
 
	.rst_o(udm_rst),
	.bus_enb_o(dbg_bus_enb),
	.bus_we_o(dbg_bus_we),
	.bus_addr_bo(dbg_bus_addr),
    .bus_wdata_bo(dbg_bus_wdata),
 
    .bus_ack_i(dbg_bus_resp),
    .bus_rdata_bi(dbg_bus_rdata)
);
 
ZPU_uC
#(
	.CPU_PRESENT(CPU_PRESENT),
	.CPU_RESET_DEFAULT(CPU_RESET_DEFAULT),
	.EXT_RESET_DEFAULT(EXT_RESET_DEFAULT),
	.A31_DEFAULT(A31_DEFAULT),
	.MEM_DATA(MEM_DATA),
	.MEM_SIZE_KB(MEM_SIZE_KB)
)
ZPU_uC
(
	.clk_i(clk_i),
 
	.arst_i(arst_i),
	.srst_o(srst_o),
 
	.srst_i(zpu_uc_srst),
	.ext_rst_o(ext_rst_o),
 
	.INT_bi(INT_bi),
 
	// Expansion bus
	.xport_req_o(xport_req_o),
	.xport_ack_i(xport_ack_i),
	.xport_err_i(xport_err_i),
	.xport_we_o(xport_we_o),
	.xport_addr_bo(xport_addr_bo),
	.xport_wdata_bo(xport_wdata_bo),
	.xport_resp_i(xport_resp_i),
	.xport_rdata_bi(xport_rdata_bi),
 
	//Debug interface
	.dbg_enb_i(dbg_bus_enb),
	.dbg_wr_i(dbg_bus_we),
	.dbg_addr_bi(dbg_bus_addr),
	.dbg_data_bi(dbg_bus_wdata),
	.dbg_resp_o(dbg_bus_resp),
	.dbg_data_bo(dbg_bus_rdata) 
);
 
endmodule