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/*
 PSS
 
 Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
 All rights reserved.
 
 Version 0.9
 
 The FreeBSD license
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions
 are met:
 
 1. Redistributions of source code must retain the above copyright
    notice, this list of conditions and the following disclaimer.
 2. Redistributions in binary form must reproduce the above
    copyright notice, this list of conditions and the following
    disclaimer in the documentation and/or other materials
    provided with the distribution.
 
 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
 
module PSS_DMA
(
	input clk_i, rst_i,
 
	input xport_busy_i,
	output xport_busy_o,
 
	output reg dma_int_o,
 
	input dma_req_i,
	input dma_cmd_i,
	input dma_autoinc_i,
	input [31:0] dma_size_bi,
	input [31:0] dma_sourceaddr_bi,
	input [31:0] dma_destaddr_bi,
 
	// RAM 1 interface
	output reg [31:0] ram_addr_bo,
	output reg ram_we_o,
	output reg [31:0] ram_wdata_bo,
	input [31:0] ram_rdata_bi,
 
	// Expansion bus //
	output reg xport_req_o,
	input  xport_ack_i,
	input  xport_err_i,
	output reg xport_we_o,
	output reg [31:0] xport_addr_bo,
	output reg [31:0] xport_wdata_bo,
	input xport_resp_i,
	input [31:0] xport_rdata_bi
);
 
localparam DMA_IDLE = 3'h0;
localparam DMA_WAIT = 3'h1;
localparam DMA_PRESTART = 3'h2;
localparam DMA_WORK = 3'h3;
localparam DMA_LOAD = 3'h4;
localparam DMA_STORE = 3'h5;
 
reg [2:0] DMA_state;
 
reg [31:0] dma_sourceaddr;
reg [31:0] dma_destaddr;
reg [31:0] dma_size, dma_size_aux;
 
assign xport_busy_o = ((DMA_state == DMA_IDLE) || (DMA_state == DMA_WAIT)) ? 1'b0 : 1'b1;
 
// DMA data logic
reg [31:0] ram1_addr, ram1_addr_shadow;
 
always @*
	begin
	if (DMA_state != DMA_LOAD)
		ram_addr_bo = ram1_addr;
	else if (xport_ack_i == 1'b1)
		ram_addr_bo = ram1_addr;
	else
		ram_addr_bo = ram1_addr_shadow;
	end
 
always @(posedge clk_i)
	begin
	if (rst_i)
		ram1_addr_shadow <= 32'h0;
	else if (xport_ack_i == 1'b1)
		ram1_addr_shadow <= ram1_addr;
	end
 
always @*
	begin
 
	xport_req_o = 1'b0;
	xport_we_o = 1'b0;
	xport_addr_bo = 32'hx;
	xport_wdata_bo = 32'hx;
 
	ram1_addr = dma_sourceaddr;
	ram_we_o = 1'b0;
	ram_wdata_bo = 32'hx;
 
	if (DMA_state == DMA_LOAD)
		begin
 
		if (dma_size != 32'h0)
			begin
			xport_req_o = 1'b1;
			xport_we_o = 1'b0;
			xport_addr_bo = dma_sourceaddr;
			xport_wdata_bo = 32'hx;
			end
 
		if (dma_size_aux != 32'h0)
			begin
			ram1_addr = dma_destaddr;
			ram_we_o = xport_resp_i;
			ram_wdata_bo = xport_rdata_bi;
			end
 
		end
 
	else if (DMA_state == DMA_STORE)
		begin
 
		if (dma_size != 32'h0)
			begin
			xport_req_o = 1'b1;
			xport_we_o = 1'b1;
			xport_addr_bo = dma_destaddr;
			xport_wdata_bo = ram_rdata_bi;
			end
 
		end
 
	end
 
// DMA control logic
always @(posedge clk_i)
	begin
	if (rst_i)
		begin
 
		DMA_state <= DMA_IDLE;
 
		dma_sourceaddr <= 32'h0;
		dma_destaddr <= 32'h0;
		dma_size <= 32'h0;
 
		dma_int_o <= 1'b0;
 
		end
	else
		begin
 
		dma_int_o <= 1'b0;
 
		case (DMA_state)
 
			DMA_IDLE:
				begin
				if (dma_req_i)
					begin
					dma_size <= dma_size_bi;
					dma_size_aux <= dma_size_bi;
					dma_sourceaddr <= dma_sourceaddr_bi;
					dma_destaddr <= dma_destaddr_bi;
 
					DMA_state <= DMA_WAIT;
					end
				end
 
			DMA_WAIT:
				begin
				if (!xport_busy_i)	// no pending requests
					if (dma_cmd_i)
						begin
						dma_sourceaddr <= dma_sourceaddr + 32'h4;
						DMA_state <= DMA_STORE;
						end
					else 
						DMA_state <= DMA_LOAD;
				end
 
			DMA_STORE:
				begin
				if (xport_ack_i == 1'b1)
					if (dma_size == 32'h4)
						begin
						DMA_state <= DMA_IDLE;
						dma_int_o <= 1'b1;
						end
					else 
						begin
						dma_size <= dma_size - 32'h4;
						dma_sourceaddr <= dma_sourceaddr + 32'h4;
						if (dma_autoinc_i == 1'b1) dma_destaddr <= dma_destaddr + 32'h4;
						end
				end
 
			DMA_LOAD:
				begin
 
				if ( (xport_ack_i == 1'b1) && (dma_size != 32'h0) )
					begin
					if (dma_autoinc_i == 1'b1) dma_sourceaddr <= dma_sourceaddr + 32'h4;
					dma_size <= dma_size - 32'h4;
					end
 
				if ( (xport_resp_i == 1'b1) && (dma_size_aux != 32'h0) )
					begin
					dma_destaddr <= dma_destaddr + 32'h4;
					dma_size_aux <= dma_size_aux - 32'h4;
					end
 
				if ( (dma_size == 32'h0) && (dma_size_aux == 32'h0) )
					begin
					DMA_state <= DMA_IDLE;
					dma_int_o <= 1'b1;
					end
 
				end
 
			default:
				DMA_state <= DMA_IDLE;
 
		endcase
		end
	end
 
endmodule