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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [zpu_uc/] [zpu_uc.v] - Rev 4
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/* PSS Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> All rights reserved. Version 0.9 The FreeBSD license Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ module ZPU_uC #( parameter CPU_PRESENT = 1, parameter CPU_RESET_DEFAULT = 1, parameter A31_DEFAULTS = 1, parameter MEM_DATA = "data.bin", parameter MEM_SIZE_KB = 1 ) ( input clk_i, rst_i, input [3:0] INT_i, // Expansion bus output xport_req_o, input xport_ack_i, input xport_err_i, output xport_we_o, output [31:0] xport_addr_bo, output [31:0] xport_wdata_bo, input xport_resp_i, input [31:0] xport_rdata_bi, //Debug interface input dbg_enb_i, input dbg_wr_i, input [31:0] dbg_addr_bi, input [31:0] dbg_data_bi, output dbg_resp_o, output [31:0] dbg_data_bo ); // ZPU system bus wire cpu_bus_enb; wire cpu_bus_we; wire cpu_bus_ack; wire [31:0] cpu_bus_read; wire [31:0] cpu_bus_write; wire [31:0] cpu_bus_addr; wire [3:0] cpu_bus_writemask; // MAU-RAM bus wire [31:0] ram0_bus_addr; wire ram0_bus_we; wire [31:0] ram0_bus_rddata; wire [31:0] ram0_bus_wrdata; wire [31:0] ram1_bus_addr; wire ram1_bus_we; wire [31:0] ram1_bus_rddata; wire [31:0] ram1_bus_wrdata; // ZPU control wire cpu_present; wire [63:0] zpu_status; wire cpu_break; wire [31:0] cpu_pc; wire cpu_interrupt; wire cpu_interrupt_ack; wire cpu_reset; wire cpu_enb; // INTC programming interface wire intc_ie; wire intc_ie_we; wire intc_ie_data; wire [7:0] intc_mask; wire [7:0] intc_pending; wire intc_clr_cmd; wire [7:0] intc_clr_code; // interrupts wire [3:0] INT; wire bus_error_int; wire trap_int; wire sgi_int; wire dma_int; generate if (CPU_PRESENT == 1) // Processor core zpu_core #( .stack_address((MEM_SIZE_KB * 1024) - 8) ) zpu_core ( .clk(clk_i), .sreset(rst_i | cpu_reset), .enable(cpu_enb), .cpu_present(cpu_present), .pc_bo(cpu_pc), .mem_req(cpu_bus_enb), .mem_we(cpu_bus_we), .mem_ack(cpu_bus_ack), .mem_read(cpu_bus_read), .mem_write(cpu_bus_write), .out_mem_addr(cpu_bus_addr), .mem_writeMask(cpu_bus_writemask), .interrupt(cpu_interrupt), .interrupt_ack(cpu_interrupt_ack), .break_o(cpu_break), .zpu_status(zpu_status) ); else zpu_core_stub zpu_core ( .clk(clk_i), .sreset(rst_i | cpu_reset), .enable(cpu_enb), .cpu_present(cpu_present), .pc_bo(cpu_pc), .mem_req(cpu_bus_enb), .mem_we(cpu_bus_we), .mem_ack(cpu_bus_ack), .mem_read(cpu_bus_read), .mem_write(cpu_bus_write), .out_mem_addr(cpu_bus_addr), .mem_writeMask(cpu_bus_writemask), .interrupt(cpu_interrupt), .interrupt_ack(cpu_interrupt_ack), .break_o(cpu_break), .zpu_status(zpu_status) ); endgenerate edge_detector edge_det0 ( .clk_i(clk_i), .rst_i(rst_i), .in(INT_i[0]), .out(INT[0]) ); edge_detector edge_det1 ( .clk_i(clk_i), .rst_i(rst_i), .in(INT_i[1]), .out(INT[1]) ); edge_detector edge_det2 ( .clk_i(clk_i), .rst_i(rst_i), .in(INT_i[2]), .out(INT[2]) ); edge_detector edge_det3 ( .clk_i(clk_i), .rst_i(rst_i), .in(INT_i[3]), .out(INT[3]) ); // Interrupt controller int_controller int_controller ( .clk_i(clk_i), .rst_i(rst_i), .interrupt_bi({INT, dma_int, sgi_int, trap_int, bus_error_int}), .ie_o(intc_ie), .ie_we_i(intc_ie_we), .ie_data_i(intc_ie_data), .mask_bi(intc_mask), .pending_bo(intc_pending), .clr_cmd_i(intc_clr_cmd), .clr_code_bi(intc_clr_code), .cpu_req_o(cpu_interrupt), .cpu_ack_i(cpu_interrupt_ack) ); ZPU_uC_SystemController #( .A31_DEFAULTS(A31_DEFAULTS), .CPU_RESET_DEFAULT(CPU_RESET_DEFAULT), .MEM_SIZE_KB(MEM_SIZE_KB) ) SystemController ( .clk_i(clk_i), .rst_i(rst_i), //// Masters //// // Debug bus // .dbg_enb_i(dbg_enb_i), .dbg_we_i(dbg_wr_i), .dbg_addr_bi(dbg_addr_bi), .dbg_wdata_bi(dbg_data_bi), .dbg_ack_o(dbg_resp_o), .dbg_rdata_bo(dbg_data_bo), // ZPU bus // .cpu_enb_i(cpu_bus_enb), .cpu_we_i(cpu_bus_we), .cpu_ack_o(cpu_bus_ack), .cpu_rdata_bo(cpu_bus_read), .cpu_wdata_bi(cpu_bus_write), .cpu_addr_bi(cpu_bus_addr), .cpu_writemask_bi(cpu_bus_writemask), //// Slaves //// // RAM0 bus // .ram0_addr_bo(ram0_bus_addr), .ram0_we_o(ram0_bus_we), .ram0_wdata_bo(ram0_bus_wrdata), .ram0_rdata_bi(ram0_bus_rddata), // RAM1 bus // .ram1_addr_bo(ram1_bus_addr), .ram1_we_o(ram1_bus_we), .ram1_wdata_bo(ram1_bus_wrdata), .ram1_rdata_bi(ram1_bus_rddata), // Expansion port // .xport_req_o(xport_req_o), .xport_ack_i(xport_ack_i), .xport_err_i(xport_err_i), .xport_we_o(xport_we_o), .xport_addr_bo(xport_addr_bo), .xport_wdata_bo(xport_wdata_bo), .xport_resp_i(xport_resp_i), .xport_rdata_bi(xport_rdata_bi), // INTC bus // .intc_ie_i(intc_ie), .intc_ie_we_o(intc_ie_we), .intc_ie_data_o(intc_ie_data), .intc_mask_bo(intc_mask), .intc_pending_bi(intc_pending), .intc_clr_cmd_o(intc_clr_cmd), .intc_clr_code_bo(intc_clr_code), .cpu_present(cpu_present), .cpu_pc_bi(cpu_pc), .cpu_break_i(cpu_break), .cpu_reset_o(cpu_reset), .cpu_enb_o(cpu_enb), .bus_error_int_o(bus_error_int), .trap_int_o(trap_int), .dma_int_o(dma_int), .sgi_int_o(sgi_int) ); ram_dual #( .mem_data(MEM_DATA), .dat_width(32), .adr_width(32), .mem_size((MEM_SIZE_KB * 1024) / 4 ) ) ram_dual_port ( .clk(clk_i), .dat0_i(ram0_bus_wrdata), .adr0_i({2'h0, ram0_bus_addr[31:2]}), .we0_i(ram0_bus_we), .dat0_o(ram0_bus_rddata), .dat1_i(ram1_bus_wrdata), .adr1_i({2'h0, ram1_bus_addr[31:2]}), .we1_i(ram1_bus_we), .dat1_o(ram1_bus_rddata) ); endmodule
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