Subversion Repositories pss

/*
 PSS
 
 Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
 All rights reserved.
 
 Version 0.99
 
 The FreeBSD license
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions
 are met:
 
 1. Redistributions of source code must retain the above copyright
    notice, this list of conditions and the following disclaimer.
 2. Redistributions in binary form must reproduce the above
    copyright notice, this list of conditions and the following
    disclaimer in the documentation and/or other materials
    provided with the distribution.
 
 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
 
module pss_soc_top
(
	input clk_i, rst_i,
 
	input rx_i,
	output tx_o,
 
	input ext_int_i,
 
	input  [7:0] SW,
	output reg [7:0] LED
);
 
wire sync_reset;
 
wire uc_bus_enb;
wire uc_bus_we;
wire [31:0] uc_bus_addr;
wire [31:0] uc_bus_wdata;
reg [31:0] uc_bus_rdata;
reg uc_bus_resp;
 
wire ext_int;
debouncer debouncer
(
	.clk_i(clk_i),
	.rst_i(rst_i),
 
	.in_i(ext_int_i),
	.out_o(ext_int)
);
 
wire [3:0] interrupts;
assign interrupts = {3'h0, ext_int};
 
pss
#(
	.CPU_PRESENT(1),
	.CPU_RESET_DEFAULT(0),
	.A31_DEFAULT(1),
	.MEM_DATA("<path_to_svn>/pss/trunk/pss/SW/onboard/Heartbeat/Heartbeat.hex"),
	.MEM_SIZE_KB(8)
)
PSS
(
	.clk_i(clk_i),
	.arst_i(rst_i),
	.srst_i(0),
	.srst_o(sync_reset),
 
	.rx_i(rx_i),
	.tx_o(tx_o),
 
	.INT_bi(interrupts),
 
	.xport_req_o(uc_bus_enb),
	.xport_ack_i(1'b1),
	.xport_err_i(1'b0),
	.xport_we_o(uc_bus_we),
	.xport_addr_bo(uc_bus_addr),
	.xport_wdata_bo(uc_bus_wdata),
	.xport_resp_i(uc_bus_resp),
	.xport_rdata_bi(uc_bus_rdata)
);
 
always @(posedge clk_i)
	begin
	if (rst_i) uc_bus_rdata <= 32'h0;
	else if (uc_bus_addr == 32'h8A000000) uc_bus_rdata <= SW;
	else uc_bus_rdata <= uc_bus_addr;
	end
 
always @(posedge clk_i)
	begin
	if (rst_i)
		uc_bus_resp <= 1'b0;
	else if ( (uc_bus_enb == 1'b1) && (uc_bus_we == 1'b0) )
		uc_bus_resp <= 1'b1;
	else
		uc_bus_resp <= 1'b0;
	end
 
always @(posedge clk_i)
	begin
	if (sync_reset)
		LED <= 8'hAA;
	else if (uc_bus_we)
		LED <= uc_bus_wdata;
	end
 
//assign uc_bus_rdata = uc_bus_addr;
 
endmodule