Subversion Repositories pulse_processing_algorithm

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--
--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration
--		p.j.j.lemmens@rug.nl
--    http://www-panda.gsi.de
--
--    As a reference, please use:
--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
--    Nuclear Inst. and Methods in Physics Research, A ....
--
--
--    This program is free software; you can redistribute it and/or modify
--    it under the terms of the GNU Lesser General Public License as published by
--    the Free Software Foundation; either version 3 of the License, or
--    (at your option) any later version.
--
--    This program is distributed in the hope that it will be useful,
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    GNU Lesser General Public License for more details.
--
--    You should have received a copy of the GNU General Public License
--    along with this program; if not, write to the Free Software
--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
--
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-- Company		:	KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands	
-- Author		:	P.J.J. Lemmens
-- Design Name	:	Feature Extraction
-- Module Name	:	SISO_add_a 
-- Description	:	Signed In Signed Out Adder Asynchronous
--						
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
 
entity SISO_add_a is
	Port (dataa		: in  STD_LOGIC_VECTOR;
			datab		: in  STD_LOGIC_VECTOR;
			result	: out  STD_LOGIC_VECTOR
			);
end SISO_add_a;
 
architecture Behavioral of SISO_add_a is
 
	constant	WIDTH		: natural		:= dataa'length;
	constant	MAXVAL	: integer		:= 2**(WIDTH - 1) - 1;
	constant	MINVAL	: integer		:= - 2**(WIDTH - 1);
 
	signal a_in_S		: std_logic_vector(WIDTH downto 0)	:= (others => '0');
	signal b_in_S		: std_logic_vector(WIDTH downto 0)	:= (others => '0');
	signal sum_S		: std_logic_vector(WIDTH downto 0)	:= (others => '0');
	signal status_S	: std_logic_vector(1 downto 0)		:= (others => '0');
--	signal overflow_S	: std_logic									:= '0';
 
begin
	a_in_S		<= dataa(dataa'high) & dataa;
	b_in_S		<= datab(datab'high) & datab;
 
	sum_S 		<=	conv_std_logic_vector((conv_integer(signed(a_in_S)) + conv_integer(signed(b_in_S))), WIDTH + 1);
	status_S		<= sum_S(WIDTH) & sum_S(WIDTH - 1);
--	overflow_S	<= sum_S(WIDTH) XOR sum_S(WIDTH - 1);
 
	result		<=	conv_std_logic_vector(MAXVAL, WIDTH)	when	(status_S = b"01") else
						conv_std_logic_vector(MINVAL, WIDTH)	when 	(status_S = b"10") else
						conv_std_logic_vector(conv_integer(signed(sum_S)), WIDTH);
 
end Behavioral;