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[/] [pulse_processing_algorithm/] [datapath_ddr2_iobs.vhd] - Rev 2
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--********************************************************************* -- DDR 72 Bit Controller DATA PATH for LEFT RIGHT Pins -- In the current DATA PATH logic DATA CAPTURE part was modified. -- The below changes were made to reduce the resources in -- the data capture -- in the current architecture data ( dq ) from ddr memory -- directly stored into the FIFO's. -- Architectural changes : -- Used only TWO FIFOs ( instead of FOUR FIFOs ) -- Used Single col ( col0 ) dqs_delayed_col signals -- Used Gray Counters for write and read pointers of the FIFOs -- fbit stage is removed from ddr1_dqbit module ( in the data capture ) -- dq_clk stage was removed -- dqs_clk_div logic was removed -- ddr1_transfer_done logic was removed -- data valid signals registering in clk90 domain was removed -- fifo_0 and fifo_1 wr_addr was double registered in clk90 domain -- only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic -- write enable for the FIFOs derived from rst_dqs_div signal -- Code revised by : Narayana Murty. -- Date : Nov 18, 2003. --********************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; --library synplify; --use synplify.attributes.all; -- -- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -- entity datapath_ddr2_iobs is port( clk : in std_logic; clk90 : in std_logic; reset90_r : in std_logic; dqs_reset : in std_logic; dqs_enable : in std_logic; ddr_dqs : inout std_logic_vector(1 downto 0); ddr_dq : inout std_logic_vector(15 downto 0); write_data_falling: in std_logic_vector(15 downto 0); write_data_rising : in std_logic_vector(15 downto 0); write_en_val : in std_logic; write_en_val1 : in std_logic; data_mask_f : in std_logic_vector(1 downto 0); data_mask_r : in std_logic_vector(1 downto 0); dqs_int_delay_in0 : out std_logic; dqs_int_delay_in1 : out std_logic; ddr_dq_in_rising : out std_logic_vector(15 downto 0); ddr_dq_in_falling : out std_logic_vector(15 downto 0); --old ddr_dq_val : out std_logic_vector(15 downto 0); ddr_dm : out std_logic_vector(1 downto 0) ); end datapath_ddr2_iobs; architecture arc_datapathiobs of datapath_ddr2_iobs is attribute syn_keep : boolean; -- Using Syn_Keep Derictive attribute syn_noprune : boolean; -- Using syn_noprune Derictive attribute syn_preserve : boolean; -- Using syn_noprune Derictive component s3_dqs_iob port( clk : in std_logic; clk180 : in std_logic; ddr_dqs_reset : in std_logic; ddr_dqs_enable : in std_logic; ddr_dqs : inout std_logic; dqs : out std_logic ); end component; COMPONENT s3_ddr_iob PORT( write_data_falling : IN std_logic; write_data_rising : IN std_logic; read_dq_ce : IN std_logic; clk_rx : IN std_logic; clk90 : IN std_logic; clk270 : IN std_logic; write_en_val : IN std_logic; reset : IN std_logic; ddr_dq_inout : INOUT std_logic; read_data_in_rising : OUT std_logic; read_data_in_falling : OUT std_logic ); END COMPONENT; component ddr2_dm port ( ddr_dm : out std_logic_vector(1 downto 0); mask_falling : in std_logic_vector(1 downto 0); mask_rising : in std_logic_vector(1 downto 0); clk90 : in std_logic; clk270 : in std_logic ); end component; component BUF port (I : in std_logic; O : out std_logic); end component; component LUT4 generic( INIT : bit_vector(15 downto 0) := x"0000" ); port( O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC ); end component; signal clk270 : std_logic; signal clk180 : std_logic; --signal ddr_dq_in : std_logic_vector( 15 downto 0); --attribute syn_keep of clk180 : signal is true; --attribute syn_keep of clk270 : signal is true; signal write_en_val_r : std_logic; --PL --signal write_en_val1_r : std_logic; signal dqs_enable1 : std_logic; signal dqs_reset1 : std_logic; signal read_dq_dqs0_ce : std_logic; signal read_dq_dqs1_ce : std_logic; signal dqs0_in : std_logic; signal dqs1_in : std_logic; attribute syn_keep of dqs0_in : signal is true; attribute syn_keep of dqs_int_delay_in0 : signal is true; attribute syn_keep of dqs_int_delay_in1 : signal is true; signal dqs0_in_delay1 : std_logic; signal dqs0_in_delay2 : std_logic; signal dqs0_in_delay3 : std_logic; signal dqs1_in_delay1 : std_logic; signal dqs1_in_delay2 : std_logic; signal dqs1_in_delay3 : std_logic; begin clk270 <= not clk90; clk180 <= not clk; dqs_enable1 <= dqs_enable; dqs_reset1 <= dqs_reset; --old ddr_dq_val <= ddr_dq_in; ddr2_dm0 : ddr2_dm port map ( ddr_dm => ddr_dm(1 downto 0), mask_falling => data_mask_f(1 downto 0), mask_rising => data_mask_r(1 downto 0), clk90 => clk90, clk270 => clk270 ); process(clk90) begin if clk90'event and clk90 = '0' then if reset90_r = '1' then write_en_val_r <= '0'; --PL -- write_en_val1_r <= '0'; else write_en_val_r <= write_en_val; --PL -- write_en_val1_r <= write_en_val1; end if; end if; end process; --*********************************************************************** -- Read Data Capture Module Instantiations --*********************************************************************** -- DQS IOB instantiations --*********************************************************************** -- dqs_int_delay_in0 <= dqs0_in ; -- dqs_int_delay_in1 <= dqs1_in ; --dqs0_buf_delay : BUF port map (I => dqs0_in, O => dqs_int_delay_in0); dqs0_lut_delay1 : LUT4 generic map (INIT => x"e2e2") port map ( I0 => '1', I1 => dqs0_in, I2 => '0', I3 => '1', O => dqs0_in_delay1 ); dqs0_lut_delay2 : LUT4 generic map (INIT => x"e2e2") port map ( I0 => '1', I1 => dqs0_in_delay1, I2 => '0', I3 => '1', -- O => dqs_int_delay_in0 O => dqs0_in_delay2 ); dqs0_lut_delay3 : LUT4 generic map (INIT => x"e2e2") port map ( I0 => '1', I1 => dqs0_in_delay2, I2 => '0', I3 => '1', O => dqs0_in_delay3 ); dqs0_lut_delay4 : LUT4 generic map (INIT => x"e2e2") port map ( I0 => '1', I1 => dqs0_in_delay3, I2 => '0', I3 => '1', O => dqs_int_delay_in0 ); dqs1_lut_delay1 : LUT4 generic map (INIT => x"e2e2") port map ( I0 => '1', I1 => dqs1_in, I2 => '0', I3 => '1', O => dqs1_in_delay1 ); dqs1_lut_delay2 : LUT4 generic map (INIT => x"e2e2") port map ( I0 => '1', I1 => dqs1_in_delay1, I2 => '0', I3 => '1', O => dqs1_in_delay2 ); dqs1_lut_delay3 : LUT4 generic map (INIT => x"e2e2") port map ( I0 => '1', I1 => dqs1_in_delay2, I2 => '0', I3 => '1', O => dqs1_in_delay3 ); dqs1_lut_delay4 : LUT4 generic map (INIT => x"e2e2") port map ( I0 => '1', I1 => dqs1_in_delay3, I2 => '0', I3 => '1', O => dqs_int_delay_in1 ); s3_dqs_iob0 : s3_dqs_iob port map ( clk => clk, clk180 => clk180, ddr_dqs_reset => dqs_reset1, ddr_dqs_enable => dqs_enable1, ddr_dqs => ddr_dqs(0), dqs => dqs0_in ); s3_dqs_iob1 : s3_dqs_iob port map ( clk => clk, clk180 => clk180, ddr_dqs_reset => dqs_reset1, ddr_dqs_enable => dqs_enable1, ddr_dqs => ddr_dqs(1), dqs => dqs1_in ); --****************************************************************************************************************************** -- DDR Data bit instantiations (-bits) --****************************************************************************************************************************** read_dq_dqs0_ce <= '1' ; read_dq_dqs1_ce <= '1' ; s3_ddr_iob0 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(0), write_data_falling => write_data_falling(0), write_data_rising => write_data_rising(0), --old read_data_in => ddr_dq_in(0), read_dq_ce => read_dq_dqs0_ce, clk_rx => dqs0_in, read_data_in_rising => ddr_dq_in_rising(0), read_data_in_falling => ddr_dq_in_falling(0), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob1 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(1), write_data_falling => write_data_falling(1), write_data_rising => write_data_rising(1), --old read_data_in => ddr_dq_in(1), read_dq_ce => read_dq_dqs0_ce, clk_rx => dqs0_in, read_data_in_rising => ddr_dq_in_rising(1), read_data_in_falling => ddr_dq_in_falling(1), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob2 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(2), write_data_falling => write_data_falling(2), write_data_rising => write_data_rising(2), --old read_data_in => ddr_dq_in(2), read_dq_ce => read_dq_dqs0_ce, clk_rx => dqs0_in, read_data_in_rising => ddr_dq_in_rising(2), read_data_in_falling => ddr_dq_in_falling(2), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob3 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(3), write_data_falling => write_data_falling(3), write_data_rising => write_data_rising(3), --old read_data_in => ddr_dq_in(3), read_dq_ce => read_dq_dqs0_ce, clk_rx => dqs0_in, read_data_in_rising => ddr_dq_in_rising(3), read_data_in_falling => ddr_dq_in_falling(3), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob4 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(4), write_data_falling => write_data_falling(4), write_data_rising => write_data_rising(4), --old read_data_in => ddr_dq_in(4), read_dq_ce => read_dq_dqs0_ce, clk_rx => dqs0_in, read_data_in_rising => ddr_dq_in_rising(4), read_data_in_falling => ddr_dq_in_falling(4), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob5 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(5), write_data_falling => write_data_falling(5), write_data_rising => write_data_rising(5), --old read_data_in => ddr_dq_in(5), read_dq_ce => read_dq_dqs0_ce, clk_rx => dqs0_in, read_data_in_rising => ddr_dq_in_rising(5), read_data_in_falling => ddr_dq_in_falling(5), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob6 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(6), write_data_falling => write_data_falling(6), write_data_rising => write_data_rising(6), --old read_data_in => ddr_dq_in(6), read_dq_ce => read_dq_dqs0_ce, clk_rx => dqs0_in, read_data_in_rising => ddr_dq_in_rising(6), read_data_in_falling => ddr_dq_in_falling(6), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob7 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(7), write_data_falling => write_data_falling(7), write_data_rising => write_data_rising(7), --old read_data_in => ddr_dq_in(7), read_dq_ce => read_dq_dqs0_ce, clk_rx => dqs0_in, read_data_in_rising => ddr_dq_in_rising(7), read_data_in_falling => ddr_dq_in_falling(7), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob8 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(8), write_data_falling => write_data_falling(8), write_data_rising => write_data_rising(8), --old read_data_in => ddr_dq_in(8), read_dq_ce => read_dq_dqs1_ce, clk_rx => dqs1_in, read_data_in_rising => ddr_dq_in_rising(8), read_data_in_falling => ddr_dq_in_falling(8), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob9 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(9), write_data_falling => write_data_falling(9), write_data_rising => write_data_rising(9), --old read_data_in => ddr_dq_in(9), read_dq_ce => read_dq_dqs1_ce, clk_rx => dqs1_in, read_data_in_rising => ddr_dq_in_rising(9), read_data_in_falling => ddr_dq_in_falling(9), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob10 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(10), write_data_falling => write_data_falling(10), write_data_rising => write_data_rising(10), --old read_data_in => ddr_dq_in(10), read_dq_ce => read_dq_dqs1_ce, clk_rx => dqs1_in, read_data_in_rising => ddr_dq_in_rising(10), read_data_in_falling => ddr_dq_in_falling(10), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob11 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(11), write_data_falling => write_data_falling(11), write_data_rising => write_data_rising(11), --old read_data_in => ddr_dq_in(11), read_dq_ce => read_dq_dqs1_ce, clk_rx => dqs1_in, read_data_in_rising => ddr_dq_in_rising(11), read_data_in_falling => ddr_dq_in_falling(11), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob12 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(12), write_data_falling => write_data_falling(12), write_data_rising => write_data_rising(12), --old read_data_in => ddr_dq_in(12), read_dq_ce => read_dq_dqs1_ce, clk_rx => dqs1_in, read_data_in_rising => ddr_dq_in_rising(12), read_data_in_falling => ddr_dq_in_falling(12), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob13 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(13), write_data_falling => write_data_falling(13), write_data_rising => write_data_rising(13), --old read_data_in => ddr_dq_in(13), read_dq_ce => read_dq_dqs1_ce, clk_rx => dqs1_in, read_data_in_rising => ddr_dq_in_rising(13), read_data_in_falling => ddr_dq_in_falling(13), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob14 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(14), write_data_falling => write_data_falling(14), write_data_rising => write_data_rising(14), --old read_data_in => ddr_dq_in(14), read_dq_ce => read_dq_dqs1_ce, clk_rx => dqs1_in, read_data_in_rising => ddr_dq_in_rising(14), read_data_in_falling => ddr_dq_in_falling(14), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); s3_ddr_iob15 : s3_ddr_iob port map( ddr_dq_inout => ddr_dq(15), write_data_falling => write_data_falling(15), write_data_rising => write_data_rising(15), --old read_data_in => ddr_dq_in(15), read_dq_ce => read_dq_dqs1_ce, clk_rx => dqs1_in, read_data_in_rising => ddr_dq_in_rising(15), read_data_in_falling => ddr_dq_in_falling(15), clk90 => clk90, clk270 => clk270, write_en_val => write_en_val_r, reset => reset90_r ); end arc_datapathiobs;